9 results about "Digital error correction" patented technology

The invention discloses a multi-channel high-speed low-power-consumption successive approximation analog-to-digital converter, system and method, and relates to the technical field of analog integrated circuit design, the analog-to-digital converter comprises an M-bit auxiliary ADC, n N-bit main ADCs, a multiplexer and a digital error correction circuit, an M-bit non-binary digital code is obtained through quantization of the auxiliary ADC, and the N-bit non-binary digital code is obtained through quantization of the N-bit main ADCs. A group of N-M-bit non-binary digital codes are obtained through quantization of multiple paths of main ADCs respectively, then combination and binary conversion are carried out on M-bit non-binary digital codes and each group of N-M-bit non-binary digital codes through a digital error correction circuit, n groups of binary digital codes are obtained and output, and multi-channel sampling, quantization, conversion and output are achieved. The device has the characteristics of low power consumption, high conversion speed and high precision, and the conversion speed and precision can be improved while the characteristic of low power consumption is maintained.

The application provides a high-speed Flash-SAR hybrid analog-digital converter and belongs to the technical field of chips.The application comprises a sampling switch, a Flash ADC, a comparator, a capacitive digital-analog converter, a successive approximation register and a digital error correction circuit.The application adopts a full-differential structure, an input signal is rapidly converted into a 3-digit code through the Flash ADC, meanwhile, the conversion of a high 3-digit capacitor corresponding switch of the capacitive digital-analog converter is controlled, and the conversion of the following digit is completed through the comparator.The capacitive array is divided into two sections, each section of capacitors adopts a capacitive architecture design based on binary error compensation, so that the errors caused by the imbalance of the comparator, the incomplete establishment of the top plate voltage and the thermal noise of the conversion switch itself are reduced;and due to the existence of the encoding circuit in the Flash ADC, the conversion from the thermometer code to the binary code is realized, the area of the chip is saved, and the power consumption is reduced.

The application discloses a single monotone switching type successive approximation analog-digital converter using bottom plate sampling time sequence, comprising a sample-and-hold circuit, a comparator, a digital-analog converter, an asynchronous clock generation module, a multi-clock time-sharing control successive approximation control module and a digital error correction circuit. The successive approximation approximation control logic adopts multi-clock time-sharing control, and uses switch switching time sequence in the bottom plate sampling technology to replace the switch switching time sequence of the top plate sampling technology of the single monotone switching type successive approximation analog-digital converter. In the sampling stage, the input signal is connected to the top plate of the capacitor array of the digital-analog converter and the input end of the comparator through the sample-and-hold circuit, but the switch in the sample-and-hold circuit and the bottom plate control switch of the capacitor array are switched using the bottom plate sampling time sequence to complete the sampling of the signal. The digital-analog converter module adopts non-binary redundancy technology and a segmented architecture, reduces the number of unit capacitors, and improves the tolerance of the reference voltage establishment error in the conversion process.

The application provides a pipeline successive approximation analog-digital converter calibration method and system, comprising the following steps: a misadjustment calibration step: calibrating the misadjustment voltage of a foreground comparator and a residual amplifier, measuring and storing the misadjustment voltage of the foreground comparator and the residual amplifier as a misadjustment calibration code, and compensating the misadjustment voltage of the foreground comparator and the residual amplifier; a mismatch calibration step: calibrating the mismatch of a foreground capacitor, measuring the capacitor mismatch in a previous CDAC, and calibrating the output code value of the pipeline successive approximation analog-digital converter in a digital error correction logic; a mismatch correction step: correcting the mismatch of an inter-stage gain combined by the foreground and the background, correcting the inter-stage gain mismatch once during startup, adjusting the gain of the residual amplifier, and detecting the inter-stage gain change by using a pseudo-random signal injection in the background and calibrating. The application can calibrate the non-ideal factors in the pipeline successive approximation analog-digital converter.

The invention discloses a high-speed low-power-consumption successive approximation type analog-to-digital converter, system and method, and relates to the technical field of analog integrated circuit design, and the analog-to-digital converter comprises an M-bit auxiliary ADC, an N-bit main ADC and a digital error correction circuit. The auxiliary ADC comprises a first gate voltage bootstrap circuit, a first non-binary DAC capacitor array, a first comparator and a first successive approximation logic module; the main ADC comprises a second gate voltage bootstrap circuit, a second non-binary DAC capacitor array, a second comparator and a second successive approximation logic module. M-bit non-binary digital codes are obtained through quantization of the auxiliary ADC, N-M-bit non-binary digital codes are obtained through quantization of the main ADC, and then the M-bit non-binary digital codes and the N-M-bit non-binary digital codes are converted into binary digital codes through the digital error correction circuit and output. According to the invention, the conversion speed and precision can be improved while the low power consumption characteristic is maintained.

Systems and methods for analog-to-digital conversion are described. A device can include a successive approximation register (SAR) analog-to-digital converter (ADC) and a flash ADC with a fractional bit resolution. The flash ADC can determine a digital code that encodes a voltage range of an input voltage, provide redundancy for digital error correction and output the digital code to the SAR ADC. The SAR ADC can decode the digital code to obtain a first set of bit values of a set of most significant bits (MSBs) of a digital output that is a digital representation of the input voltage, determine a second set of bit values of a set of least significant bits (LSBs) of the digital output, and generate the digital output based on the first set of bit values and the second set of bit values.

The invention relates to a dynamic pipeline-successive approximation hybrid high-precision low-delay analog-to-digital converter, which comprises a three-stage SAR ADC (Synthetic Aperture Radar Analog-to-Digital Converter), a two-stage dynamic open-loop integral margin amplifier and a digital error correction module. The first-stage SAR ADC adopts a grid voltage bootstrapped switch for sampling, the last two stages adopt transmission gates for sampling, and a bottom plate sampling technology is used for both the two stages. Each stage of SAR ADC comprises a sampling switch, a DAC, a dynamic comparator and an SAR logic circuit, and after part of bits are quantized, residual signals are amplified through a dynamic open-loop margin amplifier and transmitted to the next stage of SAR ADC. The operational amplifier offset elimination module corrects amplifier offset, and the digital error correction module integrates three-level output to generate final N-bit data. The architecture combines the low-power-consumption characteristic of the SAR ADC and the high-speed advantage of a pipeline structure, the power consumption is remarkably reduced through the dynamic open-loop design, the single-stage performance pressure is relieved through three-stage pipeline optimization, and the balance of high precision, low time delay and low power consumption is achieved.

The invention provides an SARADC based on a segmented redundant structure and a data conversion method thereof, and relates to the technical field of integrated circuit design. The SARADC adopts a core architecture of'segmented redundancy capacitor array + VCM differential switching + upper-level board sampling + digital error correction ', a capacitor array is divided into an MSB section and an LSB section, the highest-bit capacitor C6 of the LSB section is accurately set to be 33Cu through a non-binary redundancy weight distribution strategy, dynamic redundancy adjustment logic is combined, the total weight and M + L = 2n-1 are met, and n is the ADC bit number. The data conversion method comprises three core processes of sampling, successive approximation and digital correction, charge injection is eliminated through upper-level board sampling, power consumption is reduced through VCM differential switching, and non-binary codes are converted into standard binary codes to be output through the digital error correction circuit. Compared with a traditional SARADC, the number of capacitors is reduced by more than 80%, dynamic power consumption is reduced by 90%, the effective bit ENOB reaches 11.8 bits, gain errors and non-linear deviation are eliminated, and the SARADC is suitable for low-power-consumption and high-precision scenes such as the Internet of Things, wearable equipment and 5G communication.

This application discloses a high-speed, low-power successive approximation analog-to-digital converter (ADC), system, and method, relating to the field of analog integrated circuit design technology. The ADC includes an M-bit auxiliary ADC, an N-bit main ADC, and a digital error correction circuit. The auxiliary ADC includes a first gate voltage bootstrap circuit, a first non-binary DAC capacitor array, a first comparator, and a first successive approximation logic module. The main ADC includes a second gate voltage bootstrap circuit, a second non-binary DAC capacitor array, a second comparator, and a second successive approximation logic module. An M-bit non-binary digital code is obtained through quantization by the auxiliary ADC, and an N-M-bit non-binary digital code is obtained through quantization by the main ADC. The digital error correction circuit then converts the M-bit and N-M-bit non-binary digital codes into binary digital codes and outputs them. This application can improve conversion speed and accuracy while maintaining low power consumption.