31 results about "Digital error correction" patented technology

An apparatus for digital error correction in a successive approximation (SAR) analog to digital converter (ADC) includes a binary weighted digital to analog converter (DAC) which can be virtually divided into multiple sub-DACs for redundancy insertion; and a comparator configured to compare the analog input with a DAC level corresponding to digital. The apparatus further includes a register and control logic unit configured to control a switching operation for DAC and to add output codes obtained from sub-DACs to output the added code as a final A/D converted code.

A hybrid Analog-to-Digital Converter (ADC) has multiple stages. A first stage and a final stage each use a Successive-Approximation Register (SAR) ADC to generate the Most-Significant-Bits (MSBs) and the Least-Significant-Bits (LSBs) over successive internal cycles. Middle stage(s) use a faster flash ADC with multiple comparators in parallel to generate the middle binary bits, which are then re-converted by a Digital-to-Analog Converter (DAC) and subtracted from the stage's input analog voltage to generate a difference that is amplified by a residual amplifier that outputs an amplified voltage to the next stage. The first stage also has this multiplying DAC structure to convert the MSBs to an amplified voltage to the first of the middle stages. Finally, digital error correction logic removes redundant binary bits between stages. Initial and final SAR stages of 4 and 8 bits with a 4-bit middle stage provide a hybrid ADC of 14-bit precision.

An anti-noise successive approximation analog to digital conversion method is provided with the steps of instructing a comparison control circuit to perform a predetermined number of extra comparison cycles in a plurality of valid bit cycles and outputting a plurality of digital signals wherein no digital to analog feedback is perform; instructing a digital error correction circuit to correct any digital signals having erroneous bits due to noise interference in the outputted digital signals and output a bit or byte as a result of the correction, the bit or byte being defined as a noise free digital output bit or byte; and performing a successive approximation analog to digital conversion based on the digital output bit or byte if there are any subsequent bit cycles.

Interleaved Analogue to Digital converter, comprising a plurality of individual ADCs (71). A digital filter stage (20) is used for equalizing the responses of the individual ADCs, and comprises a FIR filter in which the coefficient table is cyclically reloaded between ADCs' samples, in order to reduce the number of multipliers required.

The present invention provides an analog-to-digital converter (ADC) circuit comprising two time-interleaved successive approximation register (SAR) ADCs. Each of the two time-interleaved SAR ADCs comprises a first stage SAR sub-ADC, a residue amplifier, a second stage SAR sub-ADC and a digital error correction logic. The residue amplifier is shared between the time-interleaved paths, has a reduced gain and operates in sub-threshold to achieve power effective design

An analog to digital converter is provided. The converter comprises a dither gain generator, a first stage, an adder, a second stage, and a digital error correction logic. The dither gain generator generates a dither gain. The first stage receives a first voltage to generate a first digital code and a second voltage. The adder is coupled to the first stage and adds the dither voltage to the second voltage to generate a third voltage. The second stage receives the third voltage to generate a second digital code. The digital error correction logic receives and corrects the first digital code and the second digital code to generate a digital code corresponding to the first voltage.

The invention relates to the technical field of audio processing devices, and particularly relates to a wireless microphone based on Bluetooth BLE transmission. A data processing and control module encodes and compresses an audio signal, and a Bluetooth BLE module transmits the audio signal encoded and compressed by the data processing and control module to electronic mobile equipment through a Bluetooth BLE mode, instead of traditional Bluetooth audio transmission modes such as BR/EDR. The wireless microphone can be applied to, for example, mobile phones, Bluetooth speakers, loudspeakers andthe like, can further achieve the transmission and playback of audios, and can meet a wide range of application requirements, such as karaoke entertainment, square dancing and the like; moreover, theBluetooth BLE has low power consumption, low cost and higher applicability, and cannot be restricted by the traditional Bluetooth applications such as BR/EDR; and an original audio signal is subjectedto digital AD sampling, the data processing and control module uses processor compression, digital error correction and compensation algorithms, and also combines with a traffic control algorithm forpackaging, thereby, the sound quality can be guaranteed, good scalability and compatibility can be achieved, and strong practical values and market promotion values can be realized.

The invention discloses a digital to analog converter. The digital to analog converter comprises a first-stage SAR digital to analog conversion sub-circuit, a second-stage SAR digital to analog conversion sub-circuit, an error amplifying circuit and a digital error correction circuit, wherein the first-stage SAR digital to analog conversion sub-circuit is used for performing 6-bit primary quantization processing on an input signal in order to obtain a high 6-bit signal and output the obtained high 6-bit signal to the digital error correction circuit, and outputting a remaining residual signal to the error amplifying circuit; the error amplifying circuit is used for amplifying the residual signal, and transmitting the amplified signal to the second-stage digital to analog conversion sub-circuit; the second-stage SAR digital to analog conversion sub-circuit is used for performing 7-bit secondary quantization processing on the amplified signal in order to obtain a low 7-bit signal and output the obtained low 7-bit signal to the digital error correction circuit; the second-stage SAR digital to analog conversion sub-circuit and the first-stage SAR digital to analog conversion sub-circuit share the same reference voltage; and the digital error correction circuit is used for performing staggered adding on the high 6-bit signal and the low 7-bit signal in order to obtain a 12-bit digitally-quantized signal. The digital to analog converter is simple in structure, and power consumption can be saved effectively.

The invention discloses an anti-noise gradual approximation type analog digital conversion device and a method thereof. The device mainly comprises a gradual approximation type analog digital converter, a digital error correction circuit and a redundancy comparison control circuit, wherein the gradual approximation type analog digital converter comprises a first comparator, a digital analog converter and a gradual approximation type control circuit. The method comprises steps that: a redundancy comparison period is carried out in a random valid bit period, before accomplishment of the redundancy comparison period, comparison motion is carried out only by a comparator, extra digital analog feedback is not carried out, after all outputs of the comparator within the redundancy comparison period are filtered through a digital low pass filter or is checked through a reference table, a digital value set is outputted, and a digital value is designated as the digital value in the valid bit period.

An error-correcting circuit comprises: a component arranged to generate a first output from a first input and a second input; an error detector arranged to generate an error flag indicative of whether or not it has detected an error in the first output, based on the first output,the first input and the second input; a correction generator suitable for generating a correcting output after a first time period beginning with a timing event, based on the first output, the first input and the second input; and an output generator arranged to generate an output of the error-correcting circuit after a second time period beginning with the timing event. If the error flag indicates that an error has been detected in the first output then the second time period may be longer than the first time period, otherwise the second time period may be not longer than the first time period.; If the error flag indicates that an error has been detected in the first output then the output of the error-correcting circuit may comprise a combination of the first output and the correcting output whereby the error detected in the first output is corrected, otherwise the output of the error-correcting circuit may correspond directly to the first output.

The invention relates to a novel fourteen-bit assembly line-successive approximation type analog-to-digital converter, which comprises a first-stage assembly line, a second-stage assembly line, a third-stage assembly line, a fourth-stage assembly line and digital error correction logic, wherein the first-stage assembly line, the second-stage assembly line and the third-stage assembly line are of afive-bit successive approximation type analog-to-digital converter structure, and one of the five bits is a redundant bit; the fourth-stage assembly line is a two-bit successive approximation type analog-to-digital converter; and an input signal passes through the first-stage assembly line, the second-stage assembly line, the third-stage assembly line and the fourth-stage assembly line to obtaina converted digital code, and the converted digital code is input into the digital error correction logic for processing to obtain a fourteen-bit digital code. The converter has the advantages of highconversion rate and low power consumption.

An analog-to-digital converter (ADC) function in which digital error correction is provided. Parallel ADC stages are synchronously clocked to convert an analog input signal into digital words; at least one of the digital outputs is encoded according to an error correction code. Decision logic circuitry decodes a code word comprised of the concatenation of the digital outputs from the parallel stages, to derive a digital output from which the digital output word corresponding to the analog input signal can be derived. The decision logic circuitry can provide an error signal used to correct the state of one or more bits of the digital output from one of the ADC stages, for the case of a systematic code; alternatively, the decision logic circuitry can directly decode the code word to provide the digital output. The architecture may be applied to stages in a pipelined ADC.

A time-to-digital converter (TDC) (300) is disclosed, which comprises a ring oscillator module (302) and a digital error correction module (304). The ring oscillator module is configured to receive asampling signal, an addressing signal, and a preset signal, and includes: a ring oscillator (3022) arranged with a plurality of inverters (3024); a phase sampler (3028) configured to sample phase signals generated by the inverters of the ring oscillator for generating a first output signal, on receipt of the sampling signal; a counter clock generator (3028) configured to generate first and secondclock signals, based on receipt of the sampling signal and respective phase signals generated by the first and last inverters of the ring oscillator; first and second counters (3030, 3032) configuredto respectively generate first and second counter output signals, based on receipt of the first and second clock signals respectively: and a data sampler (3034) configured to sample the first and second counter output signals to respectively generate second and third output signals. The digital error correction module is arranged to process the first, second and third output signals for generatinga digital signal representative of a time difference between receipt of a start signal and receipt of a stop signal by the TDC.

An analog to digital converter is provided. The converter comprises a first stage, an adjustment unit and a digital error correction logic. The first stage has a first sensing range and receives a first voltage to generate a first digital code. The adjustment unit adjusts the first sensing range of the first stage. The digital error correction logic receives and corrects the first digital code to generate a digital code corresponding to the first voltage.

The invention relates to the field of analog-to-digital circuits. For the problem that the signal-to-noise ratio of the modulator of the existing 2-1 type MASH structure is low, a modulator of 2-1 type MASH structure is proposed, which sets appropriate gain parameters in the modulator of the existing 2-1 type MASH structure to adjust the noise transfer function (NTF) of the modulator to improve the position of the zero pole, so that the quantization noise of the first stage is canceled out through the digital error correction logic due to the output of a first-stage modulator and the output ofa second-stage modulator, and the noise suppression effect within the signal bandwidth is enhanced. The structure is applicable to modulators in analog-to-digital conversion of audios.

An analog to digital converter is provided. The converter comprises a dither gain generator, a first stage, a multiplier, a second stage and a digital error correction logic. The dither gain generator generates a dither gain. The first stage receives a first voltage to generate a first digital code and a second voltage. The multiplier is coupled to the first stage and multiplies the second voltage with the dither gain to generate a third voltage. The second stage receives the third voltage to generate a second digital code. The digital error correction logic receives and corrects the first digital code and the second digital code to generate a digital code corresponding to the first voltage.