Systems and methods for analog-to-digital conversion are described. A device can include a successive approximation register (SAR) analog-to-digital converter (ADC) and a flash ADC with a fractional bit resolution. The flash ADC can determine a digital code that encodes a voltage range of an input voltage, provide redundancy for digital error correction and output the digital code to the SAR ADC. The SAR ADC can decode the digital code to obtain a first set of bit values of a set of most significant bits (MSBs) of a digital output that is a digital representation of the input voltage, determine a second set of bit values of a set of least significant bits (LSBs) of the digital output, and generate the digital output based on the first set of bit values and the second set of bit values.