7 results about "4-bit" patented technology

The application discloses an R-2R digital-analog converter with an auxiliary calibration structure and relates to the technical field of high-precision digital-analog conversion. The converter comprises a main DAC, a calibration quantity calculation module, a compensation code generation module, an auxiliary DAC and an operational amplifier circuit. The main DAC converts a digital input into an analog current. The calibration quantity calculation module generates a 15-bit compensation code containing a 1-bit sign bit and a 14-bit data bit through a 24-bit ADC, a comparator and successive approximation logic, and only calibrates the high 12 bits of the main DAC bit by bit, and the low 4 bits do not need to be calibrated. The compensation code generation module generates a total compensation code through gating by a multiplexer and superposition by an adder. The auxiliary DAC is a 14-bit binary current type structure, and realizes bidirectional compensation in cooperation with a positive and negative reference voltage source. The application has the advantages of short calibration period, small storage consumption, no need for additional bias calibration, excellent linearity, and suitability for application in the fields of wireless communication, biological medicine and the like, and meets the application requirements of high resolution and high precision.

This invention belongs to the field of wind turbine generator condition monitoring technology, and in particular to a high-precision wind turbine blade pitch angle detection system and method. The high-precision wind turbine blade pitch angle detection system includes a video acquisition module, high-reflectivity markers, an integrated processing unit, and a digital output module. The video acquisition module is installed inside the turbine hub and includes a global shutter camera and a ring infrared light source. The high-reflectivity markers are fixed on the surface of the pitch bearing and are ceramic-based reflective patches. The integrated processing unit adopts a RISC-V main control chip and FPGA collaborative architecture. This invention accelerates image preprocessing and optical flow tracking through FPGA, and combines Kalman filtering to achieve 0.1 accuracy angle detection. The result is encoded into a 7+4 bit binary signal and transmitted to the PLC via an isolated CAN bus. It is particularly suitable for real-time dynamic deviation detection in high-vibration and wide-temperature-varying environments, and especially suitable for real-time pitch control of large-megawatt wind turbine generators.

This disclosure relates to video coding and more particularly to techniques for signaling a picture type in coded video. According to an aspect of an invention, 4 bits NAL unit type information in a NAL unit header is decoded; and a NAL unit type indicating that a content of a NAL unit is trailing picture is determined.

The application discloses a lightweight dynamic S-box construction method for circuit implementation, and by using an automatic tool STP solver, a dynamic S-box structure satisfying specific cryptographic security properties can be automatically searched under given hardware resource constraints, the cryptographic security properties of the S-box under 1-4 bit dynamic control are considered, the logic gate circuit cost required can be effectively constrained, and the balance between the security performance of the dynamic S-box and the hardware implementation overhead can be explored, so that the result of considering both security and lightweight is obtained.

This invention provides a dual-table 128-entry optimization method based on activation functions. It accelerates the table lookup logic using SIMD instructions and obtains the correct table entry calculation by setting a corresponding mask through index merging. The method includes: dual-table lookup: dividing table entries into positive and negative entries; selecting either positive or negative numbers; S1, clipping the input data to a threshold range, making it a number between 0 and 127; S2, determining the range of the input data for selecting positive or negative entries; selecting Neg_dy and Neg_y0 for -127 to 0, and Pos_dy and N for 0 to 127. eg_y0; S3, Original index calculation: Original table entry index -127 to 127, each entry has 4 bits, totaling 128 numbers; (a) Word index; (b) Byte index; (c) Entry merging; S4, Determine the table entry index, use the instruction to look up the table: for positive numbers, update the table entry value corresponding to the positive number; for negative numbers, update the table entry value corresponding to the negative number; S5, Separate the high and low 4 bits to obtain the valid bit width data; when the data is negative, the corresponding data of the table entry needs to be updated; S6, Perform a multiplication operation on the data obtained from the table entry to obtain the final result.

This invention discloses a highly parallel rejection sampler for post-quantum cryptography and its operating method. The 8-bit sampled data is split into symmetrical high-4 and low-4 bit parallel sampling units: the high-4 bit unit performs data compression towards the least significant bit, and the low-4 bit unit performs data compression towards the most significant bit. The two compressed outputs are combined through physical splicing to form a pre-aligned data stream with continuous data in the middle and possible invalid data bits at the beginning and end. Subsequently, the system uses the effective data count value of the high-bit unit as a control signal to drive a multiplexer network to directly select the output result according to five preset alignment paths, thereby achieving a compact arrangement of fully parallel data. This invention avoids the complex multi-level shift operations in traditional architectures, greatly optimizes critical path latency and hardware resource overhead, and is suitable for high-speed hardware accelerator design for post-quantum cryptography algorithms.

This invention provides an optimization method for a single 128-entry table based on activation functions. The method accelerates the table lookup logic using SIMD instructions, merges indexes, sets corresponding masks, obtains the correct table entries, and then performs calculations. The method includes: Single-table lookup: Input data is determined to be positive, using only positive entries; Pos_dy: Positive entry 0, a total of 128 entries, each entry is 8 bits, totaling 512 bits, which can be stored in a register; Pos_y0: Positive entry 1, a total of 128 entries, each entry is 8 bits, totaling 512 bits, which can be stored in a register; S1: Input data is cilpped to a threshold range, making it a number between 0 and 127; S2: Original index calculation; S3: Determine the table entry index and use instructions to look up the table; S4: Separate the high and low 4 bits to obtain effective bit width data; S5: Multiply the data obtained from the table entries to obtain the final result. By using SIMD instructions and designing corresponding masks, the table lookup function based on a single 128-entry table based on activation functions is completed.