42 results about "4-bit" patented technology

The invention provides a large language model quantification method, related equipment and a computer program product, and the method comprises the steps: carrying out the reasoning of a to-be-quantized large language model through calibration data, obtaining the activation of the large language model, and carrying out the statistics of the activation distribution of a target layer according to channels; calculating a smoothing factor of each channel according to the activation distribution; compensating the weight of the target layer channel by channel according to the smoothing factor to obtain a compensated weight; performing 4-bit quantization on the compensated weight; in the model reasoning process, activation of a target layer is smoothed, and 16-bit quantization is carried out on the smoothed activation. According to the method, a W4A16 quantification scheme is adopted, compared with W8A8, the weight storage amount is compressed by half, meanwhile, the precision loss is controlled to be smaller than 3%, and deployment of a large language model on edge equipment is facilitated.

The invention discloses a hybrid precision storage and calculation control circuit based on a Sense-Switch type pFLASH. The hybrid precision storage and calculation control circuit comprises an NOR FLASH type SSpF storage and calculation array, a hybrid precision array controller, a hybrid precision shift adder and an AD module. The NOR FLASH type SSpF storage and calculation array is used for realizing convolution operation; the mixed precision array controller divides the NOR FLASH type SSpF memory calculation array according to the configured calculation precision, and completes input control and output sampling of 4, 8 or 16-bit convolution operation, and 4-bit weight programming and reading; the mixing precision shift adder performs shift addition on the output of the mixing precision array controller according to the sequence and the channel according to the configured calculation precision to obtain a 4, 8 or 16-bit convolution calculation result; the AD module is used for converting current output of the NOR FLASH type SSpF storage array into voltage output and converting an analog signal into a 4-bit digital signal. According to the method, 4, 8 or 16-bit convolution calculation can be realized in parallel, and the calculation precision can be configured.

Post-training quantization of weight values and activation values substantially reduces the memory and processing requirements of floating-point (FP) large language models (LLMs). A quantization parameter training process is performed on the FP LLM to determine quantization parameters. Weight-activation scaling may be applied to linear modules of the LLM, including down projection layers, enabling subsequent per-tensor quantization for activation values. The weight and activations values of the FP LLM are quantized from FP to integer values. Different layers may have different integer sizes. For example, weight values may be reduced to 4 bit integers and activation values to 8 bit integers. Layers within the model are modified to operate on the integer values. For example, an integer SiLU module may provide an integer approximation of a sigmoid-weighted linear unit activation function.

The invention provides a cache replacement method and device, equipment and a storage medium, a cache is formed by connecting n paths of groups, and n is 4 or 8; if n is 4, dividing every two paths into one group to obtain a first group and a second group; 4-bit access information is recorded; if n is 8, every two paths are divided into one group, and a third group, a fourth group, a fifth group and a sixth group are obtained; every two groups are divided into a large group, and a first large group and a second large group are obtained; 10 bit access information is recorded; the method comprises the following steps: acquiring cached access information; determining a cache line which is not accessed for the longest time according to the access information; and replacing the cache line which is not accessed for the longest time. According to the method provided by the invention, the cache line can be quickly replaced through the access information.

The invention provides a frequency spectrum segmentation FFT (Fast Fourier Transform) method and device based on an FPGA (Field Programmable Gate Array). The method comprises the following steps: step 1, acquiring original data of a time domain of a real-time vector signal through acquisition equipment; 2, parameters of a frequency spectrum segmentation FFT model are set, the parameters are set through an input configuration signal FFTconfig, the bit width of the signal FFTconfig is 8 bits, low 4 bits are the set point number L of each path of signal, and the calculation method is the power of a decimal number corresponding to the low 4 bits of 2; the high 4 bits are the channel number M; step 3, inputting the obtained original data of the time domain of the vector signal into a frequency spectrum segmentation FFT model; and step 4, outputting frequency domain data of the vector signal. The method supports a wide range of FFT points, can process FFT points of non-second power, and can effectively reduce the time for processing large-point FFT through multi-channel FFT parallel processing.

The invention provides a four-bit fixed-point BANKROUND implementation method based on simd. The four-bit fixed-point BANKROUND implementation method based on simd comprises the steps that S1, floating point conversion shaping and four-bit fixed-point operation are carried out; s2, performing right shift by 4 bits, i.e., after multiplying by 16, dividing by 16 for reduction, retaining an integer part of the data, and reducing the fixed-point data into original data; s3, retaining a decimal part of the data, wherein the decimal part is expressed as result3 = result1amp; 0 * 00001111, 0 * 00001111; s4, judging whether a decimal part is 0.5 or not: judging whether the decimal part is equal to 0.5 or not in banker rounding; s5, according to the BANKROUND standard, the condition of entering 1 needs to be met at the same time: case 1) decimal part gt; the condition is completed in the process of S1, and all the parts larger than or equal to 0.5 directly enter 1; 2) the decimal part is equal to 0.5, and the unit of the integer part needs to be ensured to be an odd number; s6, setting each 16-bit number meeting the condition in each result5 as 1, and setting each 16-bit number not meeting the condition as 0; and S7, subtracting the calculation result in the step S6 from the result after shifting calculated in the step S2.

The application discloses an R-2R digital-analog converter with an auxiliary calibration structure and relates to the technical field of high-precision digital-analog conversion. The converter comprises a main DAC, a calibration quantity calculation module, a compensation code generation module, an auxiliary DAC and an operational amplifier circuit. The main DAC converts a digital input into an analog current. The calibration quantity calculation module generates a 15-bit compensation code containing a 1-bit sign bit and a 14-bit data bit through a 24-bit ADC, a comparator and successive approximation logic, and only calibrates the high 12 bits of the main DAC bit by bit, and the low 4 bits do not need to be calibrated. The compensation code generation module generates a total compensation code through gating by a multiplexer and superposition by an adder. The auxiliary DAC is a 14-bit binary current type structure, and realizes bidirectional compensation in cooperation with a positive and negative reference voltage source. The application has the advantages of short calibration period, small storage consumption, no need for additional bias calibration, excellent linearity, and suitability for application in the fields of wireless communication, biological medicine and the like, and meets the application requirements of high resolution and high precision.

The present invention discloses a precision-configurable multiply-accumulate unit designed for a neural network accelerator. First, the zero-th computing unit and the first computing unit are summed through a fifth summation module, then the second computing unit and the third computing unit are summed through a sixth summation module, and finally the parts generated by the above two summations are finally summed through a third summation module. All the summation modules in the precision-configurable multiply-accumulate unit are correspondingly turned off according to different input bit widths to adapt to the multiply-accumulate operations of each layer of convolutional neural networks with different bit widths of 2 bits, 4 bits, and 8 bits. While ensuring a certain precision of the CNN, they not only simplify the computing unit and the external complex configurable logic, but also introduce the concept of approximate computing. Approximate computing is introduced into the configurable computing unit for the first time, enabling the architecture to further reduce power consumption based on bit-level flexibility and adapt to parameters from different quantization methods of the network.

The application discloses a high-performance block cipher construction method and device, electronic equipment and a storage medium, wherein the method comprises: an encryption process: using a preset round function generation algorithm to encrypt plaintext to obtain ciphertext, wherein a round key in the preset round function generation algorithm is obtained by performing position permutation on 32 positions in units of 4 bits through a 128-bit key scheduling algorithm; and a decryption process: decrypting the ciphertext through a decryption algorithm to obtain the plaintext. Thus, the problem that the existing block cipher algorithm has high resource occupation when hardware is efficiently implemented, and has low software implementation efficiency is solved.

An electronic device for performing a multiply and accumulate (MAC) operation includes at least one MAC unit, a memory, at least one 8b×8b operator, at least one 8b×4b operator, at least one 4b×4b operator, a bit shifter, an adder, at least one accumulator, and a processor. The processor receives first bit string data and second bit string data which include 12 bits, divides the first bit string data into 4 bits and 8 bits, divides the second bit string data into 4 bits and 8 bits, outputs two 8-bit results corresponding to activation 8-bit, weight 8-bit (A8W8) by using the bit shifter and a first accumulator on the basis of determining to output an A8W8 result, and outputs one 12-bit result corresponding to activation 12-bit, weight 12-bit (A12W12) on the basis of determining to output an A12W12 result.

To provide a method for confirming that an encryption algorithm for a public key longer than current 128 bits is supported between a terminal device UE and a network NW.SOLUTION: A message transmitted from a SEAF to a base station gNB in step S10 includes an ABBA parameter. Using the ABBA parameter, a terminal device UE is notified that a network NW side supports a 256-bit encryption algorithm. For example, using 4 bits in the ABBA parameter, it is achieved such that "0001: RAN is compatible with 256 bits" and "0010: AMF is compatible with 256 bits." By setting the ABBA parameter, the terminal device UE is notified that the RAN or AMF is compatible with the 256-bit encryption algorithm.SELECTED DRAWING: Figure 1

This invention belongs to the field of wind turbine generator condition monitoring technology, and in particular to a high-precision wind turbine blade pitch angle detection system and method. The high-precision wind turbine blade pitch angle detection system includes a video acquisition module, high-reflectivity markers, an integrated processing unit, and a digital output module. The video acquisition module is installed inside the turbine hub and includes a global shutter camera and a ring infrared light source. The high-reflectivity markers are fixed on the surface of the pitch bearing and are ceramic-based reflective patches. The integrated processing unit adopts a RISC-V main control chip and FPGA collaborative architecture. This invention accelerates image preprocessing and optical flow tracking through FPGA, and combines Kalman filtering to achieve 0.1 accuracy angle detection. The result is encoded into a 7+4 bit binary signal and transmitted to the PLC via an isolated CAN bus. It is particularly suitable for real-time dynamic deviation detection in high-vibration and wide-temperature-varying environments, and especially suitable for real-time pitch control of large-megawatt wind turbine generators.

The invention discloses a mixed parallel time sequence Pipelined-SAR ADC (Synthetic Aperture Radar Analog to Digital Converter), and relates to the technical field of integrated circuits, the Pipelined-SAR ADC comprises a first-stage SAR, a ring amplifier, a second-stage SAR, an inverter-based open-loop amplifier and a third-stage SAR; wherein the resolutions of the first-stage SAR, the second-stage SAR and the third-stage SAR are respectively set to be 5bit, 4bit and 5bit, and 2-bit redundancy is included in the first-stage SAR, the second-stage SAR and the third-stage SAR; the first-stage SAR adopts bottom plate sampling, and the second-stage SAR and the third-stage SAR adopt top plate sampling. According to the invention, a hybrid parallel time sequence scheme is provided, the problem that the time sequence of the second-stage SAR is tense is solved, the speed of the whole Pipelined-SAR ADC is improved, and the robustness of the ring amplifier is improved.

The invention provides a soft decision circuit and an implementation method thereof, computer equipment and a storage medium. The method comprises the following steps: acquiring an input angle value difference value; judging whether the angle value difference value is positive or negative so as to carry out reverse folding on the angle value difference value; comparing the angle value difference with a first preset angle range to match a first bit soft decision value; whether the angle value difference is larger than or equal to 90 degrees or not is judged, and rotation is conducted according to the angle value difference; and comparing the angle value difference with a second preset angle range to match the 2bit soft decision value. A soft decision circuit is adopted, and the probability of 0 and 1 is represented by 4 bits, so that the fault tolerance is enhanced. By using the method provided by the invention, under a specific application scene (DQPSK modulation mode), the information redundancy is increased by using the comparator and the selector, 0-1 weight information is provided for further channel decoding (Viterbi decoding), and the circuit is simple to implement.

The present invention describes a UE communicating with a base station. The UE may include: a receiving circuit configured to monitor a PDCCH having a DCI format; a transmitting circuit configured to transmit a PUSCH subject to a channel access procedure, the starting position of an initial symbol of the PUSCH being adjusted by x; wherein the DCI format includes a 4-bit information field, the 4 bits being characterized by at least one or more of the following values.

The application discloses a data interleaving method and device, and relates to the field of optical fiber communication systems.The method comprises the following steps: dividing an input bit data stream into a plurality of first data blocks by taking 4 bits as a unit, exchanging 2 bits of data in the middle of each first data block; dividing the exchanged bit data stream into second data blocks by taking 512 bits as a unit, and performing intra-block interleaving; and performing inter-block interleaving on the bit data stream after the intra-block interleaving through two random access memories.The application guarantees the original probability distribution characteristics of the PCS technology, and improves the ability of correcting burst errors in the joint application of the FEC technology and the PCS technology.

The application provides a design method and use method of a variable precision calculation unit applied to a quantized neural network convolution layer, shift operation is performed on a vector with a precision of 1, and the shift bit number, dimension and number of an operation basic block are determined. After the operation basic blocks are arranged, an addition tree is connected to form an array, and a variable precision fusion calculation unit is obtained. According to the actual precision of the current convolution layer activation value and the weight value, the variable precision fusion calculation unit array is configured, and each column of the fusion calculation unit is calculated in parallel. After the current convolution layer operation is completed, the two-dimensional array is reconfigured according to the data precision of the next convolution layer, and the operation of all convolution layers is completed in this way. The problems that the operation unit in the prior art is prone to causing waste of calculation resources in convolution operation less than 4 bits, and cannot dynamically adopt different quantization bit widths to process data according to the actual situation of the convolution layer are solved, and the resource utilization rate and the calculation efficiency are improved.

The invention relates to the technical field of data transmission, and discloses a bus signal for vehicle gauge level MCU chip adaptation evaluation, a generation method and a device, the bus signal is composed of a start frame, a 6-bit racing frame, a variable length control frame, a data frame, a 16-bit CRC check frame, a response frame and an end frame in sequence; 3-bit priorities and 3-bit data type identifiers are built in the race frame, the length of the control frame is dynamically expanded by multiplying the number of data type identifiers in the race frame as 0 by 4 bits, and the byte length of integer and single / double-precision floating point type data is sequentially defined 4 bits by 4 bits, so that the self-description of a protocol layer is realized. The generating device automatically completes frame coding, data filling, periodic sending and response backward reading after parameters are configured on the upper computer, a test vector can be switched in a zero script mode within the range of 1-200 ms, and a single frame bears 192-byte mixed data to the maximum extent, so that real-time blind decoding can be achieved without preset analysis of an MCU chip. According to the invention, the adaptation verification period of the vehicle-gauge-level MCU chip is obviously shortened, the test coverage rate is improved, and the manual coding error risk is reduced.

The invention provides a design method and a use method of a variable precision calculation unit applied to a quantization neural network convolutional layer, and the method comprises the steps: carrying out the shift operation of a vector with the precision of 1, and determining the shift digit, dimension and number of an operation basic block; and arranging operation basic blocks and then connecting the operation basic blocks by using an adder tree to form an array to obtain a fusion calculation unit with variable precision. According to the actual precision of the activation value and the weight value of the current convolutional layer, a variable-precision fusion calculation unit array is configured, and all columns of fusion calculation units carry out parallel calculation; and after the operation of the current convolutional layer is completed, according to the data precision of the next convolutional layer, the two-dimensional array is reconfigured, and the operation of all the convolutional layers is completed by parity of reasoning. The problems that in the prior art, an operation unit is prone to causing waste of calculation resources in convolution operation smaller than 4 bits, different quantization bit widths cannot be flexibly and dynamically adopted to process data according to the actual situation of a convolution layer, and the resource utilization rate and the calculation efficiency cannot be improved are solved.

Post-training quantization of weight values and activation values substantially reduces the memory and processing requirements of floating-point (FP) large language models (LLMs). A quantization parameter training process is performed on the FP LLM to determine quantization parameters. Weight-activation scaling may be applied to linear modules of the LLM, including down projection layers, enabling subsequent per-tensor quantization for activation values. The weight and activations values of the FP LLM are quantized from FP to integer values. Different layers may have different integer sizes. For example, weight values may be reduced to 4 bit integers and activation values to 8 bit integers. Layers within the model are modified to operate on the integer values. For example, an integer SiLU module may provide an integer approximation of a sigmoid-weighted linear unit activation function.

The invention discloses a low-power lithium battery charging device with a private protocol, and the device comprises a half-bridge rectification circuit and a private protocol module which are electrically connected with a wireless charging coil, the output end of the half-bridge rectification circuit is electrically connected with a constant voltage circuit, and the constant voltage circuit supplies power to the private protocol module and charges a battery; the protocol content of the private protocol module comprises 8-bit data bits, 2-bit data bits are adopted to transmit the voltage difference range between the rectified voltage Vrect output by the half-bridge rectifying circuit and the direct-current power supply voltage Vout output by the constant-voltage circuit, 2-3-bit data bits are adopted to transmit the direct-current power supply voltage Vout output by the constant-voltage circuit, and the voltage difference range between the rectified voltage Vrect output by the half-bridge rectifying circuit and the direct-current power supply voltage Vout output by the constant-voltage circuit and the direct-current power supply voltage Vout output by the constant-voltage circuit is within the range of 8-bit data bits. And transmitting the self-defined data by adopting data bits of 3-4 bits. The scanning power consumption of the transmitting end is saved, and the manufacturing cost is reduced.

The invention discloses a convolutional neural network pruning quantitative compression method based on an adaptive genetic algorithm. The method comprises the following implementation steps: calculating the sum of Euclidean distances between each convolution kernel of each filter in a pre-training network and other convolution kernels of a convolution layer where the filter is located; calculating the average rank of the feature map output by each filter; pruning the pre-trained convolutional neural network through an adaptive genetic algorithm, and adjusting the proportion of each filter to the convolutional layer and the network model; a hyperbolic tangent function and round operation are used to quantify the network into hardware-friendly bit widths of 2-bit, 4-bit and 8-bit, and a compressed convolutional neural network is obtained. The size of the network is reduced, it is guaranteed that the compressed network has high accuracy, the compressed network model has a hardware-friendly bit width, and the reasoning speed of the model in hardware equipment is greatly increased.

The invention provides a matmul transpose weight splitting method based on simd, in the method, weight splitting is formed by combining a series of 2bit transpose logics, an input column is transposed to an output row, the method is suitable for matmul calculation in any shape, and the method comprises the following steps: S1, reading data in a first row, namely data before transpose, from an input address by using an mx512lad (vr0, 0, input tradr, 0) instruction; s2, aggregating the 4 bit data together by using an mx512gt4bi instruction; s3, all the 2bits are aggregated together by using an mx512gt2bi instruction; s4, all the 16 bits are aggregated together by using an mx512th instruction; and S5, transposing the generated rows of data by using an mx512ilve instruction and an mx512ilvo instruction to obtain a weight splitting target output format. According to the method, additional input and output space development is reduced; a large number of la and sa instructions are reduced; and a large number of redundant instructions are removed.

This disclosure relates to video coding and more particularly to techniques for signaling a picture type in coded video. According to an aspect of an invention, 4 bits NAL unit type information in a NAL unit header is decoded; and a NAL unit type indicating that a content of a NAL unit is trailing picture is determined.

The invention discloses a method for transmitting a video signal containing an Alpha channel based on a high-definition multimedia interface, a receiving method and related electronic equipment, and relates to the technical field of digital video transmission. The method applied to the electronic equipment at the transmitting end comprises the following steps: acquiring to-be-transmitted video data with an RGB color signal and an Alpha channel signal; the RGB signal is converted into a YCbCr signal containing 8 bit Y, 4 bit Cb and 4 bit Cr; respectively filling YCbCr and Alpha channel signals into exclusive bearing intervals of the RGB three channels according to a preset mapping rule and a 24-bit width requirement, and generating to-be-sent data of which the single-frame total amount, the resolution and the time sequence are consistent with those of RGB4: 4: 4; and synchronous transmission of the video data to be transmitted is realized through a single interface. According to the scheme, the RGB color signals and the Alpha channel signals are synchronously transmitted through a single interface, and data integrity and transmission compliance are guaranteed.

The application discloses a Gamma / Vcom voltage value storage method, which comprises the following steps: receiving a plurality of voltage values generated by a first Gamma IC, converting each bit of the voltage value into a corresponding four-bit binary number, and sequentially storing the binary number into a preset position; reading the binary number, converting the binary number of every 4 bits into a decimal number, and outputting the voltage value composed of the converted decimal number by a second Gamma IC. For the Gamma / Vcom voltage value required by a customer, the application does not need to convert between two Gamma ICs, but only needs to output the Gamma / Vcom voltage value stored in the XB board EEP or FLASH, so that the application has universality and versatility, and can be used in SoCs designed by various different Gamma IC models, and has strong adaptability.

Disclosed embodiments relate to instructions for fused multiply-add (FMA) operations with variable-precision inputs. In one example, a processor to execute an asymmetric FMA instruction includes fetch circuitry to fetch an FMA instruction having fields to specify an opcode, a destination, and first and second source vectors having first and second widths, respectively, decode circuitry to decode the fetched FMA instruction, and a single instruction multiple data (SIMD) execution circuit to process as many elements of the second source vector as fit into an SIMD lane width by multiplying each element by a corresponding element of the first source vector, and accumulating a resulting product with previous contents of the destination, wherein the SIMD lane width is one of 16 bits, 32 bits, and 64 bits, the first width is one of 4 bits and 8 bits, and the second width is one of 1 bit, 2 bits, and 4 bits.

The present invention relates to a 4-bit optoelectronic adder using IR LED's, IR detectors and supporting circuit. The adder performs binary operations on two numbers each of 4 bits. The adder uses only Infrared light intensity and its combination in various forms to give the result of addition which is detected by IR detector and identified by supporting electronic circuitry to give output of addition.

This provides a suitable method for dividing video coding blocks for JVET. [Solution] The MPM set includes a set of intra predictive coding modes other than the six, and is encoded using truncated unary binarization. The 16 selected intra predictive coding modes are encoded using 4 bits of fixed-length code, and the remaining unselected coding modes are encoded using truncated binary coding. The JVET coding tree unit is coded as the root node of a QTBT structure. The QTBT structure has a quadtree branching from the root node and binary trees branching from each of the multiple leaf nodes of the quadtree, and using asymmetric binary partitioning, the coding unit represented by the leaf nodes of the quadtree is divided into multiple child nodes, and the multiple child nodes are represented as multiple leaf nodes of binary trees branching from the leaf nodes of the quadtree.

The application discloses a lightweight dynamic S-box construction method for circuit implementation, and by using an automatic tool STP solver, a dynamic S-box structure satisfying specific cryptographic security properties can be automatically searched under given hardware resource constraints, the cryptographic security properties of the S-box under 1-4 bit dynamic control are considered, the logic gate circuit cost required can be effectively constrained, and the balance between the security performance of the dynamic S-box and the hardware implementation overhead can be explored, so that the result of considering both security and lightweight is obtained.