Address error detection by merging a polynomial-based CRC code of address bits with two nibbles of data or data ECC bits

Abstract

A memory system provides data error detection and correction and address error detection. A Single-byte Error-Correcting/Double-byte Error-Detecting (SbEC/DbED) code with the byte being a 4-bit nibble is used to detect up to 8-bit errors and correct data errors of 4 bits or less. Rather than generating address parity, which is poor at detecting even numbers of errors, a cyclical-redundancy-check (CRC) code generates address check bits. A 32-bit address is compressed to just 4 address check bits using the CRC code. The 4 address check bits are merged (XOR'ed) with two 4-bit nibbles of the data SbEC/DbED code to generate a merged ECC codeword that is stored in memory. An address error causes a 2-nibble mis-match due to the redundant merging of the 4 address check bits with 2 nibbles of data correction code. The CRC code is ideal for detecting even numbers of errors common with multiplexed-address DRAMs.

Description

BACKGROUND OF INVENTION[0001]This invention relates to error detection and correction, and more particularly to address error detection merged with data error detection and correction.[0002]Digital memories are susceptible to errors caused by a variety of sources. Cosmic radiation can flip the state of individual memory cells. Pattern-sensitive capacitive coupling, noise, and hardware failures such as shorts can occur, causing multiple bits to be read incorrectly. Sometimes entire memory chips can fail. When a memory contains several memory chips, such as on a memory module, a one-chip failure may produce a multi-bit error, such as a 4-bit error in a 72-bit memory word.[0003]Additional bits are often included in the memory for storing an error-correction code (ECC). These additional ECC bits can be used to detect an error in the data bits being read, and can sometimes be used to correct those errors. Typically, a code is selected such that the data is unmodified. All error detection...

AI Technical Summary

Problems solved by technology

Digital memories are susceptible to errors caused by a variety of sources.

Pattern-sensitive capacitive coupling, noise, and hardware failures such as shorts can occur, causing multiple bits to be read incorrectly.

Sometimes entire memory chips can fail.

When a memory contains several memory chips, such as on a memory module, a one-chip failure may produce a multi-bit error, such as a 4-bit error in a 72-bit memory word.

While such S4EC / D4ED codes are useful for protecting against failures in whole memory chips, and in the wires to and from the memory chips, failures can also occur in the address lines to one or more of the memory chips.

For example, a solder connection to an address pin of one of the memory chips might start failing after some time.

A single solder connection can thus cause two bits of the address to be faulty.

Some of the memory errors may be caused by cosmic radiation.

This may cause a wrong address to be read from within the memory chip.

A data error can be signaled when the stored ECC does not match the re-generated ECC.

Some memories may lack a sufficient width to store all of the check bits.

It may be undesirable to reduce the number of data ECC bits to fit in some address parity bits.

There are trade-offs among the number of check bits and expense of the memory system, the largest multi-bit data error that can be corrected and detected, and the degree of detection of address errors.

Adding additional check bits for the address parity is often undesirable.

The use of multiplexed address bits causes 2-bit address errors to be as likely as 1-bit address errors in a real system.

However, if the address has a parity error, the extracted data ECC bits may not be able to correct an otherwise correctable data error.

Thus some data correction ability may be lost.

This happens if the address error causes an error syndrome to be created that matches the error syndrome for an otherwise correctable data error.

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