60 results about "8-bit" patented technology

Post-training quantization of weight values and activation values substantially reduces the memory and processing requirements of floating-point (FP) large language models (LLMs). A quantization parameter training process is performed on the FP LLM to determine quantization parameters. Weight-activation scaling may be applied to linear modules of the LLM, including down projection layers, enabling subsequent per-tensor quantization for activation values. The weight and activations values of the FP LLM are quantized from FP to integer values. Different layers may have different integer sizes. For example, weight values may be reduced to 4 bit integers and activation values to 8 bit integers. Layers within the model are modified to operate on the integer values. For example, an integer SiLU module may provide an integer approximation of a sigmoid-weighted linear unit activation function.

The invention relates to the technical field of digital signal processing, and particularly discloses a mixed precision low-resource digital control oscillator implementation method and system based on an FPGA (Field Programmable Gate Array), and the method comprises the steps: dividing a 32-bit phase accumulator into a high-bit 24-bit dominant frequency control section and a low-bit 8-bit dynamic compensation section, and carrying out the phase accumulation in parallel through double carry chains, the high-order section receives high 24 bits of a frequency tuning word FTW to control a dominant frequency, and the low-order section receives low 8 bits of the FTW and overlaps an overflow remainder to dynamically compensate for a phase error. According to the implementation method of the mixed precision low-resource digital control oscillator based on the FPGA disclosed by the embodiment of the invention, through collaborative innovation of mixed precision phase accumulation, hierarchical mixed storage, high-order interpolation reconstruction and dynamic phase compensation, the core problems of a traditional NCO in resource occupation, phase continuity, waveform precision and time sequence performance are systematically solved.

The invention relates to a three-dimensional data processing method and a three-dimensional data processing device. A three-dimensional data processing method of the present disclosure includes generating an N-way tree structure of a plurality of three-dimensional points, where N is an integer of 2 or more, and generating information indicating whether 8 bits corresponding to nodes included in the N-way tree structure include 4 or more bits each corresponding to a fixed value.

The invention provides a frequency spectrum segmentation FFT (Fast Fourier Transform) method and device based on an FPGA (Field Programmable Gate Array). The method comprises the following steps: step 1, acquiring original data of a time domain of a real-time vector signal through acquisition equipment; 2, parameters of a frequency spectrum segmentation FFT model are set, the parameters are set through an input configuration signal FFTconfig, the bit width of the signal FFTconfig is 8 bits, low 4 bits are the set point number L of each path of signal, and the calculation method is the power of a decimal number corresponding to the low 4 bits of 2; the high 4 bits are the channel number M; step 3, inputting the obtained original data of the time domain of the vector signal into a frequency spectrum segmentation FFT model; and step 4, outputting frequency domain data of the vector signal. The method supports a wide range of FFT points, can process FFT points of non-second power, and can effectively reduce the time for processing large-point FFT through multi-channel FFT parallel processing.

The application provides a quantization method and device of a deep neural network, equipment and a medium. The method comprises: obtaining a full floating point deep neural network training model, the storage length of at least one parameter of the full floating point deep neural network training model is less than 8 bits and / or the storage length of at least one data is less than 8 bits. According to the relationship between each operation in the operation set of the full floating point deep neural network training model, the operation set of the full floating point deep neural network training model is compressed to obtain the operation set of a deep neural network inference model corresponding to the full floating point deep neural network training model. The deep neural network inference model is sent to a terminal. Thus, the influence on the performance of the terminal can be reduced, such as the influence on the ROM, RAM, CPU, inference time and other performances of the terminal.

The present application relates to the technical field of chip packaging, and provides a computing apparatus, a memory module group, a computing device, and a computing device cluster. The computing apparatus comprises at least one memory module group, a processor, and a mainboard. Each memory module in the memory module group is formed by stacking memory chips having a bit width of at least 8 bits, the size is small, the stacking process is simple, each memory module is accessed through at least one memory channel, and the density of the memory channels in unit area is large, so that the memory module group in the computing apparatus can provide large bandwidth to meet the requirements of AI or large-scale computing scenarios on bandwidth, without adopting a HBM having high process difficulty and high costs, thereby reducing engineering difficulty and saving costs. In addition, the processor and the memory modules communicate on the basis of a DRAM interface, and compared with an HBM interface, there is less delay, resulting in lower power consumption generated by the delay, thereby improving the data read-write efficiency, and significantly improving the random access efficiency.

The application provides a pathological section recognition neural network model weight encryption method, including: acquiring a bit string as a pathological section recognition neural network model weight key; writing the bit string into a lower triangular matrix according to 8 bits as a number to obtain a first data matrix; performing digital conversion on the first 8 bits in the bit string to obtain first element data; reading a weight matrix of the pathological section recognition neural network model into a blank matrix to obtain a weight vector matrix; combining the first element data matrix and the weight vector matrix together to obtain a first data vector; obtaining an intermediate ciphertext vector by using a chaotic mapping algorithm according to the first data matrix and the first data vector; performing element data processing on the intermediate ciphertext vector to obtain a weight vector intermediate encryption matrix; and performing position disordering on the weight vector intermediate encryption matrix to obtain an encrypted weight vector matrix. The application can improve the safety coefficient of the neural network weight.

A decoder includes an entropy decoder configured to derive a number of bins of the binarizations from the data stream using binary entropy decoding by selecting a context among different contexts and updating probability states associated with the different contexts, dependent on previously decoded portions of the data stream; a desymbolizer configured to debinarize the binarizations of the syntax elements to obtain integer values of the syntax elements; a reconstructor configured to reconstruct the video based on the integer values of the syntax elements using a quantization parameter, wherein the entropy decoder is configured to distinguish between 126 probability states and to initialize the probability states associated with the different contexts according to a linear equation of the quantization parameter, wherein the entropy decoder is configured to, for each of the different contexts, derive a slope and an offset of the linear equation from first and second four bit parts of a respective 8 bit initialization value.

To provide a three-dimensional data processing method and apparatus that can improve processing efficiency. [Solution] The three-dimensional data processing method generates an N-branch tree structure of three-dimensional points where N is an integer of 2 or more, generates information indicating whether the 8 bits corresponding to the nodes included in the N-branch tree structure include 4 or more bits corresponding to a fixed value, encodes the parameters, and encodes the target nodes included in the N-branch tree structure of multiple three-dimensional points (where N is an integer of 2 or more). In encoding the target nodes, if the parameters indicate the first information, invalid bits are set from the 8 bits corresponding to the target node.

The present invention discloses a precision-configurable multiply-accumulate unit designed for a neural network accelerator. First, the zero-th computing unit and the first computing unit are summed through a fifth summation module, then the second computing unit and the third computing unit are summed through a sixth summation module, and finally the parts generated by the above two summations are finally summed through a third summation module. All the summation modules in the precision-configurable multiply-accumulate unit are correspondingly turned off according to different input bit widths to adapt to the multiply-accumulate operations of each layer of convolutional neural networks with different bit widths of 2 bits, 4 bits, and 8 bits. While ensuring a certain precision of the CNN, they not only simplify the computing unit and the external complex configurable logic, but also introduce the concept of approximate computing. Approximate computing is introduced into the configurable computing unit for the first time, enabling the architecture to further reduce power consumption based on bit-level flexibility and adapt to parameters from different quantization methods of the network.

Embodiments of this application provide a video editing method and an electronic device. When an image processor of the electronic device does not support to output a video with a bit depth of 10 bits by using an existing output function, an electronic device implementing the video editing method may edit the video with the bit depth of 10 bits based on an editing operation selected by a user, and output the video with the bit depth of 10 bits by using an existing function of outputting a video with a bit depth of 8 bits.

The invention provides a simd-based double magnification bilinear interpolation implementation method, which aims at a double magnification ratio, so that the zoom coefficients in x and y directions are 0.5, and comprises the following steps: S1, amplifying the original resolution by 2 * 2; s2, boundary point special calculation: carrying out special processing on a first row / a last row / a first column / a last column; s3, core calculation of four fixed points: S3.1, parallel calculation of two rows and two columns, and simultaneous calculation of dst (0, 0), dst (1, 0), dst (0, 1) and dst (1, 1) which respectively correspond to coordinates x and y: dst (x, y), dst (x + 1, y), dst (x, y + 1), dst (x + 1, y + 1); s3.2, calculating and multiplying the input pixel points by the corresponding weights respectively; s3.3, multiplying the input data by the weight in the w direction, and expanding the data to 16 bits to prevent overflow; and S4, according to a final result, the data is quantized to 8 bits by using bankround. According to the method, the scaling is twice scaling, 4-bit fixed-point calculation is used in the process, the calculation efficiency and accuracy are improved, floating points are converted into bit fixed-point calculation, and the calculation amount is reduced. The input data are reused, and the data repeated carrying time is shortened.

The invention provides a computing device, a memory module group, computing equipment and a computing equipment cluster, and belongs to the technical field of chip packaging. The computing device comprises at least one memory module group, a processor and a mainboard. Each memory module in the memory module group is formed by stacking the memory chips with the bit width of at least 8 bits, the size is small, the stacking process is simple, each memory module is accessed through at least one memory channel, and the density of the memory channels in unit area is large, so that the memory module group in the computing device can provide a large bandwidth, and the computing device is suitable for the computing device. According to the method, the requirements of AI or large-scale computing scenes on bandwidth are met, an HBM with high process difficulty and high cost does not need to be adopted, the engineering difficulty can be reduced, and the cost can be saved; besides, the processor and the memory module communicate based on the DRAM interface, and compared with an HBM interface, the delay is smaller, so that the power consumption generated by the delay is smaller, the data read-write efficiency is improved, and the random access efficiency is obviously improved.

This invention provides an optimized method for grayscale image mean preprocessing. For grayscale images, 128 image data points are loaded each time. One register loads 16 8-bit data points, using eight variable registers: vrd0, vrd2, vrd4, vrd6, vrd8, vrd10, vrd12, and vrd14. The loaded register data is then converted to 16 bits, meaning 16 registers are used to store the data. These variable registers are reused, and eight more variable registers are added to generate vrd0, vrd1, ..., vrd12. 5. Use a register `sum_h0` to accumulate 16-bit data. When `sum_h0` accumulates 256 times, shift the data right by 8 bits (equivalent to dividing by 256). Then, use a new register `sum_h1` to accumulate the shifted `sum_h0`, while `sum_h0` is initialized to 0. Then, re-accumulate the newly loaded data. Use `sum_h1` to accumulate the shifted `sum_h0`. When `sum_h1` accumulates 256 times, save the result of `sum_h1` to an array. Finally, accumulate the data in the array again and calculate the average. This optimization improves speed by 40 times.

An electronic device for performing a multiply and accumulate (MAC) operation includes at least one MAC unit, a memory, at least one 8b×8b operator, at least one 8b×4b operator, at least one 4b×4b operator, a bit shifter, an adder, at least one accumulator, and a processor. The processor receives first bit string data and second bit string data which include 12 bits, divides the first bit string data into 4 bits and 8 bits, divides the second bit string data into 4 bits and 8 bits, outputs two 8-bit results corresponding to activation 8-bit, weight 8-bit (A8W8) by using the bit shifter and a first accumulator on the basis of determining to output an A8W8 result, and outputs one 12-bit result corresponding to activation 12-bit, weight 12-bit (A12W12) on the basis of determining to output an A12W12 result.

Particular embodiments may remove a condition check in the semantics for checking a high-precision data flag. This simplifies the semantics used in the encoding and decoding process. In this case, even if the high-precision data flag is not set, the value of the weighted prediction syntax element is set by the BitDepth variable. However, even if the BitDepth is not considered high-precision data, such as 8 bits, the range for the weighted prediction syntax element is still the same as the fixed value. For example, the syntax elements luma_offset_10[i], luma_offset_11[i], delta_chroma_offset_10[i][j], and delta_chroma_offset_11[i][j] use the variable BitDepth as described above whether the flag extended_precision_processing_flag is enabled and not enabled to indicate whether the bit depth is above a threshold.

A communication apparatus communicates an Extremely High Throughput (EHT) Multi-User (MU) Physical Layer Protocol Data Unit (PPDU) including an Extremely High Throughput-Signal-B (EHT-SIG-B) including a resource unit (RU) allocation subfield including N×8 bits, where N=8 holds in a case where the communication apparatus uses a bandwidth of 320 MHz as a bandwidth.

This invention discloses an S-box generation method with optimal algebraic immunity and high nonlinearity, belonging to the field of cryptography. The invention comprises: a control signal register receiving and storing control signals from a nonlinear transformation controller; an information memory receiving and storing 8 bits of information to be processed; an expansion transformer expanding and transforming the information to be processed into 12 bits; a segmenter segmenting it into 6-bit groups LT and RT; the nonlinear transformation controller reading its control signal from the control signal register; if the signal is 1, the control sequence LT enters nonlinear transformation unit 1, and the sequence RT enters nonlinear transformation unit 2; if the signal is 0, the opposite occurs; a connector connecting the output sequences of nonlinear transformation units 1 and 2 yields the information output Y, which is stored in the information memory. This invention, while ensuring optimal algebraic immunity, high nonlinearity, and balance of the S-box, increases the difficulty of deciphering encrypted information by thoroughly obfuscating the plaintext.

This invention discloses an ARM-based SSI absolute encoder, including at least one MCU processor. The MCU processor's MISO pin outputs a data signal on the second edge of the clock, with the clock phase and polarity set to CPHA=0 and CPOL=1, respectively. The transmission bit length between the clock and the main controller is configured to 8 bits, the data mode is set to MSB, and the SPI interrupt is enabled. Data packets are then grouped and transmitted according to the required number of data bits. The SPI_DATA register is assigned a value within the SPI interrupt. After the last transmission, SPI is disabled, and a timer is enabled to pull the MCU processor's MISO pin low. When the count reaches the timeout period Tm, MISO is pulled high to enable SPI and the timer is disabled. The advantage of this invention is that it is suitable for applications requiring high-precision position measurement.

The present invention discloses a low-computing-power feature extraction and data compression method for acceleration sensor data. The method includes a feature extraction algorithm for three-axis acceleration sensor data, and a data compression algorithm for the extracted features. After the acceleration data is segmented by a sliding window, the resultant acceleration direction is calculated. According to the pre-defined base directions, the base direction numbers are used to replace the resultant acceleration directions in sequence according to the proximity principle. The direction codes are counted to obtain a histogram of the frequency of occurrence of each base direction in a single sliding window. In a short period of time, the distribution of the resultant acceleration direction is relatively concentrated. Based on this property, the value 0 is encoded as a single bit with a value of 0. For non-zero values, 8 bits are used to represent it. The first bit is fixed to 1 as a flag bit, and the last 7 bits are the binary values ​​of the corresponding frequencies. The encoded binary string is used for data transmission. Application of this method can save the computational overhead of the feature extraction and data compression process and reduce the overall power consumption of the device.

An information expression method for manufacturing features of a model part comprises the steps that redundant parts of a part raw material are removed through methods such as milling, and a to-be-machined blank is obtained; according to the manufacturing and machining requirements, listing the manufacturing characteristics of the model parts needing to be machined, and defining the manufacturing characteristics of the model parts in a binary mode to obtain a manufacturing characteristic database; the manufacturing features of the model part correspond to three primary color component color codes of RGB, the three primary color components of RGB are represented by 8 bits, the R primary color component color code corresponds to type information of the manufacturing features, the G primary color component color code corresponds to precision grade information of the manufacturing features, and the B primary color component color code corresponds to processing information of the manufacturing features; according to the method, the technical problem that a current numerical control automatic programming system cannot completely express geometric information and process constraint information of parts is solved, and the process of digitalization, informatization and intellectualization of numerical control programming is accelerated.

The invention provides a data routing management method and system with a plurality of AXI main equipment core particle controllers, which are used for realizing correct access of the core particle controllers which cross multiple layers and accord with the national standard GBT 46280 to far-end equipment, and the method comprises the following steps: step S1, numbering all main equipment on a current AXI bus in sequence, and configuring numbers to the core particle controllers; s2, a dynamic mapping table is arranged in the core particle controller, an ID field has 8 bits, the number of the ID fields is 256, and each item corresponds to an independent ID number; and S3, setting all entries to be in an invalid state through a starting system. By utilizing the method and the device, the problem that the ID field bits are not enough after a plurality of main devices are arranged on the AXI bus and cross the core particle controller is effectively solved, and core particle data of the plurality of AXI main devices are correctly transmitted to the remote equipment across the multi-layer core particle controller.

The present invention belongs to the technical field of measuring instruments, and is specifically a USB to 25-pin parallel port converter. The USB to 25-pin parallel port converter of the present invention includes a Teensy 3.6 single-chip microcomputer, a parallel port adapter, and a 25-pin parallel port connector; the single-chip microcomputer receives a 16-bit trigger value sent from a computer as a USB serial port device, splits it into two 8-bit integers, and then sets the levels of the pre-set 8 pins in sequence to represent the 8 bits of each integer, and transmits them to the 25-pin parallel port connector through the parallel port adapter to achieve the transmission of 16-bit integers through 8 pins. The present invention is compatible with experimental instruments that can only receive 8-bit integer trigger signals, and can operate normally in desktop or laptop computers, Windows or Ubuntu environments. It solves the problem that modern computers no longer have 25-pin parallel ports and have a small capacity for 8-bit integer trigger information, and improves the possibility of portability in implementing brain science experiments.

The present application relates to the technical field of chip packaging, and provides a memory module, an apparatus, and a server. The memory module comprises at least one memory chip set; the memory chip set comprises at least one subset; different subsets are connected to different memory channels; each subset is formed by stacking a plurality of memory chips; the bit widths of the memory chips in each subset include a first bit width and a second bit width; the first bit width is N times the second bit width, and the second bit width is greater than or equal to 8 bits, wherein N is a positive integer greater than 1. Compared with the related art, because memory chips having larger bit widths are adopted, the number of memory chips carried by a memory channel is smaller, thereby reducing the number of CA lines in the memory channel, and lowering the CA signal load of a CPU; the CPU can directly drive clock and CA signals so as to access the memory module, eliminating the need for relay driving via an RCD, reducing product costs; and moreover, the memory module is more miniaturized and can be mounted closer to the CPU, improving the signal quality.

The present application relates to a kind of fault attack methods for RIPEMD-160 hash algorithm, first randomly generates to be handled message, and to be handled message is as the input of RIPEMD-160 algorithm, using random single byte fault model, in the fifth round of import random 8 bits fault, obtains error output.Based on error output, deduce intermediate state value, then using statistical method, calculate the hamming weight of intermediate state value, according to the minimum value of hamming weight, the correct value of corresponding message is obtained.Repeat the process of importing fault and analysis, finally the complete message to be handled can be deduced.The method provided by the present application is easy to implement, fast and high accuracy, and provides important analysis basis for the security research of RIPEMD-160 hash algorithm.

The application provides a method for processing weight outliers during post-model quantization. w The critical value is max w The maximum value of full-precision data, and b is the bit width after quantization; when S w Is less than the critical value, that is, when S x Is the scale of the input feature value Feature, when the weight and Feature are quantized to 8 bits, the maximum value of W int Is 128, and the maximum value of X int Is 255; at this time, the output quantization result is determined by b i Mainly, the weight is quantized to 0, and S w Is set to 1, thereby avoiding the problem that the quantization result is incorrect due to the weight outliers. The application solves the problem that the final model precision is lost due to the overflow of the calculated quantization hyperparameters caused by the weight data outliers during the post-model quantization process, and provides a method for improving the model quantization precision.

Post-training quantization of weight values and activation values substantially reduces the memory and processing requirements of floating-point (FP) large language models (LLMs). A quantization parameter training process is performed on the FP LLM to determine quantization parameters. Weight-activation scaling may be applied to linear modules of the LLM, including down projection layers, enabling subsequent per-tensor quantization for activation values. The weight and activations values of the FP LLM are quantized from FP to integer values. Different layers may have different integer sizes. For example, weight values may be reduced to 4 bit integers and activation values to 8 bit integers. Layers within the model are modified to operate on the integer values. For example, an integer SiLU module may provide an integer approximation of a sigmoid-weighted linear unit activation function.

This invention discloses a distributed CAN data remote acquisition and monitoring system and method, including an acquisition-end device, a cloud server, and a client device. The acquisition-end device has a built-in unique hardware identifier, encapsulates CAN data frames using a 10-byte fixed header protocol, and encodes the channel identifier in the high 8 bits of the CAN identifier, achieving single-link multi-channel transmission. Before establishing a TCP connection, the acquisition-end device actively triggers an ARP request, employing a three-retry connection establishment method with a 3-second interval between each retry to solve the ARP resolution failure problem in direct connection scenarios. The cloud server establishes a long TCP connection with the acquisition-end device, receives the encapsulated data, performs device authentication, and forwards the data. The client device connects to the cloud server via WebSocket to monitor CAN data in real time. This invention achieves remote centralized monitoring of CAN devices, hardware anti-cloning, multi-channel single-link transmission, automatic reconnection after disconnection, and is compatible with existing CAN analysis software. It is suitable for scenarios such as remote vehicle diagnostics, charging pile monitoring, and BMS data acquisition.

The application discloses a kind of 8 bit S box construction method based on improved genetic algorithm, comprising the following steps: (1) by Logistic chaotic mapping and Tent chaotic mapping to form a kind of compound chaotic system, generates initialization population;(2) combined with the nonlinearity of S box, difference uniformity and strict avalanche criterion generates a multi-objective segmented weighted fitness function;(3) using the cross operation of guaranteeing S box bijectivity;(4) construct a reverse search method to search mutation point, and combined with hill climbing algorithm, random search method, generate based on 2N round search mutation operation, 2 point mutation point search is carried out in the first N rounds, 3 point mutation point search is used in the last N rounds, and a look-up table statistics method is further used to evaluate the property of optimized S box;(5) based on improved genetic algorithm constructs 8 bit password S box.The method of the application can generate 8 bit S box with excellent cryptographic properties based on improved genetic algorithm.

The invention discloses an efficient column bit feature recognition method based on byte alignment, and belongs to the technical field of data processing. According to the method, different byte alignment processing modes are adopted according to whether the frame length in a data stream is integral multiple of 8 bits or not: when the frame length is integral multiple of 8 bits, a structured data group is constructed, and byte-level sliding scanning and jumping access are performed based on a processing window so as to extract and identify a feature sequence; and when the frame length is not an integer multiple of 8 bits, combining a plurality of frames into a multiframe to realize byte alignment, and identifying by remapping original column bit features into a plurality of parallel short sequences. Complex bit-level shifting and mask calculation are avoided through the byte alignment operation, the data processing efficiency and the cache hit rate are remarkably improved, the CPU load is reduced, meanwhile, the method can flexibly adapt to column bit feature recognition requirements of different frame lengths and intervals, and the real-time processing requirement of high-speed data streams is effectively met.