41 results about "8-bit" patented technology

The invention relates to the technical field of digital signal processing, and particularly discloses a mixed precision low-resource digital control oscillator implementation method and system based on an FPGA (Field Programmable Gate Array), and the method comprises the steps: dividing a 32-bit phase accumulator into a high-bit 24-bit dominant frequency control section and a low-bit 8-bit dynamic compensation section, and carrying out the phase accumulation in parallel through double carry chains, the high-order section receives high 24 bits of a frequency tuning word FTW to control a dominant frequency, and the low-order section receives low 8 bits of the FTW and overlaps an overflow remainder to dynamically compensate for a phase error. According to the implementation method of the mixed precision low-resource digital control oscillator based on the FPGA disclosed by the embodiment of the invention, through collaborative innovation of mixed precision phase accumulation, hierarchical mixed storage, high-order interpolation reconstruction and dynamic phase compensation, the core problems of a traditional NCO in resource occupation, phase continuity, waveform precision and time sequence performance are systematically solved.

The application provides a quantization method and device of a deep neural network, equipment and a medium. The method comprises: obtaining a full floating point deep neural network training model, the storage length of at least one parameter of the full floating point deep neural network training model is less than 8 bits and / or the storage length of at least one data is less than 8 bits. According to the relationship between each operation in the operation set of the full floating point deep neural network training model, the operation set of the full floating point deep neural network training model is compressed to obtain the operation set of a deep neural network inference model corresponding to the full floating point deep neural network training model. The deep neural network inference model is sent to a terminal. Thus, the influence on the performance of the terminal can be reduced, such as the influence on the ROM, RAM, CPU, inference time and other performances of the terminal.

The present application relates to the technical field of chip packaging, and provides a computing apparatus, a memory module group, a computing device, and a computing device cluster. The computing apparatus comprises at least one memory module group, a processor, and a mainboard. Each memory module in the memory module group is formed by stacking memory chips having a bit width of at least 8 bits, the size is small, the stacking process is simple, each memory module is accessed through at least one memory channel, and the density of the memory channels in unit area is large, so that the memory module group in the computing apparatus can provide large bandwidth to meet the requirements of AI or large-scale computing scenarios on bandwidth, without adopting a HBM having high process difficulty and high costs, thereby reducing engineering difficulty and saving costs. In addition, the processor and the memory modules communicate on the basis of a DRAM interface, and compared with an HBM interface, there is less delay, resulting in lower power consumption generated by the delay, thereby improving the data read-write efficiency, and significantly improving the random access efficiency.

The application provides a pathological section recognition neural network model weight encryption method, including: acquiring a bit string as a pathological section recognition neural network model weight key; writing the bit string into a lower triangular matrix according to 8 bits as a number to obtain a first data matrix; performing digital conversion on the first 8 bits in the bit string to obtain first element data; reading a weight matrix of the pathological section recognition neural network model into a blank matrix to obtain a weight vector matrix; combining the first element data matrix and the weight vector matrix together to obtain a first data vector; obtaining an intermediate ciphertext vector by using a chaotic mapping algorithm according to the first data matrix and the first data vector; performing element data processing on the intermediate ciphertext vector to obtain a weight vector intermediate encryption matrix; and performing position disordering on the weight vector intermediate encryption matrix to obtain an encrypted weight vector matrix. The application can improve the safety coefficient of the neural network weight.

A decoder includes an entropy decoder configured to derive a number of bins of the binarizations from the data stream using binary entropy decoding by selecting a context among different contexts and updating probability states associated with the different contexts, dependent on previously decoded portions of the data stream; a desymbolizer configured to debinarize the binarizations of the syntax elements to obtain integer values of the syntax elements; a reconstructor configured to reconstruct the video based on the integer values of the syntax elements using a quantization parameter, wherein the entropy decoder is configured to distinguish between 126 probability states and to initialize the probability states associated with the different contexts according to a linear equation of the quantization parameter, wherein the entropy decoder is configured to, for each of the different contexts, derive a slope and an offset of the linear equation from first and second four bit parts of a respective 8 bit initialization value.

To provide a three-dimensional data processing method and apparatus that can improve processing efficiency. [Solution] The three-dimensional data processing method generates an N-branch tree structure of three-dimensional points where N is an integer of 2 or more, generates information indicating whether the 8 bits corresponding to the nodes included in the N-branch tree structure include 4 or more bits corresponding to a fixed value, encodes the parameters, and encodes the target nodes included in the N-branch tree structure of multiple three-dimensional points (where N is an integer of 2 or more). In encoding the target nodes, if the parameters indicate the first information, invalid bits are set from the 8 bits corresponding to the target node.

The invention provides a simd-based double magnification bilinear interpolation implementation method, which aims at a double magnification ratio, so that the zoom coefficients in x and y directions are 0.5, and comprises the following steps: S1, amplifying the original resolution by 2 * 2; s2, boundary point special calculation: carrying out special processing on a first row / a last row / a first column / a last column; s3, core calculation of four fixed points: S3.1, parallel calculation of two rows and two columns, and simultaneous calculation of dst (0, 0), dst (1, 0), dst (0, 1) and dst (1, 1) which respectively correspond to coordinates x and y: dst (x, y), dst (x + 1, y), dst (x, y + 1), dst (x + 1, y + 1); s3.2, calculating and multiplying the input pixel points by the corresponding weights respectively; s3.3, multiplying the input data by the weight in the w direction, and expanding the data to 16 bits to prevent overflow; and S4, according to a final result, the data is quantized to 8 bits by using bankround. According to the method, the scaling is twice scaling, 4-bit fixed-point calculation is used in the process, the calculation efficiency and accuracy are improved, floating points are converted into bit fixed-point calculation, and the calculation amount is reduced. The input data are reused, and the data repeated carrying time is shortened.

The invention provides a computing device, a memory module group, computing equipment and a computing equipment cluster, and belongs to the technical field of chip packaging. The computing device comprises at least one memory module group, a processor and a mainboard. Each memory module in the memory module group is formed by stacking the memory chips with the bit width of at least 8 bits, the size is small, the stacking process is simple, each memory module is accessed through at least one memory channel, and the density of the memory channels in unit area is large, so that the memory module group in the computing device can provide a large bandwidth, and the computing device is suitable for the computing device. According to the method, the requirements of AI or large-scale computing scenes on bandwidth are met, an HBM with high process difficulty and high cost does not need to be adopted, the engineering difficulty can be reduced, and the cost can be saved; besides, the processor and the memory module communicate based on the DRAM interface, and compared with an HBM interface, the delay is smaller, so that the power consumption generated by the delay is smaller, the data read-write efficiency is improved, and the random access efficiency is obviously improved.

This invention provides an optimized method for grayscale image mean preprocessing. For grayscale images, 128 image data points are loaded each time. One register loads 16 8-bit data points, using eight variable registers: vrd0, vrd2, vrd4, vrd6, vrd8, vrd10, vrd12, and vrd14. The loaded register data is then converted to 16 bits, meaning 16 registers are used to store the data. These variable registers are reused, and eight more variable registers are added to generate vrd0, vrd1, ..., vrd12. 5. Use a register `sum_h0` to accumulate 16-bit data. When `sum_h0` accumulates 256 times, shift the data right by 8 bits (equivalent to dividing by 256). Then, use a new register `sum_h1` to accumulate the shifted `sum_h0`, while `sum_h0` is initialized to 0. Then, re-accumulate the newly loaded data. Use `sum_h1` to accumulate the shifted `sum_h0`. When `sum_h1` accumulates 256 times, save the result of `sum_h1` to an array. Finally, accumulate the data in the array again and calculate the average. This optimization improves speed by 40 times.

An electronic device for performing a multiply and accumulate (MAC) operation includes at least one MAC unit, a memory, at least one 8b×8b operator, at least one 8b×4b operator, at least one 4b×4b operator, a bit shifter, an adder, at least one accumulator, and a processor. The processor receives first bit string data and second bit string data which include 12 bits, divides the first bit string data into 4 bits and 8 bits, divides the second bit string data into 4 bits and 8 bits, outputs two 8-bit results corresponding to activation 8-bit, weight 8-bit (A8W8) by using the bit shifter and a first accumulator on the basis of determining to output an A8W8 result, and outputs one 12-bit result corresponding to activation 12-bit, weight 12-bit (A12W12) on the basis of determining to output an A12W12 result.

A communication apparatus communicates an Extremely High Throughput (EHT) Multi-User (MU) Physical Layer Protocol Data Unit (PPDU) including an Extremely High Throughput-Signal-B (EHT-SIG-B) including a resource unit (RU) allocation subfield including N×8 bits, where N=8 holds in a case where the communication apparatus uses a bandwidth of 320 MHz as a bandwidth.

This invention discloses an S-box generation method with optimal algebraic immunity and high nonlinearity, belonging to the field of cryptography. The invention comprises: a control signal register receiving and storing control signals from a nonlinear transformation controller; an information memory receiving and storing 8 bits of information to be processed; an expansion transformer expanding and transforming the information to be processed into 12 bits; a segmenter segmenting it into 6-bit groups LT and RT; the nonlinear transformation controller reading its control signal from the control signal register; if the signal is 1, the control sequence LT enters nonlinear transformation unit 1, and the sequence RT enters nonlinear transformation unit 2; if the signal is 0, the opposite occurs; a connector connecting the output sequences of nonlinear transformation units 1 and 2 yields the information output Y, which is stored in the information memory. This invention, while ensuring optimal algebraic immunity, high nonlinearity, and balance of the S-box, increases the difficulty of deciphering encrypted information by thoroughly obfuscating the plaintext.

This invention discloses an ARM-based SSI absolute encoder, including at least one MCU processor. The MCU processor's MISO pin outputs a data signal on the second edge of the clock, with the clock phase and polarity set to CPHA=0 and CPOL=1, respectively. The transmission bit length between the clock and the main controller is configured to 8 bits, the data mode is set to MSB, and the SPI interrupt is enabled. Data packets are then grouped and transmitted according to the required number of data bits. The SPI_DATA register is assigned a value within the SPI interrupt. After the last transmission, SPI is disabled, and a timer is enabled to pull the MCU processor's MISO pin low. When the count reaches the timeout period Tm, MISO is pulled high to enable SPI and the timer is disabled. The advantage of this invention is that it is suitable for applications requiring high-precision position measurement.

The invention provides a data routing management method and system with a plurality of AXI main equipment core particle controllers, which are used for realizing correct access of the core particle controllers which cross multiple layers and accord with the national standard GBT 46280 to far-end equipment, and the method comprises the following steps: step S1, numbering all main equipment on a current AXI bus in sequence, and configuring numbers to the core particle controllers; s2, a dynamic mapping table is arranged in the core particle controller, an ID field has 8 bits, the number of the ID fields is 256, and each item corresponds to an independent ID number; and S3, setting all entries to be in an invalid state through a starting system. By utilizing the method and the device, the problem that the ID field bits are not enough after a plurality of main devices are arranged on the AXI bus and cross the core particle controller is effectively solved, and core particle data of the plurality of AXI main devices are correctly transmitted to the remote equipment across the multi-layer core particle controller.

The present application relates to the technical field of chip packaging, and provides a memory module, an apparatus, and a server. The memory module comprises at least one memory chip set; the memory chip set comprises at least one subset; different subsets are connected to different memory channels; each subset is formed by stacking a plurality of memory chips; the bit widths of the memory chips in each subset include a first bit width and a second bit width; the first bit width is N times the second bit width, and the second bit width is greater than or equal to 8 bits, wherein N is a positive integer greater than 1. Compared with the related art, because memory chips having larger bit widths are adopted, the number of memory chips carried by a memory channel is smaller, thereby reducing the number of CA lines in the memory channel, and lowering the CA signal load of a CPU; the CPU can directly drive clock and CA signals so as to access the memory module, eliminating the need for relay driving via an RCD, reducing product costs; and moreover, the memory module is more miniaturized and can be mounted closer to the CPU, improving the signal quality.

The present application relates to a kind of fault attack methods for RIPEMD-160 hash algorithm, first randomly generates to be handled message, and to be handled message is as the input of RIPEMD-160 algorithm, using random single byte fault model, in the fifth round of import random 8 bits fault, obtains error output.Based on error output, deduce intermediate state value, then using statistical method, calculate the hamming weight of intermediate state value, according to the minimum value of hamming weight, the correct value of corresponding message is obtained.Repeat the process of importing fault and analysis, finally the complete message to be handled can be deduced.The method provided by the present application is easy to implement, fast and high accuracy, and provides important analysis basis for the security research of RIPEMD-160 hash algorithm.

The application provides a method for processing weight outliers during post-model quantization. w The critical value is max w The maximum value of full-precision data, and b is the bit width after quantization; when S w Is less than the critical value, that is, when S x Is the scale of the input feature value Feature, when the weight and Feature are quantized to 8 bits, the maximum value of W int Is 128, and the maximum value of X int Is 255; at this time, the output quantization result is determined by b i Mainly, the weight is quantized to 0, and S w Is set to 1, thereby avoiding the problem that the quantization result is incorrect due to the weight outliers. The application solves the problem that the final model precision is lost due to the overflow of the calculated quantization hyperparameters caused by the weight data outliers during the post-model quantization process, and provides a method for improving the model quantization precision.

This invention discloses a distributed CAN data remote acquisition and monitoring system and method, including an acquisition-end device, a cloud server, and a client device. The acquisition-end device has a built-in unique hardware identifier, encapsulates CAN data frames using a 10-byte fixed header protocol, and encodes the channel identifier in the high 8 bits of the CAN identifier, achieving single-link multi-channel transmission. Before establishing a TCP connection, the acquisition-end device actively triggers an ARP request, employing a three-retry connection establishment method with a 3-second interval between each retry to solve the ARP resolution failure problem in direct connection scenarios. The cloud server establishes a long TCP connection with the acquisition-end device, receives the encapsulated data, performs device authentication, and forwards the data. The client device connects to the cloud server via WebSocket to monitor CAN data in real time. This invention achieves remote centralized monitoring of CAN devices, hardware anti-cloning, multi-channel single-link transmission, automatic reconnection after disconnection, and is compatible with existing CAN analysis software. It is suitable for scenarios such as remote vehicle diagnostics, charging pile monitoring, and BMS data acquisition.

The application discloses a kind of 8 bit S box construction method based on improved genetic algorithm, comprising the following steps: (1) by Logistic chaotic mapping and Tent chaotic mapping to form a kind of compound chaotic system, generates initialization population;(2) combined with the nonlinearity of S box, difference uniformity and strict avalanche criterion generates a multi-objective segmented weighted fitness function;(3) using the cross operation of guaranteeing S box bijectivity;(4) construct a reverse search method to search mutation point, and combined with hill climbing algorithm, random search method, generate based on 2N round search mutation operation, 2 point mutation point search is carried out in the first N rounds, 3 point mutation point search is used in the last N rounds, and a look-up table statistics method is further used to evaluate the property of optimized S box;(5) based on improved genetic algorithm constructs 8 bit password S box.The method of the application can generate 8 bit S box with excellent cryptographic properties based on improved genetic algorithm.

The invention discloses an efficient column bit feature recognition method based on byte alignment, and belongs to the technical field of data processing. According to the method, different byte alignment processing modes are adopted according to whether the frame length in a data stream is integral multiple of 8 bits or not: when the frame length is integral multiple of 8 bits, a structured data group is constructed, and byte-level sliding scanning and jumping access are performed based on a processing window so as to extract and identify a feature sequence; and when the frame length is not an integer multiple of 8 bits, combining a plurality of frames into a multiframe to realize byte alignment, and identifying by remapping original column bit features into a plurality of parallel short sequences. Complex bit-level shifting and mask calculation are avoided through the byte alignment operation, the data processing efficiency and the cache hit rate are remarkably improved, the CPU load is reduced, meanwhile, the method can flexibly adapt to column bit feature recognition requirements of different frame lengths and intervals, and the real-time processing requirement of high-speed data streams is effectively met.

This invention provides a dual-table 64-entry optimization method based on activation functions. It accelerates the table lookup logic through SIMD instructions, merges indexes, sets corresponding masks, obtains the correct table entries, and performs calculations. The method includes: Dual-table lookup: dividing table entries into positive and negative entries; input data greater than 0 uses positive entries, and input data less than 0 uses negative entries; S1, clipping the input data to a threshold range, making it a number between 0 and 63; S2, determining the range of input data for table entry selection; S3, original index calculation: original table entry index -63 to 63, each entry 8 bits, totaling 64 numbers; (a) Word index; (b) Byte index; (c) Entry merging; S4, determining the table entry index and using instructions to look up the table: if the number is positive, update the corresponding table entry value; if the number is negative, update the corresponding table entry value; S5, performing multiplication on the data obtained from the table entries to obtain the final result. A corresponding mask is designed to complete the dual-table 64-entry lookup function based on activation functions.

The invention discloses a method for transmitting a video signal containing an Alpha channel based on a high-definition multimedia interface, a receiving method and related electronic equipment, and relates to the technical field of digital video transmission. The method applied to the electronic equipment at the transmitting end comprises the following steps: acquiring to-be-transmitted video data with an RGB color signal and an Alpha channel signal; the RGB signal is converted into a YCbCr signal containing 8 bit Y, 4 bit Cb and 4 bit Cr; respectively filling YCbCr and Alpha channel signals into exclusive bearing intervals of the RGB three channels according to a preset mapping rule and a 24-bit width requirement, and generating to-be-sent data of which the single-frame total amount, the resolution and the time sequence are consistent with those of RGB4: 4: 4; and synchronous transmission of the video data to be transmitted is realized through a single interface. According to the scheme, the RGB color signals and the Alpha channel signals are synchronously transmitted through a single interface, and data integrity and transmission compliance are guaranteed.

The application provides a kind of adaptive deserializing method of SONY image sensor output data based on FPGA, for the serial data stream of synchronous image sensor, restores the RAW data of sensor acquisition.The adaptive deserializing method of data specifically includes the following steps: clock synchronization logic, serial-parallel conversion logic, synchronous alignment logic, decoding output logic.Clock synchronization logic is used to align the phase of source synchronous clock and data, so that clock sampling point is located in the center of data, to avoid collecting metastable signal;Serial-parallel conversion logic parallelizes one-bit input data into 8 bits, and the source synchronous clock is reduced to 1 / 4;Synchronous alignment logic finds the synchronization code in the data in real time, and if the match is successful, the corresponding parallel data is output to the decoding output logic;Decoding output logic obtains the corresponding field synchronization signal, line synchronization signal and valid data by comparing parallel data with the image line field valid synchronization word provided by SONY.

The application provides a hybrid structure analog-to-digital converter, belonging to the technical field of integrated circuit design, comprising a 7 bit first-order feed-forward incremental delta sigma ADC and an 8 bit single-stage cyclic ADC. The incremental delta sigma ADC adopts a first-order feed-forward structure, so that an input signal is directly fed to a comparator input end for comparison without passing through a modulator loop, thereby reducing the influence of non-ideal factors in the modulator loop on the input signal. In addition, the input end of the comparator is reset to a common mode level when the comparator is not working, so as to eliminate the influence of inconsistent voltage changes of two input ends of the comparator caused by incomplete matching of a layout wiring of the comparator input end on the circuit, and improve the overall signal-to-noise ratio of the circuit. By using the hybrid structure analog-to-digital converter provided by the application, the signal-to-noise ratio and the conversion speed are improved, and the conversion time is reduced without adding additional circuits.

Embodiments of the present disclosure relate to dynamic bit inversion for reduced overhead DC balanced coding. A computed polarity bit controls whether or not bits are inverted and is inserted in the data stream whenever DC balancing is triggered. Fixed overhead codes are commonly used to provide DC balance. However, one can do much better than a fixed overhead code by observing that many data streams are inherently DC balanced, and a random data stream does not need a correction to its disparity every byte. For example, a string of alternating 1s and 0s is naturally DC balanced. The dynamic bit inversion code has the property that overhead is inserted only when needed. For a string of alternating 1s and 0s there is no overhead. In an example, the overhead is about 4%, about ⅓ that of a fixed overhead 8 bit / 9 bit code with the same maximum output disparity.

The invention provides a memory module, a memory device and a server, and belongs to the technical field of chip packaging. The memory module comprises at least one memory chipset, the memory chipset comprises at least one sub-group, different sub-groups are connected with different memory channels, each sub-group is formed by stacking a plurality of memory chips, the bit width of the memory chips in each sub-group comprises a first bit width and a second bit width, the first bit width is N times of the second bit width, and the second bit width is N times of the first bit width. The second bit width is greater than or equal to 8 bits, and N is a positive integer greater than 1. Compared with the prior art, a memory chip with a larger bit width is adopted, and the number of memory chips borne by a memory channel is smaller, so that the number of CA lines of the memory channel is reduced, the CA signal load of a CPU is reduced, the CPU can directly drive a clock and CA signals to access the memory module, RCD relay driving is not needed, and the product cost can be reduced; and moreover, the memory module is more miniaturized and can be closer to the CPU, so that the signal quality is improved.

This application provides a communication method in which a network device, when needing to send a system message to a terminal device, obtains the system message, which includes a pdcch-ConfigSIB1 information element. This pdcch-ConfigSIB1 information element is used to indicate PRACH-related information before sending the system message to the terminal device. Specifically, the network device utilizes 8 bits in pdcch-ConfigSIB1 to indicate PRACH-related information, achieving effective use of the pdcch-ConfigSIB1 parameters and avoiding resource waste.

The invention relates to a message leakage detection method for an SHA-3 hash algorithm, and the method comprises the steps: firstly, randomly generating a message to be processed, taking the message as the input of the SHA-3 algorithm, employing an 8-bit random fault model, importing a random 8-bit fault in the last but one round, and outputting error output. An intermediate state value at a matching position and an intermediate state value at a fault import position are reversely deduced by enumerating 8 bits in a message, the range of an internal state is narrowed through the matching relation of the intermediate state values calculated by the two parts, and the fault import and analysis process is repeated for multiple times, so that a complete intermediate state value is restored; and then obtaining an originally input message. The method provided by the invention is easy to implement, high in speed and high in accuracy, and an important analysis basis is provided for the security research of the SHA-3 hash algorithm.

The invention discloses a storage and calculation integrated block multiplication and addition array, and relates to the technical field of storage and calculation integrated circuit structure design, and the storage and calculation integrated block multiplication and addition array comprises the following steps: carrying out one-time vector point integration to form a four-row storage and calculation array to complete partial multiplication and addition, and obtaining four partial multiplication and addition results PP0, PP1, PP3 and PP3; the one-bit calculation result of each partial multiplication and addition result PPI (i = 0, 1, 2, 3) is realized by adopting an accumulation mode; the one-bit calculation result of each partial multiply-add result PPi is calculated in a configurable clock beat; the partial multiply-accumulate results PPI (i = 0, 1, 2, 3) are multiplied by 20, 24, 24 and 28 respectively, namely, the partial multiply-accumulate results PPI (i = 0, 1, 2, 3) are shifted leftwards by 0, 4, 4 and 8 bits respectively, and four shifted partial multiply-accumulate results PPSi (i = 0, 1, 2, 3) are obtained; the four partial multiply-accumulate results PPSi (i = 0, 1, 2, 3) are subjected to additive operation in a clock beat through a full adder. According to the block multiplication and addition circuit, the vector dot product operation time of storage and calculation integrated implementation can be reduced by half, the effective rate is doubled, and storage and calculation integrated high-speed calculation is realized.

The application provides a partial discharge detection pattern data compression and decompression method and system, which comprises the following steps: obtaining a partial discharge pulse pattern, wherein the partial discharge pulse pattern comprises a plurality of pulse signals; during compression, one power frequency cycle is divided into a plurality of phase windows, the amplitude is represented in a logarithmic form, 7 bit positions are occupied, 1 bit position is used to represent whether the data after the amplitude data is the amplitude or the interval number, the interval number is used to replace the cycle number, and 8 bit positions are occupied; during decompression, the opposite idea is adopted to obtain decompression data.