8 results about "8-bit" patented technology

This invention discloses a distributed CAN data remote acquisition and monitoring system and method, including an acquisition-end device, a cloud server, and a client device. The acquisition-end device has a built-in unique hardware identifier, encapsulates CAN data frames using a 10-byte fixed header protocol, and encodes the channel identifier in the high 8 bits of the CAN identifier, achieving single-link multi-channel transmission. Before establishing a TCP connection, the acquisition-end device actively triggers an ARP request, employing a three-retry connection establishment method with a 3-second interval between each retry to solve the ARP resolution failure problem in direct connection scenarios. The cloud server establishes a long TCP connection with the acquisition-end device, receives the encapsulated data, performs device authentication, and forwards the data. The client device connects to the cloud server via WebSocket to monitor CAN data in real time. This invention achieves remote centralized monitoring of CAN devices, hardware anti-cloning, multi-channel single-link transmission, automatic reconnection after disconnection, and is compatible with existing CAN analysis software. It is suitable for scenarios such as remote vehicle diagnostics, charging pile monitoring, and BMS data acquisition.

This invention provides a dual-table 64-entry optimization method based on activation functions. It accelerates the table lookup logic through SIMD instructions, merges indexes, sets corresponding masks, obtains the correct table entries, and performs calculations. The method includes: Dual-table lookup: dividing table entries into positive and negative entries; input data greater than 0 uses positive entries, and input data less than 0 uses negative entries; S1, clipping the input data to a threshold range, making it a number between 0 and 63; S2, determining the range of input data for table entry selection; S3, original index calculation: original table entry index -63 to 63, each entry 8 bits, totaling 64 numbers; (a) Word index; (b) Byte index; (c) Entry merging; S4, determining the table entry index and using instructions to look up the table: if the number is positive, update the corresponding table entry value; if the number is negative, update the corresponding table entry value; S5, performing multiplication on the data obtained from the table entries to obtain the final result. A corresponding mask is designed to complete the dual-table 64-entry lookup function based on activation functions.

The application provides a hybrid structure analog-to-digital converter, belonging to the technical field of integrated circuit design, comprising a 7 bit first-order feed-forward incremental delta sigma ADC and an 8 bit single-stage cyclic ADC. The incremental delta sigma ADC adopts a first-order feed-forward structure, so that an input signal is directly fed to a comparator input end for comparison without passing through a modulator loop, thereby reducing the influence of non-ideal factors in the modulator loop on the input signal. In addition, the input end of the comparator is reset to a common mode level when the comparator is not working, so as to eliminate the influence of inconsistent voltage changes of two input ends of the comparator caused by incomplete matching of a layout wiring of the comparator input end on the circuit, and improve the overall signal-to-noise ratio of the circuit. By using the hybrid structure analog-to-digital converter provided by the application, the signal-to-noise ratio and the conversion speed are improved, and the conversion time is reduced without adding additional circuits.

This application provides a communication method in which a network device, when needing to send a system message to a terminal device, obtains the system message, which includes a pdcch-ConfigSIB1 information element. This pdcch-ConfigSIB1 information element is used to indicate PRACH-related information before sending the system message to the terminal device. Specifically, the network device utilizes 8 bits in pdcch-ConfigSIB1 to indicate PRACH-related information, achieving effective use of the pdcch-ConfigSIB1 parameters and avoiding resource waste.

This invention provides a multichannel energy spectrum data communication method based on parity bits. The multichannel energy spectrum detection device sends energy spectrum data to a host computer in real time. During transmission, the 16-bit binary data is divided into two parts: the lower 8 bits are sent as a single byte using either odd or even parity, and the higher 8 bits are sent as a single byte using either even or odd parity. The host computer receives the energy spectrum data from the multichannel energy spectrum detection device and verifies it until all data is received. This invention utilizes serial communication principles, encoding the energy spectrum data uploaded in real time by the multichannel energy spectrum detection device using parity bits as flags. After receiving the data, the host computer judges and reassembles the data based on whether the parity check is incorrect, and the order of correct and incorrect parity checks, thus parsing out the corresponding energy spectrum data. This method is particularly suitable for measuring radioactive samples with high nuclear particle energy resolution and high activity.

The application discloses an arithmetic operation unit of independent carry register, and belongs to the technical field of computer processor design. A 64-base column structure is adopted, 8 bits of each column are equal to 6 data bits plus 2 carry bits, and 8 columns are simultaneously operated through a single 64-bit adder. The carry is stored in the independent register with the high 2 bits in the column, the carry register in the column embeds the carry in the data column, and the serial carry chain is eliminated. The parallel adder array uses 8 6-bit adders to work simultaneously, and there is no cascading dependence. A carry delay propagation circuit supports a configurable threshold, and the carry is temporarily not carried out during the operation process, and is processed in batches when needed. Compared with the traditional serial carry chain, the delay of the application is reduced by 8 times, the complexity is reduced from O(64) to O(8), the number of transistors is reduced by 77%, from 2300 to 532, the power consumption is reduced by 87.5%, the gate circuit flip is reduced from 64 levels to 8 levels, and parallel operation is supported throughout the process. The application is realized by using Verilog HDL, can be adapted to FPGA and ASIC, can integrate the existing CPU architecture, does not need to change the instruction set, the compiler is automatically optimized, and the program does not need to be adjusted.

This invention provides a single-table 64-entry optimization method based on activation functions. The method accelerates the table lookup logic using SIMD instructions, merges indexes, sets corresponding masks, obtains the correct table entries, and then performs calculations. The method includes: S1: Input data is determined to be positive numbers, and only positive entries are used; S2: Input data is clipped to a threshold range, making it a number between 0 and 63; S3: Original index calculation: Original entry indexes are 0-63, each entry is 8 bits, for a total of 64 numbers; S4: Determine the entry index and use instructions to look up the table; S5: Multiply the data obtained from the entries to obtain the final result. By using SIMD instructions and designing corresponding masks, the single-table 64-entry lookup function based on activation functions is completed.

This invention provides an optimization method for a single 128-entry table based on activation functions. The method accelerates the table lookup logic using SIMD instructions, merges indexes, sets corresponding masks, obtains the correct table entries, and then performs calculations. The method includes: Single-table lookup: Input data is determined to be positive, using only positive entries; Pos_dy: Positive entry 0, a total of 128 entries, each entry is 8 bits, totaling 512 bits, which can be stored in a register; Pos_y0: Positive entry 1, a total of 128 entries, each entry is 8 bits, totaling 512 bits, which can be stored in a register; S1: Input data is cilpped to a threshold range, making it a number between 0 and 127; S2: Original index calculation; S3: Determine the table entry index and use instructions to look up the table; S4: Separate the high and low 4 bits to obtain effective bit width data; S5: Multiply the data obtained from the table entries to obtain the final result. By using SIMD instructions and designing corresponding masks, the table lookup function based on a single 128-entry table based on activation functions is completed.