82 results about "Address bus" patented technology

The invention discloses a memory signal integrity enhancing system based on multi-dimensional parameter self-adaption, and belongs to the technical field of signal transmission. The system comprises a multi-dimensional signal acquisition module, a multi-dimensional parameter analysis module, a self-adaptive adjustment module, a memory signal optimization module and a feedback monitoring module, the multi-dimensional signal acquisition module is combined with multi-dimensional parameter analysis, signals of a data bus, an address bus and a control bus are synchronously acquired, a dynamic adjustment strategy is generated according to a model, and the self-adaptive adjustment module and the memory signal optimization module are optimized according to the dynamic adjustment strategy. Different optimization means are adopted for different parameter types, a customized optimization system with one parameter and one scheme is formed, it is ensured that the optimized target signal is optimal in amplitude stability, time sequence accuracy, anti-noise capacity and impedance matching degree, the feedback monitoring module is combined with the multi-dimensional parameter analysis module, and the multi-dimensional parameter analysis module is combined with the feedback monitoring module. And through full-dimension index monitoring and dynamic calibration, the continuous adaptability of the system to the running state of the memory and the long-term stability of signal integrity are guaranteed.

The invention discloses an embedded SoC-level real-time monitoring and analyzing device. The embedded SoC-level real-time monitoring and analyzing device is composed of a bus comparator, a system event counter and a control register set. The bus comparator collects access signals of an address bus, a data bus and an instruction bus in real time, compares the access signals with a preset matching rule, generates a trigger signal for driving the event state register to record and output an interrupt signal or a debugging signal during matching, and takes the trigger signal as an input event of the system event counter; the system event counter monitors various events generated in the operation process, and when the monitoring result is equal to a preset reference value, a trigger signal is generated; and the control register group configures the matching condition of the bus comparator, sets the counting mode of the system event counter, and reads the comparison state, the event counting result and related monitoring information through the bus interface. According to the method, a configurable event capture mechanism and multiple counting modes are introduced in a hardware level, so that the dependence on software debugging is reduced, and the real-time performance of monitoring and analysis is improved.

A method and a device is provided for utilizing unused valid (V) bits residing on a previous command to transmit additional activate information to a memory device. Additional activate information may be transmitted to the memory device without increasing the tRCD time, or increasing the command / address (CA) bus pins, or adding additional circuit area, thereby reducing the impact on the performance of the memory device.

The invention relates to the technical field of steam turbine safety monitoring, in particular to a method and system for arranging an OC bus of a TSI system, and the method comprises the steps: dividing the OC bus into three types of independent main channels, namely a data collection bus, a communication bus and an address and working condition bus, in a physical layout layer; a grounding design of separating an analog ground from a digital ground and a resistance buffer circuit are arranged in a matched manner to form a multi-layer anti-interference system, and different buses are arranged in a layered manner; the hardware redundancy layer constructs a double-inter-phase hard wiring redundancy channel by depending on an independent channel reserved by physical layout, a fault switching mechanism is formed by combining a relay and a control node, and the redundancy channel is physically isolated from a main channel; and the intelligent algorithm layer constructs a state space according to an address bus and a power channel state in the physical layout layer, and performs iterative optimization on an algorithm decision through a dynamic allocation model in combination with a fault feedback signal of the hardware redundancy layer. According to the scheme, the OC bus is arranged by adopting a three-layer progressive structure, so that the transmission reliability is improved.

A semiconductor system may include a command address bus, a data bus, a management bus, a memory module including multiple memories and coupled to the command address bus, data bus and management bus, a memory controller configured to control, through the command address bus and the data bus, the memory module to perform a write operation and a read operation and a baseboard management controller configured to perform, through the management bus, a management operation of managing the multiple memories.

The invention relates to the technical field of integrated circuits and provides a command address bus training method and training device. Through optimization design of test signals and overall optimization design of the training method, influences of factors such as device characteristics, path delay, wiring layout and signal quality are fully considered, comprehensive analysis of signal integrity and power supply integrity is considered, training accuracy and signal stability are improved, and the method is suitable for being used in a large-scale industrial production line. The method is beneficial to meeting the requirements of a high-performance memory in the aspects of state alignment and synchronization, supports higher data transmission rate and higher working frequency, and is beneficial to meeting the requirements of applications such as a data center, a high-performance server, an artificial intelligence infrastructure and the like on data transmission and high-speed interconnection.

The invention provides a command processing circuit, a command processing method and a PIM device. The command processing circuit comprises a PIM command identification module which is electrically connected with a command address bus of the PIM device and is configured to receive a command signal through the command address bus and judge the type of the currently received command signal; if it is judged that the currently received command signal is a DRAM conventional command, the command signal is sent to a conventional command processing module; if it is judged that the currently received command signal is a PIM related command, the command signal is sent to a PIM command processing module; the PIM command processing module is electrically connected with the PIM command identification module and is configured to receive a PIM related command, decode the PIM related command and perform corresponding operation according to a decoding result; and the conventional command processing module is electrically connected with the PIM command identification module and is configured to receive the DRAM conventional command and decode the DRAM conventional command. The method is at least beneficial to avoiding mode switching and improving system performance.

A memory device (e.g., a high-bandwidth (HBM) memory device) that includes a memory die having multiple pseudo channels per channel is disclosed. The memory die can include first memory banks associated with a first channel (e.g., having a first command address (CA) bus) and a first pseudo channel (e.g., having a first data (DQ) bus) and second memory banks associated with the first channel and a second pseudo channel (e.g., having a second DQ bus). Operations can be performed at the first memory banks or the second memory banks in response to a command received through the first CA bus. The operations can cause data to be returned to circuitry that routes the data to an interface to the first DQ bus or an interface to the second DQ bus based on whether the data resulted from operations at the first memory banks or the second memory banks.

The invention discloses a photon NPU (Network Processing Unit) embedded neural network processor, which comprises (1) an electromagnetic wave bus, (2) a multiply-add module, (3) an activation function module, (4) a two-dimensional data operation module and (5) a decompression module, the NPU embedded neural network processor is divided into independent modules with different sizes according to functions and purposes, each functional module is provided with an independent input and output end, and each functional module is provided with an independent input end and an independent output end. All input and output ends are connected with a transmitting end and a receiving end of an electromagnetic wave bus, the bandwidth advantage of electromagnetic waves is utilized, a processing terminal is further formed through interconnection, and the electromagnetic wave bus is used for replacing a control bus, a data bus, an address bus and all replaceable circuits to transmit needed control signals, data and data addresses. An electromagnetic wave bus is used as a carrier of data needing to be processed, a data address and control signal transmission, and a photon (NPU) embedded neural network processor processes and outputs a result after passing through a radio frequency chip and a baseband chip.

A memory device includes a first address mapper and a first memory macro connected to the first address mapper. The first address mapper is configured to identify an input address that does not fall within a first address range mapped to the first memory macro, and in response to identifying that the input address does not fall within the first address range mapped to the first memory macro, prevent access to the first memory macro and set an address bus of the first memory macro to a value that depends on whether the input address is lower or higher than the first address range.

The application relates to the technical field of integrated circuits and provides a command address bus training method and a training device. Through optimization design of a test signal and overall optimization design of a training method, the influence of factors such as device characteristics, path delay, wire layout and signal quality is fully considered, and comprehensive analysis of signal integrity and power integrity is considered, so that the accuracy of training and signal stability are improved, the demand of high-performance memory in state alignment and synchronization is met, a higher data transmission rate and a higher working frequency are supported, and the demand of data centers, high-performance servers, artificial intelligence infrastructure and the like on data transmission and high-speed interconnection is met.

The utility model discloses a DSP (Digital Signal Processor) and FPGA (Field Programmable Gate Array)-based rapid control power supply system architecture, which comprises a bottom plate, an empty chip substrate, an FPGA control system and a DSP control system, the empty chip substrate is arranged on the bottom plate, the FPGA control system and the DSP control system are arranged on the bottom plate or the empty chip substrate, and the DSP control system is arranged on the FPGA control system and the DSP control system. The FPGA control system interacts with the DSP control system through an XINTF bus, an XA address bus and an XD data bus, and the DSP control system comprises a DSP logic control output conversion circuit; according to the utility model, the FPGA is used to carry out reverse solution and filtering on a large amount of data so as to share DSP storage and operation space resources, and the DSP is used to carry out rapid logic operation so as to meet the requirement of a system for rapidly controlling a DC / DC conversion switch tube, so that the stability and rapidity of the rapid power supply DC / DC converter are improved; the problems of stable operation of the rapid power supply, rapid data processing and rapid main power logic control are solved.

This invention discloses a delay device and delay control method suitable for multi-memory testing systems, relating to the field of memory testing technology. It includes a first delay register and a second delay register. The first delay register is connected to a data driver on an electronic pin in the multi-memory testing system and is used to adjust the output timing of several data signals in a test vector according to a first delay logic, to compensate for path difference delays between the command / address bus and data bus of several memories under test. The second delay register is connected to a data receiver on an electronic pin in the multi-memory testing system and is used to adjust the timing of the data receiver receiving several expected data signals according to a second delay logic, to compensate for the internal delays of several memories under test. This invention can achieve delay compensation for all signals in the test vector, ensuring effective testing of multiple memories and improving test accuracy.

A method for rapid data exchange between real-time and time-sharing systems. Different cores on a single processor work together to share hardware resources equally, improving overall system performance and efficiency. This not only meets real-time requirements and a large number of application computing requirements, but also reduces investment costs. A simple shared memory and signal notification mechanism is used between multi-core systems to increase data transmission bandwidth and efficiency, while also taking into account real-time and large data volume requirements. Real-time data processing and high-bandwidth data transmission are met. Through address bus communication, FPGAs can process large amounts of data in parallel and in real time, accelerating the data transmission process. The number of memory copies from kernel mode to user mode is reduced, eliminating unnecessary duplication during data transmission, thereby improving performance and reducing resource usage. A high-speed, large-capacity, real-time data interaction method is designed for the entire process, from data reception to processor processing, operating from the same memory area from start to finish.

A memory device (e.g., a high-bandwidth (HBM) memory device) that includes a memory die having multiple pseudo channels per channel is disclosed. The memory die can include first memory banks associated with a first channel (e.g., having a first command address (CA) bus) and a first pseudo channel (e.g., having a first data (DQ) bus) and second memory banks associated with the first channel and a second pseudo channel (e.g., having a second DQ bus). Operations can be performed at the first memory banks or the second memory banks in response to a command received through the first CA bus. The operations can cause data to be returned to circuitry that routes the data to an interface to the first DQ bus or an interface to the second DQ bus based on whether the data resulted from operations at the first memory banks or the second memory banks.

Provided in the present disclosure are a command processing circuit, a command processing method, and a PIM apparatus. The command processing circuit comprises: a PIM command identification module, which is electrically connected to a command address bus of a PIM apparatus and is configured to receive a command signal by means of the command address bus, determine the type of the currently received command signal, send, when it is determined that the currently received command signal is a conventional DRAM command, the command signal to a conventional command processing module, and send, when it is determined that the currently received command signal is a PIM-related command, the command signal to a PIM command processing module; the PIM command processing module, which is electrically connected to the PIM command identification module and is configured to receive the PIM-related command, decode the PIM-related command, and perform a corresponding operation on the basis of a decoding result; and the conventional command processing module, which is electrically connected to the PIM command identification module and is configured to receive the conventional DRAM command and decode the conventional DRAM command. The present disclosure is at least conducive to avoiding mode switching and improving system performance.

A memory device includes a first address mapper and a first memory macro connected to the first address mapper. The first address mapper is configured to determine if an input address falls within a first address range mapped to the first memory macro, in response to determining that the input address falls within the first address range mapped to the first memory macro, access the first memory macro with an address on an address bus of the first memory macro mapped from the input address, and in response to determining that the input address does not fall within the first address range mapped to the first memory macro, prevent access to the first memory macro and set the address bus of the first memory macro to a value that depends on whether the input address is lower or higher than the first address range.

A method and a device is provided for utilizing unused valid (V) bits residing on a previous command to transmit additional activate information to a memory device. Additional activate information may be transmitted to the memory device without increasing the tRCD time, or increasing the command / address (CA) bus pins, or adding additional circuit area, thereby reducing the impact on the performance of the memory device.

Apparatuses and methods are disclosed. The apparatus includes a bus master including processing circuitry and a bus interface. The processing circuitry is configured to control operation of the bus master such that the bus master transmits a first address to a bus slave through a bus in a first mode and to transmit a second address having a same first length as the first address to the bus slave through the bus in a second mode. The bus interface is configured to generate the second address such that the second address includes a plurality of short addresses corresponding to a plurality of special function registers of the bus slave, respectively, in the second mode.

Memory devices and systems with improved command / address bus utilization are disclosed herein. In one embodiment, a memory device includes a plurality of external command / address terminals and a command decoder. The plurality of external command / address terminals are configured to receive a command as a corresponding plurality of command / address bits. A first set of command / address bits indicates a read or write operation. A second set of command / address bits indicates whether to perform a refresh operation. The memory device is configured to perform a read or write operation to a portion of a memory array in response to the first set of command / address bits. The memory device is further configured to perform the refresh operation to refresh at least one memory bank of the memory array in response to the second set of command / address bits when the second set of command / address bits indicates that the refresh operation should be performed.

The invention provides a cascading type addressing method and a feeder screen, the method is applied to a communication system composed of multiple paths of unit devices, and the method comprises the steps that in the communication system, an address cascading bus is constructed in a bus mode, and a communication part is in common ground; each unit device is connected in series to an address cascade bus to form a cascade system; the address bus output side of the last-stage unit device is grounded to form an effective loop; each unit device acquires the voltage drop value of the resistor of the cascade bus connected in series with the address, and calculates the unique address of the unit device in the cascade system according to the relationship among the voltage drop value, the total input voltage of the system and the total number of the unit devices. According to the invention, high-efficiency, stable, reliable and low-cost addressing of the feeder screen feeder module can be realized, the operation and maintenance are simple, and the addressing workload is extremely low.

A memory device includes a first plurality of volatile memories, a non-volatile memory, and a controller coupled to the non-volatile memory and including a first controller output. The memory device further includes a registering clock driver (RCD) including a first RCD output, and a first multiplexer including a first mux input coupled to the first RCD output, a second mux input coupled to the first controller output, and a first mux output coupled to the first plurality of volatile memories. The first multiplexer can be configured to provide command / address signals from one of the RCD and the controller to the first plurality of volatile memories.

This invention discloses an embedded SoC-level real-time monitoring and analysis device, comprising a bus comparator, a system event counter, and a control register set. The bus comparator acquires access signals from the address bus, data bus, and instruction bus in real time and compares them with preset matching rules. Upon matching, it generates a trigger signal to drive the event status register to record, output interrupt signals, or debug signals, and serves as the input event for the system event counter. The system event counter monitors various events generated during operation, and generates a trigger signal when the monitoring result equals a preset reference value. The control register set configures the matching conditions of the bus comparator, sets the counting mode of the system event counter, and reads the comparison status, event counting results, and related monitoring information through the bus interface. This invention introduces a configurable event capture mechanism and multiple counting modes at the hardware level, reducing reliance on software debugging and improving the real-time performance of monitoring and analysis.

A semiconductor system may include a semiconductor apparatus; a controller configured to control the semiconductor apparatus through a command address bus and a data bus, and a baseboard management controller configured to control the semiconductor apparatus through a management bus. The semiconductor apparatus includes a plurality of memories each configured to store data under the control of the controller, configured to output data stored in the semiconductor apparatus, and configured to perform an on-die termination (ODT) setting operation based on an identifier (ID) that is assigned by the baseboard management controller.

The invention provides a multi-chip interconnection system and a decoding method thereof, the multi-chip interconnection system comprises a plurality of chips, each chip comprises a processor, an address resolution module, a bus matrix, an address recovery module, an interface A and an interface B, the plurality of chips are connected end to end to form an annular interconnection structure; comprising the following steps: a host sends a request; based on the chip number, the address parsing module parses the global address into a local address; based on the local address, the bus matrix sends the request to a corresponding slave; based on the chip number, the address recovery module recovers a local address to a global address; and the interface A or the interface B sends the request to an adjacent chip. The method has the beneficial effects that the logic is simple, the area is small, and the optimal access path can be obtained.

The invention provides a permanent magnet synchronous motor high-speed position acquisition system based on an FPGA and an SSI. The technical problem that the control requirement of a high-speed permanent magnet synchronous motor cannot be met is solved. Comprising a DSP which provides a reference clock, a control signal, an address bus and a data bus communicating with an FPGA through an XINTF interface; the FPGA is communicated with the DSP, forms a clock interface and a data interface which are communicated with the absolute value encoder, and provides a data transmission process between a system clock and the DSP and an acquisition and processing process of position data of the absolute value encoder; the differential signal transceiver forms a differential transmission channel between the FPGA and the absolute value encoder, outputs a system clock and receives a serial signal; and the absolute value encoder is used for collecting position information of the permanent magnet synchronous motor rotor and outputting a position signal through an SSI interface. And parallel processing of data acquisition and transmission based on clock synchronization is realized. And the control requirement of the high-speed permanent magnet synchronous motor is met.

An integrated circuit (IC) includes a memory array with M rows of N storage elements that has an N-bit wide parallel input and output, and a 1-bit wide array scan input and output. A memory built-in self-test (MBIST) circuit is connected to the memory array to generate test addresses and N-bit wide test data. Functional circuitry with a functional address bus and N-bit wide functional data path is linked to the memory array. Control circuitry enables a serial test mode for shifting data through the storage elements, a MBIST mode for test data access, and a normal operation mode for functional data access. This IC design offers versatile memory testing and operational capabilities.

This disclosure describes aspects of memory die interconnections to physical layer interfaces (PHYs) that may enable expanded channel bus width and improved signal integrity (SI). In aspects, a memory die is operably coupled to a first PHY via a command-and-address (CA) bus and data input / output (DQ) bus of the first PHY and to a second PHY via a chip select (CS) bus of the second PHY. The second PHY may provide a CS signal to the memory die, and the first PHY can perform a training procedure via CA signaling or DQ signaling. The training procedure may improve SI between the memory die and the PHYs. Additionally, a memory die may be interconnected to different PHYs to expand a channel bus width. Thus, by interconnecting memory dies to one or more PHYs as described herein, improved SI and expanded channel bus width can be achieved.

A method and device are provided in which at least a first portion of a write address bus comprising a write address from a write command is received at a first decoder of a memory device, wherein the memory device comprises a set of memory cell rows corresponding to a subset of write addresses from write commands. A first clock signal is received at a first primary integrated clock gating (ICG) cell of the memory device. The first primary ICG cell is configured to provide a first gated clock signal to a first subcircuit of the memory device, including a first non-empty proper subset of the memory cell rows, wherein the first non-empty proper subset includes a plurality of memory cell rows. The first decoder enables or disables the first primary ICG cell, when the write address is in the subset of the write addresses, based on whether the write address corresponds to any memory cell row in the first non-empty proper subset of the memory cell rows, disabling the first primary ICG cell when the write address corresponds to a memory cell row in the set of the memory cell rows but not in the first non-empty proper subset.

The invention relates to the technical field of integrated circuit design, and particularly discloses a device and method for accelerating high-precision ADC data operation, and the device comprises a bus which comprises an address bus and a data bus; the hardware algorithm accelerator comprises an address mapping logic module, an input and output mapping module, a register module and an algorithm acceleration core function module; the address mapping logic module is used for splitting an address access request from an address bus into a read-write access command of the register module and a parameter and operation command of the algorithm acceleration core function module; the register module includes a configuration register, a plurality of operand registers, and a configuration register. According to the method and the device, the address access request from the address bus is divided into two parts, meanwhile, calculation input and output are selected through address mapping, a calculation result can be directly imported into a newly-initiated calculation input end, read-write of a processor to an operand register can be reduced, and the calculation efficiency is improved.