51 results about "Address bus" patented technology

A semiconductor system may include a command address bus, a data bus, a management bus, a memory module including multiple memories and coupled to the command address bus, data bus and management bus, a memory controller configured to control, through the command address bus and the data bus, the memory module to perform a write operation and a read operation and a baseboard management controller configured to perform, through the management bus, a management operation of managing the multiple memories.

The invention provides a command processing circuit, a command processing method and a PIM device. The command processing circuit comprises a PIM command identification module which is electrically connected with a command address bus of the PIM device and is configured to receive a command signal through the command address bus and judge the type of the currently received command signal; if it is judged that the currently received command signal is a DRAM conventional command, the command signal is sent to a conventional command processing module; if it is judged that the currently received command signal is a PIM related command, the command signal is sent to a PIM command processing module; the PIM command processing module is electrically connected with the PIM command identification module and is configured to receive a PIM related command, decode the PIM related command and perform corresponding operation according to a decoding result; and the conventional command processing module is electrically connected with the PIM command identification module and is configured to receive the DRAM conventional command and decode the DRAM conventional command. The method is at least beneficial to avoiding mode switching and improving system performance.

The invention discloses a photon NPU (Network Processing Unit) embedded neural network processor, which comprises (1) an electromagnetic wave bus, (2) a multiply-add module, (3) an activation function module, (4) a two-dimensional data operation module and (5) a decompression module, the NPU embedded neural network processor is divided into independent modules with different sizes according to functions and purposes, each functional module is provided with an independent input and output end, and each functional module is provided with an independent input end and an independent output end. All input and output ends are connected with a transmitting end and a receiving end of an electromagnetic wave bus, the bandwidth advantage of electromagnetic waves is utilized, a processing terminal is further formed through interconnection, and the electromagnetic wave bus is used for replacing a control bus, a data bus, an address bus and all replaceable circuits to transmit needed control signals, data and data addresses. An electromagnetic wave bus is used as a carrier of data needing to be processed, a data address and control signal transmission, and a photon (NPU) embedded neural network processor processes and outputs a result after passing through a radio frequency chip and a baseband chip.

A memory device includes a first address mapper and a first memory macro connected to the first address mapper. The first address mapper is configured to identify an input address that does not fall within a first address range mapped to the first memory macro, and in response to identifying that the input address does not fall within the first address range mapped to the first memory macro, prevent access to the first memory macro and set an address bus of the first memory macro to a value that depends on whether the input address is lower or higher than the first address range.

The application relates to the technical field of integrated circuits and provides a command address bus training method and a training device. Through optimization design of a test signal and overall optimization design of a training method, the influence of factors such as device characteristics, path delay, wire layout and signal quality is fully considered, and comprehensive analysis of signal integrity and power integrity is considered, so that the accuracy of training and signal stability are improved, the demand of high-performance memory in state alignment and synchronization is met, a higher data transmission rate and a higher working frequency are supported, and the demand of data centers, high-performance servers, artificial intelligence infrastructure and the like on data transmission and high-speed interconnection is met.

This invention discloses a delay device and delay control method suitable for multi-memory testing systems, relating to the field of memory testing technology. It includes a first delay register and a second delay register. The first delay register is connected to a data driver on an electronic pin in the multi-memory testing system and is used to adjust the output timing of several data signals in a test vector according to a first delay logic, to compensate for path difference delays between the command / address bus and data bus of several memories under test. The second delay register is connected to a data receiver on an electronic pin in the multi-memory testing system and is used to adjust the timing of the data receiver receiving several expected data signals according to a second delay logic, to compensate for the internal delays of several memories under test. This invention can achieve delay compensation for all signals in the test vector, ensuring effective testing of multiple memories and improving test accuracy.

A memory device (e.g., a high-bandwidth (HBM) memory device) that includes a memory die having multiple pseudo channels per channel is disclosed. The memory die can include first memory banks associated with a first channel (e.g., having a first command address (CA) bus) and a first pseudo channel (e.g., having a first data (DQ) bus) and second memory banks associated with the first channel and a second pseudo channel (e.g., having a second DQ bus). Operations can be performed at the first memory banks or the second memory banks in response to a command received through the first CA bus. The operations can cause data to be returned to circuitry that routes the data to an interface to the first DQ bus or an interface to the second DQ bus based on whether the data resulted from operations at the first memory banks or the second memory banks.

Provided in the present disclosure are a command processing circuit, a command processing method, and a PIM apparatus. The command processing circuit comprises: a PIM command identification module, which is electrically connected to a command address bus of a PIM apparatus and is configured to receive a command signal by means of the command address bus, determine the type of the currently received command signal, send, when it is determined that the currently received command signal is a conventional DRAM command, the command signal to a conventional command processing module, and send, when it is determined that the currently received command signal is a PIM-related command, the command signal to a PIM command processing module; the PIM command processing module, which is electrically connected to the PIM command identification module and is configured to receive the PIM-related command, decode the PIM-related command, and perform a corresponding operation on the basis of a decoding result; and the conventional command processing module, which is electrically connected to the PIM command identification module and is configured to receive the conventional DRAM command and decode the conventional DRAM command. The present disclosure is at least conducive to avoiding mode switching and improving system performance.

A method and a device is provided for utilizing unused valid (V) bits residing on a previous command to transmit additional activate information to a memory device. Additional activate information may be transmitted to the memory device without increasing the tRCD time, or increasing the command / address (CA) bus pins, or adding additional circuit area, thereby reducing the impact on the performance of the memory device.

Apparatuses and methods are disclosed. The apparatus includes a bus master including processing circuitry and a bus interface. The processing circuitry is configured to control operation of the bus master such that the bus master transmits a first address to a bus slave through a bus in a first mode and to transmit a second address having a same first length as the first address to the bus slave through the bus in a second mode. The bus interface is configured to generate the second address such that the second address includes a plurality of short addresses corresponding to a plurality of special function registers of the bus slave, respectively, in the second mode.

Memory devices and systems with improved command / address bus utilization are disclosed herein. In one embodiment, a memory device includes a plurality of external command / address terminals and a command decoder. The plurality of external command / address terminals are configured to receive a command as a corresponding plurality of command / address bits. A first set of command / address bits indicates a read or write operation. A second set of command / address bits indicates whether to perform a refresh operation. The memory device is configured to perform a read or write operation to a portion of a memory array in response to the first set of command / address bits. The memory device is further configured to perform the refresh operation to refresh at least one memory bank of the memory array in response to the second set of command / address bits when the second set of command / address bits indicates that the refresh operation should be performed.

The invention provides a cascading type addressing method and a feeder screen, the method is applied to a communication system composed of multiple paths of unit devices, and the method comprises the steps that in the communication system, an address cascading bus is constructed in a bus mode, and a communication part is in common ground; each unit device is connected in series to an address cascade bus to form a cascade system; the address bus output side of the last-stage unit device is grounded to form an effective loop; each unit device acquires the voltage drop value of the resistor of the cascade bus connected in series with the address, and calculates the unique address of the unit device in the cascade system according to the relationship among the voltage drop value, the total input voltage of the system and the total number of the unit devices. According to the invention, high-efficiency, stable, reliable and low-cost addressing of the feeder screen feeder module can be realized, the operation and maintenance are simple, and the addressing workload is extremely low.

A memory device includes a first plurality of volatile memories, a non-volatile memory, and a controller coupled to the non-volatile memory and including a first controller output. The memory device further includes a registering clock driver (RCD) including a first RCD output, and a first multiplexer including a first mux input coupled to the first RCD output, a second mux input coupled to the first controller output, and a first mux output coupled to the first plurality of volatile memories. The first multiplexer can be configured to provide command / address signals from one of the RCD and the controller to the first plurality of volatile memories.

This invention discloses an embedded SoC-level real-time monitoring and analysis device, comprising a bus comparator, a system event counter, and a control register set. The bus comparator acquires access signals from the address bus, data bus, and instruction bus in real time and compares them with preset matching rules. Upon matching, it generates a trigger signal to drive the event status register to record, output interrupt signals, or debug signals, and serves as the input event for the system event counter. The system event counter monitors various events generated during operation, and generates a trigger signal when the monitoring result equals a preset reference value. The control register set configures the matching conditions of the bus comparator, sets the counting mode of the system event counter, and reads the comparison status, event counting results, and related monitoring information through the bus interface. This invention introduces a configurable event capture mechanism and multiple counting modes at the hardware level, reducing reliance on software debugging and improving the real-time performance of monitoring and analysis.

A semiconductor system may include a semiconductor apparatus; a controller configured to control the semiconductor apparatus through a command address bus and a data bus, and a baseboard management controller configured to control the semiconductor apparatus through a management bus. The semiconductor apparatus includes a plurality of memories each configured to store data under the control of the controller, configured to output data stored in the semiconductor apparatus, and configured to perform an on-die termination (ODT) setting operation based on an identifier (ID) that is assigned by the baseboard management controller.

The invention provides a multi-chip interconnection system and a decoding method thereof, the multi-chip interconnection system comprises a plurality of chips, each chip comprises a processor, an address resolution module, a bus matrix, an address recovery module, an interface A and an interface B, the plurality of chips are connected end to end to form an annular interconnection structure; comprising the following steps: a host sends a request; based on the chip number, the address parsing module parses the global address into a local address; based on the local address, the bus matrix sends the request to a corresponding slave; based on the chip number, the address recovery module recovers a local address to a global address; and the interface A or the interface B sends the request to an adjacent chip. The method has the beneficial effects that the logic is simple, the area is small, and the optimal access path can be obtained.

The invention provides a permanent magnet synchronous motor high-speed position acquisition system based on an FPGA and an SSI. The technical problem that the control requirement of a high-speed permanent magnet synchronous motor cannot be met is solved. Comprising a DSP which provides a reference clock, a control signal, an address bus and a data bus communicating with an FPGA through an XINTF interface; the FPGA is communicated with the DSP, forms a clock interface and a data interface which are communicated with the absolute value encoder, and provides a data transmission process between a system clock and the DSP and an acquisition and processing process of position data of the absolute value encoder; the differential signal transceiver forms a differential transmission channel between the FPGA and the absolute value encoder, outputs a system clock and receives a serial signal; and the absolute value encoder is used for collecting position information of the permanent magnet synchronous motor rotor and outputting a position signal through an SSI interface. And parallel processing of data acquisition and transmission based on clock synchronization is realized. And the control requirement of the high-speed permanent magnet synchronous motor is met.

An integrated circuit (IC) includes a memory array with M rows of N storage elements that has an N-bit wide parallel input and output, and a 1-bit wide array scan input and output. A memory built-in self-test (MBIST) circuit is connected to the memory array to generate test addresses and N-bit wide test data. Functional circuitry with a functional address bus and N-bit wide functional data path is linked to the memory array. Control circuitry enables a serial test mode for shifting data through the storage elements, a MBIST mode for test data access, and a normal operation mode for functional data access. This IC design offers versatile memory testing and operational capabilities.

This disclosure describes aspects of memory die interconnections to physical layer interfaces (PHYs) that may enable expanded channel bus width and improved signal integrity (SI). In aspects, a memory die is operably coupled to a first PHY via a command-and-address (CA) bus and data input / output (DQ) bus of the first PHY and to a second PHY via a chip select (CS) bus of the second PHY. The second PHY may provide a CS signal to the memory die, and the first PHY can perform a training procedure via CA signaling or DQ signaling. The training procedure may improve SI between the memory die and the PHYs. Additionally, a memory die may be interconnected to different PHYs to expand a channel bus width. Thus, by interconnecting memory dies to one or more PHYs as described herein, improved SI and expanded channel bus width can be achieved.

The invention relates to the technical field of integrated circuit design, and particularly discloses a device and method for accelerating high-precision ADC data operation, and the device comprises a bus which comprises an address bus and a data bus; the hardware algorithm accelerator comprises an address mapping logic module, an input and output mapping module, a register module and an algorithm acceleration core function module; the address mapping logic module is used for splitting an address access request from an address bus into a read-write access command of the register module and a parameter and operation command of the algorithm acceleration core function module; the register module includes a configuration register, a plurality of operand registers, and a configuration register. According to the method and the device, the address access request from the address bus is divided into two parts, meanwhile, calculation input and output are selected through address mapping, a calculation result can be directly imported into a newly-initiated calculation input end, read-write of a processor to an operand register can be reduced, and the calculation efficiency is improved.

Disclosed herein is memory device that includes a printed circuit board (PCB) and a plurality of dynamic random-access memory (DRAM) devices arranged on the PCB and logically divided into four pseudo-channels. A shared command / address (C / A) bus of the device is configured to transmit command signals to all four pseudo-channels and a set of multiplexers on the device are controllable to selectively couple data signals between the four pseudo-channels and a memory controller. A control interface of the device is configured to interleave data burst transactions of the data signals across the four pseudo-channels, wherein a burst of the data burst transactions is distributed across two groups, each group comprising two of the four pseudo-channels operating in parallel.

A method can include: receiving a plurality of consecutive commands on a unidirectional command-address (CA) bus input of a discrete nonvolatile memory (NVM) device, the commands being synchronous with a timing clock; for each received command, determining if the command is an express read (NVR) command, if a command is determined to be an NVR command, determining if a next consecutive command is an NVR command, wherein consecutive NVR commands form an NVR command sequence; in response to the no more than the NVR command sequence, accessing read data stored in NVM cells of the NVM device; and driving the read data on parallel data input / outputs (I / Os) of the NVM device in a burst of data values, the data values of the burst being output in synchronism with rising and falling edges of the timing clock; wherein the CA bus input includes a plurality of parallel CA signal inputs. Related memory devices and systems are also disclosed.

The embodiment of the invention discloses an address comparison circuit, a semiconductor memory and electronic equipment, and relates to the technical field of semiconductors. Address comparison delay can be reduced. Comprising a plurality of address matching units, each address matching unit comprises a plurality of switch circuits, the input end of each switch circuit receives a one-bit one-hot coding address signal, and the control end of each switch circuit receives a one-bit pre-stored fault address signal; the output ends of the plurality of switching circuits are connected in parallel so as to generate a matching result signal of each address matching unit; when a pre-stored fault address signal corresponding to a target switch circuit corresponding to an effective level bit in the one-hot coded address signal is an effective level, indicating that the address is matched; and the matching logic unit is respectively connected with the output ends of the address matching units, and outputs an address comparison result based on the matching result signals output by the address matching units. The present invention adapts to a memory scenario configured with an address bus input signal mode as multi-group one-hot coding.

The application discloses a residual magnetism control system of a satellite-borne computer, and realizes basic functions of the satellite-borne computer by setting a power management module, a processor module, an analog switch switching module, a digital quantity output and analog quantity module, a communication module, a heating driving module, a remote control terminal module and a GNSS module. When all the modules are arranged on a PCB board, the loop area of an address bus and a data bus in a system bus is not more than 8 square centimeters during PCB wiring, the power supply lines and ground lines of all the modules are arranged on a plane layer, the residual magnetism and magnetic induction of the satellite-borne computer are reduced, and the magnetic change of the satellite-borne computer under various working conditions is reduced.

The invention discloses a DDR adapter plate, a life detection method thereof and a storage medium, relates to the technical field of testing, and discloses the DDR adapter plate which comprises a golden finger, an EEPROM, a slot and an IIC address conversion circuit. The EEPROM is electrically connected with the IIC address conversion circuit, the IIC address conversion circuit is electrically connected with an address bus in the IIC bus, one end of the address bus is electrically connected with an IIC address interface of the golden finger, and the other end of the address bus is electrically connected with an IIC address interface of the slot; the IIC address conversion circuit is used for converting an IIC address of an address bus to obtain a target IIC address, and writing the target IIC address into the EEPROM; and the EEPROM is used for storing the number of times of plugging and unplugging corresponding to the adapter plate and the number of times of remaining plugging and unplugging. According to the invention, accurate detection of the service life of the DDR adapter plate is realized, and the test efficiency and quality of the SODIMM are improved.

Embodiments herein describe link stress patterns to ensure command address bus integrity. In an example, a memory controller asserts a link stress pattern of bits on command address (CA) links of a CA bus of a dynamic random-access memory (DRAM) device, while the DRAM device is in a pre-operating state in which the DRAM device does not recognize memory access commands and in which a CA bus parity circuit of the DRAM device is enabled, where the link stress pattern of bits extends over multiple clock cycles of the DRAM device. The memory controller also monitors an error output of the DRAM device for parity errors, while asserting the link stress pattern of bits on the CA links.

The invention relates to the technical field of neural network middleware underlying scheduling, and discloses a neural network adaptive architecture system for business intelligent decision making. Comprising a feature extraction module for extracting a dimension feature identifier of an operator to be executed, a kernel mapping engine for matching a target operator kernel according to the dimension feature identifier, a scheduling execution unit for modifying a bottom layer function pointer according to the target operator kernel and executing a chain type entry pre-binding regulation, and a control module for controlling the scheduling execution unit to execute the chain type entry pre-binding regulation. According to the method, logic jump between operators is converted into hardware-level addressing through space-time overlapping of a calculation period and an addressing period, the scheduling arbitration overhead at the operator boundary is eliminated, the zero pause feeling of an instruction supply end is guaranteed, and the instruction sequence is pushed to the instruction high-speed cache through the address bus idle period when prediction fails. And the energy efficiency ratio and response certainty limit of the system are improved.

This disclosure describes systems, methods, and devices related to group addressed BUs. A device may encode a traffic indication map (TIM) element with information associated with a plurality of access points (APs) in a multiple basic service set identifications (BSSIDs) set and one or more APs of the AP MLD. The device may cause to send a beacon frame comprising the TIM element to one or more station devices (STAs).

The invention provides a data transmission method and device, a data transmission controller and a storage medium, and relates to the technical field of data transmission. The method comprises the following steps: acquiring a preset number of addressing information through an addressing bus; analyzing each piece of addressing information in sequence, and acquiring and sending a data block corresponding to each piece of addressing information through a data bus according to a source address and a destination address of each piece of addressing information; according to each piece of response information received by the response bus, each piece of addressing information is discarded, new addressing information is obtained through the addressing bus, and each piece of response information is a response after each data block is sent. The data transmission efficiency can be improved.

This application discloses a method, apparatus, and phase-change memory (PCM) chip read / write monitoring system, belonging to the field of semiconductor technology. The method includes receiving read / write commands for the PCM chip; monitoring whether an anomaly occurs during the execution of the read / write commands; and if an anomaly is detected, outputting an alarm signal through an error indication signal line configured on the PCM chip. The error indication signal line is independent of the data bus, command bus, and address bus of the PCM chip, and the alarm signal is used to distinguish whether the anomaly is a write command anomaly or a read command anomaly. This application can distinguish between read / write anomaly types, thereby enabling monitoring of the internal command execution status of the chip and improving the chip's debuggability, reliability, and system-level fault location efficiency.