115 results about "Address bus" patented technology

The present application relates to the technical field of power generation, power transformation and power distribution, and provides an MLVDS bus system and a control method therefor. The MLVDS bus system comprises an MLVDS data bus, a transceiving control arbitration line, an address bus, and a processor assembly; the processor assembly comprises two or more processor modules; each processor module comprises a processor unit, an MLVDS driving unit, a state transceiving unit, and an address bus processing unit; the MLVDS data bus is connected to the processor unit by means of the MLVDS driving unit; the transceiving control arbitration line is connected to the processor unit by means of the state transceiving unit; and the address bus is connected to the processor unit by means of the address bus processing unit. The MLVDS bus system can achieve the technical effect of high-speed and low-power-consumption MLVDS bus data communication.

The invention discloses a memory signal integrity enhancing system based on multi-dimensional parameter self-adaption, and belongs to the technical field of signal transmission. The system comprises a multi-dimensional signal acquisition module, a multi-dimensional parameter analysis module, a self-adaptive adjustment module, a memory signal optimization module and a feedback monitoring module, the multi-dimensional signal acquisition module is combined with multi-dimensional parameter analysis, signals of a data bus, an address bus and a control bus are synchronously acquired, a dynamic adjustment strategy is generated according to a model, and the self-adaptive adjustment module and the memory signal optimization module are optimized according to the dynamic adjustment strategy. Different optimization means are adopted for different parameter types, a customized optimization system with one parameter and one scheme is formed, it is ensured that the optimized target signal is optimal in amplitude stability, time sequence accuracy, anti-noise capacity and impedance matching degree, the feedback monitoring module is combined with the multi-dimensional parameter analysis module, and the multi-dimensional parameter analysis module is combined with the feedback monitoring module. And through full-dimension index monitoring and dynamic calibration, the continuous adaptability of the system to the running state of the memory and the long-term stability of signal integrity are guaranteed.

The invention discloses a memory management system, method and device, a medium and a product, and relates to the technical field of computers, a processor is used for performing hardware initialization through a basic input and output system by reading hardware component information of each hardware component, therefore, different memory spaces can be allocated to each hardware component according to the obtained address bus width supported by each hardware component under the condition that the fact that any preset bus link does not comprise a switch is determined according to the hardware component information; the first hardware component may be made assignable to a first memory space that supports a first address bus width. And for the second hardware component capable of expanding the address range, the second hardware component is allocated to the second memory space supporting the second address bus width, so that each hardware component can be ensured to have an independent address range, the utilization rate of memory resources is optimized, and the system stability is improved.

The invention discloses an embedded SoC-level real-time monitoring and analyzing device. The embedded SoC-level real-time monitoring and analyzing device is composed of a bus comparator, a system event counter and a control register set. The bus comparator collects access signals of an address bus, a data bus and an instruction bus in real time, compares the access signals with a preset matching rule, generates a trigger signal for driving the event state register to record and output an interrupt signal or a debugging signal during matching, and takes the trigger signal as an input event of the system event counter; the system event counter monitors various events generated in the operation process, and when the monitoring result is equal to a preset reference value, a trigger signal is generated; and the control register group configures the matching condition of the bus comparator, sets the counting mode of the system event counter, and reads the comparison state, the event counting result and related monitoring information through the bus interface. According to the method, a configurable event capture mechanism and multiple counting modes are introduced in a hardware level, so that the dependence on software debugging is reduced, and the real-time performance of monitoring and analysis is improved.

The invention provides an MLVDS bus system and a control method thereof, and relates to the technical field of power generation, power transformation and power distribution. The MLVDS bus system comprises an MLVDS data bus, a transceiving control arbitration line, an address bus and a processor assembly, the processor assembly comprises two or more processor modules, and each processor module comprises a processor unit, an MLVDS driving unit, a state transceiving unit and an address bus processing unit; the MLVDS data bus is connected with the processor unit through the MLVDS driving unit; the transceiving control arbitration line is connected with the processor unit through the state transceiving unit; and the address bus is connected with the processor unit through the address bus processing unit. The MLVDS bus system can achieve the technical effect of MLVDS bus data communication with high speed and low power consumption.

A method and a device is provided for utilizing unused valid (V) bits residing on a previous command to transmit additional activate information to a memory device. Additional activate information may be transmitted to the memory device without increasing the tRCD time, or increasing the command / address (CA) bus pins, or adding additional circuit area, thereby reducing the impact on the performance of the memory device.

The invention relates to the technical field of steam turbine safety monitoring, in particular to a method and system for arranging an OC bus of a TSI system, and the method comprises the steps: dividing the OC bus into three types of independent main channels, namely a data collection bus, a communication bus and an address and working condition bus, in a physical layout layer; a grounding design of separating an analog ground from a digital ground and a resistance buffer circuit are arranged in a matched manner to form a multi-layer anti-interference system, and different buses are arranged in a layered manner; the hardware redundancy layer constructs a double-inter-phase hard wiring redundancy channel by depending on an independent channel reserved by physical layout, a fault switching mechanism is formed by combining a relay and a control node, and the redundancy channel is physically isolated from a main channel; and the intelligent algorithm layer constructs a state space according to an address bus and a power channel state in the physical layout layer, and performs iterative optimization on an algorithm decision through a dynamic allocation model in combination with a fault feedback signal of the hardware redundancy layer. According to the scheme, the OC bus is arranged by adopting a three-layer progressive structure, so that the transmission reliability is improved.

A semiconductor system may include a command address bus, a data bus, a management bus, a memory module including multiple memories and coupled to the command address bus, data bus and management bus, a memory controller configured to control, through the command address bus and the data bus, the memory module to perform a write operation and a read operation and a baseboard management controller configured to perform, through the management bus, a management operation of managing the multiple memories.

The invention relates to the technical field of integrated circuits and provides a command address bus training method and training device. Through optimization design of test signals and overall optimization design of the training method, influences of factors such as device characteristics, path delay, wiring layout and signal quality are fully considered, comprehensive analysis of signal integrity and power supply integrity is considered, training accuracy and signal stability are improved, and the method is suitable for being used in a large-scale industrial production line. The method is beneficial to meeting the requirements of a high-performance memory in the aspects of state alignment and synchronization, supports higher data transmission rate and higher working frequency, and is beneficial to meeting the requirements of applications such as a data center, a high-performance server, an artificial intelligence infrastructure and the like on data transmission and high-speed interconnection.

The invention provides a command processing circuit, a command processing method and a PIM device. The command processing circuit comprises a PIM command identification module which is electrically connected with a command address bus of the PIM device and is configured to receive a command signal through the command address bus and judge the type of the currently received command signal; if it is judged that the currently received command signal is a DRAM conventional command, the command signal is sent to a conventional command processing module; if it is judged that the currently received command signal is a PIM related command, the command signal is sent to a PIM command processing module; the PIM command processing module is electrically connected with the PIM command identification module and is configured to receive a PIM related command, decode the PIM related command and perform corresponding operation according to a decoding result; and the conventional command processing module is electrically connected with the PIM command identification module and is configured to receive the DRAM conventional command and decode the DRAM conventional command. The method is at least beneficial to avoiding mode switching and improving system performance.

A memory device (e.g., a high-bandwidth (HBM) memory device) that includes a memory die having multiple pseudo channels per channel is disclosed. The memory die can include first memory banks associated with a first channel (e.g., having a first command address (CA) bus) and a first pseudo channel (e.g., having a first data (DQ) bus) and second memory banks associated with the first channel and a second pseudo channel (e.g., having a second DQ bus). Operations can be performed at the first memory banks or the second memory banks in response to a command received through the first CA bus. The operations can cause data to be returned to circuitry that routes the data to an interface to the first DQ bus or an interface to the second DQ bus based on whether the data resulted from operations at the first memory banks or the second memory banks.

This document describes technology for a runtime memory system that utilizes unpredictable multiplexing of memory bus lines. The technology dynamically reassigns data and / or address bus connections between a processor and its runtime memory during warm reset operations. The bus line assignments are made through a multiplexing mechanism—for example, data bus line 01 from the processor may be reassigned to link with bus line 23 at the runtime memory system interface. When a warm reset occurs, the physical mapping of memory locations changes due to this bus line reassignment. The system maintains standard memory operations while implementing this dynamic bus line configuration. Malicious software relying upon memory-resident exploit becomes inoperable after warm reset due to the changed physical memory topology created by the bus line reassignment process.

The invention discloses a photon NPU (Network Processing Unit) embedded neural network processor, which comprises (1) an electromagnetic wave bus, (2) a multiply-add module, (3) an activation function module, (4) a two-dimensional data operation module and (5) a decompression module, the NPU embedded neural network processor is divided into independent modules with different sizes according to functions and purposes, each functional module is provided with an independent input and output end, and each functional module is provided with an independent input end and an independent output end. All input and output ends are connected with a transmitting end and a receiving end of an electromagnetic wave bus, the bandwidth advantage of electromagnetic waves is utilized, a processing terminal is further formed through interconnection, and the electromagnetic wave bus is used for replacing a control bus, a data bus, an address bus and all replaceable circuits to transmit needed control signals, data and data addresses. An electromagnetic wave bus is used as a carrier of data needing to be processed, a data address and control signal transmission, and a photon (NPU) embedded neural network processor processes and outputs a result after passing through a radio frequency chip and a baseband chip.

A memory device includes a first address mapper and a first memory macro connected to the first address mapper. The first address mapper is configured to identify an input address that does not fall within a first address range mapped to the first memory macro, and in response to identifying that the input address does not fall within the first address range mapped to the first memory macro, prevent access to the first memory macro and set an address bus of the first memory macro to a value that depends on whether the input address is lower or higher than the first address range.

The application relates to the technical field of integrated circuits and provides a command address bus training method and a training device. Through optimization design of a test signal and overall optimization design of a training method, the influence of factors such as device characteristics, path delay, wire layout and signal quality is fully considered, and comprehensive analysis of signal integrity and power integrity is considered, so that the accuracy of training and signal stability are improved, the demand of high-performance memory in state alignment and synchronization is met, a higher data transmission rate and a higher working frequency are supported, and the demand of data centers, high-performance servers, artificial intelligence infrastructure and the like on data transmission and high-speed interconnection is met.

The utility model discloses a DSP (Digital Signal Processor) and FPGA (Field Programmable Gate Array)-based rapid control power supply system architecture, which comprises a bottom plate, an empty chip substrate, an FPGA control system and a DSP control system, the empty chip substrate is arranged on the bottom plate, the FPGA control system and the DSP control system are arranged on the bottom plate or the empty chip substrate, and the DSP control system is arranged on the FPGA control system and the DSP control system. The FPGA control system interacts with the DSP control system through an XINTF bus, an XA address bus and an XD data bus, and the DSP control system comprises a DSP logic control output conversion circuit; according to the utility model, the FPGA is used to carry out reverse solution and filtering on a large amount of data so as to share DSP storage and operation space resources, and the DSP is used to carry out rapid logic operation so as to meet the requirement of a system for rapidly controlling a DC / DC conversion switch tube, so that the stability and rapidity of the rapid power supply DC / DC converter are improved; the problems of stable operation of the rapid power supply, rapid data processing and rapid main power logic control are solved.

This invention discloses a delay device and delay control method suitable for multi-memory testing systems, relating to the field of memory testing technology. It includes a first delay register and a second delay register. The first delay register is connected to a data driver on an electronic pin in the multi-memory testing system and is used to adjust the output timing of several data signals in a test vector according to a first delay logic, to compensate for path difference delays between the command / address bus and data bus of several memories under test. The second delay register is connected to a data receiver on an electronic pin in the multi-memory testing system and is used to adjust the timing of the data receiver receiving several expected data signals according to a second delay logic, to compensate for the internal delays of several memories under test. This invention can achieve delay compensation for all signals in the test vector, ensuring effective testing of multiple memories and improving test accuracy.

The invention provides a state switching simulation system and method for a wind turbine generator, and relates to the field of analog simulation. The system comprises a main control module, a test module, a human-computer interaction interface and a shared address bus, the main control module is used for sending a starting instruction to the test module and entering a starting mode, and the test module responds to the starting instruction to simulate the starting process of the wind turbine generator and shares starting simulation parameters with the main control module in real time; the main control module is used for sending a grid-connected instruction to the test module and entering a grid-connected mode after monitoring that the starting simulation parameters meet grid-connected conditions, and the test module responds to the grid-connected instruction to simulate the grid-connected process of the wind turbine generator and shares grid-connected simulation parameters with the main control module in real time; the main control module is used for sending a shutdown instruction to the test module and entering a shutdown mode after monitoring that the grid-connected simulation parameters meet shutdown conditions, and the test module responds to the shutdown instruction to simulate the shutdown process of the wind turbine generator and shares shutdown simulation parameters with the main control module in real time.

A method for rapid data exchange between real-time and time-sharing systems. Different cores on a single processor work together to share hardware resources equally, improving overall system performance and efficiency. This not only meets real-time requirements and a large number of application computing requirements, but also reduces investment costs. A simple shared memory and signal notification mechanism is used between multi-core systems to increase data transmission bandwidth and efficiency, while also taking into account real-time and large data volume requirements. Real-time data processing and high-bandwidth data transmission are met. Through address bus communication, FPGAs can process large amounts of data in parallel and in real time, accelerating the data transmission process. The number of memory copies from kernel mode to user mode is reduced, eliminating unnecessary duplication during data transmission, thereby improving performance and reducing resource usage. A high-speed, large-capacity, real-time data interaction method is designed for the entire process, from data reception to processor processing, operating from the same memory area from start to finish.

A memory device (e.g., a high-bandwidth (HBM) memory device) that includes a memory die having multiple pseudo channels per channel is disclosed. The memory die can include first memory banks associated with a first channel (e.g., having a first command address (CA) bus) and a first pseudo channel (e.g., having a first data (DQ) bus) and second memory banks associated with the first channel and a second pseudo channel (e.g., having a second DQ bus). Operations can be performed at the first memory banks or the second memory banks in response to a command received through the first CA bus. The operations can cause data to be returned to circuitry that routes the data to an interface to the first DQ bus or an interface to the second DQ bus based on whether the data resulted from operations at the first memory banks or the second memory banks.

Provided in the present disclosure are a command processing circuit, a command processing method, and a PIM apparatus. The command processing circuit comprises: a PIM command identification module, which is electrically connected to a command address bus of a PIM apparatus and is configured to receive a command signal by means of the command address bus, determine the type of the currently received command signal, send, when it is determined that the currently received command signal is a conventional DRAM command, the command signal to a conventional command processing module, and send, when it is determined that the currently received command signal is a PIM-related command, the command signal to a PIM command processing module; the PIM command processing module, which is electrically connected to the PIM command identification module and is configured to receive the PIM-related command, decode the PIM-related command, and perform a corresponding operation on the basis of a decoding result; and the conventional command processing module, which is electrically connected to the PIM command identification module and is configured to receive the conventional DRAM command and decode the conventional DRAM command. The present disclosure is at least conducive to avoiding mode switching and improving system performance.

A memory device includes a first address mapper and a first memory macro connected to the first address mapper. The first address mapper is configured to determine if an input address falls within a first address range mapped to the first memory macro, in response to determining that the input address falls within the first address range mapped to the first memory macro, access the first memory macro with an address on an address bus of the first memory macro mapped from the input address, and in response to determining that the input address does not fall within the first address range mapped to the first memory macro, prevent access to the first memory macro and set the address bus of the first memory macro to a value that depends on whether the input address is lower or higher than the first address range.

Apparatuses and methods for shared row and column address buses. Row and column addresses are distributed along separate respective global buses in a central logic region of a memory. The row and column addresses are coupled through a shared address bus from the central logic region to a bank logic region. For example the row address may be provided along the shared address bus at a first time and the column address may be provided along the shared address bus at a second time.

The present application discloses a memory management system, method, device, medium and product, which relate to the field of computer technology. The processor is used to read the hardware component information of each hardware component during the process of hardware initialization through the basic input and output system, so that when it is determined that any preset bus link does not include a switch according to the hardware component information, different memory spaces can be allocated to each hardware component according to the address bus width supported by each hardware component obtained, so that the first hardware component can be allocated to the first memory space supporting the first address bus width. For the second hardware component whose address range can be expanded, the second hardware component is allocated to the second memory space supporting the second address bus width, so as to ensure that each hardware component has an independent address range, thereby optimizing memory resource utilization and improving system stability.

A method and a device is provided for utilizing unused valid (V) bits residing on a previous command to transmit additional activate information to a memory device. Additional activate information may be transmitted to the memory device without increasing the tRCD time, or increasing the command / address (CA) bus pins, or adding additional circuit area, thereby reducing the impact on the performance of the memory device.

Apparatuses and methods are disclosed. The apparatus includes a bus master including processing circuitry and a bus interface. The processing circuitry is configured to control operation of the bus master such that the bus master transmits a first address to a bus slave through a bus in a first mode and to transmit a second address having a same first length as the first address to the bus slave through the bus in a second mode. The bus interface is configured to generate the second address such that the second address includes a plurality of short addresses corresponding to a plurality of special function registers of the bus slave, respectively, in the second mode.

Detailed herein are embodiments utilizing a cryptographically authenticated address bus (CAAB) protection that uses an intelligent memory design to prevent attacks on the address bus without detection and eliminate the memory bus as an observability surface for an attacker to do access pattern analysis. Embodiments detailed herein describe an intelligent memory module which has cryptographic capabilities. In some embodiments, a memory controller and an intelligent memory module exchange a key and using this key, the address (on the address bus) is encrypted and integrity protected using authenticated counter mode encryption. The memory controller on receiving a read or a write request encrypts the address (e.g., using pre-generated encrypted counters to minimize cryptographic overheads). A message authentication code (MAC) also gets generated along with the encrypted address to be able to detect modification to the encrypted address.

Memory devices and systems with improved command / address bus utilization are disclosed herein. In one embodiment, a memory device includes a plurality of external command / address terminals and a command decoder. The plurality of external command / address terminals are configured to receive a command as a corresponding plurality of command / address bits. A first set of command / address bits indicates a read or write operation. A second set of command / address bits indicates whether to perform a refresh operation. The memory device is configured to perform a read or write operation to a portion of a memory array in response to the first set of command / address bits. The memory device is further configured to perform the refresh operation to refresh at least one memory bank of the memory array in response to the second set of command / address bits when the second set of command / address bits indicates that the refresh operation should be performed.

The invention provides a cascading type addressing method and a feeder screen, the method is applied to a communication system composed of multiple paths of unit devices, and the method comprises the steps that in the communication system, an address cascading bus is constructed in a bus mode, and a communication part is in common ground; each unit device is connected in series to an address cascade bus to form a cascade system; the address bus output side of the last-stage unit device is grounded to form an effective loop; each unit device acquires the voltage drop value of the resistor of the cascade bus connected in series with the address, and calculates the unique address of the unit device in the cascade system according to the relationship among the voltage drop value, the total input voltage of the system and the total number of the unit devices. According to the invention, high-efficiency, stable, reliable and low-cost addressing of the feeder screen feeder module can be realized, the operation and maintenance are simple, and the addressing workload is extremely low.

Implementations described herein relate to command address fault detection using a parity bit. A memory device may receive, from a host device via a command address (CA) bus and during a unit interval, a set of CA bits associated with a CA word. The memory device may receive, from the host device via a parity bus and during the unit interval, a first parity bit that is based on the set of CA bits and a parity generation process. The memory device may generate a second parity bit based on the set of CA bits and the parity generation process. The memory device may compare the first parity bit and the second parity bit. The memory device may selectively transmit an alert signal to the host device based on a result of comparing the first parity bit and the second parity bit.