51 results about "Memory map" patented technology

The embodiment of the invention provides a model reasoning data caching method and device for a caching system and a storage medium, and the method comprises the steps: configuring a first virtual address mapped to a high-performance memory of the caching system for a data caching pool, and generating a first reasoning data according to the data size of the first reasoning data generated by a target reasoning model; determining a target memory space of the high-performance memory mapped by the first virtual address, and enabling the data volume of the first reasoning data to be in direct proportion to the memory space volume of the target memory space mapped by the first virtual address, thereby creating a dynamic data buffer pool of the target reasoning model, and then caching the first reasoning data based on the target memory space corresponding to the dynamic data buffer pool, thereby realizing on-demand allocation of the high-performance memory in the cache system, and improving the utilization efficiency and the use flexibility of the high-performance memory in the cache system.

The invention relates to the technical field of computers, discloses a heterogeneous computing low-delay communication method and system, and aims to solve the problem of high delay caused by high communication protocol overhead, lack of dynamic scheduling collaboration, memory migration redundancy and non-uniform cross-node communication abstraction in existing heterogeneous computing. The method comprises the following steps: receiving a task scheduling request and analyzing a task dependency graph; tasks are dynamically allocated based on node loads and link states; rDMA, NVLink or PCIe straight-through protocols are adaptively selected according to node types to establish communication channels; zero-copy data exchange is realized through a shared memory mapping buffer area; hardware timestamps are utilized to synchronize feedback delays with PTP to optimize scheduling. The system comprises a heterogeneous computing node cluster, a unified communication scheduling controller, a low-delay communication protocol stack, a shared memory mapping buffer area and a communication delay sensing task distributor. According to the scheme, the communication delay is remarkably reduced, and the throughput and the task execution efficiency are improved.

The invention discloses a data transmission optimization method and system in hybrid deployment of a real-time system and a non-real-time system based on Jailhouse, belongs to the technical field of data transmission, and solves the problems of low data transmission efficiency, high copy overhead, lack of universality of interfaces and the like in an existing system. Comprising the steps that a hybrid deployment platform including a real-time system and a non-real-time system is built on a multi-core processor platform, and the hybrid deployment platform runs in an isolation environment of a Jailhouse partition manager; building an abstract transmission interface layer as a unified channel for accessing a shared memory by a real-time system and a non-real-time system; establishing a plurality of shared memory channels in the abstract transmission interface layer and scheduling according to the priority of tasks; establishing a data transmission path, and compressing a memory copy operation into one time by adopting a memory mapping multiplexing technology and a DMA (Direct Memory Access) collaboration mechanism; and a cache consistency maintenance technology is adopted, so that the data consistency is ensured, and the optimization of data transmission is completed. The method is suitable for application scenes such as industrial automation, intelligent connected automobiles and edge calculation.

The invention discloses an outdoor unmanned aerial vehicle visual language navigation method based on a multi-modal memory map, and aims to solve the problems of memory discretization, insufficient space connectivity and overhigh calculation load caused by dependence on global mapping in an unstructured environment in the prior art. The method comprises the following steps: extracting semantic features from an aerial view image by using a visual language model, and constructing memory nodes in combination with a local truncated symbol distance field; establishing topological connection containing six-degree-of-freedom constraints according to a visual common-view relationship and spatial trafficability among the nodes, and performing hierarchical organization on semantic landmarks in the nodes to form a multi-modal memory map; a semantic weight is calculated based on a cross attention mechanism, and a three-dimensional semantic navigation potential field is constructed by fusing geometric accessibility probability; and determining a navigation target according to the potential field distribution, executing path search in a topology layer, and performing obstacle avoidance and track generation in a measurement layer. According to the invention, the long-voyage autonomous visual language navigation of the unmanned aerial vehicle is realized under the condition that the computing resources are limited.

The invention provides a PXE network card initialization method and device compatible with 64-bit addressing and a medium, and relates to the technical field of network card initialization, and the method comprises the steps: discovering a network card device; reading a PCI configuration space of the network card equipment, obtaining information of an extended ROM base address register, and mapping a network card Option ROM to a memory shadow region; when the access of the memory mapping input and output mode fails, the initialization code performs read-write operation on the hardware register through a self-defined capability structure in a PCI configuration space of the network card equipment; based on the successfully accessed hardware register, network card hardware initialization is completed, and a PXE protocol stack structural body is established in a memory; registering system firmware as PXE starting equipment, and entering a protocol interaction stage with a PXE server; according to the invention, smooth development of a subsequent network boot flow is guaranteed, and the deployment success rate and the system stability in a large-scale batch installation scene are improved.

Provided are a memory device and a method for dynamically mapping address thereof, in which the memory device includes a memory including a plurality of memory regions, an address register in which at least one of a memory device different from the memory device or a host stores a device address for accessing the memory, and an address translator configured to receive a first interrupt, and in response to the first interrupt, convert a physical address of the memory mapped to the device address.

Methods are provided comprising: mapping a portion of a local primary memory to an address space of a virtualization instance at a client device, wherein the address space is addressable by a processor of the client device, and wherein the virtualization instance is executed via the processor of the client device; mapping a first portion of external memory to the address space, wherein the external memory is memory that is external to the client device but treated as primary memory at the client device, and wherein a second portion of the external memory is not in any address space addressable by the processor of the client device; providing a performance indication data structure indicating a performance difference between the portion of the local primary memory mapped to the address space and the first portion of external memory mapped to the address space; and causing data to migrate between the external memory and the local primary memory based on the performance indication data structure by the virtualization instance, wherein the data is caused to migrate by the virtualization instance and / or a logic configured to operate with the virtualization instance.

A computer-implemented method for transforming a library from a source operating system to a target operating system is disclosed. Thereby, the source operating system includes a source ABI; the target operating system comprises a target ABI; the target ABI is different from the binary interface of the source application, and the library is realized by the source object file; the source object file conforms to the source application binary interface and includes at least a source memory image, source symbol information, and source relocation information, where the source relocation information is free of relative relocation information. The method further includes creating a target memory image, the target memory image conforming to the target application binary interface and derived from the source memory image; enriching the target memory image with fixed-length eye mark information; and writing the target memory image into the target object file.

The application provides a one-to-many service discovery and dynamic loading method and system in a Hongmeng application, comprising: AST analysis of ArkTS source code by a TypeScript compiler API in a compilation period, identification of a class marked by a @HMModularService decorator, extraction of a service path, a class name, a module name, an instantiation mode and a unique identifier as metadata, generation of a module-level mapping table and merging into a global mapping table, and establishment of a one-to-many mapping relationship from the service path to an implementation item array; loading of the global mapping table into a memory Map structure in a running period, receiving of a service query request from a calling party, searching for a corresponding implementation item according to the service path and supporting of filtering according to an identifier; dynamic loading of a target HSP module by calling a napi_load_module_with_info native interface, obtaining of a constructor from an export object and creation of an instance, and caching of a singleton mode implementation item.

To provide a system for preventing a forged gaming chip from being used.SOLUTION: The gaming chip reader may read one or more gaming chips from the antenna. The drawer can be read from the gaming chip. The version may be identified from the drawer. The memory map may be decrypted and the decrypted memory map may be used to decrypt the data describing the gaming chips from the drawer. The data describing the gaming chips may be matched against a gaming chip inventory data set.SELECTED DRAWING: Figure 2

An integrated circuit for translating and reverse-translating the address included in a memory request is disclosed. The integrated circuit may first comprise a processor, a first boundary function, a second boundary function, and a component device. The processor is configured to transmit a memory request to a target module over a bus of the integrated circuit. The memory request requests access to one or more memory mapped resources and the memory request includes a physical address. The first boundary function is configured to translate the physical address to a relative address which operates in or applies to a different address space than an address space that the physical address operates in or applies to. The second boundary function is configured to translate the relative address to the physical address. The device is configured utilize the physical address transmitted by the second boundary function.

An ultrasound diagnostic apparatus includes a processor. The processor is configured to acquire an evaluation value for each item of ultrasound image data sequentially acquired based on transmission and reception of ultrasound, sequentially update and display an evaluation graph showing the evaluation value in a case where ultrasound images based on the ultrasound image data sequentially acquired are displayed sequentially, and display a memory map for the ultrasound image data sequentially acquired based on the transmission and the reception of the ultrasound. The memory map indicates a storage location in a memory where each item of the ultrasound image data is stored.

The invention discloses a timing ringing method and device for campus broadcast, terminal equipment and a storage medium, and belongs to the technical field of computer application and data processing, and the method comprises the steps: storing an allocation rule in a first memory map container; if the ringing scheme is marked to be enabled, storing the ringing scheme in a second memory map container; if the ringing scheme is marked to be forbidden, storing the ringing scheme in a third memory map container; if the execution time of the ringing task in the second memory map container is in the starting time interval, storing the ringing task in a fourth memory map container; if the execution time of the ringing task in the third memory map container is in the forbidden time interval, storing the ringing task in a fifth memory map container; and performing data cleaning on the fourth memory map container, generating a control instruction, and issuing the control instruction to the campus broadcast terminal. Therefore, through the implementation of the invention, the suitability of the campus broadcast timing ringing task in a complex scene can be improved through intelligent and automatic scheduling.

The embodiment of the invention provides a vehicle attitude optimization method, a vehicle and a product. The method comprises the following steps: determining perception information obtained when a vehicle is positioned and an initial pose in a memory map; the perception information comprises at least one of semantic information and feature information, and the semantic information is obtained by detecting a panoramic image when the vehicle is positioned; the feature information is obtained by performing feature extraction on a target azimuth image used for detecting a target azimuth when the vehicle is positioned; projecting the perception information to the memory map according to the initial pose in the memory map to obtain perception projection information; and according to a re-projection error between the perception projection information and prior information, the initial pose of the vehicle is optimized, the optimized pose of the vehicle is determined, and the prior information represents real information matched with the perception information in the memory map. The method is used for achieving the effect of improving the positioning accuracy.

The invention discloses a navigation path planning method, computer equipment, a computer readable storage medium, a computer program product and a mobile platform. The navigation path planning method comprises the following steps: acquiring a current position and a destination position of a mobile platform; determining a corresponding memory map according to the current position and the destination position of the mobile platform; searching a global topological path at least according to the lane-level topological map to determine a global topological path from the current position to the destination position; and searching a local geometric path at least according to the global topological path and the road traffic information collected by the mobile platform in real time so as to determine the local geometric path. According to the method, the road smoothness from the current position of the vehicle to the destination position is ensured through global topological path search, and finer local navigation planning is realized through local geometric path search based on vehicle online sensing information.

Systems and methods for dynamic repartitioning of physical memory address mapping involve relocating data stored at one or more physical memory locations of one or more memory devices to another memory device or mass storage device, repartitioning one or more corresponding physical memory maps to include new mappings between physical memory addresses and physical memory locations of the one or more memory devices, then loading the relocated data back onto the one or more memory devices at physical memory locations determined by the new physical address mapping. Such dynamic repartitioning of the physical memory address mapping does not require a processing system to be rebooted and has various applications in connection with interleaving reconfiguration and error correcting code (ECC) reconfiguration of the processing system.

A computer-implemented method for transforming a library from a source operating system to a target operating system is disclosed. Thereby, the source operating system comprises an ABI, the target operating system comprises a target ABI, the target ABI is different from the source ABI, the library is implemented by a source object file, the source object file conforms to the source application binary interface and comprises a source memory image, a source symbol and source relocation information. The method further includes creating a target memory image conforming to the target application binary interface, where the target memory is derived from the source memory image; enriching the target memory image with address information directed to the variable length information; and writing the target memory image to the target object file to implement the transformed library from the target object file.

The application provides a PXE network card initialization method, device and medium compatible with 64-bit addressing, relates to the technical field of network card initialization, and comprises the following steps: discovering a network card device; reading the PCI configuration space of the network card device, acquiring extended ROM base address register information, and mapping the network card Option ROM to a memory shadow area; when memory mapping input / output mode access fails, the initialization code performs read / write operation on the hardware register through a self-defined capability structure in the PCI configuration space of the network card device; based on the successfully accessed hardware register, network card hardware initialization is completed, and a PXE protocol stack structure body is established in the memory; the system firmware is registered as a PXE starting device, and a protocol interaction stage with a PXE server is entered; and the application guarantees the smooth development of a subsequent network booting process, and improves the deployment success rate and system stability in a large-scale batch deployment environment.

The purpose of the present invention is to provide an ultrasound image processing device and a program product that facilitate diagnosis based on display of evaluation values for ultrasound image data. An ultrasound diagnostic device (100) is provided with a processor. The processor acquires an evaluation value for each of ultrasonic image data sequentially acquired according to transmission and reception of ultrasonic waves, sequentially updates and displays an evaluation chart indicating the evaluation value when ultrasonic images based on the sequentially acquired ultrasonic image data are sequentially displayed, and displays an evaluation chart indicating the evaluation value when the ultrasonic images based on the sequentially acquired ultrasonic image data are sequentially displayed. A memory map is displayed for ultrasonic image data sequentially acquired according to transmission and reception of ultrasonic waves. The memory map represents a storage position in a memory in which each piece of ultrasound image data is stored.

Provided are a memory device and a method for dynamically mapping address thereof, in which the memory device includes a memory including a plurality of memory regions, an address register in which at least one of a memory device different from the memory device or a host stores a device address for accessing the memory, and an address translator configured to receive a first interrupt, and in response to the first interrupt, convert a physical address of the memory mapped to the device address.

The application relates to a digital switch quantity detection device of an inertial measurement system and a method thereof, which is composed of a monitoring control display module, a configuration file module, a switch quantity analysis and combination module and a bottom layer hardware communication module. When the configuration file is loaded into the memory, switch quantity information objects are automatically generated, the switch quantity information objects are stored in a linked list and managed in the linked list mode, and each object is mapped with the linked list through a unique index number. The monitoring control display module is dynamically generated according to the configuration file. In the test process, the switch quantity analysis and combination module converts the switch quantity information in the configuration file into information that can be displayed by the monitoring control display module, converts the control operation information of the monitoring control display module into information that can be recognized by the bottom layer hardware communication module, and feeds back the switch quantity information read by the bottom layer hardware communication module to the monitoring control display module after judgment and confirmation, so that the interface display is updated. The application can quickly and efficiently construct a test scheme of the inertial measurement system.

An edge network includes an information handling system configured to manage a shared memory, and a client device. A series of edge systems each include a portion of the shared memory. The information handling system determines that the client device is bottlenecked in processing a service, locks data associated with the service in the shared memory of a first edge system, permits a second edge system to access the first data, and directs the second edge system to process the service.

The invention discloses a deep evaluation method and device suitable for a role-playing agent, relates to the technical field of artificial intelligence, and aims at relatively accurately evaluating the consistency between the role-playing agent and a real role in multiple scenes. The device comprises (1) a role characterization module based on cognitive neuroscience, namely extracting character attributes, memory maps and the like of roles according to a role summary described by a natural language; (2) a static benchmark question set module which comprises a general question evaluation set generated according to characters, value, emotion characteristics, cognitive styles and other characteristics; generating a customized question evaluation set according to the character attributes and the memory atlas; and generating a scene evaluation set according to the typical dialogue scene. And (3) a multi-agent iteration depth problem generation module which uses the creator agent to transform and complement problems in the static reference problem set, uses the verifier agent to verify the rationality of the problems proposed by the creator agent, and generates a depth evaluation problem. And (4) a consistency analysis module.

A system is disclosed for Input / Output (I / O) device emulation that allows a service provider to configure and enforce a policy for software access to some or all I / O resources in a platform. I / O device emulation enables service providers to protect their platforms from malicious guest software that may be executed on associated platforms that has direct access to I / O resources in case of bare-metal servers, escalates the privilege level from guest to host in case of hosted-Virtual Machine servers, or escalates the privilege level from guest to System Management Mode in case of either bare-metal servers or hosted-Virtual Machine servers. The technology enables service providers to protect their platforms from malicious guest software running on their platforms that either has direct access to legacy I / O and memory mapped I / O resources. In one illustrative example, the platform may include a microprocessor.

A network interface device having an FPGA for providing an FPGA application. A first interface between a host computing device and the FPGA application is provided, allowing the FPGA application to make use of data-path operations provided by a transport engine on the network interface device, as well as communicate with the host. The FPGA application sends and receives data with the host via a memory that is memory mapped to a shared memory location in the host computing device, whilst the transport engine sends and receives data packets with the host via a second memory. A second interface is provided to interface the FPGA application and transport engine with the network, wherein the second interface is configured to back-pressure the transport engine.

This invention discloses a warehouse monitoring video enhancement method based on scene state memory. By filtering low-motion, low-overexposure frames from historical videos of the same camera, lighting topology descriptors are extracted and clustered to form scene state entries, generating anchored brightness maps, confidence maps, and reflection occupancy memory maps. State matching is performed on the current frame, and candidate enhanced brightness maps are generated by combining dynamic occlusion corridor areas and reflection uncertainty areas. The optimized enhanced brightness map is obtained through enhanced confidence back-off fusion and optimization solution, and color channel synchronous mapping is achieved through shared gain. This effectively suppresses false enhancement, reflection interference, dynamic occlusion effects, and comprehensive color shift, improving the stability and adaptability of warehouse monitoring video enhancement results.

A technique for controlling access to a set of memory-mapped control registers is described. An apparatus has processing circuitry for executing program code to perform data processing operations and a set of memory-mapped control registers for storing control information for controlling operation of the processing circuitry when executing the program code. In addition, a lock register is for storing a lock value. The processing circuitry is arranged to execute store instructions for performing write operations to a memory address space, the store instructions being of a plurality of types. However, on setting the lock value, the processing circuitry is arranged to prevent the write operations from being performed unless a write operation to change the control information in the memory-mapped control registers occurs as a result of executing a store instruction from a first subset of the plurality of types of store instruction. This significantly reduces the likelihood of an attacker seeking to exploit a software vulnerability to change the control information in the memory-mapped control registers.

A memory route mapping method and apparatus, a vehicle machine controller, a vehicle, a computer-readable storage medium, and a program product, relating to the technical field of electronic maps. The method comprises: acquiring road vector information and driving trajectory information collected in real time during the driving of a user vehicle on a preset route, and acquiring navigation information provided by a vehicle-end navigation map application (S101); performing graph optimization processing on the driving trajectory information, and generating high-precision trajectory information (S102); on the basis of the high-precision trajectory information and the road vector information, aggregating a plurality of road vector elements, and generating N segments of lightweight road information on the preset route (S103); and on the basis of the N segments of lightweight road information and the navigation information, creating a memory map of the preset route (S104). According to the described method, real-time mapping data collected and reported by a mass-produced user vehicle is used, so that sampling costs can be reduced, sampling data can be conveniently and flexibly obtained, and mapping content covers an entire road. In addition, graph optimization processing is performed on sampled driving trajectory information, thereby improving the accuracy and reliability of a memory map.

The present disclosure relates to a shared virtual address space for multi-node computing systems. The shared virtual address space includes a plurality of virtual addresses (e.g. virtual memory pages). A distributed, shared physical memory of the multi-node computing system is formed by combining the physical memory resources of the plurality of nodes. The shared virtual address space enables different nodes of a multi-node computing system to maintain an identical assignment of virtual addresses to physical memory addresses.

The application discloses a method for improving real-time performance of a virtual machine by cache coloring, comprising the following steps: S1, calculating the number of current system cache colors according to the implementation of a last level cache (LLC) and a cache coloring technology; S2, configuring different cache colors for different virtual machines; S3, when a virtual machine starts, establishing a page table for the physical memory mapped to the cache color according to the configured cache color; S4, when the virtual machine runs, allocating the physical memory to the corresponding cache color according to the established page table; and S5, using different LLCs for different virtual machines. The application isolates the LLC to different virtual machines by the cache coloring technology, so that the operating systems running on the virtual machines use different LLCs, the cache data do not interfere with each other, the delay of the system running on a virtual machine is not affected by the activities of the systems running on other virtual machines, and the real-time performance of the virtual machine is improved.