103 results about "Memory map" patented technology

The invention discloses a self-adaptive learning question answering system and method based on multi-modal interaction, and particularly relates to the technical field of self-adaptive learning question answering. By constructing a modal recognition and preprocessing module, standardization and structuralization of multi-modal input of texts, voices, images and the like are realized; establishing a cross-round modal memory map through time sequence coding and map modeling; dynamically updating a user portrait in combination with user interaction history and current modal characteristics; in the question and answer generation process, current input, a user portrait and a historical graph are fused, intermediate semantic representation is generated through a context enhancement module, and the intermediate semantic representation is combined with a knowledge base to generate answers; meanwhile, a modal confidence degree dynamic evaluation mechanism is introduced, and weights are distributed according to the input quality, the user adaptation degree and the context correlation; and finally, incremental optimization is carried out on the graph structure, the user portrait and the question and answer strategy through a user feedback driving system, and multi-round, multi-mode and self-adaptive intelligent question and answer interaction is realized.

The invention discloses a memory recall method based on a large language model and a related device. The method comprises the steps that short-term memories are divided into inactive short-term memories and active short-term memories; performing semantic content analysis on the inactive short-term memory through a large language model, and converting the obtained entity information and entity relationship triad into a long-term memory graph; entity extraction and multi-level reasoning are carried out on the active short-term memory according to entities in the long-term memory map through a large language model, and the extracted entities and reasoning levels are combined to generate a query language; and querying from the long-term memory map through a query language, performing textualization processing on the obtained long-term memory triple information, and generating a reply according to the textualized long-term memory triple information and the short-term memory through a large language model. The technical problems that an existing memory recall mode based on vector indexes has limitation of memory association ability and recalled entity memory information is incomplete are solved.

The embodiment of the invention provides a model reasoning data caching method and device for a caching system and a storage medium, and the method comprises the steps: configuring a first virtual address mapped to a high-performance memory of the caching system for a data caching pool, and generating a first reasoning data according to the data size of the first reasoning data generated by a target reasoning model; determining a target memory space of the high-performance memory mapped by the first virtual address, and enabling the data volume of the first reasoning data to be in direct proportion to the memory space volume of the target memory space mapped by the first virtual address, thereby creating a dynamic data buffer pool of the target reasoning model, and then caching the first reasoning data based on the target memory space corresponding to the dynamic data buffer pool, thereby realizing on-demand allocation of the high-performance memory in the cache system, and improving the utilization efficiency and the use flexibility of the high-performance memory in the cache system.

The invention relates to the technical field of computers, discloses a heterogeneous computing low-delay communication method and system, and aims to solve the problem of high delay caused by high communication protocol overhead, lack of dynamic scheduling collaboration, memory migration redundancy and non-uniform cross-node communication abstraction in existing heterogeneous computing. The method comprises the following steps: receiving a task scheduling request and analyzing a task dependency graph; tasks are dynamically allocated based on node loads and link states; rDMA, NVLink or PCIe straight-through protocols are adaptively selected according to node types to establish communication channels; zero-copy data exchange is realized through a shared memory mapping buffer area; hardware timestamps are utilized to synchronize feedback delays with PTP to optimize scheduling. The system comprises a heterogeneous computing node cluster, a unified communication scheduling controller, a low-delay communication protocol stack, a shared memory mapping buffer area and a communication delay sensing task distributor. According to the scheme, the communication delay is remarkably reduced, and the throughput and the task execution efficiency are improved.

The present disclosure relates to a computing system, a PCI device manager and an initialization method thereof. The PCI device manager is used to realize peer-to-peer data transmission between PCI devices, and the PCI device manager includes: a DMA engine module that realizes data and command communication with a host and a PCI device through DMA; a device memory; a memory mapping module that maps a data cache space of the device memory to a physical address space of the host memory, so as to perform data communication and / or command communication with the PCI device via the DMA engine module in a running process; and a processor that sends a PCI device configuration instruction to the host through the DMA engine module, and creates PCI device objects respectively for PCI devices discovered by the host.

The invention discloses a data transmission optimization method and system in hybrid deployment of a real-time system and a non-real-time system based on Jailhouse, belongs to the technical field of data transmission, and solves the problems of low data transmission efficiency, high copy overhead, lack of universality of interfaces and the like in an existing system. Comprising the steps that a hybrid deployment platform including a real-time system and a non-real-time system is built on a multi-core processor platform, and the hybrid deployment platform runs in an isolation environment of a Jailhouse partition manager; building an abstract transmission interface layer as a unified channel for accessing a shared memory by a real-time system and a non-real-time system; establishing a plurality of shared memory channels in the abstract transmission interface layer and scheduling according to the priority of tasks; establishing a data transmission path, and compressing a memory copy operation into one time by adopting a memory mapping multiplexing technology and a DMA (Direct Memory Access) collaboration mechanism; and a cache consistency maintenance technology is adopted, so that the data consistency is ensured, and the optimization of data transmission is completed. The method is suitable for application scenes such as industrial automation, intelligent connected automobiles and edge calculation.

A data processing system, a memory, and a data read-write method and device, in the application, a processor sends a read-write request to the memory, the read-write request is used for requesting to perform data read-write on the memory, and the read-write request carries a logical address of data. After the memory receives the read-write request, mapping a logic address to target positions on BANKs of N storage particles of the memory, and performing data read-write on the target positions on the BANKs of the N storage particles; wherein the target positions on the BANK of the N storage particles are distributed in different areas, and the N target positions are no longer located in the same area, so that the error rate of the memory cannot obviously fluctuate due to different logic addresses in the single read-write process of the memory, and the error rate of the memory is stabilized in a smaller range.

The invention discloses an intelligent following robot object searching method and system based on graph structure memory. The method comprises the steps that the robot follows a user to move in real time, actively senses behaviors of the user and obtains an observation result; organizing a graph structure based on an observation result to form an initial pragmatic memory graph; forming structured memory based on the initial pragmatic memory graph, wherein the structured memory comprises continuously maintained and updated working memory and long-term memory for storing behavior habits of people; querying in the working memory or the long-term memory according to the question proposed by the user to obtain a query result; and outputting a voice prompt according to the query result. The system comprises an object observation module, a memory creation module, a structured memory storage module, a memory recall module and a reminding module. According to the method, the observation angle is flexible and active, the storage space is greatly saved, the query efficiency is improved, and based on graph structure memory, the method is closer to the memory and recall mode of human beings.

The invention discloses an outdoor unmanned aerial vehicle visual language navigation method based on a multi-modal memory map, and aims to solve the problems of memory discretization, insufficient space connectivity and overhigh calculation load caused by dependence on global mapping in an unstructured environment in the prior art. The method comprises the following steps: extracting semantic features from an aerial view image by using a visual language model, and constructing memory nodes in combination with a local truncated symbol distance field; establishing topological connection containing six-degree-of-freedom constraints according to a visual common-view relationship and spatial trafficability among the nodes, and performing hierarchical organization on semantic landmarks in the nodes to form a multi-modal memory map; a semantic weight is calculated based on a cross attention mechanism, and a three-dimensional semantic navigation potential field is constructed by fusing geometric accessibility probability; and determining a navigation target according to the potential field distribution, executing path search in a topology layer, and performing obstacle avoidance and track generation in a measurement layer. According to the invention, the long-voyage autonomous visual language navigation of the unmanned aerial vehicle is realized under the condition that the computing resources are limited.

The invention discloses a self-adaptive dialogue generation method based on a personalized memory map and a related device, and the method comprises the steps: enabling a long-term memory database on a far-end server to be associated with an intelligent outbound robot all-in-one machine after logging in the far-end server; loading the personalized memory map to the local of the intelligent outbound robot all-in-one machine for local storage; the method comprises the following steps: when entering a chat conversation mode, collecting conversation audio data of a service object user, and extracting audio emotion information, semantic information and semantic keywords in the conversation audio data; matching knowledge nodes of the semantic keywords in the personalized memory graph; and dialogue audio data corresponding to the dialogue audio data is generated based on the semantic information, the knowledge nodes and the audio emotion information, and dialogue playing processing is carried out. In the embodiment of the invention, the lightweight local storage of the intelligent outbound robot all-in-one machine is realized, the conversation with the user is realized through the personalized memory map, and the sense of reality is improved.

A data processing system, a memory, a data read-write method, and a device. In the present application, a processor sends a read-write request to a memory, wherein the read-write request is used for requesting to perform data read-write on the memory, and the read-write request carries a logic address of data. After receiving the read-write request, the memory maps the logic address to target locations on BANKs of N storage particles of the memory, and performs data read-write on the target locations on the BANKs of the N storage particles, wherein the target locations on the BANKs of the N storage particles are distributed in different areas, and N target locations are not located in the same area any more, so that in the single read-write process for the memory, the error rate of the memory cannot significantly fluctuate due to different logic addresses, ensuring that the error rate of the memory is stable in a small range.

The invention provides a PXE network card initialization method and device compatible with 64-bit addressing and a medium, and relates to the technical field of network card initialization, and the method comprises the steps: discovering a network card device; reading a PCI configuration space of the network card equipment, obtaining information of an extended ROM base address register, and mapping a network card Option ROM to a memory shadow region; when the access of the memory mapping input and output mode fails, the initialization code performs read-write operation on the hardware register through a self-defined capability structure in a PCI configuration space of the network card equipment; based on the successfully accessed hardware register, network card hardware initialization is completed, and a PXE protocol stack structural body is established in a memory; registering system firmware as PXE starting equipment, and entering a protocol interaction stage with a PXE server; according to the invention, smooth development of a subsequent network boot flow is guaranteed, and the deployment success rate and the system stability in a large-scale batch installation scene are improved.

Provided are a memory device and a method for dynamically mapping address thereof, in which the memory device includes a memory including a plurality of memory regions, an address register in which at least one of a memory device different from the memory device or a host stores a device address for accessing the memory, and an address translator configured to receive a first interrupt, and in response to the first interrupt, convert a physical address of the memory mapped to the device address.

An example of compute express link (CXL) system includes a memory, and a tensor access circuit having a memory mapper configured to configure a memory map based on a compute express link (CXL) command associated with an access operation of the memory. The memory map includes a specific sequence of CXL instructions to access to the memory via a CXL bus.

The invention provides an automobile call positioning method, an automobile call method and an automobile call system. The automobile call positioning method comprises the following steps: acquiring an image feature descriptor based on surrounding image data of a target user acquired by mobile communication equipment, and matching the image feature descriptor with a vehicle-mounted memory map pre-constructed based on environmental data of a target area according to the image feature descriptor, obtaining the pose of the mobile communication equipment relative to the vehicle-mounted memory map according to a matching result; and further obtaining the current position coordinate of the target user based on the pose. According to the application, high-precision positioning can be realized in a complex environment, and the requirement of an automobile calling function on accurate positioning of a user position is met; meanwhile, the mobile communication device is used for collecting the image data, a large number of hardware devices do not need to be additionally deployed in the target area, and the cost for achieving the automobile calling and positioning function is greatly reduced.

Methods are provided comprising: mapping a portion of a local primary memory to an address space of a virtualization instance at a client device, wherein the address space is addressable by a processor of the client device, and wherein the virtualization instance is executed via the processor of the client device; mapping a first portion of external memory to the address space, wherein the external memory is memory that is external to the client device but treated as primary memory at the client device, and wherein a second portion of the external memory is not in any address space addressable by the processor of the client device; providing a performance indication data structure indicating a performance difference between the portion of the local primary memory mapped to the address space and the first portion of external memory mapped to the address space; and causing data to migrate between the external memory and the local primary memory based on the performance indication data structure by the virtualization instance, wherein the data is caused to migrate by the virtualization instance and / or a logic configured to operate with the virtualization instance.

The application relates to the technical field of firmware updating, and discloses an intelligent toy OTA (Over-the-Air) upgrading method and system based on an SDNAND chip, which comprises the following steps: storing initial updating data in a physical isolation buffer area in blocks to obtain to-be-verified updating data; extracting an authorized signature feature and a self-digestion feature to perform consistency authentication; when the authentication fails, generating a credential interception signal; according to the credential interception signal, extracting a target physical address and a data span parameter, resetting memory area access permission, and forming a hardware channel blocking state; according to the hardware channel blocking state, generating a bottom block erasing instruction, and performing forced erasing on the physical isolation buffer area to obtain an emptied safe area; and according to system boot configuration parameters and a memory mapping table, resetting a register environment of a bottom hardware device to obtain a safe running state of the toy device. The method can reduce the risk of illegal updating data polluting a core running area.

A computer-implemented method for transforming a library from a source operating system to a target operating system is disclosed. Thereby, the source operating system includes a source ABI; the target operating system comprises a target ABI; the target ABI is different from the binary interface of the source application, and the library is realized by the source object file; the source object file conforms to the source application binary interface and includes at least a source memory image, source symbol information, and source relocation information, where the source relocation information is free of relative relocation information. The method further includes creating a target memory image, the target memory image conforming to the target application binary interface and derived from the source memory image; enriching the target memory image with fixed-length eye mark information; and writing the target memory image into the target object file.

The application provides a one-to-many service discovery and dynamic loading method and system in a Hongmeng application, comprising: AST analysis of ArkTS source code by a TypeScript compiler API in a compilation period, identification of a class marked by a @HMModularService decorator, extraction of a service path, a class name, a module name, an instantiation mode and a unique identifier as metadata, generation of a module-level mapping table and merging into a global mapping table, and establishment of a one-to-many mapping relationship from the service path to an implementation item array; loading of the global mapping table into a memory Map structure in a running period, receiving of a service query request from a calling party, searching for a corresponding implementation item according to the service path and supporting of filtering according to an identifier; dynamic loading of a target HSP module by calling a napi_load_module_with_info native interface, obtaining of a constructor from an export object and creation of an instance, and caching of a singleton mode implementation item.

To provide a system for preventing a forged gaming chip from being used.SOLUTION: The gaming chip reader may read one or more gaming chips from the antenna. The drawer can be read from the gaming chip. The version may be identified from the drawer. The memory map may be decrypted and the decrypted memory map may be used to decrypt the data describing the gaming chips from the drawer. The data describing the gaming chips may be matched against a gaming chip inventory data set.SELECTED DRAWING: Figure 2

An integrated circuit for translating and reverse-translating the address included in a memory request is disclosed. The integrated circuit may first comprise a processor, a first boundary function, a second boundary function, and a component device. The processor is configured to transmit a memory request to a target module over a bus of the integrated circuit. The memory request requests access to one or more memory mapped resources and the memory request includes a physical address. The first boundary function is configured to translate the physical address to a relative address which operates in or applies to a different address space than an address space that the physical address operates in or applies to. The second boundary function is configured to translate the relative address to the physical address. The device is configured utilize the physical address transmitted by the second boundary function.

An ultrasound diagnostic apparatus includes a processor. The processor is configured to acquire an evaluation value for each item of ultrasound image data sequentially acquired based on transmission and reception of ultrasound, sequentially update and display an evaluation graph showing the evaluation value in a case where ultrasound images based on the ultrasound image data sequentially acquired are displayed sequentially, and display a memory map for the ultrasound image data sequentially acquired based on the transmission and the reception of the ultrasound. The memory map indicates a storage location in a memory where each item of the ultrasound image data is stored.

The invention discloses a timing ringing method and device for campus broadcast, terminal equipment and a storage medium, and belongs to the technical field of computer application and data processing, and the method comprises the steps: storing an allocation rule in a first memory map container; if the ringing scheme is marked to be enabled, storing the ringing scheme in a second memory map container; if the ringing scheme is marked to be forbidden, storing the ringing scheme in a third memory map container; if the execution time of the ringing task in the second memory map container is in the starting time interval, storing the ringing task in a fourth memory map container; if the execution time of the ringing task in the third memory map container is in the forbidden time interval, storing the ringing task in a fifth memory map container; and performing data cleaning on the fourth memory map container, generating a control instruction, and issuing the control instruction to the campus broadcast terminal. Therefore, through the implementation of the invention, the suitability of the campus broadcast timing ringing task in a complex scene can be improved through intelligent and automatic scheduling.

Systems and methods for dynamic repartitioning of physical memory address mapping involve relocating data stored at one or more physical memory locations of one or more memory devices to another memory device or mass storage device, repartitioning one or more corresponding physical memory maps to include new mappings between physical memory addresses and physical memory locations of the one or more memory devices, then loading the relocated data back onto the one or more memory devices at physical memory locations determined by the new physical address mapping. Such dynamic repartitioning of the physical memory address mapping does not require a processing system to be rebooted and has various applications in connection with interleaving reconfiguration and error correcting code (ECC) reconfiguration of the processing system.

The embodiment of the invention provides a vehicle attitude optimization method, a vehicle and a product. The method comprises the following steps: determining perception information obtained when a vehicle is positioned and an initial pose in a memory map; the perception information comprises at least one of semantic information and feature information, and the semantic information is obtained by detecting a panoramic image when the vehicle is positioned; the feature information is obtained by performing feature extraction on a target azimuth image used for detecting a target azimuth when the vehicle is positioned; projecting the perception information to the memory map according to the initial pose in the memory map to obtain perception projection information; and according to a re-projection error between the perception projection information and prior information, the initial pose of the vehicle is optimized, the optimized pose of the vehicle is determined, and the prior information represents real information matched with the perception information in the memory map. The method is used for achieving the effect of improving the positioning accuracy.

The invention discloses a navigation path planning method, computer equipment, a computer readable storage medium, a computer program product and a mobile platform. The navigation path planning method comprises the following steps: acquiring a current position and a destination position of a mobile platform; determining a corresponding memory map according to the current position and the destination position of the mobile platform; searching a global topological path at least according to the lane-level topological map to determine a global topological path from the current position to the destination position; and searching a local geometric path at least according to the global topological path and the road traffic information collected by the mobile platform in real time so as to determine the local geometric path. According to the method, the road smoothness from the current position of the vehicle to the destination position is ensured through global topological path search, and finer local navigation planning is realized through local geometric path search based on vehicle online sensing information.

The present invention relates to a method for protecting an electronic system (1) comprising a secure processor (102) and an integrated sensor (101) against software-based side channel attacks targeting said secure processor using said integrated sensor, said electronic system further comprising an untrusted processor (104), a sensor register (103) isolated from said untrusted processor for storing at least one output value of the integrated sensor, a blurring device (109) connected to the sensor register and configured for outputting at least one blurred sensor output value whose bits are at least partly blurred, and a memory mapped register (110) accessible by said untrusted processor and storing outputs of the blurring device, said method comprising: - measuring, by the integrated sensor, a physical quantity representative of an activity of the secure processor to obtain a sensor output value, - storing said sensor output value into said sensor register, - generating, by said blurring device, from said sensor output value stored in the sensor register, a blurred sensor output value wherein one or more bits of said blurred sensor output value are blurred according to a blurring device configuration, - storing said blurred sensor output value in said memory mapped register.

Systems and methods for dynamic repartitioning of physical memory address mapping involve relocating data stored at one or more physical memory locations of one or more memory devices to another memory device or mass storage device, repartitioning one or more corresponding physical memory maps to include new mappings between physical memory addresses and physical memory locations of the one or more memory devices, then loading the relocated data back onto the one or more memory devices at physical memory locations determined by the new physical address mapping. Such dynamic repartitioning of the physical memory address mapping does not require a processing system to be rebooted and has various applications in connection with interleaving reconfiguration and error correcting code (ECC) reconfiguration of the processing system.

In one aspect, a disclosed method includes learning one or more chip agnostic parameters across a plurality of best known configuration (BKC) firmware versions, performing BKC attributes tuning based on said learning, implementing platform specific BKC table offsets and a handoff block to pass the table offsets to update routines by creating a trusted session for platform firmware table updates, and dynamically publishing changes in BKC policy. A BKC firmware serialization protocol may be implemented to ensure gaps in firmware versions at an end user platform are resolved by synchronizing each BKC version attribute. The serialization protocol may employ node-based cloud ecosystem learning. The method may further include reloading memory map parameters for uninterrupted services. The uninterrupted services may include, as examples, user presence detection after power resume and central processing unit (CPU) power cap functions.

The present disclosure relates to field of Dual In-Line Memory Modules that discloses method and system for generating memory maps. The method comprises detecting, by computing system, at least one of DIMM and one or more Dynamic Random Access Memory (DRAM) chips associated with computing system. The one or more accelerators are configured in at least one of DIMM and one or more DRAM chips. Further, the method includes determining accelerator information for each of one or more accelerators via at least one of Serial Presence Detect (SPD) and Multi-Purpose Register (MPR) associated with at least one of DIMM and one or more DRAM chips. Method includes generating unique memory map for each of one or more accelerators based on accelerator information of corresponding one or more accelerators. As a result, performance of computing system may be improved as accelerator capabilities of one or more accelerators are effectively utilized.