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Message transmission system for users of location-aware mobile communication devices in a local area network

Embodiments of a location-based social network manager process are described. The process is executed on a server computer coupled to a plurality of mobile communication devices over a wireless network. Each mobile device is a location-aware mobile communication device. The process determines the geographic location of a mobile communication device operated by a user within an area, displays a map representation of the area around the mobile communication device on a graphical user interface of the mobile communication device, and superimposes on the map the respective locations of one or more other users of mobile communication devices coupled to the mobile communication device over the network. The process establishes communication links between the user and the plurality of acquaintances through respective location aware mobile communication devices through a network protocol. The user can create one or more groups of acquaintances based on one or more characteristics common to members of each group. The process facilitates the transmission of a user specified message or a pre-defined message to one or more acquaintances of the groups of acquaintances within a pre-defined distance to the user. The contents of the user specified message and pre-defined message is based on the characteristics of the group and the relative distance of the members to the user. The process can also be configured to automatically transmit a message to a user who is within a pre-defined distance to a point of interest within the displayed area.
Owner:LOOPT

System for transmitting electrical current to a bodily tissue

In some embodiments, an apparatus includes a substrate, a power source, a connector, electrical circuitry, and an electrode assembly. The substrate has a first surface and a second surface different than the first surface. The power source has a positive terminal and a negative terminal Each of the positive terminal and the negative terminal are coupled to the substrate. The power source is configured to provide power to an external stimulator coupled to the apparatus. The connector is disposed proximate to the first surface of the substrate and is electrically coupled to at least one of the positive terminal and the negative terminal of the power source. The connector is configured to electrically couple the external stimulator to the power source. The electrical circuitry is coupled to the substrate. The electrical circuitry is configured to electrically couple the connector to at least one of the positive terminal and the negative terminal of the power source. At least one of the connector or the electrical circuitry is configured to prevent a short circuit of the electrical circuit. The electrode assembly is coupled to the second surface of the substrate. At least one electrode of the electrode assembly is configured to contact bodily tissue and to facilitate transmission of an electrical current through the bodily tissue.
Owner:BIONESS

Interrupt architecture for a non-uniform memory access (NUMA) data processing system

A non-uniform memory access (NUMA) computer system includes at least two nodes coupled by a node interconnect, where at least one of the nodes includes a processor for servicing interrupts. The nodes are partitioned into external interrupt domains so that an external interrupt is always presented to a processor within the external interrupt domain in which the interrupt occurs. Although each external interrupt domain typically includes only a single node, interrupt channeling or interrupt funneling may be implemented to route external interrupts across node boundaries for presentation to a processor. Once presented to a processor, interrupt handling software may then execute on any processor to service the external interrupt. Servicing external interrupts is expedited by reducing the size of the interrupt handler polling chain as compared to prior art methods. In addition to external interrupts, the interrupt architecture of the present invention supports inter-processor interrupts (IPIs) by which any processor may interrupt itself or one or more other processors in the NUMA computer system. IPIs are triggered by writing to memory mapped registers in global system memory, which facilitates the transmission of IPIs across node boundaries and permits multicast IPIs to be triggered simply by transmitting one write transaction to each node containing a processor to be interrupted. The interrupt hardware within each node is also distributed for scalability, with the hardware components communicating via interrupt transactions conveyed across shared communication paths.
Owner:IBM CORP
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