14 results about "Interrupt handler" patented technology

This application provides a method, apparatus, electronic device, and storage medium for detecting atomicity violations, belonging to the field of software testing technology. The method includes: running the program under test using different input variables, identifying global variable access pairs covered during the execution of the program under test; for each global variable access pair, re-running the program under test using the corresponding input variables, and injecting feasible interrupt handlers between the global variable access pairs; if the interrupt handlers access the same global variable, recording the global variable access pair as a candidate global variable access pair; if the candidate global variable access pair simultaneously satisfies both spatial atomicity and temporal atomicity, then determining that the candidate global variable access pair has an atomicity violation risk. This application achieves efficient and accurate detection of atomicity violations by comprehensively covering variable access pairs, actively constructing interrupt scenarios, and establishing a spatiotemporal dual verification model.

The application discloses a program updating method and an electronic device. The method comprises the following steps: a baseboard management controller acquires a software updating package of a target system management interrupt processing program; the software updating package is compiled into a corresponding target format file, and is updated into a target file volume to obtain an updated target file volume; the target file volume is used for storing the target format file corresponding to each system management interrupt processing program in the electronic device; a notification message is sent to a unified extensible firmware interface module based on the updated target file volume, so that the unified extensible firmware interface module updates the target system management interrupt processing program in a system management interrupt processing program entry list in the unified extensible firmware interface module based on the notification message and the updated target file volume; and the system management interrupt processing program entry list is used for recording the system management interrupt processing program that has been registered to the unified extensible firmware interface module.

In the present invention, if, after a timer start signal is inputted from a microcontroller 40, a first set time elapses without a clear signal being inputted from the microcontroller 40, then a watchdog timer 50 outputs, to the microcontroller 40, an interrupt signal for starting up an interrupt handler for shutting down DC-DC converters 30a-30d in a normal procedure. If a second set time elapses after a timer start signal is inputted from the interrupt handler of the microcontroller 40, then the watchdog timer 50 outputs a reset signal to the microcontroller 40.

The invention discloses a data processing method and device.The data processing method comprises the steps that in response to system management interruption, an interruption processing program runs in a main system management memory of electronic equipment; obtaining to-be-written data corresponding to the interrupt processing program; the to-be-written data are written into a main system management memory and a backup system management memory of the electronic equipment respectively, the storage capacity of the backup system management memory is equal to that of the main system management memory, and the backup system management memory is a memory mirror image of the main system management memory; and verifying first data corresponding to the to-be-written data and obtained by the main system management memory, and correcting an uncorrectable error by using second data in the backup system management memory under the condition that the uncorrectable error exists in the first data.

Utilizing kernel thread dispatch latency for input / output processing is disclosed, including executing an interrupt handler in response to an interrupt raised by an I / O adapter; dispatching, by the interrupt handler, a kernel thread configured for I / O processing; processing, by the interrupt handler while waiting for an acknowledgement by the kernel thread, one or more I / O events of a plurality of I / O events in an I / O queue for the I / O adapter; transferring, by the interrupt handler, the I / O processing to the kernel thread in response to detecting the acknowledgement by the kernel thread; and processing, by the kernel thread, remaining I / O events in the I / O queue.

The invention relates to a system-on-chip and an update data configuration method, the system-on-chip comprises a monitoring module, a system bus and a central processing unit, the central processing unit is used for executing a program and initiating a data read-write request through the system bus in the process of executing the program; the monitoring module is used for monitoring a data read-write request transmitted on a system bus, and sending an interrupt request to the central processing unit when the data read-write request meets at least one of the condition that an indicated address is matched with a pre-configured monitoring address and the condition that indicated data is matched with pre-configured monitoring data; the central processing unit is used for responding to the interrupt request, suspending an execution program and executing an interrupt processing program; wherein the interrupt processing program is pre-configured with update data and a target address to which the update data needs to be configured, and the interrupt processing program is used for writing the update data into the target address. By adopting the system, any update data can be configured for any address at any moment after the chip is started.

The present application provide a method for seamless upgrade of an interrupt handling program and a computer system, belonging to the field of data processing. The method includes responding, by a baseboard management controller (BMC), to an upgrade operation for an interrupt handling program to be upgraded, and acquiring the interrupt handling program to be upgraded and upgrade parameters; storing, by the BMC, the interrupt handling program to be upgraded in basic input output system (BIOS) Flash according to the upgrade parameters, overwriting a historical interrupt handling program corresponding to the interrupt handling program to be upgraded in the BIOS Flash, and sending an upgrade interrupt signal to an interrupt handler; starting, by the interrupt handler, an interrupt upgrade program and acquiring the upgrade parameters, moving the interrupt handling program to be upgraded in the BIOS Flash to a physical memory address according to the upgrade parameters, and overwriting a historical interrupt handling program corresponding to the interrupt handling program to be upgraded to be regarded as a new interrupt handling program. The present application aims to upgrade the interrupt handling program online.

Techniques are described for interrupt handling. A device can obtain, at a first context buffer associated with a first interrupt handler, first processing configuration data associated with a first sensor; obtain, at a second context buffer associated with a second interrupt handler, second processing configuration data associated with a second sensor; obtain, at the first interrupt handler, an error indication associated with the first sensor; perform, by the first interrupt handler, based on the error indication, an error handling operation (where the error handling operation comprises flushing the first context buffer and / or invalidating the first processing configuration data in the first context buffer); obtain, at the second interrupt handler, during a time window interval between obtaining the error indication and a completion time of the error handling operation, from the second sensor, an interrupt request (IRQ); and output, based on the IRQ, the second processing configuration data to a processor.

Within an interrupt routing structure, an interrupt handler is registered, the registering comprising storing a pointer to the interrupt handler in the interrupt routing structure. Responsive to determining that a received interrupt comprises a queuing bypass flag in a set state, the interrupt handler is executed, the executing bypassing an interrupt queueing mechanism.

The application discloses a kind of based on UDS's controller brush write optimization method and system, belong to new energy automobile field.The method includes: original brush write data is obtained and is preprocessed optimization in diagnostic equipment end, and the preprocessing optimization includes data compression, checksum calculation;UDS communication protocol between diagnostic equipment end and controller end is optimized, including introducing multithread transmission technology, diagnostic equipment end data frame format optimization, controller end protocol stack upgrade;Buffer area is established in controller end, and optimized cache management mechanism and interrupt handling procedure are used;Intelligent brush write process is designed, including intelligent detection before brush write, real-time monitoring and intelligent fault tolerance in brush write, log record and report generation after brush write;Diagnostic equipment end establishes brush write mode switching mechanism.The application improves the efficiency of brush write.

The application provides a data transmission method, which can be applied to the technical field of servers. The data transmission method comprises the following steps: a first graphics processing unit writes to-be-transmitted data according to a first address into a double-rate memory, and triggers a first quick computing link controller to monitor a first interrupt event of the first address being written into the double-rate memory when the data writing is completed; the first quick computing link controller writes the first interrupt event into a first central processing unit after encapsulation, so that the first address is written into the first central processing unit; the first central processing unit triggers a first interrupt processing program to modify the value of a memory monitoring register in the first central processing unit; in the case that an application state polling thread associated with the first graphics processing unit in the first central processing unit monitors that the value of the memory monitoring register is modified, the polling thread is interrupted, and a transmission instruction based on a quick computing link protocol is issued according to a second address which is queried according to the first address.

The present application discloses a program updating method and apparatus, an electronic device, and a non-volatile readable storage medium, which relates to the technical field of computers. The method includes: migrating a new interruption processing program to a physical memory; acquiring upgradation parameters, and according to the upgradation parameters, determining a first position of the new interruption processing program in the physical memory and a second position of a to-be-upgraded interruption processing program in the physical memory; and migrating the new interruption processing program in the first position to the second position, to replace the to-be-upgraded interruption processing program. In the program updating method according to the present application, the new interruption processing program is migrated to the position of the to-be-upgraded interruption processing program in the physical memory, and because the new interruption processing program is in the physical memory, it becomes effective immediately after the upgrading program has exited, which realizes updating of the interruption processing program without restarting the system.

A processor includes fetch circuitry configured to fetch instructions and a speculation control circuit. The fetch circuitry is configured to, in response to a first interrupt received by the processor, fetch a first interrupt handler instruction for the received first interrupt. The speculation control circuit is configured to, in response to the first interrupt received by the processor, begin speculative pushing of registers onto a memory stack in accordance with a predetermined register order prior to completion of the fetch of the first interrupt handler instruction for the first interrupt, in which a register tracking value is updated with each speculative push.

A method for operating cycle-oriented control software for controlling processes, wherein the software executes within a runtime environment on a computer system and uses two independent time bases: a first time base derived from a hardware timer, and a second time base provided by a another timer is transmitted via a network communication, and the second time base is provided via telegrams with time stamps, where a receive routine assigns time stamps to a receipt time and stores them in a buffer, an evaluation routine recognizes and compensates interrupts that disrupt the safe time base, the past values of the first time base are stored in a cyclical buffer that an interrupt handler periodically updates, the evaluation routine checks the time differences between the telegrams and corrects the second time base if required, such that reliable and safe time measurement are ensured, even in the event of system management interrupts.