42 results about "Interrupt handler" patented technology

The invention discloses a method for communication between a user program and a virtual machine on a microkernel Hypervisor, the microkernel Hypervisor is provided with two shared memory areas, the shared memory area 1 is accessed by the user program and a root service Rootserver, the shared memory area 2 is accessed by the Rootserver and the virtual machine, the user program writes communication request data with the virtual machine into the shared memory area 1, and the user program writes communication request data with the virtual machine into the shared memory area 2. The method comprises the following steps that a VMM sub-thread is used as a shared memory area 1, a Rootserver is notified through inter-process communication, the Rootserver reads communication request data from the shared memory area 1, the communication request data is written into a shared memory area 2 after being analyzed by the VMM sub-thread, a system calls a syscale to transmit a communication request to a kernel, the kernel injects virtual interrupt into a virtual machine, and the virtual machine sends the communication request to the Rootserver. And an interrupt processing program of the virtual machine processes the communication request and writes a processing result into the shared memory area 2, then the processing result is returned to the Hypervisor through the Hypercall, and a Rootserver of the Hypervisor feeds back the processing result to a user program through the IPC. The method is designed for the microkernel Hypervisor environment, and the overall performance and efficiency of the embedded virtualization system are improved.

An embodiment of an integrated circuit may comprise a processor with one or more cores and circuitry coupled to the one or more cores, the circuitry to control one or more interrupts based on an interrupt expansion data structure, and report information derived from the interrupt expansion data structure to a software interrupt handler. Other embodiments are disclosed and claimed.

The invention provides a system-on-chip and a method and electronic equipment for system RAS fault report processing, the system-on-chip comprises a plurality of function modules containing error sources, a mapping module and a universal interrupt controller, and when uncorrectable errors occur, the function modules send the error sources to the mapping module and send the error sources to the universal interrupt controller. Triggering a first peripheral interrupt and transmitting the first peripheral interrupt to the mapping module; the mapping module triggers a second interrupt processing request and transmits the second interrupt processing request to the universal interrupt controller according to the first peripheral interrupt from the functional module; and the universal interrupt controller responds to the second interrupt processing request, runs an interrupt processing program and reports fault information. According to the technical scheme, management of different error sources can be simplified through a centralized processing mode, uncorrectable errors can be efficiently and accurately responded and processed, and the reliability and maintainability of the system are improved.

Examples described herein relate to an interface and a circuitry, coupled to the interface. In some examples, the circuitry is to translate an interrupt from system management interrupt (SMI) format to a second interrupt in System Control Interrupt (SCI) format and transmit the second interrupt, by the interface, to an SCI interrupt handler to perform event handling. In some examples, the SCI interrupt handler is to execute on a single thread.

The invention discloses a method and a device for supporting consistent multi-chip interconnection interruption. The method comprises the following steps: configuring the number of supported chips, and setting cross-chip parameters of the chips to determine the address of each chip and the depth of a routing table; the method comprises the following steps of: assigning a chip to be responsible for managing consistency, recording the chip as a management chip, configuring a routing table for each chip, mutually connecting all the chips, and assigning the number of low-speed peripheral interrupts managed by each chip; after the interrupt controller of a certain chip receives the interrupt, if the interrupt is a cross-chip interrupt, distributing the interrupt to the corresponding management chip through the network-on-chip and the high-speed interconnection interface according to the interrupt route configured in the routing table; and the management chip calls the interrupt processing program for processing and returns interrupt confirmation. The method can support current multi-chip interrupt consistency maintenance, realizes interrupt processing across any number of chips, improves the performance of a processor, and has the advantages of low hardware implementation complexity, small area overhead and high cost performance.

This application discloses an interrupt control device and method based on a RISC-V architecture, relating to the field of interrupt handling technology. The device includes a processor, an interrupt controller, and a data preparation module. The interrupt controller is used to acquire a first interrupt request and enable information sent by a first interrupt source; based on the enable information and the interrupt source ID corresponding to the first interrupt source, it queries the data load address information and data load length information corresponding to the interrupt handler; and generates a first interrupt signal based on the acquired first interrupt request. The data preparation module is used to load the target data corresponding to the interrupt handler from memory into the data preparation module based on the enable information, data load address information, and data load length information. The processor is used to suspend the general program after executing the current instruction of the general program; and respond to the first interrupt signal, execute the interrupt handler, and acquire the target data corresponding to the interrupt handler from the data preparation module.

This application provides a method, apparatus, electronic device, and storage medium for detecting atomicity violations, belonging to the field of software testing technology. The method includes: running the program under test using different input variables, identifying global variable access pairs covered during the execution of the program under test; for each global variable access pair, re-running the program under test using the corresponding input variables, and injecting feasible interrupt handlers between the global variable access pairs; if the interrupt handlers access the same global variable, recording the global variable access pair as a candidate global variable access pair; if the candidate global variable access pair simultaneously satisfies both spatial atomicity and temporal atomicity, then determining that the candidate global variable access pair has an atomicity violation risk. This application achieves efficient and accurate detection of atomicity violations by comprehensively covering variable access pairs, actively constructing interrupt scenarios, and establishing a spatiotemporal dual verification model.

The application discloses a program updating method and an electronic device. The method comprises the following steps: a baseboard management controller acquires a software updating package of a target system management interrupt processing program; the software updating package is compiled into a corresponding target format file, and is updated into a target file volume to obtain an updated target file volume; the target file volume is used for storing the target format file corresponding to each system management interrupt processing program in the electronic device; a notification message is sent to a unified extensible firmware interface module based on the updated target file volume, so that the unified extensible firmware interface module updates the target system management interrupt processing program in a system management interrupt processing program entry list in the unified extensible firmware interface module based on the notification message and the updated target file volume; and the system management interrupt processing program entry list is used for recording the system management interrupt processing program that has been registered to the unified extensible firmware interface module.

The invention discloses an interrupt processing system and method based on static analysis, and the system comprises a branch processing module which is used for obtaining a hot branch code and a cold branch code; the register processing module comprises a first register processing unit, a second register processing unit, a third register processing unit and a fourth register processing unit; the first register processing unit is used for processing a register used in the hot branch code and generating first register use information; the second register processing unit is used for processing a register used in the cold branch code, and the first instruction is inserted at the beginning of the cold branch code; the third register processing unit is used for processing the interrupt processing program and deleting an original instruction assembly used for storing and recovering the register in the interrupt processing program; and the fourth register processing unit is used for processing a register used in the function called by the interrupt processing program. According to the interrupt processing system and method based on static analysis, registers for automatic storage and recovery of hardware in the delay interrupt processing process are reduced, and therefore the interrupt response speed is increased.

A high-throughput confidential computing method and system based on a RISC-V architecture are provided. The method includes: S1, acquiring a hardware device tree configuration file to classify each physical resource into a normal partition or a security partition; S2, loading a security manager; S3, mapping memory resources in the normal and security partitions to the normal and security domains, respectively; registering CPU resources in the normal and security partitions to the normal and security domains, respectively; and registering an interrupt handler function; S4, linking an image file of a security file system with a security kernel file to generate an operating system image of the security domain; S5, reading the operating system image, and loading the same to a memory address of the security domain; and S6, executing the initialization of the security domain according to an interrupt request from the normal domain.

Systems and methods are provided for implementing improved root cause analysis (“RCA”)-based node recovery. After instructing a node to enter a debug mode and based on a determination that an expected response timeout duration has elapsed, a controller instructs the node to enter a system management mode (“SMM”), and exposes a shared buffer to an SMM handler of the node. The shared buffer includes instructions for the SMM handler to set a trap flag in a saved state area of an operating system (“OS”) of the node and to use a resume execution instruction after setting the trap flag. The trap flag causes the OS to transfer control of problematic code to a trap handler, which performs operations or calls a hypervisor for a virtual machine extension (“VMX”) root mode depending on whether the problematic code execution occurs in a non-maskable interrupt (“NMI”) handler.

In the present invention, if, after a timer start signal is inputted from a microcontroller 40, a first set time elapses without a clear signal being inputted from the microcontroller 40, then a watchdog timer 50 outputs, to the microcontroller 40, an interrupt signal for starting up an interrupt handler for shutting down DC-DC converters 30a-30d in a normal procedure. If a second set time elapses after a timer start signal is inputted from the interrupt handler of the microcontroller 40, then the watchdog timer 50 outputs a reset signal to the microcontroller 40.

The invention discloses an interrupt control device and method based on an RISC-V framework, and relates to the technical field of interrupt processing. The device comprises a processor, an interrupt controller and a data preparation module; the interrupt controller is used for acquiring a first interrupt request and enabling information sent by a first interrupt source; querying data loading address information and data loading length information corresponding to the corresponding interrupt processing program based on the enabling information and an interrupt source ID corresponding to the first interrupt source; generating a first interrupt signal based on the obtained first interrupt request; the data preparation module is used for loading target data corresponding to the interrupt processing program from the memory to the data preparation module based on the enabling information, the data loading address information and the data loading length information; the processor is used for suspending the general program after the current instruction of the general program is executed; and responding to the first interrupt signal, executing an interrupt processing program, and obtaining target data corresponding to the interrupt processing program from the data preparation module.

The present invention discloses a method and device for supporting consistent multi-chip interconnect interrupts. The method includes configuring the number of chips supported, setting the cross-chip parameters of the chips to determine the addresses of each chip and the depth of the routing table; designating a chip responsible for managing consistency as a management chip, configuring a routing table for each chip and connecting all the chips to each other, and designating the number of slow peripheral interrupts that each chip is responsible for managing; when the interrupt controller of a certain chip receives an interrupt, if the interrupt is a cross-chip interrupt, it is dispatched to the corresponding management chip through the on-chip network and high-speed interconnect interface according to the interrupt route configured in the routing table; the management chip calls the interrupt handler for processing and returns an interrupt confirmation. The present invention can support the current multi-chip interrupt consistency maintenance, realize interrupt processing across any number of chips, improve the performance of the processor, and has the advantages of low hardware implementation complexity, small area overhead, and high cost performance.

The invention provides an equipment interconnection and bidirectional control system and method based on a single GPIO (General Purpose Input / Output) line. The system comprises host equipment, external equipment and the single GPIO line, the host equipment and the external equipment are interconnected through a single GPIO (General Purpose Input / Output) line; the GPIO line is used for transmitting a control signal; the control signal is a reset signal or an interrupt signal, and the external device is used for executing a reset operation based on the reset signal; and the host equipment is used for calling a corresponding interrupt processing program based on the interrupt signal. According to the invention, the number of interconnection signal lines between devices is reduced, the internal interface interconnection space of the server is saved, the design and layout of the server are simplified, the integration level and performance of the server are improved, and the cost and maintenance difficulty are reduced; the method has stability and reliability, and can meet the performance and compatibility requirements of a high-density server.

The invention discloses a data processing method and device.The data processing method comprises the steps that in response to system management interruption, an interruption processing program runs in a main system management memory of electronic equipment; obtaining to-be-written data corresponding to the interrupt processing program; the to-be-written data are written into a main system management memory and a backup system management memory of the electronic equipment respectively, the storage capacity of the backup system management memory is equal to that of the main system management memory, and the backup system management memory is a memory mirror image of the main system management memory; and verifying first data corresponding to the to-be-written data and obtained by the main system management memory, and correcting an uncorrectable error by using second data in the backup system management memory under the condition that the uncorrectable error exists in the first data.

Utilizing kernel thread dispatch latency for input / output processing is disclosed, including executing an interrupt handler in response to an interrupt raised by an I / O adapter; dispatching, by the interrupt handler, a kernel thread configured for I / O processing; processing, by the interrupt handler while waiting for an acknowledgement by the kernel thread, one or more I / O events of a plurality of I / O events in an I / O queue for the I / O adapter; transferring, by the interrupt handler, the I / O processing to the kernel thread in response to detecting the acknowledgement by the kernel thread; and processing, by the kernel thread, remaining I / O events in the I / O queue.

The invention relates to a system-on-chip and an update data configuration method, the system-on-chip comprises a monitoring module, a system bus and a central processing unit, the central processing unit is used for executing a program and initiating a data read-write request through the system bus in the process of executing the program; the monitoring module is used for monitoring a data read-write request transmitted on a system bus, and sending an interrupt request to the central processing unit when the data read-write request meets at least one of the condition that an indicated address is matched with a pre-configured monitoring address and the condition that indicated data is matched with pre-configured monitoring data; the central processing unit is used for responding to the interrupt request, suspending an execution program and executing an interrupt processing program; wherein the interrupt processing program is pre-configured with update data and a target address to which the update data needs to be configured, and the interrupt processing program is used for writing the update data into the target address. By adopting the system, any update data can be configured for any address at any moment after the chip is started.

Techniques for interrupt handling are described. The device can obtain first processing configuration data associated with the first sensor at a first context buffer associated with the first interrupt handler; obtaining second processing configuration data associated with a second sensor at a second context buffer associated with a second interrupt handler; obtaining, at the first interrupt handler, an error indication associated with the first sensor; performing, by the first interrupt handler, an error handling operation based on the error indication, wherein the error handling operation includes refreshing the first context buffer and / or invalidating first processing configuration data in the first context buffer; obtaining, at the second interrupt handler, an interrupt request (IRQ) from a second sensor during a time window interval between obtaining the error indication and a completion time of the error handling operation; and outputting the second processing configuration data to the processor based on the IRQ.

The present application relates to the technical field of computers, and provides a system crash information storage method and apparatus and a computer system. The method comprises: receiving a target interrupt signal sent by a system monitoring apparatus; sending the target interrupt signal to a first core and a second core in a processor; controlling the first core to run a first interrupt processing program, and storing first system crash information to a reserved storage space of a system memory; and controlling the second core to run a second interrupt processing program, and storing second system crash information to the system monitoring apparatus; wherein the system monitoring apparatus and the system memory are separately connected to the processor. By means of the method and apparatus provided in the present application, relevant information of the computer system when a system crash occurs can be stored as much as possible, improving the fault diagnosis efficiency of the computer system.

The present application provide a method for seamless upgrade of an interrupt handling program and a computer system, belonging to the field of data processing. The method includes responding, by a baseboard management controller (BMC), to an upgrade operation for an interrupt handling program to be upgraded, and acquiring the interrupt handling program to be upgraded and upgrade parameters; storing, by the BMC, the interrupt handling program to be upgraded in basic input output system (BIOS) Flash according to the upgrade parameters, overwriting a historical interrupt handling program corresponding to the interrupt handling program to be upgraded in the BIOS Flash, and sending an upgrade interrupt signal to an interrupt handler; starting, by the interrupt handler, an interrupt upgrade program and acquiring the upgrade parameters, moving the interrupt handling program to be upgraded in the BIOS Flash to a physical memory address according to the upgrade parameters, and overwriting a historical interrupt handling program corresponding to the interrupt handling program to be upgraded to be regarded as a new interrupt handling program. The present application aims to upgrade the interrupt handling program online.

Techniques are described for interrupt handling. A device can obtain, at a first context buffer associated with a first interrupt handler, first processing configuration data associated with a first sensor; obtain, at a second context buffer associated with a second interrupt handler, second processing configuration data associated with a second sensor; obtain, at the first interrupt handler, an error indication associated with the first sensor; perform, by the first interrupt handler, based on the error indication, an error handling operation (where the error handling operation comprises flushing the first context buffer and / or invalidating the first processing configuration data in the first context buffer); obtain, at the second interrupt handler, during a time window interval between obtaining the error indication and a completion time of the error handling operation, from the second sensor, an interrupt request (IRQ); and output, based on the IRQ, the second processing configuration data to a processor.

Within an interrupt routing structure, an interrupt handler is registered, the registering comprising storing a pointer to the interrupt handler in the interrupt routing structure. Responsive to determining that a received interrupt comprises a queuing bypass flag in a set state, the interrupt handler is executed, the executing bypassing an interrupt queueing mechanism.

The invention relates to a software running method and device. The method is applied to a processor, functional modules of software to be operated are pre-burnt in a kernel of the processor, and the method comprises the steps that data to be processed are received, and a target interrupt processing program is determined in interrupt processing programs according to the type of the data to be processed; based on the target interrupt processing program, determining a target function module in all function modules of the to-be-operated software; and operating a target function module according to the target interrupt processing program indication, wherein the target function module is used for realizing the operation of the to-be-operated software. The method can improve the success rate of the software operation method.

The invention relates to the technical field of data transmission and time service, in particular to a time service information transmission system and method based on a srio network, time service information is acquired from time service equipment according to a time synchronization request, time service information codes are embedded into a doorbell specified field, and a doorbell packet is sent to opposite-end equipment through the srio network. The doorbell packet adopts a doorbell interrupt mechanism to transmit an interrupt processing program between different devices; and receiving a doorbell packet in the srio network through continuous monitoring, analyzing a doorbell specified field and obtaining decoding time service, so as to calibrate the slave end virtual time service by using the decoding time service. The time service information transmission mechanism is adjusted according to the characteristics of the srio interface, the time service information is compressed and embedded into the doorbell info field and sent to the opposite terminal device along with the interruption of the system doorbell, special time service signal wiring is not needed, the slave does not need a time service device, the device cost is saved, wiring is reduced, and the time service precision is improved.

The present invention discloses a method for in-band firmware refresh, an electronic device, a storage medium, and a program product, which relate to the technical field of computer firmware update. By obtaining the firmware layout type of the firmware to be refreshed and the reference layout table of the firmware to be refreshed, in the cache of the current firmware, in-band refresh of the firmware to be refreshed is performed based on the reference layout table. Among them, the current firmware and the firmware to be refreshed are heterogeneous firmwares. By adding a reference layout table for distinguishing heterogeneous firmwares, mutual in-band refresh of heterogeneous firmwares is realized, solving the technical problem that the in-band refresh interrupt handler in the related technology can only refresh firmwares with the same layout, and achieving the technical effects of supporting in-band refresh of heterogeneous firmwares and different firmwares can also support refresh only by changing the structure of the reference layout table.

Techniques are disclosed for enabling programmable control of interrupts [302, 306] at a processing system by a guest virtual machine (VM) [106] using a guest owned backup page [128]. The VM programs a client-owned backup page (e.g., a data structure in memory [103]) that specifies a particular interrupt to be blocked. In response to detecting a specified interrupt, the system hardware or software blocks the interrupt rather than executing an interrupt handler to handle the interrupt. The VM is thus able to protect confidential information and program behavior, while a malicious hypervisor fails to protect the VM from, for example, unexpected or unwanted interruptions is less risk, thereby improving overall system security and predictability.

The invention discloses a method and a device for supporting chip interconnection extensible low-speed peripheral interruption. The method comprises the following steps: extending an address space of a low-speed peripheral interruption register; the number of supported low-speed peripheral interrupts is configured through a low-speed peripheral interrupt register, and the low-speed peripheral interrupts managed by each chip are set; chip connection is configured through a low-speed peripheral interrupt register, and routing configuration information of the chip is generated; when an interrupt controller in the chip detects an interrupt request, the interrupt controller processes the interrupt request after detecting the interrupt request and distributes the interrupt request to a corresponding processor core according to routing configuration information; and the processor core calls the interrupt processing program for processing and returns interrupt confirmation. The invention aims to support the arbitrary configuration of the number of low-speed peripheral interrupts so as to meet the processing requirements of the low-speed peripheral interrupts of different system architectures, and has the advantages of low hardware implementation complexity, small area overhead and high cost performance.

The invention provides a data transmission method which can be applied to the technical field of servers. The data transmission method comprises the steps that a first graphic processing unit writes to-be-transmitted data into a double-rate memory according to a first address, and when data writing is completed, a first rapid calculation link controller is triggered to monitor a first interrupt event that the first address is written into the double-rate memory; the first fast computing link controller packages the first interrupt event and then writes the first interrupt event into the first central processing unit, so that the first address is written into the first central processing unit; the first central processing unit triggers a first interrupt processing program to modify the value of a memory monitoring register in the first central processing unit; and when an application state polling thread associated with the first graphic processing unit in the first central processing unit monitors that the value of the memory monitoring register is modified, the polling thread is interrupted, a second address is inquired according to the first address, and a transmission instruction based on a fast computing link protocol is issued.