74 results about "Network interface controller" patented technology

A coherent, intelligent, packet-switched memory fabric enables predictive, cache-coherent access across distributed compute, accelerator, and memory resources using a Memory-Fabric Transaction Layer Protocol (MF-TLP). MF-TLP defines routable packet formats for read, write, vectorized, atomic, reduction, collective, and predictive-prefetch transactions executed by memory-centric network interface controllers (MC-NICs). Each MC-NIC performs packet parsing, address translation, coherence management, and near-memory arithmetic or tensor operations while coordinating with MF-TLP-aware switches providing hierarchical directory control, multi-path routing, and in-network aggregation. Vectorized and multimodal packets encode multiple addresses or tensor offsets to reduce scatter / gather overhead, and programmable caching and quality-of-service modules manage tiered memory and tenant fairness. MF-TLP supports extension headers for predictive prefetch, collective coordination, and tenant governance, operating across hierarchical leaf-spine topologies using Ultra-Ethernet Transport, InfiniBand, or CXL fabrics. The system delivers scalable, low-latency, memory-centric orchestration for large-language-model training, multimodal AI, and data-intensive analytics.

A network interface controller (NIC) capable of facilitating efficient data request management is provided. The NIC can be equipped with a command queue, a message chopping unit (MCU), and a traffic management logic block. During operation, the command queue can store a command issued via a host interface. The MCU can then determine a type of the command and a length of a response of the command. If the command is a data request, the traffic management logic block can determine whether the length of the response is within a threshold. If the length exceeds the threshold, the traffic management logic block can pace the command such that the response is within the threshold.

The invention discloses a data path structure suitable for cross-domain interaction of high-performance PCIe non-transparent bridge equipment. The data path structure comprises external equipment, an upstream endpoint, a downstream endpoint, a network interface controller connection network, a first bypass module group and a second bypass module group, the external equipment, the upstream endpoint, the network interface controller connection network and the downstream endpoint are sequentially in communication connection, the upstream endpoint and the downstream endpoint are the same in structure, the upstream endpoint is in communication connection with the first bypass module group, and the downstream endpoint is in communication connection with the second bypass module group; and the first bypass module group and the second bypass module group have the same structure. According to the data path structure provided by the invention, through mutual cooperation of the new path and the old path, the overall performance of the non-transparent bridge can be improved, and then the data path structure adapts to high-performance PCIe cross-domain transmission under high load and large flow.

An example apparatus includes a hardware platform having arithmetic circuits and a memory, the memory configured to store, at a first precision, first compressed parameters of a machine learning (ML) model; a network interface controller; and a controller, supported by the hardware platform, configured to: decompress, from the memory through an increase in precision to a second precision, the first compressed parameters to obtain decompressed parameters; control the arithmetic circuits to train, using arithmetic operations, the ML model and update the decompressed parameters; compress, using quantization and reduction in precision to the first precision, the decompressed parameters as updated to obtain second compressed parameters; send, using the network interface controller, the second compressed parameters over a network to a server; and update the first compressed parameters in the memory in response to data received, through the network interface controller, from the server over the network.

A method processes data requests from a requester to a responder over a network by using remote direct memory access. The method includes the requester issuing two or more requests into a work queue of a network interface controller. The method further includes the network interface controller executing the queued requests by sending them to the responder, and receiving responses to the sent request from the responder. One or more given requests each includes dependency information related to the response from the responder to one or more previous requests in the work queue, the method further includes, before executing the given request by the network interface controller, evaluating the dependency information and executing the given request depending on the result of the evaluation.

A computing device includes a system-on-a-chip. The computing device comprises a network interface controller (NIC) that hosts a plurality of virtual functions and physical functions. Two or more compute nodes are coupled to the NIC. Each compute node is configured to operate a plurality of Virtual Machines (VMs). Each VM is configured to operate in conjunction with a virtual function via a virtual function driver. A dedicated VM operates in conjunction with a virtual NIC using a physical function hosted by the NIC via a physical function driver hosted by the compute node. The computing device further comprises a fabric manager configured to own a physical function of the NIC, to bind virtual functions hosted by the NIC to individual compute nodes, and to pool I / O devices across the two or more compute nodes.

The present invention provides a system of trademark surveillance system with image understanding for multi-country and the method thereof, which is implemented by providing a user-operated user electronic device. The user electronic device comprises a second processor and a second network interface controller. A server comprises a second application program. The second processor is connected to the server through the second network interface controller and executes the second application program to perform trademark monitoring, particularly to monitor trademark images by inputting a text description.

An example network interface controller (NIC) includes: first resources configured to supply first traffic; second resources configured to supply second traffic; a load balancer, coupled to the first and second resources, configured to balance the first traffic and the second traffic between first and second port circuits of a link aggregation group (LAG) using a hash function; and remote direct memory access (RDMA) logic configured to, using the hash function, divide work requests into a first set of work requests for first packets that hash to the first port circuit and a second set of work requests for second packets that hash to the second port circuit, the RDMA logic configured to supply the first set of work requests to the first resources and the second set of work requests to the second resources.

The invention relates to one-to-many TCP connection splicing. A computing device includes at least one network interface controller (NIC), a memory, and at least one processor including one or more cores. The NIC (s) receive inbound transmission control protocol (TCP) data packets and transmit outbound TCP data packets. The memory stores a program of instructions that the processor executes to divide a data path within the computing device that includes both a receiving endpoint and a transmitting endpoint into a first path and a second path. In response to determining that the first inbound TCP data packet is associated with the established TCP connection and the data stitching group, the processor assigns the first inbound TCP data packet to the first path and assigns a second inbound TCP data packet that is not assigned to the first path to the second path. The processor performs a one-to-many data stitching of payload data from the first inbound TCP data packet to the outbound TCP data packet using the first path.

In one embodiment, a method is disclosed, comprising: receiving a packet; processing the packet in a Control Unit–User Plane (CU-UP) as a user-space application with kernel-bypass networking; performing packet Input / Output (I / O) by the CU-UP user-space application, wherein the CU-UP performs Internet Protocol (IP) validation on received user-plane packets before processing Packet Data Convergence Protocol (PDCP), Service Data Adaptation Protocol (SDAP) and General Packet Radio Service Tunnelling Protocol (GTPU) protocol stack and performing direct I / O to a Network Interface Controller (NIC) for sending the packet over a network to a Distributed Unit (DU). The method may further comprise using a containerized CU-UP. The method may further comprise using a plurality of worker threads. The method may further comprise using a polling user space networking accelerator framework.

The present disclosure relates to DPU infrastructure management. In one embodiment, a system includes a plurality of host computers, a plurality of data processing units (DPUs), each DPU including a network interface controller (NIC) and a processing core, each DPU connected to a respective host computer, and at least one management node to provision software on the processing core of each DPU and to synchronize a lifecycle of each DPU with a lifecycle of the respective host computer during provisioning of the software.

An electronic device may include a communication module for exchanging data with an external device, and at least one processor for controlling the electronic device, wherein the processor may: receive first information regarding the state of a network interface controller (NIC) driver for the communication module; receive, as second information, at least a part of simple network management protocol (SNMP) information regarding a network stack; receive third information regarding the state of sockets; determine a target problem state of the electronic device on the basis of the first information, the second information, and the third information; and perform a preconfigured target recovery operation corresponding to the determined target problem state.

Encryption operations are securely offloaded to a network interface controller (NIC). Encryption keys are securely transferred from a virtual machine (VM) to the NIC and data is securely transferred from encrypted VM memory to secure buffers in the NIC. The NIC handles the encryption and decryption operations in hardware, greatly increasing encryption performance while not reducing security. This is especially useful in cloud server environments, so the cloud service provider does not have access to the encryption keys or the unencrypted data. The offloaded operations are performed with numerous different communication protocols, including RDMA, QUIC, IPsec underlay and WireGuard.

The invention relates to resource management in a network interface controller with hardware link aggregation. An example network interface controller (NIC) includes a first resource configured to provision a first traffic; a second resource configured to provision a second traffic; a load balancer, coupled to the first resource and the second resource, configured to balance the first traffic and the second traffic between a first port circuit and a second port circuit of a link aggregation group (LAG) using a hash function; and a remote direct memory access (RDMA) logic configured to divide a work request into a first set of work requests for a first data packet hashed to the first port circuit and a second set of work requests for a second data packet hashed to the second port circuit using the hash function, the RDMA logic is configured to provision the first set of work requests to the first resource and the second set of work requests to the second resource.

Systems and methods transfer video data to an image processing system from a video source. Pixel data is received in a local buffer of a network interface controller and provided in a video transport packet. The video transport packet includes the pixel data, a media access control header and a video header. The video transport packet is received by another network interface controller that provides the pixel data directly into a video frame buffer of the image processing system.

This disclosure relates to systems and methods for facilitating efficient load balancing in a network interface controller (NIC). A network interface controller (NIC) capable of efficient load balancing across hardware engines is provided. The NIC may be equipped with multiple ordering control units (OCUs), queues, selection logic blocks, and allocation logic blocks. The selection logic block can determine an OCU from the multiple OCUs for commands from the queues, which may store one or more commands. The allocation logic block then determines selection settings for the OCU, selects an egress queue based on the selection settings for the command, and sends the command to the egress queue.

Apparatuses, systems, methods, and techniques to perform graphics processing unit (GPU) initiated networking (GIN). In at least one embodiment, generation of a work queue element (WQE) is offloaded from the GPU to separate hardware (e.g., an accelerator or processor in a network interface controller). In at least one embodiment, the GPU generates a GPU-friendly descriptor (GFD), instead of a WQE, that contains information to create a WQE and transfers the GFD to the separate hardware, which performs the creation of the WQE, processes a completion queue entry (CQE), and provides a notification to the GPU that processing the WQE has been completed.

A method is disclosed for managing network communication in a virtual machine hosting computer system with nested child partitions. The method involves loading a network driver in a level-one child partition and creating a virtual switch within the level-one child partition. The virtual switch establishes a synthetic data path between a synthetic network adapter offered by a root partition and a network driver in a level-two child partition. A network interface controller (NIC) switch capability is exposed to the virtual switch, and a peripheral component interconnect express (PCIe) virtual function offered by the root partition is passed from the level-one child partition to the level-two child partition, enabling the level-two child partition to take advantage of the PCIe virtual function.

A computing apparatus (402, 502, 602) configured for Remote Direct Memory Access (RDMA) is provided. The computing apparatus (402, 502, 602) includes a Network Interface Controller (NIC) (410, 704), a memory (408, 508, 708), and a controller (412). The controller (412) is configured to receive an RDMA request (702), determine that the request carries immediate data, and, in response, obtain a memory address to write to. The controller (412) writes the immediate data to the memory (408, 508, 708) using Direct Memory Access (DMA) to the memory address without placing the data in a Receive Queue (RQ). The apparatus facilitates faster data transfer by bypassing the typical queuing process for immediate data, thereby reducing latency during RDMA operations.

A Baseboard Management Controller (BMC) / multi-Graphics Processing Unit (GPU) monitoring / management system includes a computing device having a GPU system with a plurality of GPUs, and a BMC device coupled to the GPU system via a Universal Serial Bus-Network Interface Controller (USB-NIC) path and an Inter-Integrated Circuit (I2C) path. The BMC device performs first log collection operations and inventory operations via the USB-NIC path with the GPU system during initialization of the computing device. During runtime of the computing device that follows the initialization of the computing device, the BMC device performs sensor monitoring operations with the GPU system via the I2C path. During runtime of the computing device, the BMC device performs second log collection operations with the GPU system via the USB-NIC path, and will perform firmware update operations with the GPU system via the USB-NIC path in response to receiving a firmware update request.

An optical switching network is presented. The optical switching network 1000 includes a plurality of switch devices 100 and a plurality of hosts 200. Each host comprises at least one network interface controller. A network data plane and a network control plane are distributed among the plurality of hosts and the plurality of switch devices forming the network. The network interface controller is configured to provide network protocol information to the network data plane and control information to the network control plane for routing optical data to be transmitted between a source host and a destination host among the plurality of hosts.

The present disclosure relates to converging to enable congestion management. A network interface controller (NIC) that facilitates incast management at a computing system is provided. During operation, the NIC can receive a request to send data from a remote computing system via a network. The NIC can determine that the request is one of a plurality of requests from a plurality of remote computing systems that are accessible via the network. Based on a descriptor in the request, the NIC can determine a storage location of the data at the remote computing system. Then, the NIC can determine a degree of congestion at the computing system associated with the plurality of requests. The NIC can schedule data retrieval in response to the request based on the degree of congestion and with respect to the plurality of requests. Then, the NIC can retrieve the data from the storage location based on remote access.

In certain implementations, a method includes receiving, by a network interface controller (NIC), a request for inter-process communication associated with a sending process of a distributed application. The request includes a logical network address for a destination process of the distributed application. The method includes executing, by the NIC, a network address translation process to translate the logical network address for the destination process to a translated network address for the destination process. The network address translation process includes executing, using a first portion of the logical network address, a lookup of a network address translation table to determine a first address; determining a translation modifier by executing a translation algorithm using a second portion of the logical network address; and determining the translated network address using the first address and the translation modifier. The method includes processing, by the NIC, a first message using the translated network address.

A data processing system and method include an in-line network compute platform. A network interface controller receives, via a plurality of receiving pathways, data across a data communication network. The network interface controller performs inspection of the received data and identifies respective endpoint nodes to receive at least some of the received data, wherein the endpoint nodes are comprised in a parallel compute array. The network interface controller parses, as a function of the respective endpoint nodes, the at least some of the received data and normalizes, as a function of the respective endpoint nodes, the parsed at least some of the received data. Further the network interface controller routes the normalized, parsed at least some of the data from the network path panel to the respective endpoint nodes within the parallel array. The network interface controller and the parallel compute array are comprised in the in-line network compute platform.

A computer is configured to execute network file system (NFS) client software, and issue NFS commands to an NFS server along with checksums that are used by the NFS server to verify the integrity of remote procedure call (RPC) packets that include the NFS commands, by performing the steps of: computing a first checksum of a first RPC packet by applying a checksum algorithm to the first RPC packet, wherein the first RPC packet includes a first NFS packet, the first NFS packet including an NFS command to be performed by the NFS server; inserting the first checksum into the first RPC packet; creating a first transmission control protocol (TCP) packet that includes the first RPC packet having the first checksum inserted therein; and transmitting the first TCP packet to the NFS server over a network using a network interface controller (NIC).

A computing device includes at least one network interface controller (NIC), a memory, and at least one processor including one or more cores. The NIC(s) receive inbound Transmission Control Protocol (TCP) packets and transmit outbound TCP packets. The memory stores a program of instructions, which the processor executes to split a datapath including both receive endpoints and transmit endpoints within the computing device into a first path and a second path. The processor assigns first inbound TCP packets to the first path in response to determining that the first inbound TCP packets are associated with an established TCP connection and a data splicing group, and assigns second inbound TCP packets not assigned to the first path to the second path. The processor uses the first path to perform one-to-many data splicing of payload data from the first inbound TCP packets into the outbound TCP packets.

A network interface controller (NIC) circuit may control data transfers between a network interface and a memory interface circuit. The NIC circuit receives data packets on the network interface and determines whether a packet type of a data packet corresponds to one of a first plurality of operations or a second plurality of operations. For data packets that correspond to one of the first plurality of operations, the NIC circuit controls the memory interface circuit according to the packet type and for data packets that correspond to one of the second plurality of operations, the NIC sends a notification to a processor circuit in the IC to execute software instructions to control the memory interface circuit according to the packet type. The NIC circuit quickly processes data packets corresponding to the first plurality of operations without software involvement but relies on software assistance for the second plurality of operations.

The present disclosure is directed to devices and techniques for auto-qualifying images on new hardware or infrastructure configurations. The systems and methods include initiating an auto-qualification process for pre-testing one or more images registered within a bare metal system having one or more new infrastructure configurations, discovering all of the one or more images registered for use within the bare metal system, booting each of the one or more registered images into an isolated infrastructure having the one or more new infrastructure configurations, probing instances of each of the one or more registered images booted on the isolated infrastructure to determine stability of each of the one or more registered images on the one or more new infrastructure configurations, and marking each of the one or more registered images as stable or unstable.

The invention relates to a hardware architecture simulation tool oriented to system-level chip interconnection optimization, which is characterized in that a processor core, a cache controller, a memory controller and an on-chip interconnection network model with an accurate period are integrated in a full-system joint simulation framework, and the conversion between a cache consistency message and an interconnection data unit is realized through a network interface controller; network delay is fed back to a system simulation scheduler with cycle-level precision, an interconnection network adopts a router micro-architecture with an accurate cycle for modeling, key stages such as buffering, routing, virtual channel distribution, switch distribution and link traversal are finely depicted, and virtual channel flow control and a point-to-point sorting mechanism are combined, so that the routing efficiency is improved. And a power consumption analysis model based on activity counting is introduced, and the dynamic power consumption and the static leakage power consumption of the interconnection network are accurately evaluated. According to the application, various network topologies, routing strategies and hardware parameter configurations are supported, and the comprehensive influence of the interconnection architecture on the performance and energy efficiency of the chip is accurately evaluated at the system level.

Computing device (100) for timestamping data packets, the computing device comprising the following: a processor (102); a memory (104); and a network interface controller (110) to perform the following: Receiving data from another component of the computing device (302); Inserting one or more alignment markers into the data (304); Identifying a trigger pattern in the data after the insertion of one or more alignment markers (310); Triggering a timestamp according to the detection of the trigger pattern (312); and Sending the data to a remote computing device (330).