141results about "Cache memory details" patented technology

A cache writeback circuit is disclosed for writing back, without invalidating, dirty cache lines. The cache writeback circuit is configured to enter an active state based on detecting a trigger condition indicative of cache misses to a memory cache circuit within a memory hierarchy of a computer memory subsystem causing cache line eviction activity. During the active state, the cache writeback circuit is configured to identify a set of dirty cache lines in the memory cache circuit, and write back, without invalidating, cache lines of the identified set of dirty cache lines from the memory cache circuit to a memory circuit within a lower level of the memory hierarchy, such as DRAM. The cache writeback circuit may further be configured to identify the dirty cache lines via a cache walk operation, which can be suspended, for example, when a higher-priority cache operation occurs.

A prediction unit (PRU) predicts a sequence of fetch blocks (FBlks). Branch predictors provide, in response to a FBlk start address (FBSA) lookup in combination with branch history state (BHS), information to predict branch history update information (BHUI) produced by the FBlk. A buffer stores accumulated BHUJ. A macro-op (MOP) cache (MOC) includes an unrolled loop multi-FBlk MOC entry (ULP-MF-ME) built from previously observed occurrences of a loop on a loop body of FBlks. A hit on the ULP-MF-ME predicts a current occurrence of a loop on the loop body. In parallel, for N initial iterations of the loop, the PRU updates the BHS with BHUI produced by each FBlk of the N initial iterations using information provided in response to a lookup and accumulates each BHUI into the buffer. The PRU updates the BHS using the accumulated BHUI for subsequent iterations of the loop to avoid more lookups.

Various embodiments include techniques for managing cache memory in a computing system. The disclosed techniques include a cache policy manager that monitors activity of various components that access a common cache memory. The cache policy manager establishes cache rules that determine what data remains stored in cache memory and what data is removed from cache memory in order to make room for new data. As the activities of these components change over time, cache rules that work well for a previous activity profile may no longer work well for the current activity profile. Therefore, the cache policy manager dynamically modifies the cache rules as the activity profile changes in order to select cache rules at any given time that work well with the current activity profile. These techniques are advantageous over conventional approaches that employ static cache rules that work well only for specific activity profiles.

implemented method, system, and computer program product for minimizing the effects of cache thrashing involving non-temporal workloads. The cache activities of a workload, including the cache activities (e.g., number of cache hits) involving local and peer caches, are monitored. Based on analyzing the metrics of such monitored cache activities, a determination is made as to whether a non-temporal workload is identified. For example, such a determination may be based on comparing the metrics of the monitored cache activities of the workload to a threshold value. Upon identifying a non-temporal workload, the cache line(s) associated with the non-temporal workload are identified. The persistence policy for the identified cache line(s) is then altered. For example, the persistence policy for the identified cache line(s) may be altered by reducing the tenure of such a cache line(s) thereby reducing the number of cache misses or evictions and minimizing the effects of cache thrashing.

Techniques are provided for implementing a persistent key-value store for caching client data, journaling, and / or crash recovery. The persistent key-value store may be hosted as a primary cache that provides read and write access to key-value record pairs stored within the persistent key-value store. The key-value record pairs are stored within multiple chains in the persistent key-value store. Journaling is provided for the persistent key-value store such that incoming key-value record pairs are stored within active chains, and data within frozen chains is written in a distributed manner across distributed storage of a distributed cluster of nodes. If there is a failure within the distributed cluster of nodes, then the persistent key-value store may be reconstructed and used for crash recovery.

Provided are systems, methods, and apparatuses for assisted cache data placement. In one or more examples, systems, methods, and apparatuses include assigning a first identifier to first data based on an aspect of the first data, the first data being data moved from a cache and assigning a second identifier to second data based on an aspect of the second data, the second data being moved to a storage device based on a policy of the cache. In one or more examples, systems, methods, and apparatuses include storing the first data in a first storage location of the storage device based on the first identifier and storing the second data in a second storage location of the storage device based on the second identifier.

If sufficient memory resources are allowed access, components on an IC chip can operate faster or provide higher performance relative to power consumption. However, if each component is provided with its own memory, the chip becomes expensive. In the described implementation, memory is shared among two or more components (110, 114, 116). For example, a processing component (116) may include computing circuitry (206) and memory (106) coupled thereto. A multi-component cache controller (114) is coupled to memory (106). Logic circuitry (202) is coupled to the cache controller (114) and memory (106). The logic circuitry (202) selectively divides memory (106) into multiple memory partitions (108). A first memory partition (108-1) may be allocated to computing circuitry (206) and provide storage for computing circuitry (206). A second memory partition (108-2) may be allocated to the cache controller (114) and provide storage for multiple components (110). The relative capacity of memory partitions is adjustable to accommodate fluctuating demand without having to dedicate separate memory to a component.

A system and a method are disclosed. The method includes the steps of storing a first portion of a first compressed tile in a first cache line of a cache storage device, and storing a second portion of the first compressed tile in a second cache line of a cache storage device.

A data processor includes a data fabric, a memory controller, a last level cache, and a traffic monitor. The data fabric is for routing requests between a plurality of requestors and a plurality of responders. The memory controller is for accessing a volatile memory. The last level cache is coupled between the memory controller and the data fabric. The traffic monitor is coupled to the last level cache and operable to monitor traffic between the last level cache and the memory controller, and based on detecting an idle condition in the monitored traffic, to cause the memory controller to command the volatile memory to enter self-refresh mode while the last level cache maintains an operational power state and responds to cache hits over the data fabric.

A system and method for caching in storage devices. In some embodiments, the method includes: opening a first file, by a first thread; reading a first page of data, from the first file, into a page cache in host memory of a host; adding, to a first data structure, a first pointer, the first pointer pointing to the first page of data; opening a second file, by a second thread; reading a second page of data, from the second file, into the page cache; and adding, to the first data structure, a second pointer, the second pointer pointing to the second page of data.

To provide a method and system for automatically instrumenting a web application.SOLUTION: The method identifies that a web application includes an event triggered by a user interaction, logs tracing information based on execution of a first set of operations caused by the event, associates the event with a tracer that obtains a first measurement of performance of a first span, identifies in code that the execution of the first set of operations causes a request to be made to a server, and associates the request with the tracer. The tracer logs tracing information based on the execution of the second set of operations caused by the request to obtain a second measurement of performance of a second span that is a child span of the first span.SELECTED DRAWING: Figure 2

Systems for fast views of items in file directories or file folders when interacting with a cloud-based service platform. A server in a cloud-based environment interfaces with one or more storage devices to provide storage of shared content accessible by two or more user devices. A file tree request to view the file directory or file folder of a particular sought after item is issued from an application operating on one of the user devices. Additional file tree items in a file tree hierarchy are prefetched by the cloud-based service platform. The application closes the file tree metadata stream after receiving the portion of the file tree that pertains to the particular item and before receiving the entirety of the metadata pertaining to all of the file tree metadata of all of the items in the directory or folder that contains the particular sought after item.

This application is directed to notebook memory in a cache. An apparatus can operate a portion of volatile memory in a cache mode having non-deterministic latency for servicing requests of a host device. The apparatus can monitor a register having an output pin associated with the portion and indicative of a mode of operation of the portion. Based on or in response to monitoring the output pin, the apparatus can determine whether to change the mode of operation of the portion from the cache mode to a notebook mode having deterministic latency for servicing requests of the host device.

An electronic control unit in which a plurality of workloads are identified from execution of a runtime application, where each identified workload is associated with a set of cache lines of a cache resource. A priority designation of the set of cache lines is determined based at least in part on a usage of the set of cache lines during an upcoming time interval. In examples, the usage is based at least in part on memory access operations that are expected to be performed by the plurality of workloads during the upcoming time interval.

Examples described herein relate to a cache fabric that includes a set of routers of a first tier and a plurality of cache controller clusters of a second tier. A router of the set of routers is accessible via an interface to receive a memory access request from a processor and select from a set of cache controllers based on a cluster identifier and a memory address, and provide the memory access request to the selected set of cache controllers. The selected set of cache controllers may receive memory access requests and serve memory access requests from the cache device, or forward memory access requests to a second cache controller or second cache device associated with the cache device.

Graphics processor (2) comprises a programmable execution unit (65) executing programs to perform graphics processing and a machine learning (ML) processing circuit (78) (e.g. neural processing accele

A total count for an address mapping table is maintained, wherein the total count reflects a total number of updates to the address mapping table, and wherein the address mapping table comprises a plurality of sections. Respective section counts for the plurality of sections are maintained, wherein each respective section count reflects a total number of updates to a corresponding section. It is determined that the total count for the address mapping table satisfies a threshold criterion. A first section of the plurality of sections with a highest section count is identified based on the respective section counts. The first section of the address mapping table is written to a non-volatile memory device.

A memory sub-system controller performs garbage collection on flexible data placement (FDP) compliant memory sub-systems, such as solid state drives (SSDs). The controller stores a set of data across a plurality of memory components of a set of memory components, a first of the plurality of components being configured to store data in a first set of regions using a first write cursor, and a second of the plurality of components being configured to store data in a second set of regions using a second write cursor. The controller programs data, received from a host system, in a first portion of the first set of regions using the first write cursor. The controller relocates previously programmed data from a second portion of the first set of regions to the first portion of the first set of regions using the first write cursor.

A memory system includes a volatile memory device; a non-volatile memory device; and a processing device, operatively coupled with the volatile memory device and the non-volatile memory device, to perform operations including retrieving data stored in a set of source management units on the non-volatile memory device; storing the data in a set of cache management units on the volatile memory device in a predefined order of the set of cache management units; and sending the data in the predefined order to a set of destination management units on the non-volatile memory device.

A host device and a method of operating a host device are provided. The host device includes a cache configured to temporarily store data copied from a main memory, and a processor configured to process data read from the cache. The cache includes a plurality of ways, wherein each of the plurality of ways has an area distinguished by a plurality of indexes, the data includes first data, and the plurality of indexes includes a first index. The processor includes a cache management circuit configured to generate the first index by using a first adaptive matrix and a first vector, wherein the first adaptive matrix is based on upper bits of a first address corresponding to the first data, and the first vector is based on lower bits of the first address, and manage the first data to be temporarily stored in an empty area among areas corresponding to the first index in the plurality of ways.

This application is directed to writing data in a memory device supporting multiple bits per cell by dynamically using a y-level cell (YLC) cache. The memory device is coupled into a host device, and includes a plurality of x-level cell (XLC) memory blocks, where x is greater than one and greater than y. The memory device identifies a write shaping status of the host device. Based on the write shaping status, the memory device determines that the host device performs write operations without a memory-based cache. In accordance with a determination that the host device performs write operations without the memory-based cache, a YLC cache is allocated in the memory device to act as the memory-based cache. In response to one or more write requests, the memory device stores data into the plurality of XLC memory blocks via the YLC cache.

A method may include accessing a cache storing a graph index corresponding to a graph data in response to a transaction operating on the graph data. A cache miss triggered by a change to the underlying graph data may be detected. In response to detecting the cache miss, the graph index may be updated by at least replaying or rewinding one or more other changes made to the graph data by one or more other transactions between a first time of the transaction and a second time of a current version of the graph index in the cache. The graph index may be updated to avoid a full rebuild of the graph index. The transaction may be executed based on the updated graph index. Related systems and computer program products are also provided.

The embodiment of the invention relates to a method, equipment and a computer program product for writing data into a disk array in a storage system. The storage system includes a disk array. A method includes, in response to receiving a write request to write new data to a data block in at least one disk array group in a degraded mode of a disk array, reading old data stored in the data block and old check information stored in a check block associated with the data block. The method further includes determining new check information associated with the new data based on the old data, the old check information, and the new data. The method further includes writing the new data and the new check information into at least one cache page provided by a cache component in the storage system, the at least one cache page being allocated in a persistent memory in the cache component. In addition, the method further comprises the step of flushing new data and new verification information into the data blocks and the verification blocks in the at least one disk array group respectively.

An apparatus includes a central processing unit (CPU) coupled to a system-on-a-chip (SOC) interconnect. The apparatus also includes multiple logic structures coupled to a memory. The apparatus further includes a safety mechanism coupled to and inline with the memory, the logic structures, and the CPU via the SOC interconnect. The safety mechanism comprises a meta cache and is configured to detect errors in one or more of the logic structures and the memory.

A method of cache management, the method comprising: identifying, among a plurality of storage items, storage items having an access count above a first threshold to generate a set of storage items; identifying, among the set of storage items, storage items having an updated access count above a second threshold to generate a subset of storage items, wherein, for each storage item, the updated access count is dependent upon a number of accesses subsequent to generating the set of storage items; and adding the storage items of the subset of storage items to a cache.

Methods and apparatus relating to techniques for multi-tile memory management. In an example, a graphics processor includes an interposer, a first chiplet coupled with the interposer, the first chiplet including a graphics processing resource and an interconnect network coupled with the graphics processing resource, cache circuitry coupled with the graphics processing resource via the interconnect network, and a second chiplet coupled with the first chiplet via the interposer, the second chiplet including a memory-side cache and a memory controller coupled with the memory-side cache. The memory controller is configured to enable access to a high-bandwidth memory (HBM) device, the memory-side cache is configured to cache data associated with a memory access performed via the memory controller, and the cache circuitry is logically positioned between the graphics processing resource and a chiplet interface.

A method is provided that includes performing, by a processor in response to a vector matrix multiply instruction, multiplying an m×n matrix (A matrix) and a n×p matrix (B matrix) to generate elements of an m×p matrix (R matrix), and storing the elements of the R matrix in a storage location specified by the vector matrix multiply instruction.