Patents
Literature
255results about "Cache memory details" patented technology
Efficacy Topic
Property
Owner
Technical Advancement
Application Domain
Technology Topic
Technology Field Word
Patent Country/Region
Patent Type
Patent Status
Application Year
Inventor
Cache writeback circuit
ActiveUS12524344B1Memory architecture accessing/allocationMemory adressing/allocation/relocationMemory hierarchyComputer architecture
A cache writeback circuit is disclosed for writing back, without invalidating, dirty cache lines. The cache writeback circuit is configured to enter an active state based on detecting a trigger condition indicative of cache misses to a memory cache circuit within a memory hierarchy of a computer memory subsystem causing cache line eviction activity. During the active state, the cache writeback circuit is configured to identify a set of dirty cache lines in the memory cache circuit, and write back, without invalidating, cache lines of the identified set of dirty cache lines from the memory cache circuit to a memory circuit within a lower level of the memory hierarchy, such as DRAM. The cache writeback circuit may further be configured to identify the dirty cache lines via a cache walk operation, which can be suspended, for example, when a higher-priority cache operation occurs.
Owner:APPLE INC
Redundant parallel computing structures as a cache
PendingUS20250284638A1Memory architecture accessing/allocationImage memory managementComputer hardwareComputer architecture
An apparatus to facilitate redundant parallel computing structures as a cache is disclosed. The apparatus includes redundant parallel computing hardware circuitry comprising redundant sets of computing combinatorial logic and register-based storage circuitry; and crossbar fabric connected to the registers of the redundant parallel computing hardware circuitry, wherein the crossbar fabric to cause register state of the register-based storage circuitry to be selected based on a tagged cache model.
Owner:INTEL CORP
Systems and methods of cache data placement
ActiveUS20250265190A1Memory architecture accessing/allocationCache memory detailsEngineeringData placement
Provided are systems, methods, and apparatuses for assisted cache data placement. In one or more examples, systems, methods, and apparatuses include assigning a first identifier to first data based on an aspect of the first data, the first data being data moved from a cache and assigning a second identifier to second data based on an aspect of the second data, the second data being moved to a storage device based on a policy of the cache. In one or more examples, systems, methods, and apparatuses include storing the first data in a first storage location of the storage device based on the first identifier and storing the second data in a second storage location of the storage device based on the second identifier.
Owner:SAMSUNG ELECTRONICS CO LTD
Method of reducing cache thrashing in a processing system and related processing system
PendingUS20250252057A1Memory architecture accessing/allocationCache memory detailsComputer architectureParallel computing
A method of reducing cache thrashing in a processing system is provided. M threads are issued to process a workload, and a memory access request associated with the M threads is transmitted to a first-level cache of the processing system. The memory access request is then transmitted to a second-level cache of the processing system in response to the first cache miss at the first-level cache. The memory access request is transmitted to a main memory of the processing system in response to the second cache miss at the second-level cache. The value of M is decreased when the relationship between the hit rates of the second-level cache and the first-level cache satisfies a predetermined criterion. A storage capacity and an access latency of the second-level cache are higher than those of the first-level cache.
Owner:MEDIATEK INC
REDUNDANT PARALLEL COMPUTING STRUCTURES AS A CACHE
PendingDE102025107980A1Memory architecture accessing/allocationResource allocationComputer hardwareComputer architecture
A device for enabling redundant parallel computing structures as a cache is disclosed. The device includes redundant parallel computing hardware circuitry comprising redundant sets of combinational computing logic and register-based storage circuitry; and a crossbar fabric connected to the registers of the redundant parallel computing hardware circuitry, wherein the crossbar fabric causes the register state of the register-based storage circuitry to be selected based on a tagged cache model.
Owner:INTEL CORP
Redundant parallel computing structure as cache
PendingCN120634830AMemory architecture accessing/allocationImage memory managementCrossbar switchComputer architecture
The subject matter of the invention is a redundant parallel computing structure as a cache. An apparatus for facilitating a redundant parallel computing fabric as a cache is disclosed. The device comprises a redundant parallel computing hardware circuit module, wherein the redundant parallel computing hardware circuit module comprises computing combinatorial logic and a redundant set of register-based storage circuit modules; and a crossbar fabric connected to the registers of the redundant parallel computing hardware circuit module, where the crossbar fabric is to cause the tag-based cache model to select the register state of the register-based memory circuit module.
Owner:INTEL CORP
Prediction unit that predicts branch history update information produced by multi-fetch block macro-op cache entry
ActiveUS12487926B1Memory architecture accessing/allocationMemory adressing/allocation/relocationComputer engineeringReal-time computing
A prediction unit (PRU) predicts a sequence of fetch blocks (FBlks). Branch predictors provide, in response to a FBlk start address (FBSA) lookup in combination with branch history state (BHS), information to predict branch history update information (BHUI) produced by the FBlk. A buffer stores accumulated BHUJ. A macro-op (MOP) cache (MOC) includes an unrolled loop multi-FBlk MOC entry (ULP-MF-ME) built from previously observed occurrences of a loop on a loop body of FBlks. A hit on the ULP-MF-ME predicts a current occurrence of a loop on the loop body. In parallel, for N initial iterations of the loop, the PRU updates the BHS with BHUI produced by each FBlk of the N initial iterations using information provided in response to a lookup and accumulates each BHUI into the buffer. The PRU updates the BHS using the accumulated BHUI for subsequent iterations of the loop to avoid more lookups.
Owner:VENTANA MICRO SYSTEMS INC
Efficient key-value cache management for large language models
Owner:HEWLETT PACKARD ENTERPRISE DEV LP
Managing a programmable cache control mapping table in a system level cache
ActiveUS12511234B2Memory architecture accessing/allocationCache memory detailsParallel computingComputing systems
Various embodiments include techniques for managing cache memory in a computing system. The disclosed techniques include a cache policy manager that monitors activity of various components that access a common cache memory. The cache policy manager establishes cache rules that determine what data remains stored in cache memory and what data is removed from cache memory in order to make room for new data. As the activities of these components change over time, cache rules that work well for a previous activity profile may no longer work well for the current activity profile. Therefore, the cache policy manager dynamically modifies the cache rules as the activity profile changes in order to select cache rules at any given time that work well with the current activity profile. These techniques are advantageous over conventional approaches that employ static cache rules that work well only for specific activity profiles.
Owner:NVIDIA CORP
System and method for cache management of tiered storage devices
PendingCN120469627AMemory architecture accessing/allocationInput/output to record carriersComputer architectureEngineering
Owner:SAMSUNG ELECTRONICS CO LTD
Minimizing effects of cache thrashing by altering a persistence policy for non-temporal workloads
implemented method, system, and computer program product for minimizing the effects of cache thrashing involving non-temporal workloads. The cache activities of a workload, including the cache activities (e.g., number of cache hits) involving local and peer caches, are monitored. Based on analyzing the metrics of such monitored cache activities, a determination is made as to whether a non-temporal workload is identified. For example, such a determination may be based on comparing the metrics of the monitored cache activities of the workload to a threshold value. Upon identifying a non-temporal workload, the cache line(s) associated with the non-temporal workload are identified. The persistence policy for the identified cache line(s) is then altered. For example, the persistence policy for the identified cache line(s) may be altered by reducing the tenure of such a cache line(s) thereby reducing the number of cache misses or evictions and minimizing the effects of cache thrashing.
Owner:INTERNATIONAL BUSINESS MACHINE CORPORATION
Converting a stream of data using a lookaside buffer
ActiveUS12461746B2Memory architecture accessing/allocationRegister arrangementsComputational scienceParallel computing
A stream of data is accessed from a memory system by an autonomous memory access engine, converted on the fly by the memory access engine, and then presented to a processor for data processing. A portion of a lookup table (LUT) containing converted data elements is preloaded into a lookaside buffer associated with the memory access engine. As the stream of data elements is fetched from the memory system each data element in the stream of data elements is replaced with a respective converted data element obtained from the LUT in the lookaside buffer according to a content of each data element to thereby form a stream of converted data elements. The stream of converted data elements is then propagated from the memory access engine to a data processor.
Owner:TEXAS INSTRUMENTS INC
Persistent key-value store and journaling system
PendingUS20260010475A1Memory architecture accessing/allocationInput/output to record carriersEngineeringClient data
Techniques are provided for implementing a persistent key-value store for caching client data, journaling, and / or crash recovery. The persistent key-value store may be hosted as a primary cache that provides read and write access to key-value record pairs stored within the persistent key-value store. The key-value record pairs are stored within multiple chains in the persistent key-value store. Journaling is provided for the persistent key-value store such that incoming key-value record pairs are stored within active chains, and data within frozen chains is written in a distributed manner across distributed storage of a distributed cluster of nodes. If there is a failure within the distributed cluster of nodes, then the persistent key-value store may be reconstructed and used for crash recovery.
Owner:NETAPP INC
Systems and methods of cache data placement
ActiveUS12602323B2Memory architecture accessing/allocationMemory adressing/allocation/relocationEngineeringData placement
Provided are systems, methods, and apparatuses for assisted cache data placement. In one or more examples, systems, methods, and apparatuses include assigning a first identifier to first data based on an aspect of the first data, the first data being data moved from a cache and assigning a second identifier to second data based on an aspect of the second data, the second data being moved to a storage device based on a policy of the cache. In one or more examples, systems, methods, and apparatuses include storing the first data in a first storage location of the storage device based on the first identifier and storing the second data in a second storage location of the storage device based on the second identifier.
Owner:SAMSUNG ELECTRONICS CO LTD
Vector based matrix multiplication
ActiveUS12450165B2Program initiation/switchingComputation using non-contact making devicesSoftware engineeringB matrix
A method is provided that includes performing, by a processor in response to a vector matrix multiply instruction, multiplying an m×n matrix (A matrix) and a n×p matrix (B matrix) to generate elements of an m×p matrix (R matrix), and storing the elements of the R matrix in a storage location specified by the vector matrix multiply instruction.
Owner:TEXAS INSTRUMENTS INC
Streaming engine with separately selectable element and group duplication
PendingUS20250315381A1Memory architecture accessing/allocationRegister arrangementsDigital dataAddress generator
A streaming engine employed in a digital data processor specifies a fixed read only data stream defined by plural nested loops. An address generator produces address of data elements. A steam head register stores data elements next to be supplied to functional units for use as operands. An element duplication unit optionally duplicates data element an instruction specified number of times. A vector masking unit limits data elements received from the element duplication unit to least significant bits within an instruction specified vector length. If the vector length is less than a stream head register size, the vector masking unit stores all 0's in excess lanes of the stream head register (group duplication disabled) or stores duplicate copies of the least significant bits in excess lanes of the stream head register.
Owner:TEXAS INSTRUMENTS INC
Method and apparatus for vector sorting using vector permutation logic
ActiveUS12436895B2Program initiation/switchingComputation using non-contact making devicesControl vectorAlgorithm
A processor and a vector sort instruction for the processor to execute are provided, in which the vector sort instructions includes instructions for comparing a first element of a set of vector elements of a vector to a remainder of the set of vector elements; determining, based on the comparing, a control vector that specifies a respective sorted position for each element of the set of vector elements; and reordering the set of vector elements based on the control vector.
Owner:TEXAS INSTRUMENTS INC
Memory sharing
ActiveCN114402304BMemory architecture accessing/allocationCache memory detailsComputer architectureHemt circuits
If sufficient memory resources are allowed access, components on an IC chip can operate faster or provide higher performance relative to power consumption. However, if each component is provided with its own memory, the chip becomes expensive. In the described implementation, memory is shared among two or more components (110, 114, 116). For example, a processing component (116) may include computing circuitry (206) and memory (106) coupled thereto. A multi-component cache controller (114) is coupled to memory (106). Logic circuitry (202) is coupled to the cache controller (114) and memory (106). The logic circuitry (202) selectively divides memory (106) into multiple memory partitions (108). A first memory partition (108-1) may be allocated to computing circuitry (206) and provide storage for computing circuitry (206). A second memory partition (108-2) may be allocated to the cache controller (114) and provide storage for multiple components (110). The relative capacity of memory partitions is adjustable to accommodate fluctuating demand without having to dedicate separate memory to a component.
Owner:GOOGLE LLC
Anti-side channel sharing GPU cache when using physical addressing
One embodiment provides a graphics processor comprising a memory interface, a processing resource cluster comprising a plurality of processing resources, and a cache coupled with the memory interface and the processing resource cluster. In one embodiment, a cache includes an anti-side-channel circuit module to configure an anti-side-channel setting for the cache. In one embodiment, an anti-side channel circuit module configures an anti-side channel by configuring a cache isolation setting to facilitate the anti-side channel. The cache isolation setting adjusts the balance between anti-side channels and performance for the cache by configuring how many cache paths and / or groups are isolated and shared between contexts.
Owner:INTEL CORP
System and method for implementing GPU multi-tag cache architecture
PendingUS20250383990A1Memory architecture accessing/allocationCache memory detailsComputer architectureParallel computing
A system and a method are disclosed. The method includes the steps of storing a first portion of a first compressed tile in a first cache line of a cache storage device, and storing a second portion of the first compressed tile in a second cache line of a cache storage device.
Owner:SAMSUNG ELECTRONICS CO LTD
Sorting vector elements using a count value
ActiveUS12536106B2Program initiation/switchingComputation using non-contact making devicesAlgorithmVector element
Owner:TEXAS INSTRUMENTS INC
Shared buffered memory routing
ActiveUS12399832B2Memory architecture accessing/allocationInput/output to record carriersComputer networkMemory cell
A shared memory controller receives a flit from another first shared memory controller over a shared memory link, where the flit includes a node identifier (ID) field and an address of a particular line of the shared memory. The node ID field identifies that the first shared memory controller corresponds to a source of the flit. Further, a second shared memory controller is determined from at least the address field of the flit, where the second shared memory controller is connected to a memory element corresponding to the particular line. The flit is forwarded to the second shared memory controller using a shared memory link according to a routing path.
Owner:INTEL CORP
Streaming engine with stream metadata saving for context switching
PendingUS20250272097A1Memory architecture accessing/allocationRegister arrangementsDigital dataStream data
A streaming engine employed in a digital data processor specifies a fixed read only data stream defined by plural nested loops. An address generator produces addresses of data elements. A steam head register stores data elements next to be supplied to functional units for use as operands. Stream metadata is stored in response to a stream store instruction. Stored stream metadata is restored to the stream engine in response to a stream restore instruction. An interrupt changes an open stream to a frozen state discarding stored stream data. A return from interrupt changes a frozen stream to an active state.
Owner:TEXAS INSTRUMENTS INC
Persistent key-value store and journaling system
ActiveUS12417176B2Memory architecture accessing/allocationInput/output to record carriersEngineeringClient data
Techniques are provided for implementing a persistent key-value store for caching client data, journaling, and / or crash recovery. The persistent key-value store may be hosted as a primary cache that provides read and write access to key-value record pairs stored within the persistent key-value store. The key-value record pairs are stored within multiple chains in the persistent key-value store. Journaling is provided for the persistent key-value store such that incoming key-value record pairs are stored within active chains, and data within frozen chains is written in a distributed manner across distributed storage of a distributed cluster of nodes. If there is a failure within the distributed cluster of nodes, then the persistent key-value store may be reconstructed and used for crash recovery.
Owner:NETAPP INC
Last level cache access during non-cstate self refresh
PendingEP4453705A4Memory architecture accessing/allocationInput/output to record carriersCache accessParallel computing
A data processor includes a data fabric, a memory controller, a last level cache, and a traffic monitor. The data fabric is for routing requests between a plurality of requestors and a plurality of responders. The memory controller is for accessing a volatile memory. The last level cache is coupled between the memory controller and the data fabric. The traffic monitor is coupled to the last level cache and operable to monitor traffic between the last level cache and the memory controller, and based on detecting an idle condition in the monitored traffic, to cause the memory controller to command the volatile memory to enter self-refresh mode while the last level cache maintains an operational power state and responds to cache hits over the data fabric.
Owner:ADVANCED MICRO DEVICES INC
System and method for caching in storage devices
A system and method for caching in storage devices. In some embodiments, the method includes: opening a first file, by a first thread; reading a first page of data, from the first file, into a page cache in host memory of a host; adding, to a first data structure, a first pointer, the first pointer pointing to the first page of data; opening a second file, by a second thread; reading a second page of data, from the second file, into the page cache; and adding, to the first data structure, a second pointer, the second pointer pointing to the second page of data.
Owner:SAMSUNG ELECTRONICS CO LTD +1
Graphics processors
ActiveGB2639778AMemory architecture accessing/allocationImage memory managementComputer hardwareComputer architecture
A graphics processor (2) comprises a programmable execution unit (e.g. shader core 61, 62) operable to execute programs to perform graphics processing operations, and a machine learning (ML) processor
Owner:ARM LTD
Smart span prioritization based on insertion service backpressure
To provide a method and system for automatically instrumenting a web application.SOLUTION: The method identifies that a web application includes an event triggered by a user interaction, logs tracing information based on execution of a first set of operations caused by the event, associates the event with a tracer that obtains a first measurement of performance of a first span, identifies in code that the execution of the first set of operations causes a request to be made to a server, and associates the request with the tracer. The tracer logs tracing information based on the execution of the second set of operations caused by the request to obtain a second measurement of performance of a second span that is a child span of the first span.SELECTED DRAWING: Figure 2
Owner:ORACLE INT CORP
File tree streaming in a virtual file system for cloud-based shared content
ActiveUS12532008B2Memory architecture accessing/allocationDatabase updatingVirtual file systemUser device
Systems for fast views of items in file directories or file folders when interacting with a cloud-based service platform. A server in a cloud-based environment interfaces with one or more storage devices to provide storage of shared content accessible by two or more user devices. A file tree request to view the file directory or file folder of a particular sought after item is issued from an application operating on one of the user devices. Additional file tree items in a file tree hierarchy are prefetched by the cloud-based service platform. The application closes the file tree metadata stream after receiving the portion of the file tree that pertains to the particular item and before receiving the entirety of the metadata pertaining to all of the file tree metadata of all of the items in the directory or folder that contains the particular sought after item.
Owner:BOX INC
Cache memory
ActiveCN114822612BMemory architecture accessing/allocationCache memory detailsComputer hardwareEngineering
This application is directed to notebook memory in a cache. An apparatus can operate a portion of volatile memory in a cache mode having non-deterministic latency for servicing requests of a host device. The apparatus can monitor a register having an output pin associated with the portion and indicative of a mode of operation of the portion. Based on or in response to monitoring the output pin, the apparatus can determine whether to change the mode of operation of the portion from the cache mode to a notebook mode having deterministic latency for servicing requests of the host device.
Owner:MICRON TECHNOLOGY INC