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427results about "Cache memory details" patented technology
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Integrated three-dimensional (3D) DRAM cache
ActiveUS12271306B2Memory architecture accessing/allocationDigital computer detailsComputer architectureHigh density
Three-dimensional (3D) DRAM integrated in the same package as compute logic enable forming high-density caches. In one example, an integrated 3D DRAM includes a large on-de cache (such as a level 4 (L4) cache), a large on-die memory-side cache, or both an L4 cache and a memory-side cache. One or more tag caches cache recently accessed tags from the L4 cache, the memory-side cache, or both. A cache controller in the compute logic is to receive a request from one of the processor cores to access an address and compare tags in the tag cache with the address. In response to a hit in the tag cache, the cache controller accesses data from the cache at a location indicated by an entry in the tag cache, without performing a tag lookup in the cache.
Owner:INTEL CORP
Systems, methods, and apparatus for caching on a storage device
PendingUS20250173269A1Memory architecture accessing/allocationCache memory detailsPage tableDatabase
A method may include determining that data is related to an operation of an operating system; determining a score for the data; and writing the data to memory media based on the score. The data may include at least one page table. The at least one page table may include one or more entries; the one or more entries corresponds to data accessed above a threshold; and the method may further include writing data corresponding to the data accessed above a threshold from storage media to the memory media and / or storing data corresponding to the data accessed above a threshold in the memory media. The one or more entries may correspond to data accessed below a threshold; and the method may further include modifying data corresponding to the data accessed below a threshold from the memory media to storage media.
Owner:SAMSUNG ELECTRONICS CO LTD
Storage device capable of performing peer-to-peer data transfer and operating method thereof
ActiveUS20250238371A1Memory architecture accessing/allocationInput/output to record carriersExternal storageControl store
A storage device includes a non-volatile memory and a storage controller, wherein the storage controller includes a cache memory storing some of data stored in the non-volatile memory, an interface circuit receiving, from a first external host, a first request including a source address related to the external storage device, a destination address related to the storage device, and cache update information indicating an update method of the cache memory, provide a second request including the source address to the external storage device, and receive, from the external storage device in response to the second request, a response including first data corresponding to the source address, an address translation circuit generating a physical address of a first type based on the destination address, and a cache controller updating a cache area indicated by the physical address of the first type based on the cache update information.
Owner:SAMSUNG ELECTRONICS CO LTD
Efficient key-value cache management for large language models
ActiveUS12346252B1Memory adressing/allocation/relocationCache memory detailsParallel computingTerm memory
Owner:HEWLETT PACKARD ENTERPRISE DEV LP
Secure firewall configurations
PendingUS20250165588A1Memory architecture accessing/allocationKey distribution for secure communicationOperating systemReliability engineering
A kernel driver on an endpoint uses a process cache to provide a stream of events associated with processes on the endpoint to a data recorder. The process cache can usefully provide related information about processes such as a name, type or path for the process to the data recorder through the kernel driver. Where a tamper protection cache or similarly secured repository is available, this secure information may also be provided to the data recorder for use in threat detection, forensic analysis and so forth.
Owner:SOPHOS LTD
Cache writeback circuit
ActiveUS12524344B1Memory architecture accessing/allocationMemory adressing/allocation/relocationMemory hierarchyComputer architecture
A cache writeback circuit is disclosed for writing back, without invalidating, dirty cache lines. The cache writeback circuit is configured to enter an active state based on detecting a trigger condition indicative of cache misses to a memory cache circuit within a memory hierarchy of a computer memory subsystem causing cache line eviction activity. During the active state, the cache writeback circuit is configured to identify a set of dirty cache lines in the memory cache circuit, and write back, without invalidating, cache lines of the identified set of dirty cache lines from the memory cache circuit to a memory circuit within a lower level of the memory hierarchy, such as DRAM. The cache writeback circuit may further be configured to identify the dirty cache lines via a cache walk operation, which can be suspended, for example, when a higher-priority cache operation occurs.
Owner:APPLE INC
Systems and methods for improving cache efficiency and utilization
Systems and methods for improving cache efficiency and utilization are disclosed. In one embodiment, a graphics processor includes processing resources to perform graphics operations and a cache controller of a cache coupled to the processing resources. The cache controller is configured to control cache priority by determining whether default settings or an instruction will control cache operations for the cache.
Owner:INTEL CORP
Memory systems and devices including examples of accessing memory and generating access codes using an authenticated stream cipher
ActiveUS12321616B2Input/output to record carriersData stream serial/continuous modificationMemory addressControl store
Examples of systems and methods described herein provide for accessing memory devices and, concurrently, generating access codes using an authenticated stream cipher at a memory controller. For example, a memory controller may use a memory access request to, concurrently, perform translation logic and / or error correction on data associated with the memory access request; while also utilizing the memory address as an initialization vector for an authenticated stream cipher to generate an access code. The error correction may be performed subsequent to address translation for a write operation (or prior to address translation for a read operation) to improve processing speed of memory access requests at a memory controller; while the memory controller also generates the encrypted access code.
Owner:MICRON TECHNOLOGY INC
Graphics processor data access and sharing
Embodiments are generally directed to graphics processor data access and sharing. An embodiment of an apparatus includes a circuit element to produce a result in processing of an application; a load-store unit to receive the result and generate pre-fetch information for a cache utilizing the result; and a prefetch generator to produce prefetch addresses based at least in part on the pre-fetch information; wherein the load-store unit is to receive software assistance for prefetching, and wherein generation of the pre-fetch information is based at least in part on the software assistance.
Owner:INTEL CORP
Dynamic single-level cell write through in memory devices
ActiveUS20250156320A1Memory architecture accessing/allocationDigital storageComputer architectureEngineering
This application is directed to writing data in a memory device supporting multiple bits per cell by dynamically using a y-level cell (YLC) cache. The memory device is coupled into a host device, and includes a plurality of x-level cell (XLC) memory blocks, where x is greater than one and greater than y. The memory device identifies a write shaping status of the host device. Based on the write shaping status, the memory device determines that the host device performs write operations without a memory-based cache. In accordance with a determination that the host device performs write operations without the memory-based cache, a YLC cache is allocated in the memory device to act as the memory-based cache. In response to one or more write requests, the memory device stores data into the plurality of XLC memory blocks via the YLC cache.
Owner:SK HYNIX NAND PRODUCT SOLUTIONS CORP
Building management system with zero click data center heatmap
A Building Management System (BMS) can include one or more memory devices that can store instructions thereon. The instructions, when executed by one or more processors, can cause the one or more processors to receive a first set of data corresponding to a plurality of parameters of one or more aspects of a building, generate a user interface including one or more graphical representations of one or more first values, receive a dataset corresponding to a Change of Value (COV) for at least one value of the one or more first values, and update at least one graphical representation of the one or more graphical representations to reflect the COV for the at one value of the one or more first values.
Owner:TYCO FIRE & SECURITY GMBH
In-memory zero value detection
ActiveUS12242381B2Memory architecture accessing/allocationInput/output to record carriersMemory bankTerm memory
In some embodiments, an integrated circuit may include a substrate and a memory array disposed on the substrate, where the memory array includes a plurality of discrete memory banks. The integrated circuit may also include a processing array disposed on the substrate, where the processing array includes a plurality of processor subunits, each one of the plurality of processor subunits being associated with one or more discrete memory banks among the plurality of discrete memory banks. The integrated circuit may also include a controller configured to implement at least one security measure with respect to an operation of the integrated circuit and take one or more remedial actions if the at least one security measure is triggered.
Owner:NEUROBLADE LTD
Signal development caching in a memory device
ActiveUS12353762B2Memory architecture accessing/allocationInput/output to record carriersComputer architectureLogic state
Methods, systems, and devices for signal development caching in a memory device are described. In one example, a memory device in accordance with the described techniques may include a memory array, a sense amplifier array, and a signal development cache configured to store signals (e.g., cache signals, signal states) associated with logic states (e.g., memory states) that may be stored at the memory array (e.g., according to various read or write operations). In various examples, accessing the memory device may include accessing information from the signal development cache, or the memory array, or both, based on various mappings or operations of the memory device.
Owner:MICRON TECHNOLOGY INC
Redundant parallel computing structures as a cache
PendingUS20250284638A1Memory architecture accessing/allocationImage memory managementComputer hardwareComputer architecture
An apparatus to facilitate redundant parallel computing structures as a cache is disclosed. The apparatus includes redundant parallel computing hardware circuitry comprising redundant sets of computing combinatorial logic and register-based storage circuitry; and crossbar fabric connected to the registers of the redundant parallel computing hardware circuitry, wherein the crossbar fabric to cause register state of the register-based storage circuitry to be selected based on a tagged cache model.
Owner:INTEL CORP
Systems and methods of cache data placement
ActiveUS20250265190A1Memory architecture accessing/allocationCache memory detailsEngineeringData placement
Provided are systems, methods, and apparatuses for assisted cache data placement. In one or more examples, systems, methods, and apparatuses include assigning a first identifier to first data based on an aspect of the first data, the first data being data moved from a cache and assigning a second identifier to second data based on an aspect of the second data, the second data being moved to a storage device based on a policy of the cache. In one or more examples, systems, methods, and apparatuses include storing the first data in a first storage location of the storage device based on the first identifier and storing the second data in a second storage location of the storage device based on the second identifier.
Owner:SAMSUNG ELECTRONICS CO LTD
Method of reducing cache thrashing in a processing system and related processing system
PendingUS20250252057A1Memory architecture accessing/allocationCache memory detailsComputer architectureParallel computing
A method of reducing cache thrashing in a processing system is provided. M threads are issued to process a workload, and a memory access request associated with the M threads is transmitted to a first-level cache of the processing system. The memory access request is then transmitted to a second-level cache of the processing system in response to the first cache miss at the first-level cache. The memory access request is transmitted to a main memory of the processing system in response to the second cache miss at the second-level cache. The value of M is decreased when the relationship between the hit rates of the second-level cache and the first-level cache satisfies a predetermined criterion. A storage capacity and an access latency of the second-level cache are higher than those of the first-level cache.
Owner:MEDIATEK INC
Streaming Network Monitoring Caching Infrastructure
Systems and methods of network telemetry caching and distribution are provided. The system can receive network telemetry data and store it as a plurality of data nodes. The system can maintain a node pointer map and a node pointer queue. If the system receives an update to a data node having a corresponding node pointer not already present in the node pointer map, the system can add the node pointer to the node pointer queue and to the node pointer map with a count of zero. If the node pointer is already present in the node pointer map, the system can increment the node count for the node pointer in the node pointer map and not add the node pointer to the node pointer queue. The system can transmit data values and node counts to the client device for each node pointer in the node pointer queue.
Owner:GOOGLE LLC
Methods for facilitating external cache in a cloud storage environment and devices thereof
ActiveUS12287763B2Memory architecture accessing/allocationDigital data information retrievalOperational systemApplication programming interface
A method, non-transitory computer readable medium and storage server computing device that stores an identifier for a file system block evicted from a buffer cache in an entry in a table. The file system block is inserted into a victim cache hosted by an ephemeral block-level storage device by invoking a function provided by an application programming interface (API). The API exposes the ephemeral block-level storage device to a virtual storage appliance via an operating system of the storage server computing device. The entry in the table is updated to include location(s) on the ephemeral block-level storage device at which one or more portions of the file system block are stored, the location(s) returned in response to the function invocation. By this technology, performance of the virtual storage appliance is significantly improved, resulting in lower latency for client devices requesting data in a cloud storage environment.
Owner:NETAPP INC
REDUNDANT PARALLEL COMPUTING STRUCTURES AS A CACHE
PendingDE102025107980A1Memory architecture accessing/allocationResource allocationComputer hardwareComputer architecture
A device for enabling redundant parallel computing structures as a cache is disclosed. The device includes redundant parallel computing hardware circuitry comprising redundant sets of combinational computing logic and register-based storage circuitry; and a crossbar fabric connected to the registers of the redundant parallel computing hardware circuitry, wherein the crossbar fabric causes the register state of the register-based storage circuitry to be selected based on a tagged cache model.
Owner:INTEL CORP
Smart storage device using a computer express link (CXL) interface
A smart storage device is provided. The smart storage device includes a smart interface connected to a host device. An accelerator circuit is connected to the smart interface through a data bus conforming to a CXL.cache protocol and a CXL.mem protocol. The accelerator circuit is configured to perform acceleration computation in response to a computation command of the host device. A storage controller is connected to the smart interface through a data bus conforming to a CXL.io protocol. The storage controller is configured to control a data access operation for a storage device in response to a data access command of the host device. The accelerator circuit is directly accessible to the storage device through an internal bus connected directly to the storage controller.
Owner:SAMSUNG ELECTRONICS CO LTD
Redundant parallel computing structure as cache
PendingCN120634830AMemory architecture accessing/allocationImage memory managementCrossbar switchComputer architecture
The subject matter of the invention is a redundant parallel computing structure as a cache. An apparatus for facilitating a redundant parallel computing fabric as a cache is disclosed. The device comprises a redundant parallel computing hardware circuit module, wherein the redundant parallel computing hardware circuit module comprises computing combinatorial logic and a redundant set of register-based storage circuit modules; and a crossbar fabric connected to the registers of the redundant parallel computing hardware circuit module, where the crossbar fabric is to cause the tag-based cache model to select the register state of the register-based memory circuit module.
Owner:INTEL CORP
Semiconductor storage device
ActiveUS20250036310A1Memory architecture accessing/allocationInput/output to record carriersSemiconductor storage devicesHemt circuits
A semiconductor storage device includes a memory string, a sense amplifier including first and second latch circuits, a cache memory including a third latch circuit, and a control circuit. The control circuit is configured to perform a first read operation in response to a first command set and consecutively perform a second read operation in response to a second command set received during the first read operation. During the first read operation, data read from the memory string is stored in the first latch circuit. When the second command set is received at a first timing, the control circuit transfers the data to the second latch circuit, and then to the third latch circuit. When the second command set is received at a second timing before the first timing, the control circuit directly transfers the data to the third latch circuit.
Owner:KIOXIA CORP
Hybrid cache coherency
ActiveUS20250061059A1Memory architecture accessing/allocationCache memory detailsComputer hardwareEngineering
To implement a hybrid of software and hardware coherency management, a device can receive an unrestricted-access read request for memory that corresponds to a cache line from a first host and record an indication of the unrestricted-access read request with respect to the cache line. Here, the indication can include an identifier for the first host. However, if the device receives a shared-access read request for the cache line from a second host, the device does not record an identifier of the second host. Rather, the device can communicate an invalidation request for the cache line to the first host using the identifier for the first host to provoke the first host to write-back the data and invalidate the cache line.
Owner:MICRON TECHNOLOGY INC
Prediction unit that predicts branch history update information produced by multi-fetch block macro-op cache entry
ActiveUS12487926B1Memory architecture accessing/allocationMemory adressing/allocation/relocationComputer engineeringReal-time computing
A prediction unit (PRU) predicts a sequence of fetch blocks (FBlks). Branch predictors provide, in response to a FBlk start address (FBSA) lookup in combination with branch history state (BHS), information to predict branch history update information (BHUI) produced by the FBlk. A buffer stores accumulated BHUJ. A macro-op (MOP) cache (MOC) includes an unrolled loop multi-FBlk MOC entry (ULP-MF-ME) built from previously observed occurrences of a loop on a loop body of FBlks. A hit on the ULP-MF-ME predicts a current occurrence of a loop on the loop body. In parallel, for N initial iterations of the loop, the PRU updates the BHS with BHUI produced by each FBlk of the N initial iterations using information provided in response to a lookup and accumulates each BHUI into the buffer. The PRU updates the BHS using the accumulated BHUI for subsequent iterations of the loop to avoid more lookups.
Owner:VENTANA MICRO SYSTEMS INC
Efficient key-value cache management for large language models
Owner:HEWLETT PACKARD ENTERPRISE DEV LP
Managing a programmable cache control mapping table in a system level cache
ActiveUS12511234B2Memory architecture accessing/allocationCache memory detailsParallel computingComputing systems
Various embodiments include techniques for managing cache memory in a computing system. The disclosed techniques include a cache policy manager that monitors activity of various components that access a common cache memory. The cache policy manager establishes cache rules that determine what data remains stored in cache memory and what data is removed from cache memory in order to make room for new data. As the activities of these components change over time, cache rules that work well for a previous activity profile may no longer work well for the current activity profile. Therefore, the cache policy manager dynamically modifies the cache rules as the activity profile changes in order to select cache rules at any given time that work well with the current activity profile. These techniques are advantageous over conventional approaches that employ static cache rules that work well only for specific activity profiles.
Owner:NVIDIA CORP
Data caching method and apparatus, device, and storage medium
ActiveUS20250165399A1Memory architecture accessing/allocationError detection/correctionComputer networkEngineering
Owner:INSPUR SUZHOU INTELLIGENT TECH CO LTD
System and method for cache management of tiered storage devices
PendingCN120469627AMemory architecture accessing/allocationInput/output to record carriersComputer architectureEngineering
Owner:SAMSUNG ELECTRONICS CO LTD
Minimizing effects of cache thrashing by altering a persistence policy for non-temporal workloads
implemented method, system, and computer program product for minimizing the effects of cache thrashing involving non-temporal workloads. The cache activities of a workload, including the cache activities (e.g., number of cache hits) involving local and peer caches, are monitored. Based on analyzing the metrics of such monitored cache activities, a determination is made as to whether a non-temporal workload is identified. For example, such a determination may be based on comparing the metrics of the monitored cache activities of the workload to a threshold value. Upon identifying a non-temporal workload, the cache line(s) associated with the non-temporal workload are identified. The persistence policy for the identified cache line(s) is then altered. For example, the persistence policy for the identified cache line(s) may be altered by reducing the tenure of such a cache line(s) thereby reducing the number of cache misses or evictions and minimizing the effects of cache thrashing.
Owner:INTERNATIONAL BUSINESS MACHINE CORPORATION
Converting a stream of data using a lookaside buffer
ActiveUS12461746B2Memory architecture accessing/allocationRegister arrangementsComputational scienceParallel computing
A stream of data is accessed from a memory system by an autonomous memory access engine, converted on the fly by the memory access engine, and then presented to a processor for data processing. A portion of a lookup table (LUT) containing converted data elements is preloaded into a lookaside buffer associated with the memory access engine. As the stream of data elements is fetched from the memory system each data element in the stream of data elements is replaced with a respective converted data element obtained from the LUT in the lookaside buffer according to a content of each data element to thereby form a stream of converted data elements. The stream of converted data elements is then propagated from the memory access engine to a data processor.
Owner:TEXAS INSTRUMENTS INC