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338results about "Cache memory details" patented technology
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Systems, methods, and apparatus for caching on a storage device
PendingUS20250173269A1Memory architecture accessing/allocationCache memory detailsPage tableDatabase
A method may include determining that data is related to an operation of an operating system; determining a score for the data; and writing the data to memory media based on the score. The data may include at least one page table. The at least one page table may include one or more entries; the one or more entries corresponds to data accessed above a threshold; and the method may further include writing data corresponding to the data accessed above a threshold from storage media to the memory media and / or storing data corresponding to the data accessed above a threshold in the memory media. The one or more entries may correspond to data accessed below a threshold; and the method may further include modifying data corresponding to the data accessed below a threshold from the memory media to storage media.
Owner:SAMSUNG ELECTRONICS CO LTD
Storage device capable of performing peer-to-peer data transfer and operating method thereof
ActiveUS20250238371A1Memory architecture accessing/allocationInput/output to record carriersExternal storageControl store
A storage device includes a non-volatile memory and a storage controller, wherein the storage controller includes a cache memory storing some of data stored in the non-volatile memory, an interface circuit receiving, from a first external host, a first request including a source address related to the external storage device, a destination address related to the storage device, and cache update information indicating an update method of the cache memory, provide a second request including the source address to the external storage device, and receive, from the external storage device in response to the second request, a response including first data corresponding to the source address, an address translation circuit generating a physical address of a first type based on the destination address, and a cache controller updating a cache area indicated by the physical address of the first type based on the cache update information.
Owner:SAMSUNG ELECTRONICS CO LTD
Efficient key-value cache management for large language models
ActiveUS12346252B1Memory adressing/allocation/relocationCache memory detailsParallel computingTerm memory
Owner:HEWLETT PACKARD ENTERPRISE DEV LP
Secure firewall configurations
PendingUS20250165588A1Memory architecture accessing/allocationKey distribution for secure communicationOperating systemReliability engineering
A kernel driver on an endpoint uses a process cache to provide a stream of events associated with processes on the endpoint to a data recorder. The process cache can usefully provide related information about processes such as a name, type or path for the process to the data recorder through the kernel driver. Where a tamper protection cache or similarly secured repository is available, this secure information may also be provided to the data recorder for use in threat detection, forensic analysis and so forth.
Owner:SOPHOS LTD
Cache writeback circuit
ActiveUS12524344B1Memory architecture accessing/allocationMemory adressing/allocation/relocationMemory hierarchyComputer architecture
A cache writeback circuit is disclosed for writing back, without invalidating, dirty cache lines. The cache writeback circuit is configured to enter an active state based on detecting a trigger condition indicative of cache misses to a memory cache circuit within a memory hierarchy of a computer memory subsystem causing cache line eviction activity. During the active state, the cache writeback circuit is configured to identify a set of dirty cache lines in the memory cache circuit, and write back, without invalidating, cache lines of the identified set of dirty cache lines from the memory cache circuit to a memory circuit within a lower level of the memory hierarchy, such as DRAM. The cache writeback circuit may further be configured to identify the dirty cache lines via a cache walk operation, which can be suspended, for example, when a higher-priority cache operation occurs.
Owner:APPLE INC
Memory systems and devices including examples of accessing memory and generating access codes using an authenticated stream cipher
ActiveUS12321616B2Input/output to record carriersData stream serial/continuous modificationMemory addressControl store
Examples of systems and methods described herein provide for accessing memory devices and, concurrently, generating access codes using an authenticated stream cipher at a memory controller. For example, a memory controller may use a memory access request to, concurrently, perform translation logic and / or error correction on data associated with the memory access request; while also utilizing the memory address as an initialization vector for an authenticated stream cipher to generate an access code. The error correction may be performed subsequent to address translation for a write operation (or prior to address translation for a read operation) to improve processing speed of memory access requests at a memory controller; while the memory controller also generates the encrypted access code.
Owner:MICRON TECHNOLOGY INC
Dynamic single-level cell write through in memory devices
ActiveUS20250156320A1Memory architecture accessing/allocationDigital storageComputer architectureEngineering
This application is directed to writing data in a memory device supporting multiple bits per cell by dynamically using a y-level cell (YLC) cache. The memory device is coupled into a host device, and includes a plurality of x-level cell (XLC) memory blocks, where x is greater than one and greater than y. The memory device identifies a write shaping status of the host device. Based on the write shaping status, the memory device determines that the host device performs write operations without a memory-based cache. In accordance with a determination that the host device performs write operations without the memory-based cache, a YLC cache is allocated in the memory device to act as the memory-based cache. In response to one or more write requests, the memory device stores data into the plurality of XLC memory blocks via the YLC cache.
Owner:SK HYNIX NAND PRODUCT SOLUTIONS CORP
Signal development caching in a memory device
ActiveUS12353762B2Memory architecture accessing/allocationInput/output to record carriersComputer architectureLogic state
Methods, systems, and devices for signal development caching in a memory device are described. In one example, a memory device in accordance with the described techniques may include a memory array, a sense amplifier array, and a signal development cache configured to store signals (e.g., cache signals, signal states) associated with logic states (e.g., memory states) that may be stored at the memory array (e.g., according to various read or write operations). In various examples, accessing the memory device may include accessing information from the signal development cache, or the memory array, or both, based on various mappings or operations of the memory device.
Owner:MICRON TECHNOLOGY INC
Redundant parallel computing structures as a cache
PendingUS20250284638A1Memory architecture accessing/allocationImage memory managementComputer hardwareComputer architecture
An apparatus to facilitate redundant parallel computing structures as a cache is disclosed. The apparatus includes redundant parallel computing hardware circuitry comprising redundant sets of computing combinatorial logic and register-based storage circuitry; and crossbar fabric connected to the registers of the redundant parallel computing hardware circuitry, wherein the crossbar fabric to cause register state of the register-based storage circuitry to be selected based on a tagged cache model.
Owner:INTEL CORP
Systems and methods of cache data placement
ActiveUS20250265190A1Memory architecture accessing/allocationCache memory detailsEngineeringData placement
Provided are systems, methods, and apparatuses for assisted cache data placement. In one or more examples, systems, methods, and apparatuses include assigning a first identifier to first data based on an aspect of the first data, the first data being data moved from a cache and assigning a second identifier to second data based on an aspect of the second data, the second data being moved to a storage device based on a policy of the cache. In one or more examples, systems, methods, and apparatuses include storing the first data in a first storage location of the storage device based on the first identifier and storing the second data in a second storage location of the storage device based on the second identifier.
Owner:SAMSUNG ELECTRONICS CO LTD
Method of reducing cache thrashing in a processing system and related processing system
PendingUS20250252057A1Memory architecture accessing/allocationCache memory detailsComputer architectureParallel computing
A method of reducing cache thrashing in a processing system is provided. M threads are issued to process a workload, and a memory access request associated with the M threads is transmitted to a first-level cache of the processing system. The memory access request is then transmitted to a second-level cache of the processing system in response to the first cache miss at the first-level cache. The memory access request is transmitted to a main memory of the processing system in response to the second cache miss at the second-level cache. The value of M is decreased when the relationship between the hit rates of the second-level cache and the first-level cache satisfies a predetermined criterion. A storage capacity and an access latency of the second-level cache are higher than those of the first-level cache.
Owner:MEDIATEK INC
REDUNDANT PARALLEL COMPUTING STRUCTURES AS A CACHE
PendingDE102025107980A1Memory architecture accessing/allocationResource allocationComputer hardwareComputer architecture
A device for enabling redundant parallel computing structures as a cache is disclosed. The device includes redundant parallel computing hardware circuitry comprising redundant sets of combinational computing logic and register-based storage circuitry; and a crossbar fabric connected to the registers of the redundant parallel computing hardware circuitry, wherein the crossbar fabric causes the register state of the register-based storage circuitry to be selected based on a tagged cache model.
Owner:INTEL CORP
Redundant parallel computing structure as cache
PendingCN120634830AMemory architecture accessing/allocationImage memory managementCrossbar switchComputer architecture
The subject matter of the invention is a redundant parallel computing structure as a cache. An apparatus for facilitating a redundant parallel computing fabric as a cache is disclosed. The device comprises a redundant parallel computing hardware circuit module, wherein the redundant parallel computing hardware circuit module comprises computing combinatorial logic and a redundant set of register-based storage circuit modules; and a crossbar fabric connected to the registers of the redundant parallel computing hardware circuit module, where the crossbar fabric is to cause the tag-based cache model to select the register state of the register-based memory circuit module.
Owner:INTEL CORP
Prediction unit that predicts branch history update information produced by multi-fetch block macro-op cache entry
ActiveUS12487926B1Memory architecture accessing/allocationMemory adressing/allocation/relocationComputer engineeringReal-time computing
A prediction unit (PRU) predicts a sequence of fetch blocks (FBlks). Branch predictors provide, in response to a FBlk start address (FBSA) lookup in combination with branch history state (BHS), information to predict branch history update information (BHUI) produced by the FBlk. A buffer stores accumulated BHUJ. A macro-op (MOP) cache (MOC) includes an unrolled loop multi-FBlk MOC entry (ULP-MF-ME) built from previously observed occurrences of a loop on a loop body of FBlks. A hit on the ULP-MF-ME predicts a current occurrence of a loop on the loop body. In parallel, for N initial iterations of the loop, the PRU updates the BHS with BHUI produced by each FBlk of the N initial iterations using information provided in response to a lookup and accumulates each BHUI into the buffer. The PRU updates the BHS using the accumulated BHUI for subsequent iterations of the loop to avoid more lookups.
Owner:VENTANA MICRO SYSTEMS INC
Efficient key-value cache management for large language models
Owner:HEWLETT PACKARD ENTERPRISE DEV LP
Managing a programmable cache control mapping table in a system level cache
ActiveUS12511234B2Memory architecture accessing/allocationCache memory detailsParallel computingComputing systems
Various embodiments include techniques for managing cache memory in a computing system. The disclosed techniques include a cache policy manager that monitors activity of various components that access a common cache memory. The cache policy manager establishes cache rules that determine what data remains stored in cache memory and what data is removed from cache memory in order to make room for new data. As the activities of these components change over time, cache rules that work well for a previous activity profile may no longer work well for the current activity profile. Therefore, the cache policy manager dynamically modifies the cache rules as the activity profile changes in order to select cache rules at any given time that work well with the current activity profile. These techniques are advantageous over conventional approaches that employ static cache rules that work well only for specific activity profiles.
Owner:NVIDIA CORP
Data caching method and apparatus, device, and storage medium
ActiveUS20250165399A1Memory architecture accessing/allocationError detection/correctionComputer networkEngineering
Owner:INSPUR SUZHOU INTELLIGENT TECH CO LTD
System and method for cache management of tiered storage devices
PendingCN120469627AMemory architecture accessing/allocationInput/output to record carriersComputer architectureEngineering
Owner:SAMSUNG ELECTRONICS CO LTD
Minimizing effects of cache thrashing by altering a persistence policy for non-temporal workloads
implemented method, system, and computer program product for minimizing the effects of cache thrashing involving non-temporal workloads. The cache activities of a workload, including the cache activities (e.g., number of cache hits) involving local and peer caches, are monitored. Based on analyzing the metrics of such monitored cache activities, a determination is made as to whether a non-temporal workload is identified. For example, such a determination may be based on comparing the metrics of the monitored cache activities of the workload to a threshold value. Upon identifying a non-temporal workload, the cache line(s) associated with the non-temporal workload are identified. The persistence policy for the identified cache line(s) is then altered. For example, the persistence policy for the identified cache line(s) may be altered by reducing the tenure of such a cache line(s) thereby reducing the number of cache misses or evictions and minimizing the effects of cache thrashing.
Owner:INTERNATIONAL BUSINESS MACHINE CORPORATION
Converting a stream of data using a lookaside buffer
ActiveUS12461746B2Memory architecture accessing/allocationRegister arrangementsComputational scienceParallel computing
A stream of data is accessed from a memory system by an autonomous memory access engine, converted on the fly by the memory access engine, and then presented to a processor for data processing. A portion of a lookup table (LUT) containing converted data elements is preloaded into a lookaside buffer associated with the memory access engine. As the stream of data elements is fetched from the memory system each data element in the stream of data elements is replaced with a respective converted data element obtained from the LUT in the lookaside buffer according to a content of each data element to thereby form a stream of converted data elements. The stream of converted data elements is then propagated from the memory access engine to a data processor.
Owner:TEXAS INSTRUMENTS INC
Semiconductor device
A novel semiconductor device is provided. The semiconductor device includes a first cache, a second cache, a cache controller, and a core. The cache controller has a function of controlling data for performing program processing to be stored in the second cache in the case where the temperature around or inside the core is higher than or equal to a predetermined temperature threshold value, and controlling the data for performing program processing to be stored in the first cache in the case where the temperature around or inside the core is lower than the predetermined temperature threshold value.
Owner:SEMICON ENERGY LAB CO LTD
Persistent key-value store and journaling system
PendingUS20260010475A1Memory architecture accessing/allocationInput/output to record carriersEngineeringClient data
Techniques are provided for implementing a persistent key-value store for caching client data, journaling, and / or crash recovery. The persistent key-value store may be hosted as a primary cache that provides read and write access to key-value record pairs stored within the persistent key-value store. The key-value record pairs are stored within multiple chains in the persistent key-value store. Journaling is provided for the persistent key-value store such that incoming key-value record pairs are stored within active chains, and data within frozen chains is written in a distributed manner across distributed storage of a distributed cluster of nodes. If there is a failure within the distributed cluster of nodes, then the persistent key-value store may be reconstructed and used for crash recovery.
Owner:NETAPP INC
Managing a programmable cache control mapping table in a system level cache
ActiveUS20250156321A1Memory architecture accessing/allocationCache memory detailsParallel computingOperating system
Various embodiments include techniques for managing cache memory in a computing system. The disclosed techniques include a cache policy manager that monitors activity of various components that access a common cache memory. The cache policy manager establishes cache rules that determine what data remains stored in cache memory and what data is removed from cache memory in order to make room for new data. As the activities of these components change over time, cache rules that work well for a previous activity profile may no longer work well for the current activity profile. Therefore, the cache policy manager dynamically modifies the cache rules as the activity profile changes in order to select cache rules at any given time that work well with the current activity profile. These techniques are advantageous over conventional approaches that employ static cache rules that work well only for specific activity profiles.
Owner:NVIDIA CORP
Implicit fence for write messages
Embodiments described herein provide techniques to facilitate instruction-based control of memory attributes. One embodiment provides a graphics processor comprising a processing resource, a memory device, a cache coupled with the processing resources and the memory, and circuitry to process a memory access message received from the processing resource. The memory access message enables access to data of the memory device. To process the memory access message, the circuitry is configured to determine one or more cache attributes that indicate whether the data should be read from or stored the cache. The cache attributes may be provided by the memory access message or stored in state data associated with the data to be accessed by the access message.
Owner:INTEL CORP
Data reduction method, apparatus, and system
PendingUS20250165400A1Memory architecture accessing/allocationCache memory detailsTheoretical computer scienceData science
A data reduction method, apparatus, and system are provided, and belong to the field of data processing. One example method includes: obtaining a first address; and updating, based on popularity of the first address, an entry corresponding to the first address in a hot data table, where popularity of a storage address in the hot data table is greater than popularity of a storage address in a first cache table, and the first cache table is used for data reduction.
Owner:HUAWEI TECH CO LTD
Systems and methods of cache data placement
ActiveUS12602323B2Memory architecture accessing/allocationMemory adressing/allocation/relocationEngineeringData placement
Provided are systems, methods, and apparatuses for assisted cache data placement. In one or more examples, systems, methods, and apparatuses include assigning a first identifier to first data based on an aspect of the first data, the first data being data moved from a cache and assigning a second identifier to second data based on an aspect of the second data, the second data being moved to a storage device based on a policy of the cache. In one or more examples, systems, methods, and apparatuses include storing the first data in a first storage location of the storage device based on the first identifier and storing the second data in a second storage location of the storage device based on the second identifier.
Owner:SAMSUNG ELECTRONICS CO LTD
Vector based matrix multiplication
ActiveUS12450165B2Program initiation/switchingComputation using non-contact making devicesSoftware engineeringB matrix
A method is provided that includes performing, by a processor in response to a vector matrix multiply instruction, multiplying an m×n matrix (A matrix) and a n×p matrix (B matrix) to generate elements of an m×p matrix (R matrix), and storing the elements of the R matrix in a storage location specified by the vector matrix multiply instruction.
Owner:TEXAS INSTRUMENTS INC
Streaming engine with separately selectable element and group duplication
PendingUS20250315381A1Memory architecture accessing/allocationRegister arrangementsDigital dataAddress generator
A streaming engine employed in a digital data processor specifies a fixed read only data stream defined by plural nested loops. An address generator produces address of data elements. A steam head register stores data elements next to be supplied to functional units for use as operands. An element duplication unit optionally duplicates data element an instruction specified number of times. A vector masking unit limits data elements received from the element duplication unit to least significant bits within an instruction specified vector length. If the vector length is less than a stream head register size, the vector masking unit stores all 0's in excess lanes of the stream head register (group duplication disabled) or stores duplicate copies of the least significant bits in excess lanes of the stream head register.
Owner:TEXAS INSTRUMENTS INC
Method and apparatus for vector sorting using vector permutation logic
ActiveUS12436895B2Program initiation/switchingComputation using non-contact making devicesControl vectorAlgorithm
A processor and a vector sort instruction for the processor to execute are provided, in which the vector sort instructions includes instructions for comparing a first element of a set of vector elements of a vector to a remainder of the set of vector elements; determining, based on the comparing, a control vector that specifies a respective sorted position for each element of the set of vector elements; and reordering the set of vector elements based on the control vector.
Owner:TEXAS INSTRUMENTS INC
Memory sharing
ActiveCN114402304BMemory architecture accessing/allocationCache memory detailsComputer architectureHemt circuits
If sufficient memory resources are allowed access, components on an IC chip can operate faster or provide higher performance relative to power consumption. However, if each component is provided with its own memory, the chip becomes expensive. In the described implementation, memory is shared among two or more components (110, 114, 116). For example, a processing component (116) may include computing circuitry (206) and memory (106) coupled thereto. A multi-component cache controller (114) is coupled to memory (106). Logic circuitry (202) is coupled to the cache controller (114) and memory (106). The logic circuitry (202) selectively divides memory (106) into multiple memory partitions (108). A first memory partition (108-1) may be allocated to computing circuitry (206) and provide storage for computing circuitry (206). A second memory partition (108-2) may be allocated to the cache controller (114) and provide storage for multiple components (110). The relative capacity of memory partitions is adjustable to accommodate fluctuating demand without having to dedicate separate memory to a component.
Owner:GOOGLE LLC