14 results about "Hardware thread" patented technology

A system can include a plurality of hardware threads, one or more schedulers, and one or more execution pipelines. At least one hardware thread of the plurality of hardware threads can include one or more finite state machines. At least one finite state machine of the one or more finite state machines can be of a first type. The at least one finite state machine can process hazards on instructions. The at least one finite state machine can determine cycles in which the instructions are safe to issue to at least one of the one or more execution pipelines.

A method of microprocessor validation includes creating a plurality of actionable items in a system memory for execution by multiple hardware threads, creating a hardware thread table structure in the system memory, wherein the hardware thread table structure contains the multiple hardware threads, creating a Process Table Structure (PTS) table in the system memory, where the PTS table includes entry points into the plurality of actionable items, creating a re-entrant entry point function (FSCHED) in the system memory to allow the multiple hardware threads to enter the plurality of actionable items, inspecting each of actionable items to identify an inactive actionable item, where if an inactive actionable item is identified, the FSCHED atomically locks the inactive actionable item and a hardware thread enters the inactive actionable item and executes the inactive actionable item until finished, where the FSCHED locks the inactive actionable item and continues searching for inactive actionable items.

A method of microprocessor validation includes creating a plurality of actionable items in a system memory for execution by multiple hardware threads, creating a hardware thread table structure in the system memory, wherein the hardware thread table structure contains the multiple hardware threads, creating a Process Table Structure (PTS) table in the system memory, where the PTS table includes entry points into the plurality of actionable items, creating a re-entrant entry point function (FSCHED) in the system memory to allow the multiple hardware threads to enter the plurality of actionable items, inspecting each of actionable items to identify an inactive actionable item, where if an inactive actionable item is identified, the FSCHED atomically locks the inactive actionable item and a hardware thread enters the inactive actionable item and executes the inactive actionable item until finished, where the FSCHED locks the inactive actionable item and continues searching for inactive actionable items.

The invention discloses a message interruption transmission system and a message interruption transmission method, and belongs to the technical field of integrated circuit processing systems. The system comprises an interrupt controller, a system bus, a first conversion module and a first hardware thread, the interrupt controller is used for sending a first message interrupt to the system bus, a destination node of the first message interrupt is the first hardware thread, and a destination node of the first message interrupt is the second hardware thread. The first hardware thread does not have an adaptive incoming message interrupt controller (IMSIC); the system bus is used for interrupting and routing the first message to the first conversion module connected with the first hardware thread; and the first conversion module is used for converting the first message interrupt into a line interrupt request and providing the line interrupt request for the first hardware thread.

An apparatus and method for hard-partitioned threading in a clustered processor core. For example, one embodiment of a processor comprises: front end circuitry to fetch instructions of a number of software threads from a memory; out-of-order execution circuitry comprising a set of partitionable execution resources to execute the instructions; and circuitry to dynamically allocate the set of partitionable execution resources to a plurality of hardware threads, wherein a different isolated subset of the partitionable execution resources are allocated to each hardware thread based, at least in part, on characteristics of each respective software thread and the number of software threads.

The application discloses a message interrupt transmission system and a message interrupt transmission method, and belongs to the technical field of integrated circuit processing systems. The system comprises an interrupt controller, a system bus, a first conversion module and a first hardware thread. The interrupt controller is used for sending a first message interrupt to the system bus. The destination node of the first message interrupt is the first hardware thread, and the first hardware thread does not have an adaptive incoming message interrupt controller (IMSIC). The system bus is used for routing the first message interrupt to the first conversion module connected with the first hardware thread. The first conversion module is used for converting the first message interrupt into a line interrupt request, and providing the line interrupt request to the first hardware thread.

This application provides a hardware thread switching method and device. The method includes: sending a PackSave instruction to a control unit; wherein the PackSave instruction is used to trigger saving the context, and the PackSave instruction carries a thread identifier; the processor, based on the PackSave instruction, blocks the pipeline and stops dispatching new instructions into the pipeline; saving relevant context data according to the thread identifier; and restoring the pipeline; wherein the relevant context data includes, but is not limited to: register file information, logical register-physical register mapping table, condition register information, and status register information. The method provided by this application can achieve hardware thread switching with a single PackSave instruction, reducing hardware thread switching time and improving hardware thread switching speed.

A multi-thread processor can include logic that can be implemented in a form of physical logic gates, a plurality of hardware threads, one or more execution units that can execute one or more instructions, a least a level 1 cache that can be for data, and selection logic. Each hardware thread of the plurality of hardware threads can fetch instructions from a software thread of execution assigned to a corresponding hardware thread of the plurality of hardware threads. The selection logic can include one or more fair ready-schedulers. Each fair ready-scheduler of the one or more fair ready-schedulers can select instructions that are ready for execution from among the plurality of hardware threads. A distribution of which a hardware thread is chosen can be consistent with a pattern expected from choosing a ready instruction according to a uniform probability distribution.

A DMA architecture capable of performing multi-level, multi-step, and parallel determination of multiple memory addresses is described. In one aspect, the DMA system includes one or more hardware DMA threads. Each DMA thread includes a request generator configured to generate m memory addresses for a multidimensional tensor in parallel during each parallel memory address computation cycle, and to generate a corresponding request for performing a memory operation on the memory system for each address. The request generator includes m memory address units, each memory address unit including a step size tracker configured to generate a corresponding step size index value for each dimension of the tensor, and to generate a corresponding step offset value for that dimension based on the corresponding step size index value. Each memory address unit includes a memory address computation element configured to generate memory addresses for tensor elements and send requests to perform memory operations.

A device includes a hardware data processing node configured to perform corresponding tasks, and a hardware thread scheduler including a hardware task scheduler (300). The hardware task scheduler (300) is coupled to the hardware data processing node and has a producer socket (304), a consumer socket (302), and a spare socket (306, 307). The spare socket is configured to provide data control signals, also provided by the first socket of the producer and consumer sockets, in response to a first value of the memory-mapped register (224). The spare socket is configured to provide data control signals, also provided by the second socket of the producer and consumer sockets, in response to a second value of the memory-mapped register (224).

Techniques for broadcast translation lookaside buffer invalidation are described. In some examples, an instance of a single instruction includes fields for a single instruction having fields to indicate one or more operations to perform, an identifier of a first source operand, and, in some examples, an identifier of a second source operand is to be handled by execution circuitry. The execution circuitry of a first hardware thread is to execute the decoded instruction according to the fields to indicate one or more operations to broadcast a command to a plurality of hardware threads to cause an invalidation one or more translation lookaside buffer (TLB) entries for each of the plurality of hardware threads in accordance with a value of the first source operand and / or a value of the second source operand.

This invention comprises three layers of parallelism: 1. A 64-bit parallel layer, using a single 64-bit instruction within a single 64-bit CPU core to simultaneously process arithmetic operations on eight base-64 data columns, each column consisting of 6 data bits and 2 carry bits. 2. A multi-core parallel layer, executing 64-bit instructions simultaneously on multiple CPU cores, with each core executing independently. 3. A hyper-threaded parallel layer, using two hardware threads within each core to simultaneously execute different tasks, sharing an execution unit. These three layers are independent, requiring no synchronization between them, resulting in a total performance improvement to multiplicative level rather than additive level. Real-world testing shows a 128x speedup on an 8-core, 16-thread CPU, breaking the Amdahl's Law limitation and achieving linear scalability without a saturation point compared to traditional architectures.

A deterministic replay of a multi-threaded trace on a multi-threaded processor is described. An example of a computer-readable storage medium includes instructions to cause at least one processor to receive graphics processing unit (GPU) program code for tracing, the program code including a plurality of instructions; analyze the plurality of instructions to identify instructions of the program code that are events requiring synchronization; instrument each of the identified events to generate instrumented program code; execute the instrumented program code on a plurality of hardware threads of the GPU to generate trace data; and emulate the trace data utilizing an emulator on a plurality of hardware traces of a central processing unit (CPU), including replaying the identified events according to an order of occurrence of the identified events.

A network device includes a programmable core and a hardware pipeline having a parser engine to parse and retrieve information from a network packet and a set of hardware engines coupled to the parser engine. The set of hardware engines is to determine a packet-processing action to be performed based on the retrieved information and send an action request to the programmable core to trigger the programmable core to execute a hardware thread to perform a job. The job is associated with the packet-processing action and generates contextual data. The set of hardware engines retrieves and integrates the contextual data into performing the packet-processing action.