7 results about "Priority inversion" patented technology

The embodiment of the invention provides a thread processing method and device, relates to the technical field of computers, and can solve the problem of priority inversion in a conditional variable scene and improve the execution efficiency of threads. The method is applied to the electronic equipment, the electronic equipment comprises a target processor, the target processor comprises a target running queue, the target running queue comprises a first thread, a second thread and a third thread, and the method comprises the steps that under the condition that the condition of a target condition variable is not met, the first thread enters a sleep state, and the third thread enters a sleep state; the data is not cleared from the target operation queue; the condition of setting the target condition variable by the second thread is met, and the first thread is awakened; under the condition that the condition of the target condition variable is met, the first thread continues to run; after the first thread runs, the third thread runs, and the priority of the third thread is higher than that of the second thread and lower than that of the first thread.

The application discloses a real-time task scheduling method and system based on an industrial Internet of Things, and a medium, the method comprising: taking a heterogeneous two-level bitmap structure as a unique carrier of task priority and readiness state, incorporating corresponding heterogeneous two-level bitmap search fixed overhead, and completing provable real-time admission control of a newly-built task through a response time iteration criterion; a ready task that passes the provable real-time admission control completes heterogeneous two-level bitmap search within a limited clock cycle; when the heterogeneous two-level bitmap search identifies mutual exclusion lock competition and priority inversion risk, a deterministic bitmap migration protocol is executed through a processor atomic instruction, the readiness queue is physically migrated at the moment when priority inheritance takes effect through the deterministic bitmap migration protocol, the problem of inheritance taking effect but scheduling lagging is eliminated, and the response certainty of a control task in a resource competition scene is ensured.

The present application belongs to the technical field of integrated circuit design, and provides a multi-level multi-priority DMA arbitration circuit and arbitration method, which is decoupled into three orthogonal scheduling levels on the logic and physical levels, including: a first-level arbitration layer, a channel-level arbitrator for receiving concurrent requests of multiple independent DMA channels and screening out a unique authorized channel; a channel-level multiplexer for performing data and attribute gating of the authorized channel; a second-level arbitration layer, a function-level arbitrator for distinguishing request types, including descriptor requests and data requests, and dynamically adjusting arbitration priorities between different requests through a priority inversion signal provided by an internal state machine and an external configuration state register interface; a third-level arbitration layer connected with the output of the second-level arbitration layer, for mapping internal arbitration results to an external system bus, maximizing bus bandwidth utilization through read-write separation and response demultiplexing mechanism. The bottleneck of the traditional arbitration mechanism is effectively overcome.

The invention provides a thread locking method and related equipment, and the method comprises the steps: setting a first structure body of a mutual exclusion lock according to first identification information under the condition that a first thread holds the mutual exclusion lock of a target resource, and obtaining a first feature value; under the condition that the second thread requests to access the target resource, determining the current state of the mutual exclusion lock; when the current state represents that the mutex lock is occupied, calling the first characteristic value to a kernel space of the operating system, and controlling the second thread to enter the kernel space; in the kernel space, comparing the second priority of the second thread with the first priority; when the comparison result is that the second priority is greater than the first priority, increasing the first priority; and when it is detected that the first thread releases the mutual exclusion lock, controlling the second thread to occupy the mutual exclusion lock. By means of the method, priority inversion can be avoided when threads with high priorities wait for exclusive resources, and the task execution efficiency is improved.

The invention relates to a message processing method and system based on dynamic priority management. The invention relates to the field of message processing. The method comprises the following steps: acquiring an original message field; analyzing to obtain a message key field; calculating a priority level of an original message field based on a multi-dimensional comprehensive judgment rule and a dynamic context sensing mechanism; putting the original message fields into a message queue according to priorities; the priority of the enqueued original message field is dynamically adjusted in real time; popping up an original message field with the highest priority from the message queue; and processing the popped original message field. The method comprises the following steps: calculating a priority level of an original message field based on a multi-dimensional comprehensive judgment rule and a dynamic context sensing mechanism; and the priority of the enqueued original message field is dynamically adjusted in real time to form a systematic solution for the problems of main thread blockage, priority inversion and queue oscillation of the browser, so that the message processing efficiency and real-time performance are remarkably improved.

This application provides a hardware request scheduling method and system based on kernel ioctl hijacking. The method includes: intercepting character device ioctl requests, obtaining the calling process attributes, request command codes, and parameters; rewriting the parameters of matching requests according to a pre-defined security equivalence rewriting rule verified by formal verification and differential fuzzing testing, while directly passing through unmatched requests; allocating the processed requests to corresponding priority queues according to process attributes, retrieving requests sequentially by priority and calling the device's original ioctl processing function, thereby enabling the request to be sent to the device driver for execution. This application does not require modification of existing drivers and user programs, and relies on verifiable ioctl hijacking and request aggregation mechanisms to avoid priority inversion problems and stably improve hardware scheduling throughput performance.

A storage device may dynamically adjust priorities for types of data placed on a bus between the storage device and a host to optimize a bus pipeline and maximize the performance on the storage device, while minimizing inefficiencies and latencies on the storage device. A controller on the storage device may access data on a host memory buffer (HMB) and identify different types of data on a bus between the storage device and a host. The controller assigns priorities to the types of data placed on the bus and processes the data on the bus according to an assigned priority. The controller also determines a current system state and adjusts the priorities assigned to the types of data based on the current system state.