6 results about "Bitwise operation" patented technology

Systems and methods are disclosed including a memory device and a processing device, operatively coupled with the memory device, to perform operations comprising: receiving a write command to store data on the memory device; identifying a block of the memory device referenced by the write command; identifying, based on a number of pages in the block, a number of bits of an address referenced by the write command; generating a seed value by performing one or more transformation operations on a subset of bits comprising the identified number of bits of the address; generating an output sequence using the seed value; generating modulated data by performing one or more bitwise operations on the output sequence and the data; and storing, in the block of the memory device, the modulated data.

This invention relates to a method and electronic device for obtaining blocking information of an uninterruptible sleep state of a process, belonging to the field of computer technology. The method includes: when a process triggers a lock contention start tracking point due to resource contention, determining the lock type by parsing the lock contention start tracking point parameters; in response to the lock type being a mutex lock, obtaining the lock address by parsing the lock contention start tracking point parameters; clearing the flag bits in the owner member of the kernel lock structure pointed to by the lock address by performing bitwise operations, obtaining a pointer to the process descriptor of the holder; obtaining the process identifier and process name of the mutex lock holder by accessing the pointer to the process descriptor of the holder; and storing the process identifier, process name, and lock address of the mutex lock holder in a task blocking context structure with the process identifier of the mutex lock holder as the key, thereby achieving accurate acquisition of the mutex lock holder information.

This invention relates to the field of byte processing technology, providing a method and apparatus for accelerating byte encryption and decryption. The invention adds operation bits to bitwise operation instructions; uses corresponding operation bits to perform byte selection, endianness conversion, single-input multiple shift processing, and / or efficient table lookup operations. Specifically, byte selection avoids invalid bit calculations, improving instruction utilization. Endianness conversion ensures correct data order, minimizing duplicate data requests due to order errors, thus reducing the need for bitwise operations and improving GPU bandwidth utilization. Single-input multiple shift processing reduces the number of shift instructions, increasing throughput and avoiding repeated loading of the same data; efficient table lookup operations improve bitwise computation throughput, significantly reducing bandwidth pressure. This invention optimizes the granularity of bitwise operations, enabling encryption and decryption algorithms to efficiently utilize computing resources on the GPU while minimizing bandwidth consumption.

The invention discloses a high-dimensional feature matching method and system for a multi-view image, and belongs to the technical field of computer vision and remote sensing surveying and mapping, and the method comprises the following steps: S1, extracting high-dimensional feature descriptors and feature point coordinates of the multi-view image, and constructing a feature data set; s2, binary coding is carried out on the high-dimensional feature descriptors based on a multi-view feature adaptive Hash method (MFAH), and then an initial multi-view feature trajectory is generated through Hash space fast bit operation; and S3, performing gross error elimination on the initial multi-view feature trajectory, preferably introducing a multi-view local geometric consistency strategy (MLGC), and obtaining an optimized multi-view feature trajectory set. According to the technical scheme, efficient simultaneous matching and lightweight gross error elimination of multi-view high-dimensional features can be achieved, the matching efficiency is remarkably improved while the considerable matching quality is kept, and the method is suitable for multi-view image processing scenes such as large-scale three-dimensional reconstruction and remote sensing image change monitoring.

This invention provides a business processing method for a smart factory platform based on BeiDou grid codes. The method involves multi-level grid subdivision of the factory's physical space using BeiDou grid codes to generate unique grid codes. These grid codes represent location information in integer format. Equipment sensor data, personnel positioning data, and business logic data are bound to the grid codes to construct a spatiotemporal joint index table. Real-time correction of positioning data is performed using grid neighborhood topology relationships and personnel movement speed constraints to generate high-precision positioning trajectories. A rule engine maps business logic to grid codes, triggering automated operations based on grid attributes. By replacing traditional floating-point latitude and longitude coordinates with integer codes and optimizing data computation efficiency through bitwise operations, this method supports cross-level business associations and rapid path planning, thereby improving business response efficiency.

Methods, systems, and apparatus, including computer programs encoded on computer storage media, for performing conditional statements by arithmetic and / or bitwise units. A computer program including a conditional statement is accessed. The conditional statement includes a Boolean condition. The Boolean condition is transformed into an arithmetic and / or bitwise expression of the Boolean condition. The arithmetic and / or bitwise expression of the computer program includes the arithmetic and / or bitwise expression of the Boolean condition in place of the Boolean condition. The arithmetic and / or bitwise expression of the computer program is executed by an arithmetic and / or bitwise operation unit of a processor.