164 results about "Bitwise operation" patented technology

A bi-directional reflective memory channel between a pair of storage controllers is used to maintain a mirrored copy of each storage controller's native buffer contents within the buffer of the other storage controller. To maintain such mirrored copies, buffer write operations that fall within a reflective memory segment of one storage controller are automatically reflected across this channel to the other storage controller for execution, and vice versa. The write operations are preferably transmitted across the reflective memory channel using a protocol that provides for error checking, acknowledgements, and retransmissions. This protocol is preferably implemented entirely in automated circuitry, so that the mirrored copies are maintained without any CPU intervention during error-free operation. When a failover occurs, the surviving storage controller uses the mirrored copy of the failed storage controller's native buffer contents to assume control over the failed storage controller's disk drives.

A real-time processing system that executes a plurality of threads, each of the threads being a unit of execution of a real-time operation, comprises a plurality of processors, a unit which selects a tightly coupled thread group from among the threads based on coupling attribute information indicative of a coupling attribute between the threads, the tightly coupled thread group including a set of tightly coupled threads running in cooperation with each other, and a unit which performs a scheduling operation of dispatching the tightly coupled threads to several of the processors that are equal to the tightly coupled threads to simultaneously execute the tightly coupled threads by the several of the processors.

The invention relates to a method for allocating internal memory of real time operating system, which comprises the following steps: applying a big internal memory area from operating system, dividing the big internal memory area into internal memory polls with different sizes and the same internal memory poll comprises internal memory block with the same size, initialing each internal memory poll controlling bar. When it needs internal memory block, it finds the corresponding internal memory poll according to the size of internal memory block, and quotes weather the internal memory poll has free block, if it has free block, it fetches a block from the head of the team and modifies the referent information of internal memory poll controlling bar, and then the allocation finishes; if not, it dose dynamic adjustment to internal memory; when it releases the internal memory, it finds the corresponding internal memory poll according to the size of internal memory and returns it into the tail of the team and rewrites the referent information of internal memory poll controlling bar.

It is intended to provide control method and a nonvolatile semiconductor memory device capable of erase operation or write operation in high speed securing reliability without applying excessive electric field. An operation unit consists of a plurality of operation cycles each of which has a bias-application period and a verification period. Addition voltage ΔV is added to each operation unit as bias voltage, whereby a write operation can be carried out with characteristic of injected current IFG that is uniform among respective operation units duration of which are generally same. In this case, duration of operation cycles are shortened by each operation unit and duration of verification periods are shortened so as to avoid a situation such that a write operation completes in the middle of a bias-application period and after that, another write operation continues to cause excessive voltage stress on non-volatile semiconductor memory cells.

A method includes adjusting a counter value to indicate an access operation to a first portion of a non-volatile memory. The access operation is an erase operation or a write operation. The adjusted counter value indicates that a number of access operations to the first portion have been performed since an access operation to a second portion of the non-volatile memory has been performed. The method also includes selectively initiating a remedial action to the second portion in response to a comparison of the number of access operations to a threshold.

A well advisor system and console for monitoring and managing well drilling and production operations. The system may be accessed through one or more workstations, or other computing devices, which may be located at a well site or remotely. The system is in communication with and receives input from various sensors. It collects real-time sensor data sampled during operations at the well site. The system processes the data, and provides nearly instantaneous numerical and visual feedback through a variety of graphical user interfaces (“GUIs”), which are presented in the form of an operation-specific console. The input and data provides information related to geologic uncertainty concerning a well being drilled, with a focus on the safety of the drilling operation.

System and methods for performing microgrids cooperation by optimal coalition formation in a distribution network are disclosed. A Microgrid Cooperation Module (MCM) is designed for utility EMS. MCM contains a coalition formation unit and an energy exchange decision unit. Furthermore, a communication protocol for energy exchange between two microgrids is designed. The coalition formation unit applies an innovative hierarchical coalition formation algorithm to provide optimal coalition for real time operation. The real time energy status of microgrids will be provided to coalition formation unit which will determine the coalitions (given a distance threshold) among microgrids to minimize the power loss. Energy exchange decision unit then determine actual energy transfer between pairs of microgrids within a coalition. Upon receiving the energy transfer information through a communication channel, the microgrids will start communicating and process energy transfer. The optimality of the formed coalitions is ensured by performing coalitional game theoretical analysis.

The invention belongs to the technical field of computer equipment and relates to a hardware real-time operation system. A timing manager is used for realizing time delay and periodic execution of a task through a hardware timer; a task manager is used for realizing operation management of a task control block queue; an event manager is used for realizing operation and management of a semaphore control block, a mutually exclusive semaphore control block, a semaphore set control block, a message mailbox control block and an event control block of a message queue control block; and a bus interface manager is used for realizing data transmission and control between a processor and the real-time operation system. The hardware real-time operation system has a reliable design principle, an advanced design concept and a scientific contract technical means, adopts a cross embedded technology and an integrated circuit technology to achieve a hardware real-time operation system IC (integrated circuit), effectively improves real-time performance, reliability and stability of the real-time operation system, and has wide development and application values.

A host device, a portable storage device, and a method of updating an RO stored in the portable storage device are provided. The method includes receiving a predetermined bitmap from a host device, performing a bitwise operation on the received bitmap and meta information indicating a state of the RO, and updating the meta information using a result of the bitwise operation.

A method and system for rendering three-dimensional graphics, including text, provide a compressed texture bitmap. The texture bitmap may represent multiple symbols, each comprised of multiple pixels. Each pixel in the texture bitmap may store information for more than one symbol, including compressed pixels corresponding to multiple distinct symbols. For example, the compressed texture bitmap may have n-bit pixels (e.g., 8-bit pixels) that each store m (e.g., four) n/m-bit (e.g., 2-bit) compressed values. The compressed texture bitmap may be configured for unpacking by a conventional pixel shader, such as a pixel shader that does not typically perform bitwise operations. The unpacking may include matching a fetched pixel to a value in a lookup table, such as a 32-bit value from a 256-color palette. The looked-up value can be separated into separate sub-values to facilitate processing by the pixel shader. For example, the looked-up value can be split into RGBA values conventionally used in processing colored pixels.

The invention provides a method for carrying out back-up protection on the data of storage equipment and a computer system. The method comprises the following steps of: obtaining a write operation command of at least one client operation system for a first storage unit; recording the first time for obtaining the write operation command; carrying out write operation on the first storage unit according to the write operation command, wherein the write operation is used for writing first data at the first address of the first storage unit; and writing the operation information corresponding to the first time and the write operation command onto a second storage unit, wherein the operation information comprises the first address of the first storage unit corresponding to the write operation command and the first data corresponding to the write operation command. The method can realize continuous data back-up protection supporting the concurrency of multiple operation systems, without depending on the operation systems and third-party software.

An information processing system performs a real-time operation including a combination of a plurality of tasks. The system includes a plurality of processors, a unit which stores structural description information and a plurality of programs describing procedures corresponding to the tasks, the structural description information indicating a relationship in input/output between the programs and including cost information concerning time required for executing each of the programs, a unit which determines an execution start timing and execution term of each of a plurality of threads for execution of the programs based on the structural description information, and a unit which performs a scheduling operation of assigning the threads to at least one of the processors according to a result of the determining.

The invention discloses a hardware real-time operation system. The hardware real-time operation system comprises an ARM (advanced RISC machines) processor and an FPGA (field programmable gate array) which are connected via an FSMC (fuzzy sliding mode control) bus, wherein the FPGA is used for realizing a preemptive scheduler, and managements on tasks, a signal quantity, an oil tank, a message queue, a mutual exclusion signal quantity and an event flag group based on the preemptive scheduler; and the ARM processor is used for executing the tasks and realizing task switchover. By implementing the technical scheme of the invention, the FPGA does not occupy the processing time of the ARM processor because of running independently from the ARM processor, and the saved time is used for executing task programs, thus successfully reducing the system expense of the ARM processor; in particular, the utilization rate of the ARM processor is effectively increased in applications needing rapid task switchover. Therefore, via the operation system realized by hardware, the schedulability and real-time performance of the task set are improved.

The invention provides a method and apparatus for simulating user real-time operation. The method comprises following steps: receiving simulation operation requests carrying user identification of a simulated user; acquiring corresponding relations of attribute identification and attribute values according to the simulation operation requests, wherein the attribute identification and the attribute values belong to the user identification and are used for representing history operation behaviors; working out preset key operation items corresponding to the attribute identification and operation content items corresponding to the attribute values according to the acquired corresponding relations; and generating real-time simulation operation commands and executing the commands according to the acquired preset key operation items and the operation content items. By employing the method for simulating user real-time operation, real-time operation commands which ought to be triggered by the simulated user can be accurately simulated, the artificial intelligence degree is high, and the real user can be better substituted for real-time operation.

The present invention provides a circuit for detecting and correcting errors in a bit stream. The circuit consists of a plurality of circuit elements, a least one operation circuit means, and at least two logic gates. The logic gates receive inputs from the plurality of circuit elements. The plurality of circuit elements are coupled to receive and store a portion of a bit stream. The operation circuit elements perform bitwise operations on the contents of at least two of the circuit elements. The bitwise operations are dictated by a cyclical redundancy check (CRC) polynomial and are used to perform the CRC error detection division operation. At the end of the division process for the data to be checked, each circuit element corresponds to a bit in a bit error pattern syndrome and the logic gates determine if the contents of the circuit elements match specific bit error patterns. The circuit causes the state of at least one bit in the bit stream to change if the contents of the plurality of circuit elements match one of the specific bit patterns. The circuit is advantageous in that it may detect single bit errors, and double bit errors that may be caused by error duplication characteristic of a scrambler.