29 results about "Bitwise operation" patented technology

The invention relates to the technical field of electric digital data processing, and discloses a multi-dimensional data logic processing method based on an artificial intelligence algorithm, which comprises the following steps: receiving a target discrete data packet, extracting metadata, and calculating to generate a dimension entropy feature vector representing data logic complexity; inputting the vector into a preset topological mapping model, and outputting an initial adjacent matrix; calling a feedback suppression mask matrix generated based on a historical operator utility state, and executing bitwise logic AND operation with the initial adjacent matrix to generate a corrected effective topological matrix; the matrix is analyzed, a logic operator function pointer is dynamically indexed in an instruction cache, and a directed acyclic execution linked list is constructed; according to the method, redundant logic nodes in AI prediction are definitely eliminated through a bit operation mask mechanism based on historical feedback, and deterministic convergence of processing delay and optimal matching of computing power resources are achieved.

A data aggregation service is engineered to generate aggregated data values based on encrypted data received from a variety of providers, without being exposed to the underlying plaintext data. A homomorphic encryption scheme is used in a threshold cryptography scenario that allows aggregation of the encrypted data without requiring decryption. An independent decryption service can partially decrypt the aggregated result, which can ultimately be decrypted to plaintext for use by the provider. Bitwise operations can be defined to support aggregation with error tolerance, and the operations can be constrained to a smaller bit size to reduce circuit complexity.

Systems and methods are disclosed including a memory device and a processing device, operatively coupled with the memory device, to perform operations comprising: receiving a write command to store data on the memory device; identifying a block of the memory device referenced by the write command; identifying, based on a number of pages in the block, a number of bits of an address referenced by the write command; generating a seed value by performing one or more transformation operations on a subset of bits comprising the identified number of bits of the address; generating an output sequence using the seed value; generating modulated data by performing one or more bitwise operations on the output sequence and the data; and storing, in the block of the memory device, the modulated data.

An in-memory bitwise operation circuit and method thereof are provided. The circuit includes a memory array, storing page data each having strings; a page buffer, storing the strings and selecting a portion of the strings as operands; a pop-count counter, receiving the operands and an operator flag, counting the number of bit 1 at corresponding bit positions of the operands, and generating a bitwise operation result corresponding to the operator; a bitwise operation processing unit, receiving and temporally storing the bitwise operation result, and outputting a final bitwise operation result when receiving a final result flag. In case that the operator is a last operator, the bitwise operation result is output as the final bitwise operation result. The circuit and method are suitable for 3D NAND flash memory that has high capacity and high performance.

An in-memory bitwise operation circuit and method thereof are provided. The circuit includes a memory array, storing page data each having strings; a page buffer, storing the strings and selecting a portion of the strings as operands; a pop-count counter, receiving the operands and an operator flag, counting the number of bit 1 at corresponding bit positions of the operands, and generating a bitwise operation result corresponding to the operator; a bitwise operation processing unit, receiving and temporally storing the bitwise operation result, and outputting a final bitwise operation result when receiving a final result flag. In case that the operator is a last operator, the bitwise operation result is output as the final bitwise operation result. The circuit and method are suitable for 3D NAND flash memory that has high capacity and high performance.

This invention relates to a method and electronic device for obtaining blocking information of an uninterruptible sleep state of a process, belonging to the field of computer technology. The method includes: when a process triggers a lock contention start tracking point due to resource contention, determining the lock type by parsing the lock contention start tracking point parameters; in response to the lock type being a mutex lock, obtaining the lock address by parsing the lock contention start tracking point parameters; clearing the flag bits in the owner member of the kernel lock structure pointed to by the lock address by performing bitwise operations, obtaining a pointer to the process descriptor of the holder; obtaining the process identifier and process name of the mutex lock holder by accessing the pointer to the process descriptor of the holder; and storing the process identifier, process name, and lock address of the mutex lock holder in a task blocking context structure with the process identifier of the mutex lock holder as the key, thereby achieving accurate acquisition of the mutex lock holder information.

The application relates to the technical field of electric digital data processing, and discloses a multi-dimensional data logic processing method based on an artificial intelligence algorithm, which comprises the following steps: receiving a target discrete data packet, extracting metadata and calculating a dimension entropy feature vector representing data logic complexity; inputting the vector into a preset topological mapping model to output an initial adjacency matrix; calling a feedback inhibition mask matrix generated based on a historical operator utility state, performing bitwise logical AND operation on the initial adjacency matrix to generate a corrected effective topological matrix; analyzing the matrix, dynamically indexing a logical operator function pointer in an instruction cache, and constructing a directed acyclic execution linked list; and driving a processor to sequentially call logical operator execution operation, wherein the application determines redundant logic nodes in AI prediction through a bitwise operation mask mechanism based on historical feedback, realizes the deterministic convergence of processing delay and the optimal matching of algorithm resource.

A computing device (101), method and computer program product herein for replicating a three-dimensional label mask (20) for a three-dimensional volumetric data set (190) in a network (100) of computing devices. The device (101) receives, from a further computing device (102) of the network, a series of segmented input data (21) describing an edit (2-1) of a tag mask (20) on the further computing device (102). The segment input data includes current location data, size data, and a tag identifier associated with a spherical segment object (102-1) used by the second computing device (102) to interactively edit the tag mask. A replicator module (101-10) replicates an edited tag mask of the further computing device (102) associated with the series of segmented input data by: calculating a respective ellipsoid corresponding to the spherical segmented object (102-1) stretched inversely proportional to the shape of voxels in the tag mask; determining voxels (vi) of a label mask having positions inside the segmented object on the basis of the ratio of the distance between the respective voxel position and the center position of the ellipsoid divided by the respective semi-axis length of the ellipsoid in all three dimensions, wherein the division is performed using a bitwise operation on a graphics processing unit of the computing device (101) to invert an index of each denominator; and updating the determined voxels in the replicated tag mask (10) in accordance with the tag identifier of the segmented input data (21).

The embodiments of the present application relate to the field of big data. Provided are a method and apparatus for determining duplicate data, and a device. The method comprises: on the basis of a merged computing node, acquiring bitmap arrays and single-machine duplicate sets of M computing nodes; performing pairwise bitwise operation processing on the bitmap arrays of the M computing nodes, so as to obtain M duplicate values; acquiring local reverse dictionaries corresponding to the computing nodes, and on the basis of the local reverse dictionaries, performing secondary duplicate check processing on the duplicate values, so as to obtain multi-machine duplicate sets corresponding to the duplicate values; and merging the multi-machine duplicate sets and the single-machine duplicate sets, so as to obtain a global duplicate set. The method in the present application improves data duplicate detection efficiency.

The invention relates to a user management method for hybrid deployment of an RTOS (Real Time Operating System) end operating system, which comprises the following steps of: dividing a high 32-bit user existence area and a low 32-bit permission area based on a 64-bit unsigned long shaping storage unit, defining a coding rule, configuring an initial state, and finishing user creation and group permission configuration through an instruction. And finally, realizing resource access control through user existence verification, Hash binding verification and permission analysis. Compared with a traditional scheme, the method has the advantages that the memory occupation is greatly saved, the CPU overhead is reduced, the real-time response performance of the system is improved, meanwhile, fine-grained permission control is realized, and the operation complexity is reduced.

This invention relates to the field of byte processing technology, providing a method and apparatus for accelerating byte encryption and decryption. The invention adds operation bits to bitwise operation instructions; uses corresponding operation bits to perform byte selection, endianness conversion, single-input multiple shift processing, and / or efficient table lookup operations. Specifically, byte selection avoids invalid bit calculations, improving instruction utilization. Endianness conversion ensures correct data order, minimizing duplicate data requests due to order errors, thus reducing the need for bitwise operations and improving GPU bandwidth utilization. Single-input multiple shift processing reduces the number of shift instructions, increasing throughput and avoiding repeated loading of the same data; efficient table lookup operations improve bitwise computation throughput, significantly reducing bandwidth pressure. This invention optimizes the granularity of bitwise operations, enabling encryption and decryption algorithms to efficiently utilize computing resources on the GPU while minimizing bandwidth consumption.

A computing device (101), a method, and a computer program product for replicating a three-dimensional label mask (20) of a three-dimensional volumetric data set (190) in a network of computing devices (100), wherein the device (101) receives, from a further computing device (102) of the network, a set of segmentation input data (21) describing an edit (2-1) of the label mask (20) at the further computing device (102), the set of segmentation input data comprising current position data, size data, and a label identifier associated with a spherical segmentation object (102-1) used by the second computing device (102) to interactively edit the label mask. The replication module (101-10) replicates an edited label mask of a further computing device (102) associated with a set of segmentation input data by calculating respective ellipsoids corresponding to the spherical segmentation object (102-1) stretched inversely proportional to the shapes of the voxels in the label mask, determining voxels (vi) of the label mask having positions inside the segmentation object based on the ratio of the distance between each voxel position in all three dimensions and the center position of the ellipsoid divided by the respective semi-axis lengths of the ellipsoid, the division being performed by negating the exponents of each denominator using respective bitwise operations on a graphics processing unit of the computing device (101), and updating the determined voxels in the replicated label mask (10) according to the label identifiers of the segmentation input data (21).

This invention discloses a fast calculation method for text logical expressions based on low-frequency indexing. First, the expression is traversed and grouped according to the operation conditions. Then, the scores of each OR operation group are calculated through dynamic weighting, and the OR operation group with the highest keyword frequency score is used as the index group. Next, keywords in all groups are globally deduplicated to generate a matching machine for multi-modal keyword matching. Finally, based on the original binary tree rules, OR nodes are merged into bitmap nodes, and the target text is matched with the matching machine. The matched keywords form a set, and the intersection of this set and the index is calculated. Whether the intersection is greater than 0 determines whether a node is matched. This invention reduces the computational load by using low-frequency indexing and improves computational performance through bitwise operations, ensuring high computational performance even with an increased number of keywords and expressions, thus meeting the timeliness requirements of business data.

The application claims a video coding CU block classification method based on a lightweight deep learning model, which is suitable for the field of video coding. The method first performs block processing on the input image, divides it into multiple 128x128 pixel image blocks, and extracts the brightness information of each image block. After normalization processing, the brightness data is used as the input of the deep learning model to generate classification probabilities of multiple categories. For each subunit of the image block, the probabilities of different categories are compared pixel by pixel, and the category label with the highest probability is assigned to it. Subsequently, based on the classification results of the subunits, the number of each category in each CU block is counted, and the corresponding type of the CU block is assigned according to the statistical information. The CU block can belong to multiple categories at the same time, and the final category is determined by bitwise operation. Through accurate CU block classification, the application not only improves the coding efficiency, but also provides data support for subsequent mode division and selection, and is suitable for video coding application scenarios with high real-time requirements.

A Montgomery multiplication apparatus (MMA) for multiplying two multiplicands and then taking a modulus of a predefined number includes a precomputation circuit and a Montgomery multiplication circuit. The precomputation circuit is configured to compute Montgomery precomputation values by performing a series of iterations. In a given iteration, the precomputation circuit is configured to modify one or more intermediate values by performing bitwise operations on the intermediate values computed in a previous iteration. The Montgomery multiplication circuit is configured to multiply the two multiplicands and then take the modulus of the predefined number by performing a plurality of Montgomery reduction operations using the Montgomery precomputation values computed by the precomputation circuit.

Techniques for document sorting with bitmap indexes are described. A request to sort a set of documents is received. A bitmap that identifies the set of documents to be sorted is obtained. An ordered set of sort bitmaps is obtained, each sort bitmap in the ordered set of sort bitmaps corresponding to a bit in an encoding of a data type to be sorted. A series of passes of bitwise operations is performed with the ordered set of sort bitmaps, each pass to identify a next document identifier to add to a sorted set of document identifiers by processing an initial bitmap with bitwise operations in order against at least a portion of the ordered set of sort bitmaps. The initial bitmap of the first pass in the series of passes is initialized with the obtained bitmap. The sorted set of document identifiers is stored.

The invention provides a bit operation circuit and method in a memory. In one embodiment, a circuit includes a memory array having a plurality of page data, each page data having a plurality of strings; a page buffer storing a plurality of strings and selecting a portion of the strings from the plurality of strings as a plurality of operands; the total quantity counter is used for receiving the plurality of operands and the operand identifiers, and carrying out bit 1 counting on the bits corresponding to the positions in the operands based on the operand identifiers so as to generate a bit operation result of the operands and the operands; and the bit operation processing unit is used for receiving and temporarily storing the bit operation result, and outputting a final bit operation result when the final result identifier is received. And when the operator is the last operator, taking the bit operation result as a final bit operation result. The method is suitable for the 3D NAND flash memory, and has the characteristics of high capacity and high performance.

The invention relates to a multifunctional bitwise operation method and system based on double-array co-location index, in particular to the field of communication, and remarkably improves the reliability and efficiency of the operation system by introducing mode and data collaborative verification and structural consistency deep analysis. In the initialization stage, the compatibility of the operation mode and the input data is subjected to prospective judgment, operation errors and resource waste caused by mismatching of the data and the mode in a traditional method are effectively avoided, the system can intelligently analyze the operation requirement, structural consistency verification is conducted on the multi-source input data, and the system reliability is improved. On the basis of ensuring that subsequent operation is established on a reliable data basis, an optimized bitwise operation rule is adopted in an execution stage, calculation precision and consistency are guaranteed, final output is synthesized and optimized, the result is accurate, the structure is normative, the whole scheme realizes full-process optimization from data verification, operation execution to result output, and the calculation efficiency is improved. And the overall performance and stability of the system in processing complex and changeable scenes are greatly improved.

Embodiments of the present invention disclose a report calculation system, method, electronic device, and storage medium. The report calculation method includes: obtaining source data and parsing the source data to obtain a cross-tabulation table to be calculated; analyzing the cross-tabulation table to obtain calculation units; calculating the calculation units of each sample in the source data to obtain a first calculation result; obtaining bit data of each calculation unit based on the first calculation result; converting the cross-tabulation table into a reverse Polish notation, and using bitwise operations to calculate the reverse Polish notation based on the bit data to obtain a second calculation result; summarizing the second calculation result to obtain summary data; and calculating based on the summary data to obtain a final result. This report calculation method solves the problems of report configuration calculation in the prior art, such as insufficient configuration flexibility, inability to support complex population attribute configurations, and slow calculation speed.

The invention discloses a high-dimensional feature matching method and system for a multi-view image, and belongs to the technical field of computer vision and remote sensing surveying and mapping, and the method comprises the following steps: S1, extracting high-dimensional feature descriptors and feature point coordinates of the multi-view image, and constructing a feature data set; s2, binary coding is carried out on the high-dimensional feature descriptors based on a multi-view feature adaptive Hash method (MFAH), and then an initial multi-view feature trajectory is generated through Hash space fast bit operation; and S3, performing gross error elimination on the initial multi-view feature trajectory, preferably introducing a multi-view local geometric consistency strategy (MLGC), and obtaining an optimized multi-view feature trajectory set. According to the technical scheme, efficient simultaneous matching and lightweight gross error elimination of multi-view high-dimensional features can be achieved, the matching efficiency is remarkably improved while the considerable matching quality is kept, and the method is suitable for multi-view image processing scenes such as large-scale three-dimensional reconstruction and remote sensing image change monitoring.

The invention discloses a database Boolean flag bit mapping storage method and device and a medium, and relates to the technical field of electric digital data processing. The method comprises the steps that according to the preset basic bitmap granularity, a Boolean mark in a database is compressed and stored, so that the Boolean mark is converted into a Boolean mark bitmap from an original array form; wherein the compression storage operation is used for compressing the number of storage units of the Boolean mark; according to the real-time access feature corresponding to the Boolean flag, recombining the Boolean flag bitmap to obtain a recombined global Boolean flag bitmap; and in response to an operation request sent by a user, calling a preset bit operation interface, and processing the specified Boolean flag in the global Boolean flag bitmap or the Boolean flag in the specified bitmap block.

Described is an improved method of for compressing a sparse matrix. The method comprises reading a first subset of one or more values from the sparse matrix comprising at least one zero and performing a logical bitwise operation on each value to identify the at least one zero. The method comprises writing the first subset of values to an output array, and incrementing an offset counter based on a number of identified non-zeros. The method then comprises reading a second subset of one or more values from the sparse matrix containing at least one non-zero value and performing a logical bitwise operation on each value in the second subset to identify the at least one non-zero value, and writing the second subset to the output array at a position defined by the offset counter, comprising overwriting at least one zero in the output array with at least one non-zero value.

This invention discloses a method, device, and medium for storing Boolean flags in a database using a bitmap format, relating to the field of electronic digital data processing technology. The method includes: performing a compression storage operation on Boolean flags in the database according to a preset basic bitmap granularity, converting the Boolean flags from their original array form into a Boolean flag bitmap; wherein the compression storage operation is used to compress the number of storage units for the Boolean flags; reorganizing the Boolean flag bitmap according to the real-time access characteristics corresponding to the Boolean flags, obtaining a reorganized global Boolean flag bitmap; and responding to an operation request sent by a user, calling a preset bitwise operation interface to process a specified Boolean flag in the global Boolean flag bitmap or a Boolean flag in a specified bitmap block.

The invention discloses a high-compatibility communication data processing method and system, and the method comprises the steps: unifying register addressing by taking double bytes as a unit, building a mapping relation from a register byte address to a double-byte buffer area, and calculating an index, a modulus and a shift amount based on bit operation; unified cross-boundary access operation is carried out on data possibly crossing the boundary of the buffer area. Therefore, the problems that data processing on microcontrollers (MCU) with different unit address sizes is incompatible and codes are difficult to transplant when the register length is mixed with single bytes and double bytes in a user-defined communication protocol are solved. Seamless compatibility between single-byte and double-byte MCUs is achieved, code transportability is remarkably improved, flexible access and processing of data of any initial address, length and mixed bytes are supported, and the method is suitable for scenes such as CAN communication needing high-compatibility data packaging.

Systems and methods for performing a Winograd transform operation with reduced precision loss. The Winograd transform operation is performed by iterating over each matrix element of a first matrix (U) and a second matrix (V) of the Winograd transform operation, wherein for each element: when a respective matrix element value exceeds one or more maximum threshold values or one or more minimum threshold values, right-shifting the respective matrix element value by at least one bit, performing a matrix multiplication of the first matrix (U) and second matrix (V) using one or more bitwise operations to obtain a result matrix, iterating over each matrix element of the result matrix, and for each matrix element: multiplying corresponding matrix elements from the first matrix (U) and second matrix (V), left-shifting a multiplication result of the matrix multiplication based on the right-shifting to adjust the result matrix, outputting the adjusted result matrix.

This invention provides a business processing method for a smart factory platform based on BeiDou grid codes. The method involves multi-level grid subdivision of the factory's physical space using BeiDou grid codes to generate unique grid codes. These grid codes represent location information in integer format. Equipment sensor data, personnel positioning data, and business logic data are bound to the grid codes to construct a spatiotemporal joint index table. Real-time correction of positioning data is performed using grid neighborhood topology relationships and personnel movement speed constraints to generate high-precision positioning trajectories. A rule engine maps business logic to grid codes, triggering automated operations based on grid attributes. By replacing traditional floating-point latitude and longitude coordinates with integer codes and optimizing data computation efficiency through bitwise operations, this method supports cross-level business associations and rapid path planning, thereby improving business response efficiency.

Methods, systems, and apparatus, including computer programs encoded on computer storage media, for performing conditional statements by arithmetic and / or bitwise units. A computer program including a conditional statement is accessed. The conditional statement includes a Boolean condition. The Boolean condition is transformed into an arithmetic and / or bitwise expression of the Boolean condition. The arithmetic and / or bitwise expression of the computer program includes the arithmetic and / or bitwise expression of the Boolean condition in place of the Boolean condition. The arithmetic and / or bitwise expression of the computer program is executed by an arithmetic and / or bitwise operation unit of a processor.

Cache logic (100) for generating a cache address from a binary input memory address (101) comprising a first binary string (102) which is a first sequence of bits with a first predetermined length, and a second binary string which is a second sequence of bits with a second predetermined length, wherein the cache logic (100) comprises: a hash engine (106) for generating a third binary string from the first binary string (102), wherein the third binary string has the second predetermined length, and wherein the hash engine (106) is configured to form each bit of the third binary string by combining a respective subset of bits of the first binary string (102) by a first bitwise operation, wherein the subsets of bits of the first binary string (102) at the hash engine (106) are defined such that each subset is unique and comprises on average about half of the bits of the first binary string (102); and a combination unit (107) for combining the third binary string with the second binary string by a reversible operation to form a binary output string (116) for use in at least part of a cache address in a cache memory (110).

The invention discloses an enterprise memory-oriented retrieval pre-access control method, which comprises the following steps of: generating a user capability bitmap for each user, and generating a fragment requirement bitmap for each enterprise memory fragment; receiving a user query and generating a query vector, and recalling a candidate fragment identification sequence from the vector index based on approximate nearest neighbor search; for each candidate fragment, reading a fragment requirement bitmap of the candidate fragment, and carrying out bit operation inclusion judgment on the fragment requirement bitmap and the user capability bitmap; and sorting the candidates in the candidate pool according to the similarity, performing secondary permission verification on a sorting result by using the latest user capability bitmap and the fragment requirement bitmap before final output, removing the candidates which do not pass the verification, and recording an audit log. According to the retrieval pre-access control method for enterprise memory, permission judgment is pre-posed before vector loading and actuarial, the non-permission content contact surface is blocked, the computing power waste and delay are reduced, and the output compliance under dynamic permission change is ensured through secondary verification.