84 results about "Write protection" patented technology

The invention discloses a power grid material sampling inspection management method for realizing whole-course tracing based on intelligent sample sealing, and relates to the technical field of electric power material management and intelligent perception, and the method comprises the following steps: S1, an initialization stage: executing a sample sealing coding segmentation pre-configuration process, distributing independent numbered segments to each sample sealing terminal, and the central control module synchronizes the use state of the terminal code to realize distributed isolation of code generation. According to the invention, coding uniqueness is realized through segmented pre-configuration and global duplicate checking, identity information security is guaranteed by adopting chip one-time write protection and tamper-proof technologies, and sample packet switching and data counterfeiting are effectively prevented by combining automatic acquisition and multi-round consistency comparison. Abnormal recognition and closed-loop processing ensure that abnormal events are frozen in time and responsibility is traced, and irregular samples are prevented from flowing into subsequent links. The whole-process auditing and dynamic optimization enable the management process to be self-perfected, and the intelligence, standardization and reliability of sampling inspection of the power grid materials are remarkably improved.

Described are techniques for write protecting a non-volatile memory (NVM) after the contents of the NVM have been set. In some examples, a computing device or system having an NVM also includes a Root of Trust (RoT) configured to generate a write protect command as an input to the NVM. The RoT generates the write protect command in response to detecting a write protect signal from an electronic controller. The write protect command sets one or more areas in the NVM to be read-only. Further, the write protect command can make the one or more areas read-only on a power-on basis so that write protection is maintained until the next power cycle. The electronic controller can be configured to assert the write protect signal each time the computing device or system is powered on, for instance during a reboot, thereby causing the RoT to renew the write protection.

The invention provides a power failure protection module and an implementation method. The method comprises the following steps: acquiring a voltage state of a main power supply; performing segmented monitoring on the voltage state of the main power supply through a voltage monitoring module, and determining a plurality of preset voltage nodes; if the voltage of the main power supply drops to any node in the preset voltage nodes, a standby power supply module is switched to provide a standby power supply through a control unit; according to the descending sequence of the preset voltage nodes, coordinating a data write-back operation and a write protection operation through the control unit; and completing transmission of the cached data to the storage unit through the data protection interface to obtain a data protection result.

The invention relates to a satellite-borne router software security reconstruction method, aims to solve the problems of transmission monitoring lag, high-delay verification and insufficient isolation, provides an integrity chain verification and firewall double-layer verification cooperation scheme, and is combined with a modular physical isolation design. When the routing module receives the data packet, a hardware write protection lock is activated, unauthorized modification is forbidden, and strategy lock-free update is supported; the platform management module downloads an accumulated verification value in real time, and pays attention to a reconstruction instruction after ground verification; and the program programming module adopts double Bank storage, supports atomization programming and credible verification, and automatically returns a safe version when an exception occurs. Attacks are defended through satellite-ground cooperative double-closed-loop verification (firewall filtering, token bucket current limiting and ground CRC verification), hardware isolation guarantees updating without interrupting routing operation, and intelligent backspacing improves the fault-tolerant capability. The method is suitable for a high-delay and strong-interference satellite-borne routing scene, ensures zero interruption of a reconstruction service during in-orbit maintenance of a transit / overseas satellite, and meets the security requirement of a modern satellite network.

The invention discloses a method and a device for optimizing read-write performance of a database, computer equipment and a storage medium, the method comprises the following steps: setting to use an atomic variable to replace a common variable, setting to use an atomic read operation to replace a LwLock read protection operation, and setting to use an atomic write operation to replace a LwLock write protection operation to obtain set content; and initializing a database according to the set content to obtain an atomic variable database. According to the method, under the multi-core processor environment, the lock-free characteristic enables different cores to independently and efficiently process data without waiting for release of a lock, the parallel computing capacity of the multi-core processor is fully utilized, efficient execution of database read-write operation on the multi-core processor is achieved, and the data processing efficiency is improved. The scheme can be applied to the business fields of financial science and technology business, medical health maintenance and the like.

The invention relates to a microcontroller system firmware upgrading method and device based on an IAP technology, and aims to solve the problem that in the prior art, an external FLASH memory needs to be added or the occupation of a high RAM (Random Access Memory) needs to be increased. Safe and reliable online updating of firmware is achieved through the built-in Bootloader program, additional storage hardware is not needed, and the requirement for RAM resources is reduced by means of a subpackage transmission and packet-by-packet verification write-in mechanism. Meanwhile, a dual identification mechanism of an update flag bit and a write protection flag bit is introduced, so that the system can automatically identify and take proper recovery measures if power failure or abnormal interruption occurs in the update process, and the situation that the system is unavailable due to partial update of firmware is prevented. The hardware cost and the system complexity are effectively reduced, the fault-tolerant capability of firmware updating and the system stability are improved, and the method is suitable for application scenes with high requirements for reliability and maintenance convenience such as industrial control, automotive electronics and remote terminal equipment.

The invention relates to the field of artificial intelligence hardware, in particular to a neural network training method based on quantum annealing optimization, and the method comprises the steps: firstly solving a gradient at a graphics processor, and generating an energy coefficient through neuromorphic coding; dividing the weight into sub-blocks according to a coupling threshold value, outputting initial spinning by an optical coherence Isin optimizer, performing reverse annealing by a quantum annealing processor to obtain optimal spinning, and freezing scale parameters; then, a noise consistency optimizer is used for finely adjusting scale parameters, discrete weights are reconstructed according to spin-scale and written into the memristive cross array unit by unit, and hardware errors are eliminated through read-write-check cycle and column gain-row bias dual calibration; and generating a deployment model file and executing write protection after double-end multi-time sampling is carried out at a reference low temperature to confirm spin consistency. The method has high-speed convergence, low-energy-consumption writing and long-term reasoning stability, and the training and deployment efficiency of a large-scale neural network on light-quantum-memristive heterogeneous hardware is remarkably improved.

The invention discloses a read-only device supporting multi-channel M.2 interfaces. The read-only device adopts a main control module and integrates PCIe and SATA protocol analysis engines, and the main control module identifies protocols followed by M.2 devices connected with all the interfaces and carries out protocol processing logic switching; the main control module is further provided with a plurality of arbitration logic units used for adjusting resource distribution among the interfaces. The interface module at least comprises multiple paths of M.2 interfaces, and each path of M.2 interface is independently provided with a PCIe channel and an SATA channel to be connected with the main control module; and the security interception module is used for synchronizing protocol information followed by the M.2 equipment connected with each interface and write protection state information of each interface from the main control module, and judging and executing whether write protection is carried out on the interface or not. According to the method and the device, the problem that the existing evidence obtaining equipment lacks M.2 native support and is coordinated with the requirement of high-concurrency secure data transmission of a plurality of transmission channels is solved.

A computer-implemented method and a computer program product for device pairing security. A computer scans a media device for a potential threat. In response to determining that the potential threat does not exist, a computer copies content of the media device to a secure media device. A computer configures a write protection mode on the secure media device. A computer configures a geofence policy, a low battery policy for the secure media device, and a security alert notification policy for the secure media device. A computer configures a policy of immediately wiping storage on the secure media device. A computer activates the secure media device for use on a host device in a secure facility. The secure media device includes an antenna of radio frequency identification, an antenna of a network, a microcontroller, and a battery.

The invention discloses a low-interaction secure handshake method, device and system based on spatio-temporal context constraint, order deviation extraction and polarity hedging verification, a chip and a storage medium. According to the method, local physical feature anchor points formed by a plurality of physical nodes in a hardware carrier are extracted, in combination with context parameters such as time, space, environment, operation state and historical state abstracts, order deviation parameters related to a current session are generated, session mapping factors are constructed according to the order deviation parameters, and constraint mapping is executed on a to-be-processed load. At a receiving end, a verification end or a local processing end, a matching result is obtained by simulating in-situ polarity hedging verification, differential matching, residual auditing or closed auditing of a front end, and control such as session establishment, limited release, load zero clearing, blocking or write protection is executed according to a complete matching state, a partial matching state and a mismatching state. According to the scheme, the physical state of the device, the environmental condition and the session history can be jointly incorporated into a safety judgment chain, so that the interactive burden of the explicit key is reduced, and the countermeasure ability to replay, counterfeit, ectopic reproduction and high-frequency heuristic is improved; the method can be applied to scenes such as equipment access authentication, secure communication handshake, high-value operation admission, controlled terminal access and off-line signature.

The invention discloses a method for releasing a data block and a storage device, and the method comprises the steps: obtaining the capacity of a super data block in the storage device, and configuring the size of a write-in distribution unit as the capacity of the super data block; receiving a write-in command of a host, and detecting whether the write-in command belongs to a duplicating command or not; if yes, the super data block is rewritten according to current write-in data issued based on the write-in distribution unit in the write-in command to obtain an invalid data block, and the invalid data block is released. According to the method, all the super data blocks can be released through a copying mechanism, so that the starting frequency of a garbage collection mechanism is reduced, and a write protection mechanism is prevented from being triggered.

The application discloses a method for managing IO write operation and a storage device. The method comprises the following steps: receiving an IO write operation issued by a host; detecting whether the host starts a high-load write protection mode; if yes, obtaining write management information of the high-load write protection mode, wherein the write management information comprises data stream information of historical IO write operation; judging whether the IO write operation is a sequential write operation according to the data stream information; and if yes, updating the data stream information according to position metadata of the IO write operation. The application can improve the reliability and write performance of the device when high-load video recording is performed.

A display module and a control method thereof, as well as a display device. The display module includes a display panel, a control module, a selection module, and a storage module. The storage module includes a first storage unit and a second storage unit. The control module is electrically connected to the display panel, the selection module, and the storage module. The selection module receives a reference write protection signal generated by the control module and outputs a selection control signal. The control module, based on a reference clock signal and a reference data signal generated by the control module and the selection control signal, execute one or more instructions stored in the first storage unit to enable a sensing function of the display panel, or execute one or more instructions stored in the second storage unit to disable the sensing function of the display panel.

The application relates to the technical field of servers and discloses a fault memory positioning method, system and device, computer equipment and a storage medium, the method comprising the following steps: in the case that a memory fault signal is received and a server is in a shutdown state, the write protection state of a power management chip register is released; candidate fault memories are determined according to the memory fault signal; a disable command is written into the power management chip register of the candidate fault memories, wherein the disable command is used to not power on the candidate fault memories when the server enters a startup state; in the case that the server enters the startup state, log information of the candidate fault memories is acquired; and according to the log information, a target fault memory and slot position information of the target fault memory are determined from the candidate fault memories. The application solves the problems that it is difficult to acquire abnormal information capable of accurately positioning the fault memories and the PMIC fault memories cannot be positioned.

The embodiment of the invention provides a data transfer system and an image processing device. According to the data circulation system, the public cache module is arranged, so that the upstream module can call the cache blocks which are divided in advance from the public cache module to cache the target data. And the downstream module can search the cache block through the preset identifier issued by the upstream module to obtain the target data. By introducing a reference counting mechanism, write protection can be set for the called cache block, and the public cache module can release the cache block only when the reference times of the cache block return to zero from a non-zero number. Therefore, one-to-many transmission between the upstream module and the downstream module can be realized, the control logic of the target data acquisition process is reduced, and the data circulation efficiency is improved.

Write protection can be provided in mixed-media datasets. Contextual details may be extracted from a set of media to form a mixed-media dataset. The mixed-media dataset may be used to train a machine-learning model. A request to modify the mixed-media dataset may be received causing the machine-learning model to determine if implementing the request to modify the mixed-media dataset will introduce conflict or a deviation from the current mixed-media dataset. Upon confirming that implementing the request will not introduce a conflict or deviate from the from the current mixed-media, the mixed-media dataset may be modified according to the request and the machine-learning model may be retrained using the modified mixed-media dataset.

Disclosed are devices and methods for protecting the register file of a power management integrated circuit (PMIC). In one embodiment, a device is disclosed comprising: a register file comprising a plurality of a registers, at least one register in the register file containing a write register bit (WRB); and an interface configured to receive messages from a host application, the messages including a WRB enablement signal, wherein the device is configured to enable writing to the register file in response to receiving the WRB enablement signal over the interface, write data in response to write messages while writing to the register file is enabled, and disable writing to the register file in response to receiving a stop bit over the interface.

A secure boot method of an Internet of Things (IoT) apparatus includes: in response to a system boot signal of the IoT apparatus, verifying an authentication signature of a bootloader firmware and an authentication signature of an application layer (App) firmware; reading an encryption key stored in a one-time programmable memory in response to determining that the authentication signature of the bootloader firmware and the authentication signature of the App firmware both pass verification, in which the encryption key is configured to have a write protection attribute; decrypting the App firmware according to the encryption key, and running the decrypted App firmware; and in response to determining to read encrypted flash-memory partition data in a flash memory (Flash), decrypting the encrypted flash-memory partition data according to the encryption key, so as to securely boot up the IoT apparatus.

A pluggable communication module (200) includes a circuit card (250) having a substrate (258) with an edge (252). The pluggable communication module includes an EEPROM device (300) having a power supply pin (312), a serial data pin (314), a serial clock pin (316), a ground pin (318), and a write control pin (320) for programming the EEPROM device. The pluggable communication module includes a contact pad region (262) near the edge having a signal pad (264), a ground pad (266), a power pad, a serial data pad (270), a serial clock pad (272), and a write pad (280). The write pad is located at a programming depth of the circuit card edge in front of the signal pad to mate the write pad to the receptacle connector (112) without mating the signal pad to the receptacle connector.

Various illustrative aspects are directed to a data storage device, comprising one or more disks; an actuator system configured to position a selected head among one or more heads proximate to a corresponding disk surface among the one or more disks; and one or more processing devices. The selected head comprises a write element, an assistive energy emitter, an energizing interface coupled to the assistive energy emitter, and a detector. The assistive energy emitter is driven separately from driving of the write element. The one or more processing devices are configured to detect, via the detector, an energy anomaly at the energizing interface; detect, in response to detecting the energy anomaly, whether a previously written track yields an anomalous readback signal; and rewrite, in response to detecting that the previously written track yields an anomalous readback signal, data designated for the previously written track to the previously written track.

The present application relates to a kind of on-orbit router software security reconstruction method, for transmission monitoring lag, high delay verification and insufficient isolation problem, propose integrity chain check and firewall double-layer verification collaborative scheme, combined with modular physical isolation design.Routing module activates hardware write protection lock when receiving data packet, prohibits unauthorized modification and supports policy lock-free update;Platform management module real-time download cumulative check value, ground verification after upper reconstruction instruction;Program burn module uses double Bank storage, supports atomization burn and trusted verification, abnormal automatic rollback safety version.Through space-earth collaborative double-loop verification (firewall filtering, token bucket flow limiting, ground CRC check) to resist attack, hardware isolation ensures that updating does not interrupt routing operation, intelligent rollback improves fault tolerance.Ceiling for high delay, strong interference on-orbit routing scene, guarantee transit / overseas satellite on-orbit maintenance when reconstructing business zero interruption, meet modern satellite network security needs.

The invention discloses a method, a device and equipment for protecting a nonvolatile memory, and relates to the field of automation control, the method comprises the following steps: acquiring an erasing condition of a target nonvolatile memory in a preset time period; if the erasing condition is an erasing state, increasing a time integral count value by using a preset accumulated value; when the time integral count value is greater than or equal to a frequent erasing threshold value, determining that frequent erasing exists in the target nonvolatile memory, and executing a preset frequent erasing protection operation; according to the method, frequent erasing and writing of the target nonvolatile memory are recognized by adopting the thought of writing time integration, the process of counting the writing times of each storage unit is avoided, and accurate recognition of frequent erasing and writing of the nonvolatile memory can be realized with relatively small resource occupation, so that after the frequent erasing and writing are recognized, the storage efficiency of the nonvolatile memory is improved. By executing the preset frequent erasing and writing protection operation, the writing protection function of the nonvolatile memory is realized, and long-term and low-frequency accumulated erasing and writing can be effectively identified and blocked.

The application discloses a data erasing method and an electronic device, relates to the technical field of data processing, and comprises the following steps: a processor only allows to start a write protection closing and a data erasing process when a management board is a secondary return board type, so that the miserasing operation of a non-target scene such as first production and operation and maintenance is avoided from a scene source. In addition, the closing of the write protection function is directly linked depending on a hardware pin, so that the risk of mistriggering or vulnerability at the software level is reduced. Therefore, the data erasing method provided by the application improves the security of data erasing processing on data in a target address range.

The invention discloses a bus control module for converting an SPI bus into an AHB. The bus control module comprises an SPI slave instruction data analysis module, a register module, a mode configuration module, a data transmission cache module, a data detection module and a state detection module, wherein the instruction data analysis module is used for instructions, addresses and data, the register module comprises a plurality of registers used for configuring module functions, and the mode configuration module is used for configuring a transmission mode; according to the invention, the read-write control of the register in the module can be realized through the read-write instruction section, the stability of data transmission is ensured through a dual write protection mechanism, and an external SPI host realizes the read-write of the register in the SOC and the reading and loading of firmware through the SPI bus-to-AHB bus control module, so that the stability of data transmission is ensured. Wherein the firmware is stored in an RAM (Random Access Memory) storage area or a plug-in FLASH storage area in the SOC.

The invention discloses a firmware updating method, electronic equipment, firmware updating equipment and a firmware updating system. The method comprises the following steps: entering a firmware updating file system; when the device information of the storage device is obtained, whether the storage device meets a firmware updating condition or not is judged according to the device information; when it is judged that the storage device meets the firmware updating condition, whether the storage device is in a write protection state or a normal working state or not is judged according to the fault information; when it is judged that the storage device is in a write protection state according to the fault information, all storage data and the fault information are cleared according to the updating command or the device information, and firmware of the storage device is updated into firmware of a target version; when it is judged that the storage device is in a normal working state according to the fault information, firmware of the storage device is updated to firmware of a target version, and all storage data are reserved. According to the method, the firmware of the storage device can be updated when the updating command is received or not received, so that the difficulty of firmware updating is greatly reduced.

The application provides an eBPF-based Redis large Key real-time detection and protection method and system. The method obtains Redis process information, probe mounting parameters and large Key judgment threshold, loads an eBPF program to a kernel and writes the eBPF program into a BPF Map to obtain a runtime monitoring configuration; based on the runtime monitoring configuration, a probe is mounted on a Redis command receiving, command processing, response construction and command returning path; when a client request arrives, a request buffer and a client connection context are read, a RESP length prefix is parsed to obtain a command type, a target key and a request data size; according to the command type, a write detection process or a read detection process is entered, a write protection strategy is generated and executed when the request data size exceeds a write threshold, and a large Key read event is generated when an accumulated response data size exceeds a read threshold, so that real-time detection, write protection and read alarm of a Redis large Key are realized.

The application discloses a method for binding and unbinding of a master and slave lock. The application realizes a convenient and safe operation trigger mode by using the encryption information carried by an RFID card and the advanced read-write protection characteristics thereof. The scheme simplifies the complex process of traditional manual information filling of terminal equipment into two core operations of "swiping the master lock -> swiping the slave lock". The operator does not need to learn the complex terminal operation logic, nor does the operator need to remember or input long device ID, key and other information, and the binding process can be triggered only by holding the RFID card and touching the master and slave lock in sequence.

The present application relates to a kind of solid state disk fault pre-diagnosis and data security self-repair processing method and device, belong to memory technical field, method includes: in the running process of solid state disk, the block erase time of each memory block is monitored, when the block erase time of one or more memory blocks is first exceeded early warning threshold, the memory block is marked as early warning state;The block erase time variation rate of memory block marked as early warning state is continuously monitored, if the block erase time variation rate exceeds acceleration degradation threshold, then determine that memory block enters high-risk state;Hot data identification operation is carried out to the memory block of high-risk state, identify the data page of the wear value in the memory block higher than set level;The identified high wear value data page is migrated to the reserved healthy memory block, and after migration is completed, write protection locking operation is carried out to the memory block of original high-risk state;Realize the effect of data security initiative protection and storage life collaborative optimization.

The invention discloses a method for managing IO write operation and a storage device. The method comprises the steps that IO write operation issued by a host is received, and whether the host starts a high-load write protection mode or not is detected; if the high-load write protection mode is started, write management information of the high-load write protection mode is obtained, and the write management information comprises data flow information of historical IO write operation; judging whether the IO write operation is sequential write operation or not according to the data stream information; and if yes, updating the data stream information according to the position metadata of the IO write operation. According to the invention, the reliability and the write-in performance of the device during execution of high-load video recording can be improved.

This invention discloses a controller and control method for SRAM erase protection verification in an MCU architecture, belonging to the field of memory technology. This invention solves the problem that existing devices cannot simultaneously include multiple functions. By employing an SRAM erase protection verification device, write protection can be configured for each page individually, achieving write protection for SRAM data. The entire SRAM data is erased, and after erasure, write protection and data verification functions continue to be executed, improving read / write efficiency. Furthermore, SRAM data can be verified. When the SRAM controller reads any address, it latches that address and pulls up the read verification flag for that address. Then, an even-number verification is performed on the byte with the verification bit and the latched address. If the verification result is low, the verification passes; otherwise, it indicates a data error, and the error verification result is fed back to the system, thereby meeting the high requirements of the system for the SRAM controller.