34 results about "Write protection" patented technology

The invention discloses a low-interaction secure handshake method, device and system based on spatio-temporal context constraint, order deviation extraction and polarity hedging verification, a chip and a storage medium. According to the method, local physical feature anchor points formed by a plurality of physical nodes in a hardware carrier are extracted, in combination with context parameters such as time, space, environment, operation state and historical state abstracts, order deviation parameters related to a current session are generated, session mapping factors are constructed according to the order deviation parameters, and constraint mapping is executed on a to-be-processed load. At a receiving end, a verification end or a local processing end, a matching result is obtained by simulating in-situ polarity hedging verification, differential matching, residual auditing or closed auditing of a front end, and control such as session establishment, limited release, load zero clearing, blocking or write protection is executed according to a complete matching state, a partial matching state and a mismatching state. According to the scheme, the physical state of the device, the environmental condition and the session history can be jointly incorporated into a safety judgment chain, so that the interactive burden of the explicit key is reduced, and the countermeasure ability to replay, counterfeit, ectopic reproduction and high-frequency heuristic is improved; the method can be applied to scenes such as equipment access authentication, secure communication handshake, high-value operation admission, controlled terminal access and off-line signature.

The application relates to the technical field of servers and discloses a fault memory positioning method, system and device, computer equipment and a storage medium, the method comprising the following steps: in the case that a memory fault signal is received and a server is in a shutdown state, the write protection state of a power management chip register is released; candidate fault memories are determined according to the memory fault signal; a disable command is written into the power management chip register of the candidate fault memories, wherein the disable command is used to not power on the candidate fault memories when the server enters a startup state; in the case that the server enters the startup state, log information of the candidate fault memories is acquired; and according to the log information, a target fault memory and slot position information of the target fault memory are determined from the candidate fault memories. The application solves the problems that it is difficult to acquire abnormal information capable of accurately positioning the fault memories and the PMIC fault memories cannot be positioned.

Disclosed are devices and methods for protecting the register file of a power management integrated circuit (PMIC). In one embodiment, a device is disclosed comprising: a register file comprising a plurality of a registers, at least one register in the register file containing a write register bit (WRB); and an interface configured to receive messages from a host application, the messages including a WRB enablement signal, wherein the device is configured to enable writing to the register file in response to receiving the WRB enablement signal over the interface, write data in response to write messages while writing to the register file is enabled, and disable writing to the register file in response to receiving a stop bit over the interface.

A pluggable communication module (200) includes a circuit card (250) having a substrate (258) with an edge (252). The pluggable communication module includes an EEPROM device (300) having a power supply pin (312), a serial data pin (314), a serial clock pin (316), a ground pin (318), and a write control pin (320) for programming the EEPROM device. The pluggable communication module includes a contact pad region (262) near the edge having a signal pad (264), a ground pad (266), a power pad, a serial data pad (270), a serial clock pad (272), and a write pad (280). The write pad is located at a programming depth of the circuit card edge in front of the signal pad to mate the write pad to the receptacle connector (112) without mating the signal pad to the receptacle connector.

Various illustrative aspects are directed to a data storage device, comprising one or more disks; an actuator system configured to position a selected head among one or more heads proximate to a corresponding disk surface among the one or more disks; and one or more processing devices. The selected head comprises a write element, an assistive energy emitter, an energizing interface coupled to the assistive energy emitter, and a detector. The assistive energy emitter is driven separately from driving of the write element. The one or more processing devices are configured to detect, via the detector, an energy anomaly at the energizing interface; detect, in response to detecting the energy anomaly, whether a previously written track yields an anomalous readback signal; and rewrite, in response to detecting that the previously written track yields an anomalous readback signal, data designated for the previously written track to the previously written track.

The present application relates to a kind of on-orbit router software security reconstruction method, for transmission monitoring lag, high delay verification and insufficient isolation problem, propose integrity chain check and firewall double-layer verification collaborative scheme, combined with modular physical isolation design.Routing module activates hardware write protection lock when receiving data packet, prohibits unauthorized modification and supports policy lock-free update;Platform management module real-time download cumulative check value, ground verification after upper reconstruction instruction;Program burn module uses double Bank storage, supports atomization burn and trusted verification, abnormal automatic rollback safety version.Through space-earth collaborative double-loop verification (firewall filtering, token bucket flow limiting, ground CRC check) to resist attack, hardware isolation ensures that updating does not interrupt routing operation, intelligent rollback improves fault tolerance.Ceiling for high delay, strong interference on-orbit routing scene, guarantee transit / overseas satellite on-orbit maintenance when reconstructing business zero interruption, meet modern satellite network security needs.

The invention discloses a method, a device and equipment for protecting a nonvolatile memory, and relates to the field of automation control, the method comprises the following steps: acquiring an erasing condition of a target nonvolatile memory in a preset time period; if the erasing condition is an erasing state, increasing a time integral count value by using a preset accumulated value; when the time integral count value is greater than or equal to a frequent erasing threshold value, determining that frequent erasing exists in the target nonvolatile memory, and executing a preset frequent erasing protection operation; according to the method, frequent erasing and writing of the target nonvolatile memory are recognized by adopting the thought of writing time integration, the process of counting the writing times of each storage unit is avoided, and accurate recognition of frequent erasing and writing of the nonvolatile memory can be realized with relatively small resource occupation, so that after the frequent erasing and writing are recognized, the storage efficiency of the nonvolatile memory is improved. By executing the preset frequent erasing and writing protection operation, the writing protection function of the nonvolatile memory is realized, and long-term and low-frequency accumulated erasing and writing can be effectively identified and blocked.

The invention discloses a bus control module for converting an SPI bus into an AHB. The bus control module comprises an SPI slave instruction data analysis module, a register module, a mode configuration module, a data transmission cache module, a data detection module and a state detection module, wherein the instruction data analysis module is used for instructions, addresses and data, the register module comprises a plurality of registers used for configuring module functions, and the mode configuration module is used for configuring a transmission mode; according to the invention, the read-write control of the register in the module can be realized through the read-write instruction section, the stability of data transmission is ensured through a dual write protection mechanism, and an external SPI host realizes the read-write of the register in the SOC and the reading and loading of firmware through the SPI bus-to-AHB bus control module, so that the stability of data transmission is ensured. Wherein the firmware is stored in an RAM (Random Access Memory) storage area or a plug-in FLASH storage area in the SOC.

The present application relates to a kind of solid state disk fault pre-diagnosis and data security self-repair processing method and device, belong to memory technical field, method includes: in the running process of solid state disk, the block erase time of each memory block is monitored, when the block erase time of one or more memory blocks is first exceeded early warning threshold, the memory block is marked as early warning state;The block erase time variation rate of memory block marked as early warning state is continuously monitored, if the block erase time variation rate exceeds acceleration degradation threshold, then determine that memory block enters high-risk state;Hot data identification operation is carried out to the memory block of high-risk state, identify the data page of the wear value in the memory block higher than set level;The identified high wear value data page is migrated to the reserved healthy memory block, and after migration is completed, write protection locking operation is carried out to the memory block of original high-risk state;Realize the effect of data security initiative protection and storage life collaborative optimization.

This invention discloses a controller and control method for SRAM erase protection verification in an MCU architecture, belonging to the field of memory technology. This invention solves the problem that existing devices cannot simultaneously include multiple functions. By employing an SRAM erase protection verification device, write protection can be configured for each page individually, achieving write protection for SRAM data. The entire SRAM data is erased, and after erasure, write protection and data verification functions continue to be executed, improving read / write efficiency. Furthermore, SRAM data can be verified. When the SRAM controller reads any address, it latches that address and pulls up the read verification flag for that address. Then, an even-number verification is performed on the byte with the verification bit and the latched address. If the verification result is low, the verification passes; otherwise, it indicates a data error, and the error verification result is fed back to the system, thereby meeting the high requirements of the system for the SRAM controller.

The invention discloses a data writing method and a nonvolatile memory. The data writing method comprises the steps that a writing instruction sent by a display driving chip is received, the writing instruction carries to-be-written data and a writing address, the writing address indicates a target writing area, the multiple data storage areas comprise the target writing area, and the target writing area corresponds to the to-be-written data; the to-be-written data comprises DBI data corresponding to at least one compensation moment; a write protection state corresponding to the target write-in area is obtained from write protection information, and the write protection information is used for indicating the write protection state of each data storage area; and writing the to-be-written data into the target write-in area under the condition that the write protection state of the target write-in area is an open state.

The application belongs to the field of memory devices, and particularly relates to a memory device based on two-dimensional ferromagnetic intrinsic temperature-controlled magnetization characteristics and a preparation method. The memory device comprises a substrate, a source electrode, a drain electrode, a gate electrode, a channel layer and a gate dielectric layer. The source electrode, the drain electrode and the gate electrode are arranged on the substrate. The channel layer is arranged between the source electrode and the drain electrode, and comprises a two-dimensional ferromagnetic material sheet. The gate dielectric layer covers the gate electrode and the entire channel layer. Under the condition of being higher than a carrier type transition temperature, the channel layer magnetism can be non-volatile programmed by a gate voltage. Under the condition of being lower than the transition temperature, the channel layer presents magnetic state stability to the same gate write operation, and realizes heat-controlled write protection. The two-dimensional ferromagnetic memory device does not need a complex stacking structure or an external magnetic field, and can realize programmable, non-volatile and high-stability magnetic storage functions only by temperature and gate voltage cooperation. The device structure is simple, and power consumption is low.

The present application relates to the field of intelligent agriculture technology, and provides a lightweight intelligent production management system for multiple breeding varieties, which comprises a three-layer lightweight architecture using a hardware acquisition end, an edge operation end and a local interaction end. Each end cooperates to realize local data acquisition, analysis, operation, storage and interaction without cloud dependence. The system is based on the core data flow logic of real-time sharing of environmental monitoring data and precise feeding data linkage, feeding and weighing data and inventory accounting data, and integrally realizes intelligent regulation and control of breeding environment, precise feeding management, full-dimension production data acquisition, inventory digital accounting, equipment state monitoring and remote visualized supervision. By accurately implementing the hash value evidence mechanism into specific breeding business scenarios such as feed weight, weighing at slaughter, and feed into warehouse, and combining with multiple technical means such as device unique identification, timestamp, database encryption storage and write protection, the data is prevented from being tampered with throughout the whole process, and the authenticity and traceability of the data are guaranteed.

The utility model provides a switching circuit, a mainboard and electronic equipment. The switching circuit comprises a first BIOS (Basic Input / Output System) chip, a second BIOS chip, a change-over switch and a standby BIOS socket, the change-over switch comprises a first input pin, a second input pin, a first output pin and a second output pin; the standby BIOS socket comprises a first universal pin corresponding to a second chip selection pin of the second BIOS chip and a second universal pin corresponding to a second write protection pin of the second BIOS chip; the first output pin is electrically connected with a first chip selection pin of the first BIOS chip, the second output pin is electrically connected with the first universal pin, and the second universal pin is electrically connected with the second input pin; and when the standby BIOS socket is connected to the second BIOS chip, the second universal pin is configured to be in a low-level state from a high-level state. According to the embodiment of the utility model, when the BIOS chip is repaired, hardware is not easy to damage, and the BIOS chip repairing device is simpler and more efficient.

A processing device, operatively coupled with a memory device, retrieves data from the memory device for merging at one or more sectors of a cache line in a cache, wherein the cache line comprises a plurality of sectors. The processing device determines, based on one or more bits associated with each sector of the cache line, whether each sector of the cache line is configured with at least one of a write protection mode and enable mode, respectively. The processing device writes the data from the memory device to each sector of the cache line using the at least one of the write protection mode or the enable mode.

The invention provides a data security write protection judgment method, a controller, a medium and a product, which are applied to the technical field of data storage and applied to eMMC equipment, and the method comprises the following steps: acquiring write protection information of a persistent storage unit and current security write protection modes of a plurality of write protection areas; mapping the write protection information according to the current security write protection mode to obtain a mapping value, and obtaining an equipment cache value according to the mapping value; in response to the setting instruction, updating the device cache value to obtain an updated device cache value; and in response to a user operation instruction, performing operation judgment according to the updated equipment cache value to obtain a judgment result, and performing data writing or data erasing according to the judgment result. According to the method and the device, the write protection information can be mapped through the current security write protection mode to obtain the equipment cache value, so that whether data writing or data erasing can be performed or not is determined by judging the equipment cache value, and therefore, the write protection judgment efficiency can be improved.

The application discloses a software-based write protection device and method, and relates to the technical field of storage. The device comprises an acquisition unit, which is used for acquiring write protection region information from a preset storage region, wherein the write protection region information contains a protection range for performing a control operation on a write operation, and the protection range contains at least one address information that needs to be protected; a determination unit, which is used for determining write address information from a write operation instruction when the write operation instruction is received; a judgment unit, which is used for judging whether the write address information matches the address information in the write protection region information; and an execution unit, which is used for intercepting the write operation instruction if the write address information matches the address information in the write protection region information.

The invention discloses a write protection method, electronic equipment and a storage medium, and relates to the technical field of storage, the method comprises the following steps: receiving an erasing request for flash, and obtaining a target erasing area from the erasing request; a target area identifier of the target erasing and writing area is obtained in a preset area protection mapping relation, the area protection mapping relation comprises the area identifier of each storage area in a plurality of storage areas in the flash, and the area identifier support is configured to be a write protection identifier or an erasable identifier; and controlling the erasing permission of the target erasing area according to the target area identifier. The technical problem that high flexibility and high safety are difficult to consider in flash storage is solved.

The present invention relates to an electronic device, wherein the storage device according to the present invention includes a memory device and a memory controller. The memory device includes a write protection area. The memory controller controls the memory device to perform a read operation on the write protection area in response to a series of requests regarding a secure read received from a host, provides read data received from the memory device to the host, and generates a device authentication code based on the read data. The memory controller performs the generation of the device authentication code and the provision of read data to the host in parallel.

The invention provides a data management method and an intelligent card, and the method comprises the steps: enabling a transaction management layer to respond to a transaction request sent by an interface layer, and judging whether a volatile memory has an available storage space meeting a preset condition or not; if not, the transaction management layer executes an NVMlog backup mode, so that the physical write protection layer writes the to-be-written data into the target storage address; if yes, the transaction management layer executes an RAMlog backup mode, so that the physical write protection layer writes the to-be-written data into the target storage address; wherein if the length of the to-be-written data is larger than one page, the transaction management layer controls the current transaction to be in an unsubmitted state until the historical data corresponding to all the to-be-written data is backed up. According to the mode, dynamic switching can be carried out between the RAM log backup mode with the cache as the main part and the NVMlog backup mode with the direct writing as the main part, and therefore the data writing efficiency and reliability of the intelligent card are improved.

The application relates to the technical field of community owner voting, and discloses a community owner online voting system and method supporting a temporary voting locking mechanism, which comprises the following modules: a voting terminal module used for collecting voting messages; a voting processing module used for analyzing and extracting a house property identifier and processing data to generate desensitization intention data; a voting locking cache module used for establishing mutual exclusion index bits in memory to lock the intention data; an identity verification module used for querying a property right database and triggering comparison; an effective period control module used for setting a constraint window; and a ticket generation module used for releasing write protection permission and realizing atomic storage when the window is valid and the comparison is passed. The application uses a memory mutual exclusion locking architecture based on a house property identifier, solves voting right conflicts under shared property rights, reduces property right database query pressure, and guarantees the certainty of voting intention under complex working conditions.

The embodiment of the present application relates to the application field of storage devices, and discloses a data write protection method and a storage device, the method comprising the following steps: when the storage device is in a write state, obtaining the compression ratio and the residual effective capacity of each valid super block of the storage device; calculating a first approximate compression ratio according to the compression ratio of each valid super block; and determining the write protection strategy of the storage device according to the comparison result of the first approximate compression ratio and a preset compression ratio, and the comparison result of the residual effective capacity and a capacity threshold. The write protection strategy of the storage device is determined according to the comparison result of the first approximate compression ratio and the preset compression ratio, and the comparison result of the residual effective capacity and the capacity threshold, so that the problem that the storage device is down due to the continuous data writing of the host can be solved, and the stability of the storage device is improved.

The invention discloses a main and standby database switching method and system based on performance self-adaptive evaluation. According to the method, multi-dimensional performance indexes of main and standby database nodes are collected in real time, the service health score of each node is dynamically calculated based on an adaptive weight model, and the fundamental transformation from recovery after failure to prevention before performance degradation is realized. And when the health score of the main node is continuously lower than a preset threshold value and a standby node with obviously higher health score exists, the system automatically triggers a preventive switching instruction and sequentially executes an elegant degradation process of write protection, data chasing, flow switching and role flipping. According to the method, the problems of single state judgment dimension, switching trigger lagging and extensive process control of a traditional heartbeat mechanism are effectively solved, the sub-health risk that the process survives but the service is unavailable can be accurately identified, the data consistency and the service continuity in the switching process are guaranteed, the service influence is remarkably reduced, and the user experience is improved. The method is suitable for key business scenes with strict high-availability requirements, such as finance and telecommunication.

The application discloses a machining center FANUC coordinate system protection method, comprising the following steps: step S1: dividing the coordinate system parameters according to the importance degree to divide the protection level, switching the parameter write protection control right to the PMC signal through the system parameter setting, and writing the permission judgment logic in the PMC ladder diagram; step S2: constructing the background parameter monitoring mechanism based on the macro program interruption function and the PMC window function, periodically reading the current value of each level parameter and comparing with the reference value; step S3: triggering the differential early warning and processing mechanism according to the safety level of the modified parameter, and automatically executing the parameter backup after the authorized modification confirmation; step S4: establishing the log buffer area in the PMC, and real-time recording the coordinate system related operation behavior and storing in the non-volatile area. The application can cover more than 90% of the FANUC system machining center on the market, and can be used for self-owned factory equipment batch upgrading, and can also carry out technical service, technical consultation and technology transfer.

Various embodiments of this disclosure provide file write protection methods, apparatuses, electronic devices, storage media, and products. The file write protection method according to an embodiment includes: when an application modifies a page of a target file in the page cache through a file write operation, intercepting the dirty page marking function of the system call executing the file write operation; determining that the target file is in a protected state if the inode of the target file has a protection flag set; and based on the target file being in a protected state, intercepting the dirty page marking function's dirty page marking of the target file's pages. Through this disclosure, file write protection can intercept file writes in a timely manner at the page cache level, effectively blocking malicious file writes.

The invention discloses an embedded system snapshot optimization method and system oriented to a resource-constrained environment. The method comprises the following steps: firstly, configuring snapshot parameters according to hardware parameters of the embedded equipment; secondly, constructing a page state management structure, and continuously capturing page writing events during scanning in a pre-copying stage so as to distinguish a high-writing-frequency page from a low-writing-frequency page; executing multiple rounds of traversal in the pre-copying stage to ensure the convergence of the working set, and judging whether to terminate the pre-copying stage or not according to the convergence; storing the identified working set pages instead of all dirty pages in the shutdown stage again, setting write protection for non-working set pages, and restoring the operation of the virtual machine; after the operation of the virtual machine is recovered, a non-working set is stored in the background; and finally, real-time redundancy elimination and writing are carried out. According to the method, the shutdown duration can be effectively shortened in an embedded scene with dense dynamic write-in and obvious working set change, the snapshot duration and the storage write-in burden are reduced, and the overall performance of an embedded virtualization operation framework is improved.

The invention discloses a display device, a control method and display equipment, and relates to the field of display, the display device comprises a time schedule controller and an I2C bus, the time schedule controller is provided with a write protection end, and a bus control end of the time schedule controller is connected with the I2C bus; the time schedule controller is used for controlling the communication state of the I2C bus to be a communication stop state under the condition that the write protection end is detected to be at a preset protection level; and the time schedule controller is used for controlling the communication state of the I2C bus to be a communication allowing state under the condition that the write protection end is detected to be at a preset write level. According to the method and the device, the technical problem of abnormal display caused by the fact that the Code is easily rewritten by mistake is solved.

Methods, systems, and devices for techniques for a sequential write protection mode in a memory system are described. A memory system may receive one or more commands to write data to associated sequential memory addresses using a write automation block (WAB) while monitoring the addresses of the data. In the case that a write command may be associated with a non-sequential memory address, the memory system may store an associated pointer to a cache. The memory system may continue to write data indicated via incoming commands using the WAB until the memory system detects and writes the sequential command or a threshold quantity of commands have been received. If the threshold is reached prior to receiving the missing command, the memory system may disable the WAB and transmit an error message. The memory system may block and return error messages to any subsequent commands until the missing command is received.

This invention provides a multi-protocol compatible write protection method and system for storage media, comprising: generating a PCIe configuration space read request when a device is detected inserted into a host; responding to the request, virtualizing the back-end connected storage media into a USB controller under the xHCI protocol to generate virtualization information; based on the virtualization information, prefetching command transfer request blocks for new events and performing deep inspection to obtain the instruction type of the command transfer request block; if the instruction type is a write instruction type, discarding data and generating a virtual completion event message for the new event; if the instruction type is a read instruction type, remapping and protocol conversion of the address corresponding to the command transfer request block to obtain a converted read instruction; and generating and outputting an interrupt instruction based on the virtual completion event message or the converted read instruction. This method eliminates the bandwidth bottleneck of USB read-only locks and improves transmission efficiency.

The invention provides a dynamic self-protection method, device and equipment of a vehicle-mounted electronic control unit (ECU), and the dynamic self-protection method of the vehicle-mounted electronic control unit comprises the steps: dividing the storage space of the ECU to obtain at least two functional areas, namely a target protection area and an application storage area, the storage space is an external Flash chip externally connected with the ECU; after the vehicle-mounted ECU is powered on and started, the Bootloader program detects whether the current ECU has a legal programming request or not and judges whether the application program is valid or not so as to determine that the current running scene is a normal starting scene or an authorized updating scene; if the scene is judged to be a normal starting scene, executing write protection enabling operation, and skipping to the application program after the target protection area is in a non-erasable and non-writable state; if it is judged that the scene is authorized to be updated, write protection removing operation is executed after security authentication so as to allow firmware updating, and after updating is completed, the ECU is controlled to reset and the scene judgment process is triggered again.