65 results about "Write protection" patented technology

The invention discloses a power grid material sampling inspection management method for realizing whole-course tracing based on intelligent sample sealing, and relates to the technical field of electric power material management and intelligent perception, and the method comprises the following steps: S1, an initialization stage: executing a sample sealing coding segmentation pre-configuration process, distributing independent numbered segments to each sample sealing terminal, and the central control module synchronizes the use state of the terminal code to realize distributed isolation of code generation. According to the invention, coding uniqueness is realized through segmented pre-configuration and global duplicate checking, identity information security is guaranteed by adopting chip one-time write protection and tamper-proof technologies, and sample packet switching and data counterfeiting are effectively prevented by combining automatic acquisition and multi-round consistency comparison. Abnormal recognition and closed-loop processing ensure that abnormal events are frozen in time and responsibility is traced, and irregular samples are prevented from flowing into subsequent links. The whole-process auditing and dynamic optimization enable the management process to be self-perfected, and the intelligence, standardization and reliability of sampling inspection of the power grid materials are remarkably improved.

The invention relates to a satellite-borne router software security reconstruction method, aims to solve the problems of transmission monitoring lag, high-delay verification and insufficient isolation, provides an integrity chain verification and firewall double-layer verification cooperation scheme, and is combined with a modular physical isolation design. When the routing module receives the data packet, a hardware write protection lock is activated, unauthorized modification is forbidden, and strategy lock-free update is supported; the platform management module downloads an accumulated verification value in real time, and pays attention to a reconstruction instruction after ground verification; and the program programming module adopts double Bank storage, supports atomization programming and credible verification, and automatically returns a safe version when an exception occurs. Attacks are defended through satellite-ground cooperative double-closed-loop verification (firewall filtering, token bucket current limiting and ground CRC verification), hardware isolation guarantees updating without interrupting routing operation, and intelligent backspacing improves the fault-tolerant capability. The method is suitable for a high-delay and strong-interference satellite-borne routing scene, ensures zero interruption of a reconstruction service during in-orbit maintenance of a transit / overseas satellite, and meets the security requirement of a modern satellite network.

The invention relates to the field of artificial intelligence hardware, in particular to a neural network training method based on quantum annealing optimization, and the method comprises the steps: firstly solving a gradient at a graphics processor, and generating an energy coefficient through neuromorphic coding; dividing the weight into sub-blocks according to a coupling threshold value, outputting initial spinning by an optical coherence Isin optimizer, performing reverse annealing by a quantum annealing processor to obtain optimal spinning, and freezing scale parameters; then, a noise consistency optimizer is used for finely adjusting scale parameters, discrete weights are reconstructed according to spin-scale and written into the memristive cross array unit by unit, and hardware errors are eliminated through read-write-check cycle and column gain-row bias dual calibration; and generating a deployment model file and executing write protection after double-end multi-time sampling is carried out at a reference low temperature to confirm spin consistency. The method has high-speed convergence, low-energy-consumption writing and long-term reasoning stability, and the training and deployment efficiency of a large-scale neural network on light-quantum-memristive heterogeneous hardware is remarkably improved.

The invention discloses a low-interaction secure handshake method, device and system based on spatio-temporal context constraint, order deviation extraction and polarity hedging verification, a chip and a storage medium. According to the method, local physical feature anchor points formed by a plurality of physical nodes in a hardware carrier are extracted, in combination with context parameters such as time, space, environment, operation state and historical state abstracts, order deviation parameters related to a current session are generated, session mapping factors are constructed according to the order deviation parameters, and constraint mapping is executed on a to-be-processed load. At a receiving end, a verification end or a local processing end, a matching result is obtained by simulating in-situ polarity hedging verification, differential matching, residual auditing or closed auditing of a front end, and control such as session establishment, limited release, load zero clearing, blocking or write protection is executed according to a complete matching state, a partial matching state and a mismatching state. According to the scheme, the physical state of the device, the environmental condition and the session history can be jointly incorporated into a safety judgment chain, so that the interactive burden of the explicit key is reduced, and the countermeasure ability to replay, counterfeit, ectopic reproduction and high-frequency heuristic is improved; the method can be applied to scenes such as equipment access authentication, secure communication handshake, high-value operation admission, controlled terminal access and off-line signature.

The application discloses a method for managing IO write operation and a storage device. The method comprises the following steps: receiving an IO write operation issued by a host; detecting whether the host starts a high-load write protection mode; if yes, obtaining write management information of the high-load write protection mode, wherein the write management information comprises data stream information of historical IO write operation; judging whether the IO write operation is a sequential write operation according to the data stream information; and if yes, updating the data stream information according to position metadata of the IO write operation. The application can improve the reliability and write performance of the device when high-load video recording is performed.

The application relates to the technical field of servers and discloses a fault memory positioning method, system and device, computer equipment and a storage medium, the method comprising the following steps: in the case that a memory fault signal is received and a server is in a shutdown state, the write protection state of a power management chip register is released; candidate fault memories are determined according to the memory fault signal; a disable command is written into the power management chip register of the candidate fault memories, wherein the disable command is used to not power on the candidate fault memories when the server enters a startup state; in the case that the server enters the startup state, log information of the candidate fault memories is acquired; and according to the log information, a target fault memory and slot position information of the target fault memory are determined from the candidate fault memories. The application solves the problems that it is difficult to acquire abnormal information capable of accurately positioning the fault memories and the PMIC fault memories cannot be positioned.

Disclosed are devices and methods for protecting the register file of a power management integrated circuit (PMIC). In one embodiment, a device is disclosed comprising: a register file comprising a plurality of a registers, at least one register in the register file containing a write register bit (WRB); and an interface configured to receive messages from a host application, the messages including a WRB enablement signal, wherein the device is configured to enable writing to the register file in response to receiving the WRB enablement signal over the interface, write data in response to write messages while writing to the register file is enabled, and disable writing to the register file in response to receiving a stop bit over the interface.

A secure boot method of an Internet of Things (IoT) apparatus includes: in response to a system boot signal of the IoT apparatus, verifying an authentication signature of a bootloader firmware and an authentication signature of an application layer (App) firmware; reading an encryption key stored in a one-time programmable memory in response to determining that the authentication signature of the bootloader firmware and the authentication signature of the App firmware both pass verification, in which the encryption key is configured to have a write protection attribute; decrypting the App firmware according to the encryption key, and running the decrypted App firmware; and in response to determining to read encrypted flash-memory partition data in a flash memory (Flash), decrypting the encrypted flash-memory partition data according to the encryption key, so as to securely boot up the IoT apparatus.

A pluggable communication module (200) includes a circuit card (250) having a substrate (258) with an edge (252). The pluggable communication module includes an EEPROM device (300) having a power supply pin (312), a serial data pin (314), a serial clock pin (316), a ground pin (318), and a write control pin (320) for programming the EEPROM device. The pluggable communication module includes a contact pad region (262) near the edge having a signal pad (264), a ground pad (266), a power pad, a serial data pad (270), a serial clock pad (272), and a write pad (280). The write pad is located at a programming depth of the circuit card edge in front of the signal pad to mate the write pad to the receptacle connector (112) without mating the signal pad to the receptacle connector.

Various illustrative aspects are directed to a data storage device, comprising one or more disks; an actuator system configured to position a selected head among one or more heads proximate to a corresponding disk surface among the one or more disks; and one or more processing devices. The selected head comprises a write element, an assistive energy emitter, an energizing interface coupled to the assistive energy emitter, and a detector. The assistive energy emitter is driven separately from driving of the write element. The one or more processing devices are configured to detect, via the detector, an energy anomaly at the energizing interface; detect, in response to detecting the energy anomaly, whether a previously written track yields an anomalous readback signal; and rewrite, in response to detecting that the previously written track yields an anomalous readback signal, data designated for the previously written track to the previously written track.

The present application relates to a kind of on-orbit router software security reconstruction method, for transmission monitoring lag, high delay verification and insufficient isolation problem, propose integrity chain check and firewall double-layer verification collaborative scheme, combined with modular physical isolation design.Routing module activates hardware write protection lock when receiving data packet, prohibits unauthorized modification and supports policy lock-free update;Platform management module real-time download cumulative check value, ground verification after upper reconstruction instruction;Program burn module uses double Bank storage, supports atomization burn and trusted verification, abnormal automatic rollback safety version.Through space-earth collaborative double-loop verification (firewall filtering, token bucket flow limiting, ground CRC check) to resist attack, hardware isolation ensures that updating does not interrupt routing operation, intelligent rollback improves fault tolerance.Ceiling for high delay, strong interference on-orbit routing scene, guarantee transit / overseas satellite on-orbit maintenance when reconstructing business zero interruption, meet modern satellite network security needs.

The invention discloses a method, a device and equipment for protecting a nonvolatile memory, and relates to the field of automation control, the method comprises the following steps: acquiring an erasing condition of a target nonvolatile memory in a preset time period; if the erasing condition is an erasing state, increasing a time integral count value by using a preset accumulated value; when the time integral count value is greater than or equal to a frequent erasing threshold value, determining that frequent erasing exists in the target nonvolatile memory, and executing a preset frequent erasing protection operation; according to the method, frequent erasing and writing of the target nonvolatile memory are recognized by adopting the thought of writing time integration, the process of counting the writing times of each storage unit is avoided, and accurate recognition of frequent erasing and writing of the nonvolatile memory can be realized with relatively small resource occupation, so that after the frequent erasing and writing are recognized, the storage efficiency of the nonvolatile memory is improved. By executing the preset frequent erasing and writing protection operation, the writing protection function of the nonvolatile memory is realized, and long-term and low-frequency accumulated erasing and writing can be effectively identified and blocked.

The application discloses a data erasing method and an electronic device, relates to the technical field of data processing, and comprises the following steps: a processor only allows to start a write protection closing and a data erasing process when a management board is a secondary return board type, so that the miserasing operation of a non-target scene such as first production and operation and maintenance is avoided from a scene source. In addition, the closing of the write protection function is directly linked depending on a hardware pin, so that the risk of mistriggering or vulnerability at the software level is reduced. Therefore, the data erasing method provided by the application improves the security of data erasing processing on data in a target address range.

The invention discloses a bus control module for converting an SPI bus into an AHB. The bus control module comprises an SPI slave instruction data analysis module, a register module, a mode configuration module, a data transmission cache module, a data detection module and a state detection module, wherein the instruction data analysis module is used for instructions, addresses and data, the register module comprises a plurality of registers used for configuring module functions, and the mode configuration module is used for configuring a transmission mode; according to the invention, the read-write control of the register in the module can be realized through the read-write instruction section, the stability of data transmission is ensured through a dual write protection mechanism, and an external SPI host realizes the read-write of the register in the SOC and the reading and loading of firmware through the SPI bus-to-AHB bus control module, so that the stability of data transmission is ensured. Wherein the firmware is stored in an RAM (Random Access Memory) storage area or a plug-in FLASH storage area in the SOC.

The application provides an eBPF-based Redis large Key real-time detection and protection method and system. The method obtains Redis process information, probe mounting parameters and large Key judgment threshold, loads an eBPF program to a kernel and writes the eBPF program into a BPF Map to obtain a runtime monitoring configuration; based on the runtime monitoring configuration, a probe is mounted on a Redis command receiving, command processing, response construction and command returning path; when a client request arrives, a request buffer and a client connection context are read, a RESP length prefix is parsed to obtain a command type, a target key and a request data size; according to the command type, a write detection process or a read detection process is entered, a write protection strategy is generated and executed when the request data size exceeds a write threshold, and a large Key read event is generated when an accumulated response data size exceeds a read threshold, so that real-time detection, write protection and read alarm of a Redis large Key are realized.

The application discloses a method for binding and unbinding of a master and slave lock. The application realizes a convenient and safe operation trigger mode by using the encryption information carried by an RFID card and the advanced read-write protection characteristics thereof. The scheme simplifies the complex process of traditional manual information filling of terminal equipment into two core operations of "swiping the master lock -> swiping the slave lock". The operator does not need to learn the complex terminal operation logic, nor does the operator need to remember or input long device ID, key and other information, and the binding process can be triggered only by holding the RFID card and touching the master and slave lock in sequence.

The present application relates to a kind of solid state disk fault pre-diagnosis and data security self-repair processing method and device, belong to memory technical field, method includes: in the running process of solid state disk, the block erase time of each memory block is monitored, when the block erase time of one or more memory blocks is first exceeded early warning threshold, the memory block is marked as early warning state;The block erase time variation rate of memory block marked as early warning state is continuously monitored, if the block erase time variation rate exceeds acceleration degradation threshold, then determine that memory block enters high-risk state;Hot data identification operation is carried out to the memory block of high-risk state, identify the data page of the wear value in the memory block higher than set level;The identified high wear value data page is migrated to the reserved healthy memory block, and after migration is completed, write protection locking operation is carried out to the memory block of original high-risk state;Realize the effect of data security initiative protection and storage life collaborative optimization.

This invention discloses a controller and control method for SRAM erase protection verification in an MCU architecture, belonging to the field of memory technology. This invention solves the problem that existing devices cannot simultaneously include multiple functions. By employing an SRAM erase protection verification device, write protection can be configured for each page individually, achieving write protection for SRAM data. The entire SRAM data is erased, and after erasure, write protection and data verification functions continue to be executed, improving read / write efficiency. Furthermore, SRAM data can be verified. When the SRAM controller reads any address, it latches that address and pulls up the read verification flag for that address. Then, an even-number verification is performed on the byte with the verification bit and the latched address. If the verification result is low, the verification passes; otherwise, it indicates a data error, and the error verification result is fed back to the system, thereby meeting the high requirements of the system for the SRAM controller.

The utility model relates to a video signal device for providing multiple EDID data. Comprising an EDID storage circuit, an EDID switching circuit, an EDID forbidding circuit and a write protection switching circuit. The multi-EDID display device has a multi-EDID data storage and switching function, so that a user can select different display modes. The EDID forbidding circuit ensures that the display card can normally read EDID data when the HPD is lowered and recovered to a high level. And the write protection function of the EDID memory can be controlled.

The invention discloses a data writing method and a nonvolatile memory. The data writing method comprises the steps that a writing instruction sent by a display driving chip is received, the writing instruction carries to-be-written data and a writing address, the writing address indicates a target writing area, the multiple data storage areas comprise the target writing area, and the target writing area corresponds to the to-be-written data; the to-be-written data comprises DBI data corresponding to at least one compensation moment; a write protection state corresponding to the target write-in area is obtained from write protection information, and the write protection information is used for indicating the write protection state of each data storage area; and writing the to-be-written data into the target write-in area under the condition that the write protection state of the target write-in area is an open state.

A control circuit including a storage circuit, a register, and a write protection logic circuit is provided. The storage circuit stores data, an enable-set value and a mode-set value. The register stores a protection-set value. The write protection logic circuit determines whether to change at least one of the enable-set value, the mode-set value, and the protection-set value according to the mode-set value after receiving a write command. In response to the mode-set value matching a pre-determined value, the write protection logic circuit changes at least one of the enable-set value, the mode-set value, and the protection-set value according to the protection-set value. In response to the mode-set value not matching the pre-determined value, the write protection logic circuit does not change the enable-set value and the mode-set value.

The application belongs to the field of memory devices, and particularly relates to a memory device based on two-dimensional ferromagnetic intrinsic temperature-controlled magnetization characteristics and a preparation method. The memory device comprises a substrate, a source electrode, a drain electrode, a gate electrode, a channel layer and a gate dielectric layer. The source electrode, the drain electrode and the gate electrode are arranged on the substrate. The channel layer is arranged between the source electrode and the drain electrode, and comprises a two-dimensional ferromagnetic material sheet. The gate dielectric layer covers the gate electrode and the entire channel layer. Under the condition of being higher than a carrier type transition temperature, the channel layer magnetism can be non-volatile programmed by a gate voltage. Under the condition of being lower than the transition temperature, the channel layer presents magnetic state stability to the same gate write operation, and realizes heat-controlled write protection. The two-dimensional ferromagnetic memory device does not need a complex stacking structure or an external magnetic field, and can realize programmable, non-volatile and high-stability magnetic storage functions only by temperature and gate voltage cooperation. The device structure is simple, and power consumption is low.

The present application relates to the field of intelligent agriculture technology, and provides a lightweight intelligent production management system for multiple breeding varieties, which comprises a three-layer lightweight architecture using a hardware acquisition end, an edge operation end and a local interaction end. Each end cooperates to realize local data acquisition, analysis, operation, storage and interaction without cloud dependence. The system is based on the core data flow logic of real-time sharing of environmental monitoring data and precise feeding data linkage, feeding and weighing data and inventory accounting data, and integrally realizes intelligent regulation and control of breeding environment, precise feeding management, full-dimension production data acquisition, inventory digital accounting, equipment state monitoring and remote visualized supervision. By accurately implementing the hash value evidence mechanism into specific breeding business scenarios such as feed weight, weighing at slaughter, and feed into warehouse, and combining with multiple technical means such as device unique identification, timestamp, database encryption storage and write protection, the data is prevented from being tampered with throughout the whole process, and the authenticity and traceability of the data are guaranteed.

The utility model provides a switching circuit, a mainboard and electronic equipment. The switching circuit comprises a first BIOS (Basic Input / Output System) chip, a second BIOS chip, a change-over switch and a standby BIOS socket, the change-over switch comprises a first input pin, a second input pin, a first output pin and a second output pin; the standby BIOS socket comprises a first universal pin corresponding to a second chip selection pin of the second BIOS chip and a second universal pin corresponding to a second write protection pin of the second BIOS chip; the first output pin is electrically connected with a first chip selection pin of the first BIOS chip, the second output pin is electrically connected with the first universal pin, and the second universal pin is electrically connected with the second input pin; and when the standby BIOS socket is connected to the second BIOS chip, the second universal pin is configured to be in a low-level state from a high-level state. According to the embodiment of the utility model, when the BIOS chip is repaired, hardware is not easy to damage, and the BIOS chip repairing device is simpler and more efficient.

The utility model discloses a KVM (Keyboard Video Mouse) multi-host read-write protection system, which comprises a storage module, at least two input devices and a data interface, and further comprises a data module connected with the input devices; the signal switching logic module is connected with a downlink port of the data module, and the downlink port of the signal switching logic module is connected with a plurality of data interfaces; the read-write monitoring module is connected with the data module; the read-write protection module is respectively connected with the storage module, the read-write monitoring module and the signal switching logic module and realizes communication with the storage module, the read-write monitoring module and the signal switching logic module; and the power supply control module is connected with the read-write protection module, and when the data module switches the host equipment and the read-write monitoring module detects that the equipment connected with the data interface or the storage module is performing read-write operation, the power supply control module controls the read-write protection module to feed back a signal that the host equipment is not allowed to be switched. And the host is allowed to be switched until reading and writing of the equipment or the storage module connected with the data interface are completed.

A processing device, operatively coupled with a memory device, retrieves data from the memory device for merging at one or more sectors of a cache line in a cache, wherein the cache line comprises a plurality of sectors. The processing device determines, based on one or more bits associated with each sector of the cache line, whether each sector of the cache line is configured with at least one of a write protection mode and enable mode, respectively. The processing device writes the data from the memory device to each sector of the cache line using the at least one of the write protection mode or the enable mode.

The invention discloses a method for updating DMI information based on an onboard EEPROM (Electrically Erasable Programmable Read-Only Memory), which comprises the following steps: a HOST module closes write protection of an EEPROM module, clears original DMI data in the EEPROM module, and then writes new DMI data; the HOST module opens write protection of the EEPROM module, and proofreading is carried out on newly written DMI data; if the proofreading fails, the steps are repeated, if the proofreading succeeds, the HOST module waits for the DMI updating signal, and after the DMI updating signal is received, the HOST module reads the DMI data from the EEPROM module and updates the DMI information in the SMBIOS table. According to the method, the defects in the prior art can be overcome, the data read-write stability of the EEPROM is improved, and the EEPROM is applied to DMI information updating of a computer.

The invention provides a data security write protection judgment method, a controller, a medium and a product, which are applied to the technical field of data storage and applied to eMMC equipment, and the method comprises the following steps: acquiring write protection information of a persistent storage unit and current security write protection modes of a plurality of write protection areas; mapping the write protection information according to the current security write protection mode to obtain a mapping value, and obtaining an equipment cache value according to the mapping value; in response to the setting instruction, updating the device cache value to obtain an updated device cache value; and in response to a user operation instruction, performing operation judgment according to the updated equipment cache value to obtain a judgment result, and performing data writing or data erasing according to the judgment result. According to the method and the device, the write protection information can be mapped through the current security write protection mode to obtain the equipment cache value, so that whether data writing or data erasing can be performed or not is determined by judging the equipment cache value, and therefore, the write protection judgment efficiency can be improved.

The application discloses a software-based write protection device and method, and relates to the technical field of storage. The device comprises an acquisition unit, which is used for acquiring write protection region information from a preset storage region, wherein the write protection region information contains a protection range for performing a control operation on a write operation, and the protection range contains at least one address information that needs to be protected; a determination unit, which is used for determining write address information from a write operation instruction when the write operation instruction is received; a judgment unit, which is used for judging whether the write address information matches the address information in the write protection region information; and an execution unit, which is used for intercepting the write operation instruction if the write address information matches the address information in the write protection region information.

The invention discloses a method for binding and unbinding a primary lock and a secondary lock. According to the invention, by using the encrypted information carried by the RFID card and the advanced read-write protection characteristic of the RFID card, a convenient and safe operation triggering mode is realized. According to the scheme, the traditional complex process of manually filling information depending on terminal equipment is simplified into two-step core operation of'brushing a mother lock 'and brushing a lock'. An operator does not need to learn complex terminal operation logic and does not need to memorize or input information such as lengthy equipment ID and secret keys, and the binding process can be triggered only by holding the RFID card to touch the primary lock and the secondary lock in sequence.