12 results about "Write protection" patented technology

The application relates to the technical field of servers and discloses a fault memory positioning method, system and device, computer equipment and a storage medium, the method comprising the following steps: in the case that a memory fault signal is received and a server is in a shutdown state, the write protection state of a power management chip register is released; candidate fault memories are determined according to the memory fault signal; a disable command is written into the power management chip register of the candidate fault memories, wherein the disable command is used to not power on the candidate fault memories when the server enters a startup state; in the case that the server enters the startup state, log information of the candidate fault memories is acquired; and according to the log information, a target fault memory and slot position information of the target fault memory are determined from the candidate fault memories. The application solves the problems that it is difficult to acquire abnormal information capable of accurately positioning the fault memories and the PMIC fault memories cannot be positioned.

Disclosed are devices and methods for protecting the register file of a power management integrated circuit (PMIC). In one embodiment, a device is disclosed comprising: a register file comprising a plurality of a registers, at least one register in the register file containing a write register bit (WRB); and an interface configured to receive messages from a host application, the messages including a WRB enablement signal, wherein the device is configured to enable writing to the register file in response to receiving the WRB enablement signal over the interface, write data in response to write messages while writing to the register file is enabled, and disable writing to the register file in response to receiving a stop bit over the interface.

This invention discloses a controller and control method for SRAM erase protection verification in an MCU architecture, belonging to the field of memory technology. This invention solves the problem that existing devices cannot simultaneously include multiple functions. By employing an SRAM erase protection verification device, write protection can be configured for each page individually, achieving write protection for SRAM data. The entire SRAM data is erased, and after erasure, write protection and data verification functions continue to be executed, improving read / write efficiency. Furthermore, SRAM data can be verified. When the SRAM controller reads any address, it latches that address and pulls up the read verification flag for that address. Then, an even-number verification is performed on the byte with the verification bit and the latched address. If the verification result is low, the verification passes; otherwise, it indicates a data error, and the error verification result is fed back to the system, thereby meeting the high requirements of the system for the SRAM controller.

The present application relates to the field of intelligent agriculture technology, and provides a lightweight intelligent production management system for multiple breeding varieties, which comprises a three-layer lightweight architecture using a hardware acquisition end, an edge operation end and a local interaction end. Each end cooperates to realize local data acquisition, analysis, operation, storage and interaction without cloud dependence. The system is based on the core data flow logic of real-time sharing of environmental monitoring data and precise feeding data linkage, feeding and weighing data and inventory accounting data, and integrally realizes intelligent regulation and control of breeding environment, precise feeding management, full-dimension production data acquisition, inventory digital accounting, equipment state monitoring and remote visualized supervision. By accurately implementing the hash value evidence mechanism into specific breeding business scenarios such as feed weight, weighing at slaughter, and feed into warehouse, and combining with multiple technical means such as device unique identification, timestamp, database encryption storage and write protection, the data is prevented from being tampered with throughout the whole process, and the authenticity and traceability of the data are guaranteed.

The present invention relates to an electronic device, wherein the storage device according to the present invention includes a memory device and a memory controller. The memory device includes a write protection area. The memory controller controls the memory device to perform a read operation on the write protection area in response to a series of requests regarding a secure read received from a host, provides read data received from the memory device to the host, and generates a device authentication code based on the read data. The memory controller performs the generation of the device authentication code and the provision of read data to the host in parallel.

The application relates to the technical field of community owner voting, and discloses a community owner online voting system and method supporting a temporary voting locking mechanism, which comprises the following modules: a voting terminal module used for collecting voting messages; a voting processing module used for analyzing and extracting a house property identifier and processing data to generate desensitization intention data; a voting locking cache module used for establishing mutual exclusion index bits in memory to lock the intention data; an identity verification module used for querying a property right database and triggering comparison; an effective period control module used for setting a constraint window; and a ticket generation module used for releasing write protection permission and realizing atomic storage when the window is valid and the comparison is passed. The application uses a memory mutual exclusion locking architecture based on a house property identifier, solves voting right conflicts under shared property rights, reduces property right database query pressure, and guarantees the certainty of voting intention under complex working conditions.

The application discloses a machining center FANUC coordinate system protection method, comprising the following steps: step S1: dividing the coordinate system parameters according to the importance degree to divide the protection level, switching the parameter write protection control right to the PMC signal through the system parameter setting, and writing the permission judgment logic in the PMC ladder diagram; step S2: constructing the background parameter monitoring mechanism based on the macro program interruption function and the PMC window function, periodically reading the current value of each level parameter and comparing with the reference value; step S3: triggering the differential early warning and processing mechanism according to the safety level of the modified parameter, and automatically executing the parameter backup after the authorized modification confirmation; step S4: establishing the log buffer area in the PMC, and real-time recording the coordinate system related operation behavior and storing in the non-volatile area. The application can cover more than 90% of the FANUC system machining center on the market, and can be used for self-owned factory equipment batch upgrading, and can also carry out technical service, technical consultation and technology transfer.

Various embodiments of this disclosure provide file write protection methods, apparatuses, electronic devices, storage media, and products. The file write protection method according to an embodiment includes: when an application modifies a page of a target file in the page cache through a file write operation, intercepting the dirty page marking function of the system call executing the file write operation; determining that the target file is in a protected state if the inode of the target file has a protection flag set; and based on the target file being in a protected state, intercepting the dirty page marking function's dirty page marking of the target file's pages. Through this disclosure, file write protection can intercept file writes in a timely manner at the page cache level, effectively blocking malicious file writes.

Methods, systems, and devices for techniques for a sequential write protection mode in a memory system are described. A memory system may receive one or more commands to write data to associated sequential memory addresses using a write automation block (WAB) while monitoring the addresses of the data. In the case that a write command may be associated with a non-sequential memory address, the memory system may store an associated pointer to a cache. The memory system may continue to write data indicated via incoming commands using the WAB until the memory system detects and writes the sequential command or a threshold quantity of commands have been received. If the threshold is reached prior to receiving the missing command, the memory system may disable the WAB and transmit an error message. The memory system may block and return error messages to any subsequent commands until the missing command is received.

This invention provides a multi-protocol compatible write protection method and system for storage media, comprising: generating a PCIe configuration space read request when a device is detected inserted into a host; responding to the request, virtualizing the back-end connected storage media into a USB controller under the xHCI protocol to generate virtualization information; based on the virtualization information, prefetching command transfer request blocks for new events and performing deep inspection to obtain the instruction type of the command transfer request block; if the instruction type is a write instruction type, discarding data and generating a virtual completion event message for the new event; if the instruction type is a read instruction type, remapping and protocol conversion of the address corresponding to the command transfer request block to obtain a converted read instruction; and generating and outputting an interrupt instruction based on the virtual completion event message or the converted read instruction. This method eliminates the bandwidth bottleneck of USB read-only locks and improves transmission efficiency.