43results about How to "Improve bus efficiency" patented technology

A asynchronous bridge consists of asynchronous slave interface for emitting transmission request signal, secondary synchronous unit for secondary-synchronizing said transmission request signal, asynchronous master interface for setting up bus transmission of the second clock domain, two-way storage with its one end being connected to asynchronous slave interface and another end being connected to asynchronous master interface for storing data signal of bus burst transmission. Its data transmitting method is also disclosed.

The invention discloses a data packet segmentation and recombination system and method based on a CLOS switching network, and relates to the field of communication technology. The CLOS switching network includes several input modules IM, several intermediate modules CM and several output modules OM; each The CM is respectively connected with each IM and each OM; each IM includes a composite packet scheduler, a variable-length slice unit, and a routing unit; each OM includes a reassembly unit. The invention improves the efficiency of the bus, and under the condition of the same bus width and bus operating frequency, can significantly improve the throughput of short packets and special-length packets, and realizes significant improvement of system performance.

Data transmission between transmitting / receiving nodes in a bus system may be controlled based on an error check of received data. When an error in the received data is detected, the transmitting node may cease data transmission, and other nodes, which may not have detected the error, may be notified of the detected error.

An access method of image data includes storing multiple pixel line of image block into one line of storage space, automatically switching line when storage edge in met and calculating composite address of said image block, continuously storing data of the other image block at blank position of this line storage space if a line space in not fully occupied by data of said image block, picking up data of said image block according to composite address of said image block. Two decoding methods of image data and their devices are also disclosed.

The invention discloses a PCI (Peripheral Component Interconnect) bus controller and a control method thereof. Through SPI (Serial Peripheral Interface) signal multiplexing, two configuration information initialization ways including EEPROM (Electrically Erasable Programmable Read-Only Memory) loading or unloading are provided so as to be flexible in use; and through the arrangement of a plurality of interface modules, a SPI bus, a PCI bus, a Local bus and corresponding pin interfaces can be realized. The PCI bus controller can be used as PCI master / slave equipment, has a wide application range and meets different requirements of a system; and when the PCI bus controller is used as the PCI master equipment, DMA (Direct Memory Access) data transmission is carried out, CPU (Central Processing Unit) intervention is avoided, and system efficiency is improved. When the PCI bus controller is used as the PCI bus master equipment to initiate a bus operation, data interaction between system memory and Local equipment is finished; and during non DMA transmission, the PCI bus controller is used as the PCI bus slave equipment to response to the bus operation. The PCI bus controller provides 8-bit, 16-bit, 32-bit multiplex / non-multiplex Local bus interfaces, can configure and realize various working ways including emergency, prefetching, internal waiting, external waiting, write cycle maintaining, read-write gating delay, big end and small end alignment, local chip selection, local interruption and the like, and is high in universality.

The present invention provides a cache consistency write-back method, device, device, and medium. The method includes: in response to the memory controller receiving a read request issued by the first processor cache and simultaneously receiving a read request from the second processor cache. write request, determine whether the type of the read request is an exclusive request; in response to the type of the read request being an exclusive request, the memory controller sends the data to be read by the first processor to the first processor; the memory controller makes the received The write request waits and sends a write completion response to the second processor; in response to the completion of the read request processing, the memory controller processes the pending write request. By using the solution of the present invention, the cache coherence system bus efficiency can be improved, and the bandwidth requirement for writing memory can be reduced.