Method and device for achieving convolution interleave/de-interleave

Abstract

The invention provides a method and device for achieving convolution interleave / de-interleave. The method and device improve bus efficiency and reduce DDR bandwidth. The method at least includes the steps that the minimum occupied bandwidth of a DDR is calculated according to the interleave transmission rate of a transmitting / receiving system; according to convolution interleave parameters, DDR storage space needed for the minimum occupied bandwidth is calculated; according to the DDR parameters, AXI bus parameters and interleave parameters, parameters of a data shaping storage device are calculated, and a Local address and an AXI bus continuous read or write range are generated; according to the generated parameters of the data shaping storage device, the Local address is converted into an AXI bus address, and data interaction with the DDR is finished. According to the method, considerations are preferably given to reduction of the DDR bandwidth and the improvement of the bus efficiency, a storage rule and a read-write address are specifically designed, so that DDR bandwidth occupied by interleave is minimized, and meanwhile read-write efficiency of a bus is improved substantially.

Description

technical field [0001] The invention relates to a method and device for realizing convolution interleaving / deinterleaving for improving bus efficiency and reducing DDR bandwidth. Background technique [0002] Convolutional interleaving has the function of breaking up burst errors and is widely used in communication systems, which can improve the performance of the entire system and reduce the decoding threshold. However, when the traditional SRAM or SDR SDRAM resources are used to realize the convolution interleaving function, SDRAM will be used to describe SDR SDRAM in this article, and its storage space size is often considered. When the convolution interleaving function is implemented in the SOC system, its storage carrier is DDR1 / 2 / 3, and it interacts with it through the AXI bus. At this time, the size of the storage space is not important, but the occupied bandwidth and bus efficiency are particularly important. important. [0003] Convolutional interleaving / deinterle...

AI Technical Summary

Problems solved by technology

When the convolutional interleaving / deinterleaving function is implemented in the SOC system, its storage carrier is DDR1 / 2 / 3, and it interacts with it through the AXI bus. At this time, the size of the storage space is not important, but the occupied bandwidth and bus efficiency It is particularly important. At this time, if the read-write address and storage method of the prior art are still used, only W bits are valid for each operation, which greatly wastes the DDR bandwidth; and the operation addresses are not continuous, and continuous reading of a longer Burst cannot be performed. Continuous writing, the bus efficiency is very low

Images