A DDR management and control system based on FPGA hardware acceleration

Abstract

The invention discloses a DDR management and control system based on FPGA hardware acceleration, the system including a host, an FPGA terminal and a memory DDR. The system is characterized in that theFPGA terminal comprises a DMA transfer control logic unit, a DDR conversion controller and a transmission state finding unit which are connected through an AXI bus, the FPGA terminal also comprises an algorithm logic unit connected to the DDR conversion controller, the FPGA terminal is connected with the host through the DMA transmission control logic unit, the FPGA terminal is connected with thememory DDR through the AXI bus, and the DDR conversion controller is connected with the transmission state finding unit. The system adopts the data transmission state index value in the data processing process and realizes the corresponding data processing operation according to the recorded index value, which simplifies the operation mode of the memory DDR and improves the data reading and writing efficiency by cooperating with the AXI bus. A DMA transmission mechanism is adopted to speed up the data transmission efficiency, reduce the CPU occupancy of the host terminal, and improve the dataprocessing efficiency.

Description

technical field [0001] The invention belongs to the technical field of digital integrated circuit DDR management, and in particular relates to a DDR management control system based on FPGA hardware acceleration. Background technique [0002] FPGA (Field-Programmable Gate Array), that is, Field Programmable Gate Array, is a product of further development on the basis of programmable devices such as PAL, GAL, and CPLD. It emerged as a semi-custom circuit in the field of application-specific integrated circuits (ASIC), which not only solves the shortcomings of custom circuits, but also overcomes the shortcomings of the limited number of original programmable device gates. [0003] DDR=Double Data Rate double rate synchronous dynamic random access memory. Strictly speaking, DDR should be called DDR SDRAM. DDR SDRAM is the abbreviation of Double Data Rate SDRAM, which means double-rate synchronous dynamic random access memory. DDR memory is developed on the basis of SDRAM memor...

AI Technical Summary

Problems solved by technology

Therefore, DDR is widely used in the large-capacity cache space of the FPGA data processing system and the host computer data transmission process, but the existing DDR control logic and read and write methods exist: complex operation methods, unclear storage information, low read and write efficiency, and Poor portability and other shortcomings lead to low system bandwidth and high difficulty in system implementation, which is not conducive to data efficiency and high-speed read and write cache in the process of hardware data processing

Images