3 results about "DDR SDRAM" patented technology

The invention provides a circuit packaging part and electronic equipment. The circuit packaging part comprises a circuit board, a CPU, an adapter and a DDR SDRAM. The circuit board comprises a first surface and a second surface, and the first surface and the second surface are opposite in the first direction; the first surface is concavely provided with a first accommodating groove, and the second surface is concavely provided with a second accommodating groove; the first accommodating groove and the second accommodating groove are opposite and communicated in the first direction; the adapter is arranged in the first accommodating groove, the DDR SDRAM is arranged in the second accommodating groove, and the adapter and the DDR SDRAM are fixedly and electrically connected along the first direction; in the first direction, a part of the CPU is stacked on the first surface, and the CPU is fixedly and electrically connected with the circuit board; the other part of the CPU is opposite to the first containing groove, the other part of the CPU is stacked on the adapter, and the CPU is fixedly and electrically connected with the adapter. The circuit package is relatively low in thickness, relatively low in cost and relatively high in memory efficiency.

The invention provides a system for realizing high-speed data acquisition and a high-precision signal source based on FPGA (Field Programmable Gate Array) integration. The invention aims to integrate a plurality of functional modules such as a high-speed ADC interface, real-time data processing, high-precision DAC control and complex waveform generation into a single chip through the high programmability and parallel processing capability of the FPGA, so that the miniaturization of the system is realized, and the real-time performance of data processing, the multi-channel synchronization precision and the flexibility of signal generation are remarkably improved. The core of the embodiment of the invention is that an FPGA (Field Programmable Gate Array) chip is used as a master control and data processing center, and a high-speed ADC (Analog to Digital Converter) chip, a high-precision DAC (Digital to Analog Converter) chip, a clock circuit, an external memory (such as DDR SDRAM (Double Data Rate Synchronous Dynamic Random Access Memory)) and necessary interface circuits (such as gigabit Ethernet, SFP (Small Form-factor Pluggable) + optical ports and the like) are peripherally connected to form a highly integrated hardware platform.

The present invention relates to a memory module having an electronic fuse which protects devices within the memory module by shutting off excessive current or voltage in an electrical overstress condition in which the excessive current or voltage is applied, the memory module comprising: a memory device array composed of a DDR SDRAM; a register clock driver chip which distributes signals received from a memory controller to the memory device array; a power management integrated circuit chip which distributes and supplies input power to components including the memory device array and an RCD; a serial configuration recognition chip which stores initial device information; and an electronic fuse which shuts off the input power when the input power is under electrical overstress, wherein the memory module may further comprise an electronic fuse integrated package in which the register clock driver chip or the power management integrated circuit chip and the electronic fuse are embedded in a single package.