11 results about "DDR SDRAM" patented technology

The present invention discloses a method for hardware acceleration of immersive projection mapping based on a CACHE architecture, and belongs to the field of image processing. The method includes six parts: target graphic scanning, source image coordinate calculation, on-chip buffering, coordinate conversion, interpolation processing, and image processing. A group-associated CACHE structure is used to optimize the problem of low efficiency of accessing SDR / DDR SDRAM due to discontinuous reading of source image pixels during graphic image projection transformation. Through a flexible CACHE structure and replacement strategy, it is ensured that better efficiency is achieved at different deformation angles. At the same time, by caching the source image coordinates to the on-chip cache, the main processing modules can be executed in parallel, further improving the processing speed. This method can achieve real-time processing of three-dimensional transformation of images with a resolution above full HD, avoiding the waste of storage bandwidth caused by writing to the memory area again.

The invention discloses a DDR (Double Data Rate) dynamic frequency switching method, device and equipment in an SSD (Solid State Disk) service scene and a medium, and relates to the technical field of DDR frequency switching. Comprising the steps that a frequency switching mode is enabled, a DDR SDRAM ensures that an instruction is normally completed before the frequency switching mode is enabled, and the instruction after the frequency switching mode is enabled is imported into a system public RAM; acquiring configuration parameters of the target frequency point, and configuring the configuration parameters of the target frequency point into the DDR SDRAM; after the DDR SDRAM is started, a frequency switching mode is configured to quit enabling, the system public RAM ensures that an instruction before the frequency switching mode quits enabling can be normally completed, and the instruction after the frequency switching mode quits enabling is sent to the DDR SDRAM; in the embodiment of the invention, the access to the DDR SDRAM does not need to be cut off in the whole process, and the DDR SDRAM does not need to be initialized again, so that the frequency switching efficiency is greatly improved, the quick frequency switching operation of the DDR SDRAM is realized, and the partial access requirement of the system can be ensured while the power consumption is reduced.

The invention provides a random trigger type data stream transmission method and device based on XDMA, and the method comprises the steps: distributing a DDR SDRAM space of a board card, and obtaining a data record storage region for storing data records generated by the board card in each triggering event and a shared control word storage region for storing control word information, after an upper computer controls to start data acquisition, an XDMA of a board card writes control word information into a shared control word storage area based on a preset interruption period to generate periodic PCIe interruption, and after the board card generates the PCIe interruption, the upper computer receives the PCIe interruption in time and responds to the PCIe interruption in time to read the control word information of the shared control word storage area, so that the control word information of the shared control word storage area is read. And on the basis of the control word information of the shared control word storage area, corresponding data records are read in the DDR SDRAM space.

The invention provides a circuit packaging part and electronic equipment. The circuit packaging part comprises a circuit board, a CPU, an adapter and a DDR SDRAM. The circuit board comprises a first surface and a second surface, and the first surface and the second surface are opposite in the first direction; the first surface is concavely provided with a first accommodating groove, and the second surface is concavely provided with a second accommodating groove; the first accommodating groove and the second accommodating groove are opposite and communicated in the first direction; the adapter is arranged in the first accommodating groove, the DDR SDRAM is arranged in the second accommodating groove, and the adapter and the DDR SDRAM are fixedly and electrically connected along the first direction; in the first direction, a part of the CPU is stacked on the first surface, and the CPU is fixedly and electrically connected with the circuit board; the other part of the CPU is opposite to the first containing groove, the other part of the CPU is stacked on the adapter, and the CPU is fixedly and electrically connected with the adapter. The circuit package is relatively low in thickness, relatively low in cost and relatively high in memory efficiency.

The present application provides a random triggered data stream transmission method and device based on XDMA, the method comprising: allocating DDR SDRAM space of a board card to obtain a data record storage area for storing data records generated by the board card for each trigger event and a shared control word storage area for storing control word information; after a host computer controls to start data acquisition, the XDMA of the board card writes the control word information to the shared control word storage area based on a preset interrupt cycle to generate a periodic PCIe interrupt; after the board card generates a PCIe interrupt, the host computer promptly receives the PCIe interrupt and promptly responds to the PCIe interrupt to read the control word information in the shared control word storage area, promptly clear the interrupt, and read the corresponding data record in the DDR SDRAM space based on the control word information in the shared control word storage area.

The invention provides a system for realizing high-speed data acquisition and a high-precision signal source based on FPGA (Field Programmable Gate Array) integration. The invention aims to integrate a plurality of functional modules such as a high-speed ADC interface, real-time data processing, high-precision DAC control and complex waveform generation into a single chip through the high programmability and parallel processing capability of the FPGA, so that the miniaturization of the system is realized, and the real-time performance of data processing, the multi-channel synchronization precision and the flexibility of signal generation are remarkably improved. The core of the embodiment of the invention is that an FPGA (Field Programmable Gate Array) chip is used as a master control and data processing center, and a high-speed ADC (Analog to Digital Converter) chip, a high-precision DAC (Digital to Analog Converter) chip, a clock circuit, an external memory (such as DDR SDRAM (Double Data Rate Synchronous Dynamic Random Access Memory)) and necessary interface circuits (such as gigabit Ethernet, SFP (Small Form-factor Pluggable) + optical ports and the like) are peripherally connected to form a highly integrated hardware platform.

A memory module includes: a first memory device; a second memory device; and a processing buffer circuit connected to the first memory device and the second memory device (independent of each other) and a host. A processing buffer circuit is provided, which includes a processing circuit and a buffer. The processing circuit processes at least one of data received from the host, data stored in the first memory device, or data stored in the second memory device based on a processing command received from the host. The buffer is configured to store data processed by the processing circuit. The processing buffer circuit is configured to communicate with the host according to the DDR SDRAM standard.

The present invention relates to an image warping system and method capable of performing image warping quickly at low cost by using a cache memory. The image warping system is provided to generate a transformed image by warping an input image with the help of a cache-based warping engine. The warping engine accesses the input image and loads a portion of the image to a cache memory in order to speed up the engine process. The warping engine performs interpolation on the input image to generate an output image without distortion. The obtained output image is then stored in a DDR SDRAM of an electronic device.

The present invention discloses a four-way parallel SAR imaging data transposition system based on DDR SDRAM. The present invention divides the data matrix into 4×4 small matrix blocks for data processing, so that the 4-beat data processed in the range direction and the 4-beat data processed in the azimuth direction are just the same 4×4 matrix, which mainly solves the problems of many DDR line changes, low efficiency and large RAM cache required during 4-way parallel processing. The implementation steps are: writing the original data entering sequentially into the DDR SDRAM memory in a block storage manner; storing the data read out of the asynchronous FIFO into the RAM after passing through three shift registers to obtain 4 4×4 small matrix blocks for range data processing; writing the 4×4 small matrix block data into the DDR SDRAM memory again in a block storage manner through a serial-to-parallel conversion module and an asynchronous FIFO; each data read out through the asynchronous FIFO is just a 4×4 small matrix block, which is stored in the RAM and then the azimuth data is processed.

The invention discloses a feed-forward balanced transmitting circuit based on pulse width detection. The feed-forward balanced transmitting circuit comprises an FFE transmitting circuit and an FFE delay line pulse width detection circuit. The FFE transmitting circuit adopts a structure that a main circuit extends to form two branch circuits; the main path comprises an emission training delay line module. And the FFE driving branch comprises an FFE delay line module. An FFE delay line module in the FFE transmitting circuit is copied in the FFE delay line pulse width detection circuit, and the FFE delay line pulse width detection circuit is used for obtaining the size relation between the actual delay duration of the FFE delay line module and one UI of the DDR SDRAM. According to the invention, a feed-forward equalization function capable of adjusting the delay value is realized, and the area and the power consumption can be reduced.

The present invention relates to a memory module having an electronic fuse which protects devices within the memory module by shutting off excessive current or voltage in an electrical overstress condition in which the excessive current or voltage is applied, the memory module comprising: a memory device array composed of a DDR SDRAM; a register clock driver chip which distributes signals received from a memory controller to the memory device array; a power management integrated circuit chip which distributes and supplies input power to components including the memory device array and an RCD; a serial configuration recognition chip which stores initial device information; and an electronic fuse which shuts off the input power when the input power is under electrical overstress, wherein the memory module may further comprise an electronic fuse integrated package in which the register clock driver chip or the power management integrated circuit chip and the electronic fuse are embedded in a single package.