Synchronous dynamic storage controller designing method

A technology of synchronous dynamics and design methods, applied in the direction of static memory, digital memory information, information storage, etc., to achieve the effect of improving utilization rate, satisfying high-speed communication, and reducing command pipeline conflicts

Inactive Publication Date: 2006-08-09
宁波中科集成电路设计中心有限公司
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On the other hand, the bus frequency and bandwidth of the system are often limited by actual condi

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Embodiment Construction

[0020] The present invention will be further described in detail below in conjunction with the accompanying drawings and embodiments.

[0021] The specific implementation of the present invention on SDRAM is as follows, and the implementation on DDR SDRAM is similar to SDRAM.

[0022] 1. Technical solution of SDRAM controller

[0023] Such as figure 1 As shown, according to the specification of SDRAM, to read and write any data on SDRAM, it must first be activated to open the row where it is located, and then read and write. After the read and write is completed, the row needs to be pre-charged to close the row. In order to get a data, additional time tRCD and tRP must be added to open and close the row where the data is located, and the whole process is also limited by tRC and tRAS.

[0024] There are 4 relatively independent banks in SDRAM. After the initialization operation is completed, except for commands such as refresh (Refresh) and reset register (LMR), each bank is ...

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Abstract

The method includes following steps: (1) optimizing parsed address; (2) setting up first order state register and using Auto Pre-charge mode; (3) optimizing sending time for Active command; (4) dynamic controlling Refreshing time interval; (5) buffering reading/writing commands, dividing reading/writing time slices, sending reading/writing commands in concentration respectively. Advantages are: four banks in SDRAM in collaborative work to take full advantage of SDRAM ability to communicate; bandwidth use ratio reached to more than 85úÑ, realizing decoding for AVS and H.264 video in high resolution, raised reading/writing efficiency greatly, and east of implementation by hardware. Moreover, the invention is not only suitable to SDRAM and DDR SDRAM, and video decoding.

Description

technical field [0001] The invention relates to a design method of a memory controller, in particular to a design method of a synchronous dynamic memory controller. Background technique [0002] AVS is China's first digital audio and video codec standard with independent intellectual property rights, and its full name is "Advanced Audio and Video Coding Standard for Information Technology". H.264 is a video coding standard developed by the Joint Video Working Group (JVT) composed of relevant video coding experts from ITU-T and ISO two international standardization organizations. Video compression standards have been significantly improved, but at the same time, the complexity of hardware decoding has also increased, which brings certain challenges to hardware design. [0003] In the real-time high-definition video decoding operation, there is a large amount of intermediate data that needs to be saved and read. Most of the data, such as all pixel values ​​​​of the decoded im...

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Application Information

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IPC IPC(8): G11C11/401G11C11/409H04N7/24
Inventor 彭聪黄晁孙宁龚国旺
Owner 宁波中科集成电路设计中心有限公司
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