2805 results about "Pre-charge" patented technology

A non-volatile semiconductor memory system (or other type of memory system) is programmed in a manner that avoids program disturb. In one embodiment that includes a flash memory system using a NAND architecture, program disturb is avoided by increasing the channel potential of the source side of the NAND string during the programming process. One exemplar implementation includes applying a voltage (e.g. Vdd) to the source contact and turning on the source side select transistor for the NAND sting corresponding to the cell being inhibited. Another implementation includes applying a pre-charging voltage to the unselected word lines of the NAND string corresponding to the cell being inhibited prior to applying the program voltage.

A method of optimizing lifetime of an OLED display element and an OLED display element with optimized lifetime for possible use in a tiled display, while maintaining light output are described. It compensates an OLED operating parameter such as supply voltage and / or on-time of the operating current based on at least one environmental factor which affects aging and on at least one operating factor which is indicative of aging, e.g. by determining the brightness of an OLED display element. To optimize the light output, pre-charge of the aged OLED display elements can be optimized. The knowledge of the working temperature of OLED tiles may be used to regulate the cooling and thus the working temperature, thus improving the lifetime of the display. Furthermore the intensity and contrast of the display illumination may be set within predefined limits to reduce the aging.

A method for reading non-volatile memory arranged in columns and rows which reduces adjacent cell coupling, sometimes referred to as the Yupin effect. The method includes the steps of: selecting a bit to be read in a word-line; reading an adjacent word line written after word line; and reading the selected bit in word line by selectively adjusting at least one read parameter. In one embodiment, the read parameter is the sense voltage. In another embodiment, the read parameter is the pre-charge voltage. In yet another embodiment, both the sense and the pre-charge voltage are adjusted.

Multi-gate NOR flash thin-film transistor (TFT) string arrays are organized as three dimensional stacks of active strips. Each active strip includes a shared source sublayer and a shared drain sublayer that is connected to substrate circuits. Data storage in the active strip is provided by charge-storage elements between the active strip and a multiplicity of control gates provided by adjacent local word-lines. The parasitic capacitance of each active strip is used to eliminate hard-wire ground connection to the shared source making it a semi-floating, or virtual source. Pre-charge voltages temporarily supplied from the substrate through a single port per active strip provide the appropriate voltages on the source and drain required during read, program, program-inhibit and erase operations. TFTs on multiple active strips can be pre-charged separately and then read, programmed or erased together in a massively parallel operation.

A method of optimizing lifetime of an OLED display element and an OLED display element with optimized lifetime for possible use in a tiled display, while maintaining light output are described. It compensates an OLED operating parameter such as supply voltage and / or on-time of the operating current based on at least one environmental factor which affects aging and on at least one operating factor which is indicative of aging, e.g. by determining the brightness of an OLED display element. To optimize the light output, pre-charge of the aged OLED display elements can be optimized. The knowledge of the working temperature of OLED tiles may be used to regulate the cooling and thus the working temperature, thus improving the lifetime of the display. Furthermore the intensity and contrast of the display illumination may be set within predefined limits to reduce the aging.

Circuits and methods to achieve a buck-boost converter, capable to achieve a constant output voltage by pre-charging of an inductor if the input voltage is close to the output voltage has been achieved. The prior art problem of output voltage variations occurring while the input voltage is close to the output voltage is avoided. In case the input voltage is lower than a defined threshold voltage or the duty cycle exceeds a defined maximum allowable level, the inductor of the converter is pre-charged followed by boosting of the energy of the inductor to the output of the converter. In both modes the control loops of the buck converter can be used for buck duty cycle control. The duration of the pre-charge depends upon the level of the input voltage, the lower the input level is the longer is the pre-charge performed.

In a Dickson type charge pump in which a plurality of serially connected diodes sequentially respond to anti-phase 50 / 50 clock cross over or overlapped (φ1, φ2), efficiency of the charge pump is increased by providing with each diode a charge transfer transistor in parallel therewith between two adjacent nodes, and driving the charge transfer transistor to conduction during a time when the parallel diode is conducting thereby transferring any residual trapped charge at one node through the charge transfer transistor to the next node. Operating frequency can be increased by providing a pre-charge diode coupling an input node to the gate of the charge transfer transistor to facilitate conductance of the charge transfer transistor, and by coupling the control terminal of the charge transfer transistor to an input node in response to charge on an output node to thereby equalize charge on the control terminal and on the input node during a recovery period.

A pre-charge voltage supply circuit of a semiconductor device is disclosed which includes a first switch which supplies a pre-charge voltage in response to a first signal having a predetermined voltage level, and has a turn-on resistance of a predetermined level, and a second switch which is connected in parallel to the first switch, supplies the pre-charge voltage in response to a second signal, and has a turn-on resistance lower than the turn-on resistance of the first switch.

A power inverter system includes a DC to AC inverter configured to convert DC voltage from a DC power source to AC voltage. A DC link couples the DC power source and the inverter. An inverter pre-charger operates to pre-charge the inverter to achieve a desired DC link voltage prior to connecting the power inverter system to an AC power grid. A phased lock loop synchronizes the pre-charged inverter to the AC power grid prior to connecting the power inverter system to the AC power grid. The pre-charged inverter regulates the DC link voltage to about the minimum voltage level that allows control of AC grid currents via the inverter subsequent to connecting the power inverter system to the AC grid. The inverter operates in a maximum power point tracking control mode only subsequent to a first voltage transient caused by connecting the DC power source to energize the power inverter system.

A non-volatile semiconductor memory system (or other type of memory system) is programmed in a manner that avoids program disturb. In one embodiment that includes a flash memory system using a NAND architecture, program disturb is avoided by increasing the channel potential of the source side of the NAND string during the programming process. One exemplar implementation includes applying a voltage (e.g. Vdd) to the source contact and turning on the source side select transistor for the NAND sting corresponding to the cell being inhibited. Another implementation includes applying a pre-charging voltage to the unselected word lines of the NAND string corresponding to the cell being inhibited prior to applying the program voltage.

The display matrix section 200 has pixel circuits 210 arranged in the form of a matrix, a plurality of gate lines Y1, Y2 . . . that extend in the row direction, and a plurality of data lines X1, X2 . . . that extend in the column direction. The scan lines are connected to a gate driver 300, and the data lines are connected to a data line driver 400. A pre-charging circuit 600 or additional current generation circuit is installed for each data line as means for accelerating the charging or discharging of the data line. For each data line, charging or discharging is accelerated by pre-charging or current addition prior to the completion of the setting of the light emission level in the corresponding pixel circuit 210.

The display matrix section 200 has pixel circuits 210 arranged in the form of a matrix, a plurality of gate lines Y1, Y2 . . . that extend in the row direction, and a plurality of data lines X1, X2 . . . that extend in the column direction. The scan lines are connected to a gate driver 300, and the data lines are connected to a data line driver 400. A pre-charging circuit 600 or additional current generation circuit is installed for each data line as means for accelerating the charging or discharging of the data line. For each data line, charging or discharging is accelerated by pre-charging or current addition prior to the completion of the setting of the light emission level in the corresponding pixel circuit 210.

The invention provides a gate drive circuit and method and a display device and relates to the technical field of display. The method includes the steps that gate row drive scanning is performed on shifting register units located in a first area in the gate drive circuit; after gate row drive scanning of the shifting register units in the first area is finished, touch scanning is performed; after touch scanning is finished, the last-level shifting register unit located in the first area is scanned again so that the last-level shifting register unit located in the first area can be used for pre-charging a first-level shifting register unit located in a second area; gate row drive scanning is performed on shifting register units located in the second area in the gate drive circuit, and the last-level shifting register unit located in the first area is in cascade connection with the first-level shifting register located in the second area. The method can overcome the defect that the row pixel charging rate is insufficient and solve the problem of dark lines or poor bright lines.

A semiconductor memory device includes a memory cell array having first and second blocks, respectively including first and second memory cells with floating bodies. The first memory cell is connected between a first bit line and a source line, and the second memory cell is connected between a second bit line and the source line. A sense amplifier equalizes the sense bit line and the inverted sense bit line to be an equalization voltage during an equalization operation, pre-charges the sense bit line and the inverted sense bit line to first and second pre-charge voltages during a pre-charge operation, and amplifies a voltage difference between the sense bit line and the inverted sense bit line during read and write operations. The first pre-charge voltage is higher than the equalization voltage and the second pre-charge voltage is higher than the equalization voltage and lower than the first pre-charge voltage.

A power converter for and method of producing a monotonic rise in output voltage at start-up. In one embodiment, the power converter includes a switch and an error amplifier coupled to an output terminal of the power converter. The power converter also includes a comparator with an output terminal coupled to a control terminal of the switch and an input terminal coupled to an output terminal of the error amplifier configured to enable the switch to conduct for a duty cycle. Additionally, the switch is configured to be turned off at a start-up of the power converter until a voltage of the output terminal of the error amplifier provides a duty cycle for the switch corresponding to an output characteristic pre-charge condition.

A circuit and method thereof for measuring leakage current are described. The circuit includes a pre-charge device subject to a first backbias voltage and a leakage test device subject to a second backbias voltage. The leakage test device is coupled to the pre-charge device. The leakage test device is biased to an off state. A differential amplifier is coupled to the pre-charge device and the leakage test device. A delay unit is coupled to the differential amplifier and to an input of the pre-charge device. The pre-charge device is turned on and off at a frequency that corresponds to said leakage current.

The present invention is directed to Bidirectional Multimode Power Converter which employs a high frequency dynamically varying amplitude modulation and voltage steering method to convert the source AC or DC voltages to output AC or DC voltages, with programmable output voltage levels, output voltage frequency and duration. The inrush current control, turning off the idle converter, line voltage brown out protection, soft start, high pre-charge voltage generation, soft shut down of converter, dimming operation modes are inherent characteristics of the Bidirectional Multimode power converter. The Bidirectional Multimode Power Converters of the present invention facilitates bidirectional conversion and coupling multiple bidirectional sources and or loads.The Bidirectional Multimode Power Converter of the present invention supports local and remote control for changing operational characteristics of the converter on demand or on a programmed time of the day for a specified duration of time.

A method and apparatus for maintaining the single phase integrity of a deep well formation sample that is removed to the surface comprises a vacuum jacket insulated single working cylinder divided by two free pistons into three variable volume chambers. The intermediate chamber is pre-charged with a fixed quantity of high pressure gas. Wellbore fluid freely admitted to one end chamber bears against one free piston to further compress the gas. The formation sample is pumped into the other end chamber to first, displace the wellbore fluid from the first end chamber and, sequentially, to further compress the gas to preserve the sample phase state upon removal to the surface.

A low power (and lower cost) implementation for amplifier used in delivering a stimulation pulse is provided according to embodiments through use of a pre-charge period for each pulse. For example, a voltage at a variable output terminal of a digital-to-analog converter is increased on the leading edge of PULSE and INVERTCLK signals to result in an output of an operational amplifier increasing to a predetermined voltage prior to output of a stimulation pulse, according to an embodiment. A shunt path may be implemented to shunt current away from a load during the pre-charge period.

Circuits for programming a circuit with decreased programming time are provided. Such circuits include a storage device such as a capacitor for storing display information and for ensuring a driving device such as a driving transistor drives a light emitting device according to the display information. To increase programming time, the pixel circuits may be pre-charged or a biasing current may be applied to charge and / or discharge a data line and / or the driving device. Aspects of the present disclosure allow for the biasing current to drain partially through the storage device to allow the portion of the biasing current applied to the driving device to remain small while the data line discharges. Furthermore, the present disclosure provides display architectures and operation schemes for display arranged in segments each including a plurality of pixel circuits.0

A vehicle propulsion includes an alternating current (AC) traction drive, a first energy storage system electrically coupled to the traction drive through a direct current (DC) link, a second energy storage system electrically coupled to the traction drive such that the voltage output from the second energy storage system is decoupled from the DC link using a bi-directional boost converter, and an energy management system configured to control said first and second energy storage systems when the vehicle is operating in at least one of a pre-charge mode and a normal operation mode with the traction drive system enabled.

A vehicle propulsion includes an alternating current (AC) traction drive, a first energy storage system electrically coupled to the traction drive through a direct current (DC) link, a second energy storage system electrically coupled to the traction drive such that the voltage output from the second energy storage system is decoupled from the DC link using a bidirectional boost converter, and an energy management system configured to control said first and second energy storage systems when the vehicle is operating in at least one of a pre-charge mode and a normal operation mode with the traction drive system enabled.

A Switch Node Assisted Linear architecture, including a linear amplifier in parallel with a switched converter, is configurable in two tracking modes: (a) a SMAL regulator in which the amplifier sets toad voltage with an envelope tracking bandwidth, and the switched converter is configured for current assist, and (b) a Switched Mode Power Supply configuration in which the amplifier is switch-decoupled, and the switcher circuit is switched configured with an output capacitor, operable as an SMPS providing load voltage with an adaptive tracking bandwidth that is less than the envelope tracking bandwidth. Staged switching effects substantially seamless transitions between tracking modes, with the amplifier holding the load voltage at a substantially constant envelope tracking voltage (CVET): (a) for ET-AT transitions, the CVET mode enables pre-charging the output capacitor to a target AT voltage, prior to switch-decoupling the amplifier; and (b) for AT-ET transitions, CVET mode enables discharging the output capacitor.

A combination EEPROM and Flash memory is described containing cells in which the stacked gate transistor of the Flash cell is used in conjunction with a select transistor to form an EEPROM cell. The select transistor is made sufficiently small so as to allow the EEPROM cells to accommodate the bit line pitch of the Flash cell, which facilitates combining the two memories into memory banks containing both cells. The EEPROM cells are erased by byte while the Flash cells erased by block. The small select transistor has a small channel length and width, which is compensated by increasing gate voltages on the select transistor and pre-charge bitline during CHE program operation.

Power conversion systems and diagnostic techniques are presented for detecting suspected converter faults when a pre-charge circuit is engaged during system startup, in which known or estimated system characteristics are used to derive expected converter voltage values or rate of change values and the levels are measured during startup to ascertain whether the pre-charge circuit or other converter components are faulted.

An aspiration system is disclosed for removing body liquid (e.g. urine or a secretion) discharged by the human body. The aspiration system comprises a body interface device with a liquid sensor, and an aspiration unit coupled to the body interface device. The liquid sensor comprises a temperature sensor and / or a resistance bridge. The aspiration unit includes: a vacuum chamber; a pump for pre-charging the vacuum chamber with a vacuum; a valve coupled between the vacuum chamber and the body interface device; and a control circuit for controlling the valve to apply aspiration suction from the vacuum chamber to the body interface device in response to detection of body liquid at the liquid sensor.