277results about How to "Increase clock frequency" patented technology

A semiconductor product includes a first semiconductor chip that includes input/output circuitry enabling transfer of data from memory banks of the semiconductor product to an external electronic device and/or from an external electronic device to the memory banks of the semiconductor product. A number of second semiconductor chips are stacked on and electrically coupled to the first semiconductor chip. The second semiconductor chips are stacked on one another. Each second semiconductor chip of the plurality of second semiconductor chips comprises at least one of the memory banks of the semiconductor product. The memory banks of the second semiconductor chips are accessible by the input/output circuitry arranged on the first semiconductor chip.

A method and system for transferring information within a computer system is provided. The system includes a memory device that has a lower power mode in which data transfer circuitry is not driven by a clock signal, and a higher power mode in which data transfer circuitry is driven by a clock signal. The system further includes a memory controller that sends control signals to the memory device to initiate a data transfer transaction. The memory device receives the control signals asynchronously, and assumes the second mode in response to one of the control signals. While the memory device is in the second mode, the memory controller sends a control signal to identify a particular clock cycle. The memory device synchronously transfers the data. The memory device determines when to begin the data transfer based on the identified clock cycle and the type of data transfer that has been specified.

In a method for program-controlled information processing, resources for information processing form a resource pool. Suitable resources are selected from the resource pool and connections between the selected resources are configured. Parameters are supplied to the selected resources and information processing operations are initiated in the selected resources. Data are transported between the selected resources and results are assigned. Connections that are no longer needed are disconnected between the selected resources. The selected resources that are no longer needed are returned to the resource pool.

Aspects of the invention can provide an image processing circuit for gray scale correction, an image display apparatus, and an image processing method that allow reduction in the storage capacity needed for storing correction characteristics data without increasing clock rate in relation to interpolation processing of correction characteristics. A exemplary image processing circuit according to the invention can be applied, for example, to color correction or gamma correction of color image data. Gray scale correction characteristics data for a number of gray scale levels that is less than the number of gray scale levels of input image data can be stored in first and second lookup table storing units. Considering a gray scale value of a pixel that is being considered for gray scale correction processing as an input gray scale value, the first and second lookup-table storing units are referred to, obtaining an output gray scale value corresponding to the input gray scale value and an output gray scale value corresponding to an adjacent input gray scale value. An adjacent gray scale value refers to a gray scale value that is higher by one or lower by one than another input gray scale value. Then, output gray scale values between these two adjacent output gray scale values can be calculated by linear interpolation, obtaining output values for all input gray scale values. Subsequently, gray scale correction can be performed for each pixel of input image data, outputting corrected image data.

In a Dickson type charge pump in which a plurality of serially connected diodes sequentially respond to anti-phase 50/50 clock cross over or overlapped (φ1, φ2), efficiency of the charge pump is increased by providing with each diode a charge transfer transistor in parallel therewith between two adjacent nodes, and driving the charge transfer transistor to conduction during a time when the parallel diode is conducting thereby transferring any residual trapped charge at one node through the charge transfer transistor to the next node. Operating frequency can be increased by providing a pre-charge diode coupling an input node to the gate of the charge transfer transistor to facilitate conductance of the charge transfer transistor, and by coupling the control terminal of the charge transfer transistor to an input node in response to charge on an output node to thereby equalize charge on the control terminal and on the input node during a recovery period.

A method for interchanging data between two devices in a network which utilizes a communication protocol with an interface based on the OPC-UA standard to interchange the data, wherein the communication protocol comprises an interface based on the stream reservation protocol standard or an interface based on the multiple stream registration protocol standard in accordance with IEEE standard 802.1Qat, such that the data is interchangeable between the two devices using both interfaces in a prescribed period of time.

An LRU array and method for tracking the accessing of lines of an associative cache. The most recently accessed lines of the cache are identified in the table, and cache lines can be blocked from being replaced. The LRU array contains a data array having a row of data representing each line of the associative cache, having a common address portion. A first set of data for the cache line identifies the relative age of the cache line for each way with respect to every other way. A second set of data identifies whether a line of one of the ways is not to be replaced. For cache line replacement, the cache controller will select the least recently accessed line using contents of the LRU array, considering the value of the first set of data, as well as the value of the second set of data indicating whether or not a way is locked. Updates to the LRU occur after each pre-fetch or fetch of a line or when it replaces another line in the cache memory.

The present invention relates to a CCD solid state image sensor of a scanning read-out type and to a drive method thereof as well as an image pick-up method and the image pick-up device, particularly in which a plurality of vertical CCD columns can be assigned to one electric-charge detection unit with the small number of wiring. In the present invention, adjacent columns of the vertical CCDs are assigned to one electric-charge detection unit. Further, the stages of the voltage transfer between the vertical CCD column and a voltage detection unit is made different; the electrode arrangement is devised; or the drive timing is adjusted. Accordingly, the phase of electric-charge transfer with respect to the plurality of adjacent vertical CCD columns, when the horizontal electric-charge at the same position in the direction of the row obtained by the photo-conductive units is made to reach the electric-charge detection unit, becomes different.

A data processing unit having a field of clocked logic cells (PAEs) which is operable in different configuration states and a clock preselecting means for preselecting logic cell clocking. The clock preselecting means is designed in such a way that, depending on the state, a first clock is preselected at least at a first cell (PAE) and an additional clock is preselected at least at an additional cell.

A system and method for dynamically altering a clock speed of a clock signal used for timing of data signal transmissions and receptions within an integrated circuit (IC) device. The system includes a clock generator circuit for providing a clock signal used for timing of data signal transmission and reception within the IC; a monitoring circuit for receiving data transmissions generated at different clock speeds and detecting when a data transmission fail point is achieved at a particular clock speed; and, a device for adjusting the clock speed according to a maximum speed allowed for the IC that avoids the data transmission fail point.

The invention discloses a passive ultrahigh-frequency ultralow-power consumption RFID chip with a built-in temperature sensor. The chip comprises a power management module, a modulation-demodulation module, a clock generation module, a digital base-band module, a temperature sensor module and a memory. By low-power consumption treatment processing of the passive ultrahigh-frequency RFID chip with the built-in temperature sensor, the sensitivity and the read-write distance of the RFID chip with the built-in temperature sensor are improved. In addition, the built-in temperature sensor is subjected to high-precision and low-error processing, and thus a more stable and more accurate temperature measurement value can be obtained, thereby providing more reliable temperature data.

Methods and apparatus for reducing the effects of digital-to-analog converter (DAC) images and transmission spurious effects in a receive frequency band of a radio frequency (RF) transceiver. A transceiver apparatus includes a transmitter portion having a DAC, a receiver portion configured to receive RF signals in a receive frequency band, and a variable rate clock generator. The variable rate clock generator is used to provide an oversampling clock for the DAC. The rate of the oversampling clock is adjustable and is selected so that an upconverted version of a DAC image created by the DAC is steered away from frequencies within the receive frequency band. A notch-effect low-pass filter (NELPF) may also, or alternatively, be used in the transceiver to reduce transmission spurious effects in the receive frequency band.

Systems and methods for encoding a data word using an 8b/9b encoding scheme that eliminates two-aggressor crosstalk are disclosed. The 8b/9b encoding scheme enables a data word that can be subdivided into portions of eight bits or less to be encoded using code words having one extra bit than the corresponding portion of the data word. Each of the valid code words does not include any three consecutive bits having a logic level of logic-high (i.e., ‘1’), and represent transition vectors for consecutive symbols transmitted over the high speed parallel bus. An encoder and corresponding decoder are disclosed for implementing the 8b/9b encoding scheme. In one embodiment, the encoder/decoder implements a modified Fibonacci sequence algorithm. In another embodiment, the encoder/decoder implements a look-up table. In some embodiments, data words may be less than eight bits wide.

A method and apparatus for computing a convolution between an input GPS signal and a C/A code reference by generating the convolution result in real time without storing unprocessed signal samples. The apparatus comprises a vector multiplier running at high speed to achieve the same result as a vector multiplier sized to process an entire epoch. Additionally, the input samples to, and the output samples of, the vector multiplier can be quantized to reduced circuit complexity.