9results about How to "Increase clock frequency" patented technology

The invention discloses an FPGA-oriented DSP layout optimization method for a CNN accelerator, and the method comprises the following steps: S1, DSP path information extraction: converting a designed netlist into graph representation, and carrying out data path DSP node recognition and data path DSP graph construction; and S2, data path driven DSP layout: distributing data path DSP nodes to specific positions on the FPGA according to the extracted data path DSP diagram. According to the method, a data path DSP graph is automatically extracted and constructed through DSP node classification based on a graph neural network (GCN) and an optimization algorithm of a minimum cost flow (MCF) model, and compact layout and cascade constraint optimization are combined, so that the time sequence performance and the calculation efficiency of the layout are greatly improved, meanwhile, the clock frequency and the throughput are remarkably improved, and the time sequence performance and the calculation efficiency of the layout are greatly improved. And a universal and efficient FPGA layout solution is provided for various CNN accelerator architectures.

A low-complexity 1-bit signal decoder and a design method thereof, the decoder includes a counter module, a fixed subtraction module, M decoder submodules and an output control signal generating module; the counter module inputs a reset signal and a clock signal, the M decoder submodules form a parallel operation processing unit, M-1 fixed subtraction modules are arranged one-to-one between the counter module and the decoder submodule, and the address values ​​of adjacent decoder submodules differ by L; the data inputs of the M decoder submodules are all 1-bit digital signal streams, the enable ends are all connected to the output control signal generating module, and the outputs are all N-bit digital signal streams. The present invention also provides a design method for a low-complexity 1-bit signal decoder. The present invention has extremely low complexity and power consumption, is suitable for high-speed data processing, can be implemented in the form of an integrated circuit, and is suitable for high-bandwidth signal processing.

The embodiment of the invention provides a method for executing target transformation and acceleration hardware. The target transformation is decomposed into n11-point target transformation, n12-point target transformation, n21-point target transformation and n22-point target transformation, and the acceleration hardware comprises a first transposition unit which comprises a first transposition module, a second transposition module, a third transposition module, a fourth transposition module and a first data exchange module. The method comprises the steps that a first matrix with the dimension of n2 * n1 is halved along rows and columns, a first matrix block, a second matrix block, a third matrix block and a fourth matrix block are obtained, n1 is the product of n11 and n12, n2 is the product of n21 and n22, and the product of n1 and n2 is N; the first to fourth transposition modules receive the data of the first to fourth matrix blocks in parallel respectively, and transpose the first to fourth matrix blocks in parallel respectively to obtain transposed first to fourth matrix blocks; and the first data exchange module performs data exchange on the transposed second matrix block and the transposed third matrix block to obtain a transposed first matrix, and the second matrix block and the third matrix block are located at the upper right corner and the lower left corner of the first matrix respectively.

A method and device for constructing a RISC‑V extended instruction set supporting dynamic reconstruction can use the RISC‑V instruction set to tightly couple dynamic reconstruction control with a processor, thereby solving the problem of high resource occupation of bus logic in the traditional processor instruction set structure. The method includes: (1) constructing an extended instruction set adapted to an on-chip dynamic reconstruction interface for interactive operations between registers and ICAP interface data; (2) DPRC connects the on-chip reconstruction interface to the processor data path, thereby coupling the dynamic reconstruction controller with the processor data path; (3) After the DPRC instruction is fetched by the instruction fetch unit IF, it is sent to the DPRC module for processing through the instruction decoding unit IDU and the pre-decoding unit PDU, and finally the read data is written back to the register through the write back unit WBU.

The embodiment of the present disclosure discloses an instruction fixed-length coding method, a processor, a storage medium and a program product. The method comprises the following steps: obtaining an original program, wherein the original program comprises original instructions; in a compilation stage, constructing a format protocol and a coding rule of instruction fixed-length based on a fixed coding length agreed by an architecture layer; compiling the original instructions into fixed-length instructions based on the format protocol and transmitting the fixed-length instructions into a processor; and the processor performs a coding operation on the fixed-length instructions based on the coding rule and outputs a coding result. The method can fundamentally eliminate the complex variable-length instruction coding logic by converting the variable-length instructions into a fixed-length format, simplify the processor hardware, save multiple hardware coding modules required by the variable-length instructions, reduce the chip area and power consumption, break through the rigid limitation of instruction processing throughput, adapt to parallel execution demand and improve the coding and execution efficiency.

The invention discloses a phase frequency detector, a phase-locked loop and a chip. The phase frequency detector comprises N sub-modules. Each sub-module comprises a first trigger, a second trigger, a third trigger, an AND gate, a first switch unit and a first phase inverter. In the N sub-modules, a control end of a first switch unit of a first sub-module is connected with a first reset signal, a first end is connected with a first power supply signal, and a second end is connected with an output end of an AND gate in the first sub-module; the control end of the first switch unit in the ith sub-module is connected with a second reset signal, the first end is connected with the output end of the AND gate in the ith sub-module, and the second end is connected with a second power supply signal; the input end of the first phase inverter in the ith sub-module is connected with the output end of the AND gate in the ith sub-module, and the output end of the first phase inverter in the ith sub-module is connected with the setting end of the third trigger in the (i + 1) th sub-module. According to the invention, the phase discrimination range of the phase frequency detector can be improved.

The utility model relates to filter protection circuit and camera of camera head, including image acquisition sensor, connecting port and image processing chip, still including TF common mode filter circuit, electrostatic protection circuit and spread spectrum IC circuit, TF common mode filter circuit is connected with image acquisition sensor, electrostatic protection circuit and TF common mode filter circuit and connecting port are connected, and the CSI the CLK port of image processing chip, the MCLK port of connecting port all are connected with spread spectrum IC circuit, application circuit of this application can reduce the common mode noise of data to the greatest extent, reduce EMI radiation, can reduce electrostatic interference data transmission, can also make the synchronous clock of protocol also have spread spectrum, thereby reducing clock radiation, this application can solve the EMI radiation emission and electrostatic protection problem of MIPI CSI -2 camera head very well, especially applicable to small, data bandwidth is high, clock frequency is high and the camera product of transmission MIPI CSI -2 protocol.

The invention provides a PCIe exchange delay testing device and method, and relates to the technical field of PCIe exchange delay. The testing device mainly comprises a CPU module, an NOC module, a first bridging module, a second bridging module, a memory module, a local time module, a first timestamp adding module, a first calculation module, a second timestamp adding module, a second calculation module, an RC controller module and an EP controller module. According to the scheme, the structure is simple, the operation is convenient, and after the tested PCIe exchange chip is connected, accurate delay information of the tested PCIe exchange chip can be obtained only by writing data into a specified address and then reading the address; according to the scheme, the switching delay measurement of the PCIe switching chip in two directions from the UP port to the DP port or from the DP port to the UP port can be supported; according to the scheme, the measurement precision can be further improved by improving the clock frequency of a counter in the local time module.

The utility model discloses an aging board used for memory chip screening, comprising an aging mother board, the aging mother board is connected with a controller and a plurality of tested chip aging seats, each tested chip aging seat is internally provided with a tested chip, each tested chip is correspondingly connected with a relay unit, and each relay unit is connected with the controller. According to the burn-in board for screening the memory chips disclosed by the utility model, burn-in testing of a plurality of parallel SRAM memories can be realized by using one FPGA chip, and the number of parallel testing is increased; and for a specific number of tested chips, the FPGA with less tube legs and less resources can be used for building the test system, so that the development and construction cost of the test system is reduced.