97 results about "Circuit complexity" patented technology

Ultra-Wideband (UWB) technology is a wireless technology supporting the transmission of large amounts of digital data over short distances using coded impulses over a wide frequency spectrum with very low power. Enhanced link performance and functionality of such UWB systems is presented exploiting multiple directive antennas for spatially filtering undesired signals and increasing signal strength whilst circuit complexity is reduced by eliminating baluns in prior art solutions. Further enhancements support payloads with flexible encoding schemes, improved channel utilization, reduced processing logic, improved robustness in correlation techniques, versatile synchronisation techniques, improved ranging, as well as providing for improved inter-symbol interference tolerance and detection.

The invention relates to a storage processing method and device based on a capacitance-free DRAM (Dynamic Random Access Memory), and the method comprises the steps: preparing a corresponding writing transistor and a corresponding reading transistor through a preset oxide semiconductor and a silicon transistor; based on a preset heterogeneous integration strategy, vertically stacking the write transistor on the read transistor to establish a capacitance-free DRAM memory unit; the method comprises the following steps: establishing a heterogeneous integrated capacitance-free DRAM memory macro based on a pre-established storage unit peripheral circuit and a capacitance-free DRAM memory unit, and establishing a corresponding in-memory processing architecture according to the heterogeneous integrated capacitance-free DRAM memory macro and a pre-established convolution kernel logic circuit, so as to execute corresponding storage operation through the in-memory processing architecture. Therefore, the technical problems that in the prior art, a DRAM memory processing framework is high in process cost, incompatible in preparation process, high in circuit complexity, poor in memory processing speed and the like are solved.

The invention discloses a floating-point number format conversion device and method, a storage medium and a program product, and relates to the technical field of floating-point number format conversion. The device comprises a preprocessing unit and a conversion mapping unit; the preprocessing unit is used for receiving input data in a first floating point format and performing bit width compression processing on at least part of digits influencing rounding operation in the input data to generate a corresponding index value, and the bit width of the index value is smaller than the mantissa bit width of the input data; the conversion mapping unit is coupled to the preprocessing unit, a plurality of mapping relations between index value ranges and numerical value representations in a second floating point format are stored in the conversion mapping unit, and the conversion mapping unit is used for searching the corresponding numerical value representations in the second floating point format according to the index values to serve as output data. The invention aims to reduce the number of logic gates and the circuit complexity required by floating-point number format conversion, so that the area of a related chip is reduced, the power consumption is reduced, and the operation delay is shortened.

The present invention discloses a hybrid quenching circuit and operating method for implementing gated quenching and rapid active quenching, relating to the field of weak light detection technology. The circuit comprises a first high-speed comparator, a second high-speed comparator, a quenching transistor, a high-speed operational amplifier, and a balanced noise cancellation network. The first high-speed comparator has a non-inverting input connected to the anode of an active photodiode (APD), an inverting input connected to an adjustable discrimination level and the anode of the APD, and an inverting output connected to its latch-enable inverting input. The non-inverting output is connected to the input of the quenching transistor, and the output of the quenching transistor is connected to the anode of the APD. The output of the high-speed operational amplifier is connected to the output of the quenching transistor. The inverting output and latch-enable inverting input of the first high-speed comparator are connected to the inverting input of the second high-speed comparator. The non-inverting input of the second high-speed comparator is connected to the adjustable discrimination level. The present invention is compatible with both gated and free-running operating modes, achieving minimal circuit complexity and dual-mode detection performance.

A data aggregation service is engineered to generate aggregated data values based on encrypted data received from a variety of providers, without being exposed to the underlying plaintext data. A homomorphic encryption scheme is used in a threshold cryptography scenario that allows aggregation of the encrypted data without requiring decryption. An independent decryption service can partially decrypt the aggregated result, which can ultimately be decrypted to plaintext for use by the provider. Bitwise operations can be defined to support aggregation with error tolerance, and the operations can be constrained to a smaller bit size to reduce circuit complexity.

The invention relates to a matching system capable of automatically adjusting impedance, a radio frequency system and an impedance matching method, an inverted L-shaped matching network circuit in which an inductor is connected in series with a second adjustable capacitor and a first adjustable capacitor is connected in parallel is adopted to replace a traditional impedance matcher, the number of series elements is reduced to two (the inductor and the second adjustable capacitor), and only one parallel element (the first adjustable capacitor) is adopted. The circuit complexity is remarkably reduced, the adjustable capacitor is used for replacing a fixed capacitor / inductor, dynamic impedance adjustment is achieved, and debugging redundancy caused by traditional multi-element combination is avoided; a signal acquisition unit, a signal processing unit and a signal execution unit are integrated on a main control board, a data interaction path is shortened (for example, voltage and current signals are directly converted by an analog-to-digital converter and then processed by the processing unit), communication delay in a traditional separated design is eliminated, and the processing unit calculates and generates a capacitance adjustment amount instruction. And the execution unit respectively adjusts the capacitance values of the first adjustable capacitor and the second adjustable capacitor, so that impedance matching between the radio frequency source and the load is realized.

This application discloses a floating-point number format conversion apparatus and method, storage medium, and program product, relating to the field of floating-point number format conversion technology. The apparatus includes a preprocessing unit and a conversion mapping unit. The preprocessing unit receives input data in a first floating-point format and performs bit-width compression processing on at least a portion of the bits in the input data that affect rounding operations to generate corresponding index values, wherein the bit width of the index values ​​is smaller than the mantissa bit width of the input data. The conversion mapping unit is coupled to the preprocessing unit and stores multiple mapping relationships between index value ranges and numerical representations in a second floating-point format, used to look up the corresponding numerical representation in the second floating-point format as output data based on the index values. This application aims to reduce the number of logic gates and circuit complexity required for floating-point number format conversion, thereby reducing the chip area, power consumption, and operation latency.

This invention discloses a 4-2 approximation compressor based on memristors, a control method, an apparatus, and applications. It approximates and compresses four 1-bit numbers X1, X2, X3, and X4 using two identical memristor-based majority gate circuits. The two majority gate circuits respectively implement traditional majority gate logic and a novel majority gate logic including inversion logic. The first majority gate circuit implements the traditional majority gate logic M(X1, X3, X4) to obtain the carry result of the 4-2 approximation compressor. The second majority gate circuit implements the novel majority gate logic including inversion logic to obtain the pseudo-sum result of the 4-2 approximation compressor. This invention does not rely on the cascading of a large number of basic logic units such as NAND gates and NOR gates, has a shallow logic depth, and can achieve a 4-2 compressor with good error performance with low circuit complexity, high operation speed, and low power consumption.

The present invention discloses a reconfigurable ultra-wideband, high-precision variable-gain amplifier core circuit. The core circuit primarily comprises a three-stage wideband variable-gain unit and a digitally controllable current source array. This circuit utilizes a novel gain control method, achieving not only high-precision gain control but also complete independence between coarse and fine gain adjustments. This significantly reduces circuit complexity and improves broadband performance. Furthermore, the bandwidth remains constant across the entire variable gain range, ensuring that the core circuit maintains constant group delay at varying gains. Furthermore, the core circuit features configurable gain and bandwidth, enabling configuration of both gain and bandwidth without affecting the variable gain range, thus meeting the gain-bandwidth and other performance requirements of diverse broadband systems.

The application discloses a kind of based on 3M-1R memristor complete non-volatile Boolean logic circuit and control method, belong to microelectronic device technical field, this logic circuit mainly consists of three memristors and a fixed resistance, the area occupied by circuit is smaller, circuit complexity is lower, wherein, one input P in logic calculation process is defined as the resistance state of input memristor 1, another input Q is defined as the resistance state of input memristor 2, the resistance state of output memristor is as output, by the gating state of control multiplexer, and corresponding voltage is applied to each memristor, namely, one-step calculation operation can realize arbitrary Boolean logic operation, and in the operation process of logic calculation, the resistance state of input memristor 1 and input memristor 2 does not change, input information is completely non-volatile saved in corresponding memristor, can use as few as possible device and operation step number while in the calculation process, the integrity of input information is protected.

To provide a processor, an information processor, and a control method of the processor for reducing an increase in circuit scale and circuit complexity.SOLUTION: The package-unit allowable power determination unit 102 determines the smaller one of the first required power required for the entire CPU core die and the first power limit for the entire CPU core die as the first allowable power allowed for the entire CPU core die. The per-die allowable power determination unit 106 determines the second allowable power of each CPU core die based on the first allowable power and the smaller one of the second required power and the second power limit of each CPU core die. The transmitter transmits the second allowable power to the CPU core die and causes the CPU core die to be supplied with the second allowable power.SELECTED DRAWING: Figure 3

The invention discloses an analog-to-digital conversion circuit based on small value priority and a double-end differential capacitor. The analog-to-digital conversion circuit comprises a quantization mode control circuit, a digital-to-analog converter, a main comparator, a successive approximation type logic circuit, an asynchronous clock generation circuit and a quantization code register, wherein the quantization mode control circuit outputs a quantization mode according to the magnitude of input voltage; each of two double-end differential capacitor arrays in the digital-to-analog converter comprises N capacitor assemblies with capacitance values in binary distribution, each capacitor assembly comprises two interdigital capacitors which share an upper polar plate and are independent in lower polar plate, and the digital-to-analog converter outputs differential voltage; the main comparator outputs a comparison result of the differential voltage; the successive approximation type logic circuit controls the voltage connected with the lower polar plate of the capacitor assembly and the number of the capacitor assemblies contributing the weight in the digital-to-analog converter according to the comparison result and the quantization mode; the quantized code register generates a quantized code according to the comparison result. According to the invention, the power consumption, hardware overhead and circuit complexity of the analog-to-digital converter are effectively reduced.

According to certain aspects, the present embodiments relate to techniques to provide the ability to monitor one or more operating parameters of a voltage regulator. In an embodiment, the voltage regulator is a multi-phase voltage regulator having a plurality of power stages corresponding to respective phases. In these and other embodiments, the operating parameter includes one or both of a phase current and a phase temperature. According to further certain aspects, the present embodiments provide the ability to independently monitor individual phase current outputs and phase temperatures for each phase. According to a further aspect, this ability to monitor operating parameters is obtained while minimizing circuit complexity.

The application relates to an operational amplifier offset voltage automatic correction circuit and method, which comprises an operational amplifier main circuit, the operational amplifier main circuit comprises an operational amplifier basic circuit and an input offset correction transistor array connected in sequence, and the operational amplifier main circuit at least comprises a same-phase input end Vi+, an opposite-phase input end Vi- and an output end Vout; an automatic correction circuit, the automatic correction circuit comprises a correction control circuit and a correction flag generation circuit connected in sequence, the correction control circuit is electrically connected with the operational amplifier main circuit, and the correction flag generation circuit is electrically connected with the output end Vout of the operational amplifier main circuit. The application can adapt to a wide power voltage range, has higher offset correction precision, the proposed offset voltage automatic correction circuit does not need additional comparators and filters and other analog circuits, only uses digital logic to complete automatic correction control, and reduces the circuit complexity and cost.

The invention relates to the technical field of power electronic conversion, and discloses a power conversion circuit and a UPS (Uninterrupted Power Supply) system, which realize an AC / DC (Alternating Current / Direct Current) rectification function in a mains supply mode and a DC / DC boosting function in a battery mode on a single set of hardware through innovative circuit design and device multiplexing on the premise of not obviously increasing hardware cost, and further realize a power conversion function in a battery mode. The system structure is simplified, the cost is reduced, and the power density is improved. According to the design, the multifunctionality of the existing device is fully utilized, and the problems of hardware redundancy and cost increase are avoided. Meanwhile, as the number of devices and the circuit complexity are reduced, the reliability of the system is improved, and the maintenance difficulty is reduced. Besides, due to the improvement of the power density, the whole power conversion circuit can support higher power output under the same size, or more compact design can be realized under the same power requirement, and powerful support is provided for integration and miniaturization of medium-power UPS power supply equipment.

Methods, error correction circuits, and circuit modules using error correction circuits are provided for performing co-bit calculations for error correction by means of circuit complexity reduction. Methods and related devices for co-bit computations for error correction by means of circuit complexity reduction are provided. The method comprises: in an error correction circuit using a predetermined error correction code, configuring a first group of XOR operational circuits in a plurality of XOR operational circuits corresponding to a predetermined codeword length, rather than all XOR operational circuits in the plurality of XOR operational circuits, so as to reduce the circuit complexity of the error correction circuit and improve the error correction efficiency of the error correction circuit. Wherein the first set of XOR operational circuits may be a set of optimized XOR operational circuits implemented based on co-located bit coverage reduction; and performing the co-bit calculation using the first set of XOR operational circuits for error correction corresponding to a shorter codeword length, where a smaller XOR operand and a shorter critical path length can be achieved.

The invention relates to the technical field of electrical variable measurement, in particular to an electronic equipment electrical performance testing device and method based on voltage signal processing. The method comprises the following steps: acquiring an eye pattern; processing the eye pattern to obtain a signal connected domain, and obtaining a shaking condition and an eye opening degree based on the signal connected domain and the eye pattern center opening area; acquiring a line in the circuit diagram, acquiring circuit complexity based on the area and the edge of the line, constructing a curve for eye diagram characteristics, and determining an accumulated residual value based on the difference between the curve and a fitting straight line; obtaining a change trend; screening standard points, and obtaining an unstable coefficient according to the variation trend difference of parameter iteration and the eye pattern feature difference to screen an optimal oscilloscope parameter; and carrying out performance test through the optimal oscilloscope parameters. The problem that the electrical performance of the equipment is poor due to the parameter setting problem of the oscilloscope during the electrical performance test is avoided.

The invention relates to the technical field of integrated circuits and electronic circuits, in particular to a multi-mode multiplexing differential driving circuit based on a CMOS (complementary metal oxide semiconductor) process, which comprises an auxiliary current control circuit and a core current control circuit, and is characterized in that the auxiliary current control circuit comprises a first auxiliary circuit and a second auxiliary circuit; the first auxiliary circuit and the second auxiliary circuit have the same structure and are symmetrically arranged on the left and right sides of the core current control circuit. The problems of large output parasitic capacitance, limited circuit speed, high power consumption and large circuit complexity caused by multi-mode multiplexing realized through module parallel connection in the prior art are solved.

The invention discloses an analog-to-digital converter with a voltage monitoring function. The analog-to-digital converter comprises a voltage comparator and a control logic circuit. The control logic circuit is used for switching the working modes of the analog-to-digital converter, and the working modes comprise a data acquisition mode and a real-time monitoring mode. When working in a data acquisition mode, the voltage comparator is used for converting an analog electric signal input into the analog-to-digital converter into a discrete digital logic level signal so as to output a digital signal according to the digital logic level signal. When working in a real-time monitoring mode, the voltage comparator is used for comparing an input analog electric signal with a threshold setting electric signal and outputting a monitoring result signal obtained through comparison. By means of the working mode switching mode, the voltage comparator of the analog-to-digital converter is fully applied, so that the circuit complexity of a signal acquisition chip in a scene where the analog signal subjected to analog-to-digital conversion is limited by a voltage value is simplified, and the cost is reduced.

The application discloses a linearization calibration circuit and method applied to a pipeline ADC without a sampling and holding structure, and the circuit comprises a signal generation module, a pipeline ADC quantization module and a linear calibration module. The signal generation module is used for generating a pseudo-random signal, and the pseudo-random signal is converted into a dithering signal and then input into the pipeline ADC quantization module. The dithering signal comprises a first dithering signal and a second dithering signal. The pipeline ADC quantization module is used for superimposing the first dithering signal and the second dithering signal on an input signal respectively after the first dithering signal and the second dithering signal are processed through different paths, generating a to-be-calibrated signal, and quantizing the to-be-calibrated signal to obtain an output digital code. The linear calibration module is used for calibrating the to-be-calibrated signal based on a preset weight coefficient, the output digital code and the pseudo-random signal, and obtaining a calibrated signal. The application does not affect the main function of the circuit during calibration, is suitable for the pipeline ADC without the sampling and holding structure, can be operated in the background, has low circuit complexity, and has important significance for improving the linearity of the ADC applied to various communication systems.

Ultra-Wideband (UWB) technology is a wireless technology supporting the transmission of large amounts of digital data over short distances using coded impulses over a wide frequency spectrum with very low power. Enhanced link performance and functionality of such UWB systems is presented exploiting multiple directive antennas for spatially filtering undesired signals and increasing signal strength whilst circuit complexity is reduced by eliminating baluns in prior art solutions. Further enhancements support payloads with flexible encoding schemes, improved channel utilization, reduced processing logic, improved robustness in correlation techniques, versatile synchronization techniques, improved ranging, as well as providing for improved inter-symbol interference tolerance and detection.

The invention relates to the technical field of power grid fault analysis, in particular to a digital power grid fault analysis system, which comprises a data acquisition unit used for acquiring power data of each power region; the load analysis unit is used for determining a circuit load state according to the load intensity and the harmonic load proportion of each power region, and determining the duration of the detection period according to the circuit load state; the adjusting unit is used for adjusting the duration of the detection period according to the circuit complexity coefficient; the analysis unit is used for determining a priority value according to the first priority coefficient and the second priority coefficient, and performing fault analysis on the power regions in sequence according to a priority value sequence; the processing unit is used for determining a fault processing priority coefficient according to the fault duration and the fault index proportion of the fault area, and transmitting the power data of the fault area to the user side in sequence; and the accuracy and efficiency of power grid fault detection and analysis are improved.

The present application proposes a method, device, and equipment for protecting a memory chip test key, specifically comprising: when the chip is powered on again, the target key processing module obtains a pre-stored target key and a target key enable field, wherein the target key enable field includes a port level signal for controlling the activation of the test control module; the target key processing module loads the target key into a target key register that clears data upon power failure; the target key processing module controls the activation of the test control module according to the port level signal of the target key enable field, so that the test control module receives and compares the user input key with the target key to determine whether it is consistent, and determines whether the user input key is correct. The method, device, and equipment for protecting a memory chip test key described in the present application improve the timing complexity and circuit complexity, making it difficult for other organizations or individuals to determine the target key and the target key enable field through circuit analysis.

This invention discloses a power amplifier and its design method: replacing the microstrip lines in a power divider with lumped elements; merging the lumped elements in at least one input circuit and / or the output matching circuit connected to the same node with the lumped elements in the power divider. This invention achieves circuit miniaturization, reduced circuit complexity, and lower material costs without increasing the complexity of the driver stage output matching circuit and the final stage input matching circuit, and without affecting the performance of the power amplifier link.

The embodiment of the invention relates to the field of integrated circuits, and discloses a floating-point number addition and subtraction device and method. Through a negation control mechanism, only a small mantissa is executed once or complement taking operation does not need to be executed, multiple times of conversion between an original code and a complement are avoided, the circuit complexity and hardware resource waste are reduced, and the operation efficiency is improved. The mantissa operation module efficiently processes the aligned mantissa, outputs positive numbers all the time, simplifies leading zero statistical logic, and reduces the circuit scale. In the mantissa processing module, a transmission gate control signal is directly generated by sharing a leading zero preprocessing function, and partial functions of a leading zero counting module are integrated into a normalization circuit, so that the logic path is shortened, and the delay is reduced. The transmission gate array submodule further improves mantissa processing efficiency through efficient normalized shift operation. The whole scheme is compatible with the IEEE-754 standard, and the requirements of high-performance calculation for high efficiency, low power consumption and high precision are met.

The present invention relates to a micro-power consumption redundant task layered universal execution circuit. The execution circuit is arranged in a terminal, which is connected to a gateway. The execution circuit includes a central controller, a task instruction cache circuit, a sensor control circuit, an off-chip task execution circuit, and a data encoder. The central controller parses the control instructions of the gateway, controls the task instruction cache circuit to write and erase instructions, outputs instructions to the sensor control circuit and the off-chip task execution circuit, and controls the data encoder to output uplink data. The sensor control circuit outputs data to the off-chip task execution circuit, and the off-chip task execution circuit outputs control data to the task instruction cache circuit. The present invention implements data processing and sensor control task logic with a minimalist hardware circuit combination, replacing the traditional task execution method of running software programs on a microprocessor platform, thereby reducing the terminal's power consumption, circuit complexity, and development cost.

Embodiments of the present application provide a shift logic circuit optimization method, a computer device and a storage medium. The method comprises: obtaining a first shift logic circuit, the first shift logic circuit comprising a first shift sub-circuit; determining a minimum input signal set corresponding to the first shift logic circuit, the minimum input signal set comprising the least input signals driving all logic outputs of the first shift logic circuit; constructing a second shift sub-circuit based on the minimum input signal set; and replacing the first shift sub-circuit in the first shift logic circuit with the second shift sub-circuit to obtain a second shift logic circuit. The technical solution provided by the embodiments of the present application has the advantages that the number of combination logic blocks included in the second shift logic circuit is also less than the number of combination logic blocks included in the first shift logic circuit, the number of logic levels included in the second shift logic circuit is generally shallower, the circuit complexity is lower, and it is easier to implement further optimization of the second shift logic circuit by a subsequent synthesis tool.

The invention discloses a method and a circuit for detecting a safe working area of an electronic resistance wire in a slow start stage, and relates to the technical field of server board cards, compared with an existing scheme, the method only introduces an analog-to-digital sampling technology to simulate voltage at the two ends of the electronic resistance wire and current flowing through the electronic resistance wire, so that the circuit complexity is reduced, and the detection efficiency is improved. In addition, the voltage at the two ends of the electronic resistance wire and the current flowing through the electronic resistance wire are simulated, and finally, the electronic resistance wire is determined to be abnormal in the slow start stage under the condition that the average power is not in the safe working area, so that the detection of the safe working area can be completed, the circuit complexity can be reduced, and the reliability is improved. Therefore, no extra time sequence risk is generated, and the problems that the complexity of a detection circuit is improved and the extra time sequence risk is possibly generated due to the fact that a plurality of extra hardware modules need to be introduced in a safe working area detection method in an existing scheme are solved.

The application discloses a TOF measurement circuit and a measurement method based on column-shared TDC, which comprises a pixel array, a time address detection circuit and a readout circuit; the pixel array detects photons and outputs avalanche signals; the time address detection circuit measures the time of flight of the photons and encodes the row address of the pixels responding to the photons; and the readout circuit sequentially reads out the time of flight data and the address data column by column; the time address detection circuit proposed by the application can avoid the problem of inaccurate measurement results caused by photon event collision to the greatest extent while quantizing the time of flight of the photons; on the other hand, the circuit can directly encode the row address and read out the time of flight data and the row address data of the photons through the readout circuit, without additional column address encoding and control logic circuit, thereby effectively reducing the circuit complexity and saving the chip area; in addition, the application has a simple structure and is easy to realize large-scale pixel array expansion integration.

The present invention proposes a parameter identification method based on an improved Gray Wolf algorithm for a wireless power transmission system. The wireless power transmission system of the present invention includes a DC power supply, an inverter circuit module, a transmitting end resonant compensation capacitor, a transmitting coil inductance, a transmitting coil equivalent resistance, a receiving end resonant compensation capacitor, a receiving coil inductance, a receiving coil equivalent resistance, and a load resistance. The method of the present invention combines a wireless power transmission efficiency model to construct a parameter identification target model, and uses an improved Gray Wolf algorithm to transform the load and mutual inductance identification problem of the wireless power transmission system into a problem of solving the minimum error between the actual detection value and the calculated value of the transmitting end resonant current, and optimally identifies the load resistance and mutual inductance value with the minimum error value. The present invention effectively reduces circuit complexity and system volume, and can prevent the Gray Wolf algorithm from falling into a local optimal solution, so as to better design the wireless power transmission system as a whole.