18 results about "Circuit complexity" patented technology

The application discloses a linearization calibration circuit and method applied to a pipeline ADC without a sampling and holding structure, and the circuit comprises a signal generation module, a pipeline ADC quantization module and a linear calibration module. The signal generation module is used for generating a pseudo-random signal, and the pseudo-random signal is converted into a dithering signal and then input into the pipeline ADC quantization module. The dithering signal comprises a first dithering signal and a second dithering signal. The pipeline ADC quantization module is used for superimposing the first dithering signal and the second dithering signal on an input signal respectively after the first dithering signal and the second dithering signal are processed through different paths, generating a to-be-calibrated signal, and quantizing the to-be-calibrated signal to obtain an output digital code. The linear calibration module is used for calibrating the to-be-calibrated signal based on a preset weight coefficient, the output digital code and the pseudo-random signal, and obtaining a calibrated signal. The application does not affect the main function of the circuit during calibration, is suitable for the pipeline ADC without the sampling and holding structure, can be operated in the background, has low circuit complexity, and has important significance for improving the linearity of the ADC applied to various communication systems.

This invention discloses a power amplifier and its design method: replacing the microstrip lines in a power divider with lumped elements; merging the lumped elements in at least one input circuit and / or the output matching circuit connected to the same node with the lumped elements in the power divider. This invention achieves circuit miniaturization, reduced circuit complexity, and lower material costs without increasing the complexity of the driver stage output matching circuit and the final stage input matching circuit, and without affecting the performance of the power amplifier link.

Embodiments of the present application provide a shift logic circuit optimization method, a computer device and a storage medium. The method comprises: obtaining a first shift logic circuit, the first shift logic circuit comprising a first shift sub-circuit; determining a minimum input signal set corresponding to the first shift logic circuit, the minimum input signal set comprising the least input signals driving all logic outputs of the first shift logic circuit; constructing a second shift sub-circuit based on the minimum input signal set; and replacing the first shift sub-circuit in the first shift logic circuit with the second shift sub-circuit to obtain a second shift logic circuit. The technical solution provided by the embodiments of the present application has the advantages that the number of combination logic blocks included in the second shift logic circuit is also less than the number of combination logic blocks included in the first shift logic circuit, the number of logic levels included in the second shift logic circuit is generally shallower, the circuit complexity is lower, and it is easier to implement further optimization of the second shift logic circuit by a subsequent synthesis tool.

The application discloses a TOF measurement circuit and a measurement method based on column-shared TDC, which comprises a pixel array, a time address detection circuit and a readout circuit; the pixel array detects photons and outputs avalanche signals; the time address detection circuit measures the time of flight of the photons and encodes the row address of the pixels responding to the photons; and the readout circuit sequentially reads out the time of flight data and the address data column by column; the time address detection circuit proposed by the application can avoid the problem of inaccurate measurement results caused by photon event collision to the greatest extent while quantizing the time of flight of the photons; on the other hand, the circuit can directly encode the row address and read out the time of flight data and the row address data of the photons through the readout circuit, without additional column address encoding and control logic circuit, thereby effectively reducing the circuit complexity and saving the chip area; in addition, the application has a simple structure and is easy to realize large-scale pixel array expansion integration.

The application relates to a high-linearity sample-and-hold circuit for an electric energy metering chip, and belongs to the technical field of integrated circuits. The circuit aims to solve the problem of serious deterioration of linearity caused by substrate bias effect and parasitic diode leakage of a traditional sample-and-hold switch under the condition of zero common-mode voltage input. The core of the technical scheme is to introduce a dynamic substrate bias module, so that the substrate potential of a sampling tube and a reset switch can change in real time along with the input signal, and the substrate and the source-drain end are always maintained in reverse bias, and a gate voltage self-boosting circuit is combined to stabilize the gate-source voltage of the sampling tube. The design effectively eliminates threshold voltage drift and substrate leakage current under the premise of almost no increase in circuit complexity, thereby realizing high-linearity signal sampling under the condition of zero common-mode input, and significantly improving the precision and reliability of the electric energy metering chip.

The invention relates to the technical field of optical communication, in particular to a bias voltage automatic control circuit and method and a silicon-based optical modulator. Through cooperative adaptation of the control circuit, the drive circuit, the signal generation circuit and the signal detection circuit, differential sine disturbance signals are accurately coupled to the radio frequency modulation phase shifter of the silicon-based light modulator, and synchronous detection of average light current and the disturbance signals is achieved by means of a built-in light detector. And the control circuit is linked with the driving circuit to accurately adjust the driving current of the thermo-optic phase shifter and efficiently lock a bias working point. The problems that a traditional scheme is low in precision and complex in circuit are solved, the locking speed and stability are improved, meanwhile, hardware design is simplified, the number of components is reduced, the requirement for miniaturization of a high-speed silicon-based optical module is met, working point drifting caused by environment changes is effectively restrained, and the optical signal quality and the long-term working performance of a communication system are guaranteed.

This application provides an ADC pixel and column-level coarse and fine quantization readout circuit suitable for infrared arrays, relating to the field of integrated circuit technology. An oscillator is connected to the pixel infrared detector, counter, and pulse generation unit respectively; the counter and pulse generation unit are both connected to a memory unit; the memory unit is connected to a bus; each pixel is connected to the column-level decoding unit of its column via the bus; the input of the column-level decoding unit is connected to the bus. This application, by employing a pixel structure where the oscillator is directly driven by photocurrent for integration, reduces circuit complexity and area overhead without significantly increasing additional power consumption, which is beneficial for realizing highly integrated small pixel arrays. It eliminates the need for a highly complex ADC structure or additional analog modules, achieving an optimized trade-off between power consumption, area, and accuracy. Reducing the number of buses and wiring resources, lowering bus parasitic capacitance and dynamic power consumption of the readout switches, helps to reduce the layout area.

The application provides an OTP balance protection circuit, and relates to the field of protection circuits.The OTP balance protection circuit comprises a flyback topology main circuit, a VCC power supply circuit, an OTP protection pin control circuit and an OTP balance control circuit.The utility model discloses a single point detection is realized to many devices balance protection, reduces circuit complexity and cost;the OTP protection point is adaptively adjusted, and the reliability under different input voltages and load conditions is ensured;the insulation problem of cross connection is avoided, and the design is simplified;the OTP function is closed when the load is light, and the risk of false triggering is reduced;the circuit can reliably protect various power devices under different input voltages and different load currents.

The application belongs to the field of analog integrated circuit design, and particularly relates to a redundant current range current steering DAC based on digital pre-distortion. The application carries out rotation correction through an improved DEM decoding circuit, measures and quantizes error codes corresponding to the static mismatch error of each current unit, and reduces the circuit area and the influence of additional circuit parasitic on the DAC speed without additional control circuit. A redundant current unit is introduced at the highest bit to expand the quantization range, and the error code and clipping problem introduced by DPD correction are solved. Only a simple algorithm of a 14-bit adder and a 14-bit subtractor is needed to directly operate on binary codes, and a secondary decoding is used to realize thermometer code addition operation compatible with DEM, so that the timing delay and circuit complexity of the thermometer code addition circuit are greatly reduced. The circuit timing delay of the application meets the speed requirement of high-speed and high-precision current steering DAC, and compared with DEM correction only, the application significantly improves the SFDR without raising the noise floor.

The application belongs to the technical field of digital-analog hybrid integrated circuits, and relates to a high-precision low-latency exponential increment successive approximation analog-digital converter, which comprises an exponential delay integrator module, a multi-bit quantizer and a digital-analog converter module.The exponential delay integrator module is used for amplifying the residual voltage of the last round by using a proportional floating inverting amplifier, and is used for realizing exponential form integration and accumulation of the residual voltage by using a stacked capacitor module to control different stacked capacitors to work alternately in odd and even periods through ping-pong timing to delay and store the amplified residual voltage.The multi-bit quantizer is used for multi-bit quantization of the integrated signal to obtain a multi-bit digital signal.The digital-analog converter module is used for converting the multi-bit digital signal into an analog output signal to realize successive approximation logic.The exponential delay integrator module is realized by using a proportional floating inverting amplifier and a stacked capacitor module, which significantly reduces the circuit complexity and processing delay, and improves the robustness and energy efficiency of the system in high-precision application scenarios.

The utility model relates to chip on -line control technical field, concretely for adjustable chip power -on time sequence control circuit. Including at least two stages of DC -DC power module of concatenation, every stage DC -DC power module includes input power end, output voltage end, enable control end (EN) and power good signal end (PG). The utility model discloses through the DC -DC power module of cascaded setting, utilizes the RC delay circuit between power good signal end (PG) of preceding stage module and enable control end (EN) of rear stage module, has realized the flexible adjustment of rear stage module power -on delay time, need not to rely on complex control chip or software program, can accurate matching chip required power -on time sequence only through the adjustment of resistance capacitor parameter, has reduced circuit complexity and cost.

Ultra-Wideband (UWB) technology is a wireless technology supporting the transmission of large amounts of digital data over short distances using coded impulses over a wide frequency spectrum with very low power. Enhanced link performance and functionality of such UWB systems is presented exploiting multiple directive antennas for spatially filtering undesired signals and increasing signal strength whilst circuit complexity is reduced by eliminating baluns in prior art solutions. Further enhancements support payloads with flexible encoding schemes, improved channel utilization, reduced processing logic, improved robustness in correlation techniques, versatile synchronisation techniques, improved ranging, as well as providing for improved inter-symbol interference tolerance and detection.

The application relates to an LCC-S type wireless power transmission system modeling and parameter identification method and belongs to the wireless charging field. The modeling and parameter identification method accurately analyzes and calculates the influence of a receiving end rectifier circuit of a wireless power transmission system on a load impedance, combines a high-order harmonic mathematical model of the wireless power transmission system, collects inverter bridge output voltage, current and energy receiving coil output voltage, and realizes high-precision identification of mutual inductance and load resistance by using a genetic algorithm. The application establishes a related model of the rectifier circuit, completes parameter identification under the premise of not increasing the circuit complexity, and is convenient for further optimization design of wireless power transmission system parameters and control.

This invention relates to the field of oscillation circuit technology, and discloses a low-power RC oscillation circuit, an RC oscillator, and an analog signal chip. The circuit constructs a highly efficient and collaborative oscillation system by dividing the circuit into a power supply module, a switch control module, a reference resistor module, a capacitor charging / discharging module, and a comparison switching module, and clearly defining the electrical connections and signal transmission relationships between each module. This architecture fundamentally solves the circuit complexity problem of traditional RC oscillators. Oscillation is achieved through a single comparison correlation module in conjunction with switch control, significantly reducing the number of active devices and the continuous operating time. Simultaneously, the precise coordination of each module allows for the sharing of the reference resistor, greatly improving frequency stability. Furthermore, the optimized connections between modules reduce the layout space occupied by redundant circuits, and the precise control of the charging / discharging process by the switch control module reduces static current consumption, thus meeting the overall design requirements of low power consumption, high integration, and high precision.

The embodiment of the present application provides a full-bridge driving chip and a driving circuit.The full-bridge driving chip comprises a logic control module (1), a register (2) and a plurality of driving modules (3), the logic control module (1) is connected with the register (2), wherein the driving module (3) comprises a pre-driving current collection pump (31), a high-side switch (32) and a low-side switch (33), the pre-driving current collection pump (31) is connected with the high-side switch (32), the high-side switch (32) is connected with the low-side switch (33), the logic control module (1) is connected with the pre-driving current collection pump (31), the logic control module (1) is connected with the low-side switch (33), the high-side switch (32) is connected with an input power supply Vcc, and the low-side switch (33) is grounded.In the technical scheme provided by the embodiment of the present application, the full-bridge driving chip integrates the functions of a half-bridge driving chip, a high-side switch chip and a low-side switch chip, the circuit complexity is reduced, and the flexibility of circuit application is improved.

This application discloses a touch detection method, readout circuit, and electronic device to solve the problem of balancing signal-to-noise ratio, frame rate, and circuit complexity in high-channel-count touch detection. The method includes: generating and applying a code-frequency hybrid driving signal; acquiring a sensed signal and converting it into a digital signal; performing double cross-correlation demodulation on the digital signal, and obtaining accurate touch information by calculating its cross-correlation values ​​with in-phase and quadrature reference signals and summing the squares of the two values. The circuit includes corresponding functional modules. This invention improves the signal-to-noise ratio through code-frequency hybridization and simultaneously completes decoding and frequency discrimination while eliminating phase errors through double cross-correlation demodulation, achieving a balance between high frame rate and low circuit complexity.