490 results about "Circuit complexity" patented technology

A modulated transformer-coupled gate control signaling method and apparatus provides reduction of circuit complexity and robust design characteristics in switching power circuits having a transformer-coupled gate drive. A modulated control signal at a rate substantially higher than the switching circuit gate control rate is provided from the controller circuit to a demodulator via transformer coupling. Power for the demodulator can be obtained by rectifying the modulated control signal at the demodulator, or from another transformer winding. The modulation scheme is chosen to have a DC average value of zero, eliminating any magnetization current management requirements. The modulated control signal may carry redundant control information and/or may encode additional information to provide a more sophisticated gate drive control, such as oversampled gate control information.

A transformer-isolated analog-to-digital converter (ADC) feedback apparatus and method provides reduction of circuit complexity in high power/high voltage systems having a transformer-isolated sensing circuit. The feedback apparatus is a circuit including an ADC for receiving an analog input signal and a transformer having a first winding that receives a modulated output of the analog-to-digital converter. A second winding of the transformer provides an isolated data output of the ADC. A demodulator is coupled to the second winding of the transformer and demodulates the isolated output to generate a digital representation of the analog input signal. The ADC may be a delta-sigma converter and the demodulator may be the corresponding decimation filter. The circuit further includes an isolation circuit for introducing a clock signal and/or power supply waveform at the second winding of the transformer, so that the ADC circuit is supplied with an isolated clock and/or an isolated power supply.

A digital passband matched filter is automatically adapted to a carrier wave ω in accordance with a frequency offset of the carrier wave, to obtain a passband digital signal having no frequency distortion due to the frequency offset. Thus, a receiver in which drawbacks such as decrease of SNR and increase of circuit complexity caused by the fixed baseband/passband matched filter is obtained. Since a cosine wave generating section operates in a carrier wave frequency restoring mode and a carrier wave frequency adaptive mode, respectively, a single cosine wave ROM table can be used regardless of the respective operating modes, thereby reducing circuit complexity. Since the digital passband matched filter acts to renew the filter coefficients adapted to the carrier wave adaptive mode only, power consumption required to operate the filter can be minimized.

In a low-pass filter which is preferably used as a loop filter in a PLL or DLL, filter characteristics which are the same as those of a conventional low-pass filter are realized without causing collateral problems, such as an increase in the circuit area, the circuit complexity, or the resistance value, which may be caused due to size reduction of a capacitive element in the conventional low-pass filter. Thus, in a loop filter including a capacitive element and a resistive element which are connected in series, the first input terminal is provided at the side including the resistive element, and the second input terminal is provided at a connection point of the capacitive element and the resistive element. The first input terminal is supplied with the first electric current. On the other hand, the second electric current, which is a part of the first electric current supplied to the first input terminal, is extracted from the second input terminal, so that the electric current flowing into the capacitive element is smaller than the electric current flowing through the resistive element.

The invention provides a memory device of an embedded system and a starting method and an upgrading method of a firmware, wherein the memory device is a read-write flash memory and at least comprises a first subregion used for storing a starting guide part of the embedded system as well as a main subregion and an auxiliary subregion which have consistent capacity and are used for storing parameters and data used for starting and upgrading the firmware; and the starting method based on the memory device comprises the following steps: starting a guide part and judging the firmware attributes oftwo subregions; verifying the validity of a cyclic redundancy check code of the current subregion, if so, erasing data of the main subregion, copying contents of the auxiliary subregion onto the mainsubregion, and then starting the auxiliary subregion; and if not, starting a program image from the main subregion. The flash memory is set in a partitioning way, the system functions can be realizedonly by utilizing one storage, therefore, the invention has the effects of reducing the circuit complexity and the cost of the system compared with the prior art. The starting method has better reliability.

A means of ballasting for high intensity discharge (HID) lamps, wherein the necessary lamp striking voltage, warm-up current and steady state running current may all be controlled using only two power switching transistors 9,10 operating in two discrete modes. A further feature provides a means of lamp power control over a range of lamp voltages such that the lamp power input remains substantially constant throughout the ageing of the lamp 19. The use of this means of ballasting HID lamps can offer major cost benefits, lower circuit complexity, longer lamp life and colour maintenance and increased flexibility of the wiring installation and lamp position relative to the ballasting and striking means.

The invention discloses a circuit for controlling light sources, method and display system. The circuit for controlling light sources comprises a converter, a feedback circuit and a current distribution controller. The converter is operable for converting an input voltage to an output current and for providing the output current to the light sources. The feedback circuit is coupled to the light sources for generating feedback signals indicative of currents flowing through the light sources respectively. The current distribution controller is coupled to the feedback circuit for generating control signals based on the feedback signals respectively so as to regulate the currents of the light sources respectively, and for controlling the converter to regulate the output current based on the feedback signals. The circuit for controlling light sources without a plurality of linear regulators or switch controllers and switch regulators reduces the circuit cost, increases the circuit efficiency and reduces the circuit complexity.

The present invention discloses a decomposition method for a random quantum bit gate, and belongs to the field of the quantum state manipulating technology. The method includes: the bit gate U of a random quantum n is decomposed into a plurality of uninterrupted Cn (U) and the decomposition of a random quantum bit gate is achieved by adopting an index decomposition mode and a polynomial decomposition mode with circuit complexities of O (2n) and O (n2) respectively through the fundamental segment and the correcting segment of the structure and utilizing the mode of nested recursion. The present invention achieves that a random quantum bit gate is decomposed into a qubit index form and a polynomial form of complexities, gives the quantum circuit and the relevant analytical expression containing only two quantum bit CNOTs and a single quantum bit accurately, thereby achieving an arbitrary operation to a quantum state in the transmission process of the quantum state, figures out the number of a basic logic gate that the two decomposed forms need, uses a phaseshift approximate gate to replace the Toffolin gate and reduces the complexity of the circuit greatly.

The invention relates to a method and a circuit for dynamically equalizing a battery management system. The method comprises the following steps of: 1) detecting the voltage of each single battery in each group of battery packs sequentially connected in series by using embedded control software; 2) judging the location number of the single battery which needs to be charged or discharged separately and has excessively low or high voltage by using a central processing unit (CPU); 3) giving a control command out by using the CPU, controllably gating a corresponding polarity selecting switch block to perform polarity inversion on a collection bus, controllably gating a corresponding battery selecting switch block to perform polarity matching at the same time, controlling the working direction of a bidirectional isolation transformer and connecting the single battery which needs to be charged or discharged separately and has the excessively low or high voltage to the connection bus for charging or discharging so as to realize energy transfer; and 4) repeating the steps 1) to 3) until the voltage of each single battery in each group of battery packs sequentially connected in series is in a set allowable error range so as to realize dynamic equilibrium. The number of charging and discharging devices and circuit complexity of the battery management system can be reduced remarkably.

The invention discloses an ASIP based on an extensible processor architecture and a realizing method thereof, which mainly solve the problem of high circuit complexity and large resource consumption in the prior art. Aiming at the extensible processor architecture after optimization, the invention adopts a five-level-pipeline realizing method, and adopts a data orientation technology and a branch non-execution strategy to solve data hazards and control hazards in pipeline treatment respectively. The ASIP comprises an instruction fetch unit, a decoding unit, an execution unit, a memory access unit, a write-back unit, a pipeline control unit, a timer and an interrupt controller. According to the ASIP and the method, the characteristics of a pipeline processor and an FPGA (field-programmable gate array) are considered sufficiently, the pipeline structure is partitioned reasonably, and the hardware resources of the FPGA are utilized to the utmost extent; and the ASIP and the method have the advantages of simple circuit design, low resource consumption, high processor performance and low power consumption, and are highly suitable for large-scale parallel processing.

The invention discloses a successive approximation register analog to digital converter (SAR ADC) and a switching method during analog-digital conversion thereof. The SAR ADC comprises a multi-reference generating circuit, a capacitor array digital-to-analog converter (DAC), a comparator and successive approximation control logic. The capacitor array DAC may comprise couple capacitors with binary coding bits of N-3 which are 3 less than the binary coding bits of N outputted by the SAR ADC, the capacitors with N-3 bits can achieve excellent effects of resolution of N bits, the capacitor array area can be effectively reduced, the total number of unit capacitors can be reduced by 87.5%, therefore, the circuit complexity is reduced, the manufacturing cost is saved, and the small size is satisfied. With the switching method provided by the invention, in the switching process, no energy is consumed for the first two comparisons and afterwards, the amount of power consumption for each comparison is less than that of a traditional structure; and compared with the traditional structure, the invention can save up to 99.4% of an average amount of dynamic power consumption in the switching, thereby reducing the overall power consumption.

The invention relates to power management technologies, solves the problem that generally voltage spike in output voltage is overcome for the existing low-dropout regulator at the costs of increased circuit complexity, decreased load capacity, increased output voltage noise and the like, and provides a High-PSR (high power supply rejection) low-dropout regulator with a slew rate enhancement circuit integrated thereto. According to the scheme, the regulator compared to the existing LDO regulators has the advantages that the slew rate enhancement circuit and a compensation capacitor are added, the positive phase input end of an error amplifier is connected with a reference voltage source, the negative phase input end of the error amplifier is connected with a resistance feedback circuit, the output end of the error amplifier is connected with the input end of the slew rate enhancement circuit, the output end of the slew rate enhancement circuit is connected with a gate of a pass transistor, one end of the compensation capacitor is connected with the negative phase input end of the error amplifier, and the other end of the compensation capacitor is connected with the output end of the error amplifier. The high-PSR low-dropout regulator has the advantages that transient response is enhanced and the scheme is applied to low-dropout regulators.

An interface transceiver power management method and apparatus including controlled circuit complexity and power supply voltage reduces power consumption when interface conditions will support a transceiver having reduced complexity. The power supply voltage of the reduced complexity logic is then reduced if the lowered complexity will support a lower power supply voltage. The reduced complexity in combination with a reduced power supply voltage decreases power consumption to a greater degree than reducing transceiver complexity alone. The complexity of processing blocks within the receiver and/or transmitter are adjusted in conformity with one or more selection signals and an operating voltage level is selected in accordance with the requirements of the reduced complexity circuit. An interface quality measurement circuit may provide the selection signal, so that the transceiver complexity is adjusted in response to measured interface conditions or an external pin or register bit may be coupled to a select input.

An analog variable-frequency controller includes a first current generator, a second current generator, a clock generator and a light/heavy load selector. The first and second current generator receive a load current signal and then output a first voltage signal and a second voltage signal, respectively. The clock generator generates a corresponding switching frequency according to the first voltage signal or the second voltage signal. The light/heavy load selector, connected with the first current generator, the second current generator and the clock generator, receives a control signal for controlling the clock generator to receive the first voltage signal or the second voltage signal. The abovementioned controller is implemented by an analog circuit, which has a lower circuit complexity, lower cost and is easy to be integrated into a switching converter.

The invention discloses a control and protection circuit for a single-lithium battery electric tool and a detection and control method for the control and protection circuit. The control and protection circuit comprises a singlechip power supply circuit, a battery charging and discharging voltage detection circuit, a battery charging and discharging temperature detection circuit, a battery charging control management circuit, a motor switching and commutation control circuit and a working state indication circuit. A singlechip is used as a master control integrated circuit (IC), and is matched with simple peripheral components to realize all functions of protecting and controlling the single-lithium battery electric tool, so that the functions are flexibly designed, circuit complexity is lowered, the number of electronic components is decreased, cost is lowered, and the circuit is high in safety and reliability, and is almost power consumption-free when not working, and has the advantages of environment friendliness, energy saving, lightweight, convenience for use, high operation efficiency, long cycle life of a battery, and the like.

The invention relates to a slow clock crystal frequency compensation method and a slow clock crystal frequency compensation device for a mobile communication terminal. The method comprises the following steps of: entering an idle mode; judging a previous mode before entering the idle mode; acquiring a calibration parameter if the previous mode is a normal working mode; calculating slow clock crystal frequency; and if the previous mode is a sleep mode, firstly acquiring synchronism deviation, then judging whether the synchronism deviation is in a set threshold value, if the synchronism deviation is in the set threshold value, compensating the slow clock crystal frequency, and otherwise, forcibly calibrating the slow clock crystal frequency; the device comprises a forcible calibration unit, a synchronism deviation unit, a correction and calibration unit and a power-saving control unit; accurate sleep timing is guaranteed and a system does not fall out of step after being awakened without increasing the circuit complexity and terminal hardware cost, and starting of a clock calibration unit to the minimum extent is also guaranteed, so that the sleep time is maximized when the mobile communication terminal is in the idle mode, and the power consumption of the mobile communication terminal is reduced.

The invention belongs to the technical field of data converters in integrated circuit design, and discloses a double-input operational amplifier shared margin gain amplifying circuit. The amplifying circuit comprises a double-input operational amplifier, a clock generating circuit, a sub digital-to-analog converter, a sub analog-to-digital converter, a capacitor, a switch and the like. Two groups of differential input pair tubes are controlled through the switch controlled by bidirectional overlapped clocks and embedded inside the operational amplifier by adopting the operational amplifier of two groups of input differential pairs and are alternately used at two phases of the clocks, and meanwhile the input differential pairs are alternately reset to a common-mode input voltage so as to fully eliminate the influence of memory effect and inter-stage feed-through in the traditional circuit, improve the signal establishing precision under the condition of keeping the same area, power consumption and circuit complexity and further improve the precision of analog-to-digital conversion.

A design structure for an apparatus for utilizing a single set of one or more thermal sensors, e.g., thermal diodes, provided on the integrated circuit device, chip, etc., to control the operation of the integrated circuit device, associated cooling system, and high-frequency PLLs, is provided. By utilizing a single set of thermal sensors to provide multiple functions, e.g., controlling the operation of the integrated circuit device, the cooling system, and the PLLs, silicon real-estate usage is reduced through combining circuitry functionality. Moreover, the integrated circuit device yield is improved by reducing circuitry complexity and increasing PLL robustness to temperature. Furthermore, the PLL circuitry operating range is improved by compensating for temperature.

A method and apparatus for computing a convolution between an input GPS signal and a C/A code reference by generating the convolution result in real time without storing unprocessed signal samples. The apparatus comprises a vector multiplier running at high speed to achieve the same result as a vector multiplier sized to process an entire epoch. Additionally, the input samples to, and the output samples of, the vector multiplier can be quantized to reduced circuit complexity.