69 results about "Circuit complexity" patented technology

Ultra-Wideband (UWB) technology is a wireless technology supporting the transmission of large amounts of digital data over short distances using coded impulses over a wide frequency spectrum with very low power. Enhanced link performance and functionality of such UWB systems is presented exploiting multiple directive antennas for spatially filtering undesired signals and increasing signal strength whilst circuit complexity is reduced by eliminating baluns in prior art solutions. Further enhancements support payloads with flexible encoding schemes, improved channel utilization, reduced processing logic, improved robustness in correlation techniques, versatile synchronisation techniques, improved ranging, as well as providing for improved inter-symbol interference tolerance and detection.

The invention discloses a floating-point number format conversion device and method, a storage medium and a program product, and relates to the technical field of floating-point number format conversion. The device comprises a preprocessing unit and a conversion mapping unit; the preprocessing unit is used for receiving input data in a first floating point format and performing bit width compression processing on at least part of digits influencing rounding operation in the input data to generate a corresponding index value, and the bit width of the index value is smaller than the mantissa bit width of the input data; the conversion mapping unit is coupled to the preprocessing unit, a plurality of mapping relations between index value ranges and numerical value representations in a second floating point format are stored in the conversion mapping unit, and the conversion mapping unit is used for searching the corresponding numerical value representations in the second floating point format according to the index values to serve as output data. The invention aims to reduce the number of logic gates and the circuit complexity required by floating-point number format conversion, so that the area of a related chip is reduced, the power consumption is reduced, and the operation delay is shortened.

A data aggregation service is engineered to generate aggregated data values based on encrypted data received from a variety of providers, without being exposed to the underlying plaintext data. A homomorphic encryption scheme is used in a threshold cryptography scenario that allows aggregation of the encrypted data without requiring decryption. An independent decryption service can partially decrypt the aggregated result, which can ultimately be decrypted to plaintext for use by the provider. Bitwise operations can be defined to support aggregation with error tolerance, and the operations can be constrained to a smaller bit size to reduce circuit complexity.

This application discloses a floating-point number format conversion apparatus and method, storage medium, and program product, relating to the field of floating-point number format conversion technology. The apparatus includes a preprocessing unit and a conversion mapping unit. The preprocessing unit receives input data in a first floating-point format and performs bit-width compression processing on at least a portion of the bits in the input data that affect rounding operations to generate corresponding index values, wherein the bit width of the index values ​​is smaller than the mantissa bit width of the input data. The conversion mapping unit is coupled to the preprocessing unit and stores multiple mapping relationships between index value ranges and numerical representations in a second floating-point format, used to look up the corresponding numerical representation in the second floating-point format as output data based on the index values. This application aims to reduce the number of logic gates and circuit complexity required for floating-point number format conversion, thereby reducing the chip area, power consumption, and operation latency.

This invention discloses a 4-2 approximation compressor based on memristors, a control method, an apparatus, and applications. It approximates and compresses four 1-bit numbers X1, X2, X3, and X4 using two identical memristor-based majority gate circuits. The two majority gate circuits respectively implement traditional majority gate logic and a novel majority gate logic including inversion logic. The first majority gate circuit implements the traditional majority gate logic M(X1, X3, X4) to obtain the carry result of the 4-2 approximation compressor. The second majority gate circuit implements the novel majority gate logic including inversion logic to obtain the pseudo-sum result of the 4-2 approximation compressor. This invention does not rely on the cascading of a large number of basic logic units such as NAND gates and NOR gates, has a shallow logic depth, and can achieve a 4-2 compressor with good error performance with low circuit complexity, high operation speed, and low power consumption.

The application discloses a kind of based on 3M-1R memristor complete non-volatile Boolean logic circuit and control method, belong to microelectronic device technical field, this logic circuit mainly consists of three memristors and a fixed resistance, the area occupied by circuit is smaller, circuit complexity is lower, wherein, one input P in logic calculation process is defined as the resistance state of input memristor 1, another input Q is defined as the resistance state of input memristor 2, the resistance state of output memristor is as output, by the gating state of control multiplexer, and corresponding voltage is applied to each memristor, namely, one-step calculation operation can realize arbitrary Boolean logic operation, and in the operation process of logic calculation, the resistance state of input memristor 1 and input memristor 2 does not change, input information is completely non-volatile saved in corresponding memristor, can use as few as possible device and operation step number while in the calculation process, the integrity of input information is protected.

To provide a processor, an information processor, and a control method of the processor for reducing an increase in circuit scale and circuit complexity.SOLUTION: The package-unit allowable power determination unit 102 determines the smaller one of the first required power required for the entire CPU core die and the first power limit for the entire CPU core die as the first allowable power allowed for the entire CPU core die. The per-die allowable power determination unit 106 determines the second allowable power of each CPU core die based on the first allowable power and the smaller one of the second required power and the second power limit of each CPU core die. The transmitter transmits the second allowable power to the CPU core die and causes the CPU core die to be supplied with the second allowable power.SELECTED DRAWING: Figure 3

According to certain aspects, the present embodiments relate to techniques to provide the ability to monitor one or more operating parameters of a voltage regulator. In an embodiment, the voltage regulator is a multi-phase voltage regulator having a plurality of power stages corresponding to respective phases. In these and other embodiments, the operating parameter includes one or both of a phase current and a phase temperature. According to further certain aspects, the present embodiments provide the ability to independently monitor individual phase current outputs and phase temperatures for each phase. According to a further aspect, this ability to monitor operating parameters is obtained while minimizing circuit complexity.

The application relates to an operational amplifier offset voltage automatic correction circuit and method, which comprises an operational amplifier main circuit, the operational amplifier main circuit comprises an operational amplifier basic circuit and an input offset correction transistor array connected in sequence, and the operational amplifier main circuit at least comprises a same-phase input end Vi+, an opposite-phase input end Vi- and an output end Vout; an automatic correction circuit, the automatic correction circuit comprises a correction control circuit and a correction flag generation circuit connected in sequence, the correction control circuit is electrically connected with the operational amplifier main circuit, and the correction flag generation circuit is electrically connected with the output end Vout of the operational amplifier main circuit. The application can adapt to a wide power voltage range, has higher offset correction precision, the proposed offset voltage automatic correction circuit does not need additional comparators and filters and other analog circuits, only uses digital logic to complete automatic correction control, and reduces the circuit complexity and cost.

The invention relates to the technical field of power electronic conversion, and discloses a power conversion circuit and a UPS (Uninterrupted Power Supply) system, which realize an AC / DC (Alternating Current / Direct Current) rectification function in a mains supply mode and a DC / DC boosting function in a battery mode on a single set of hardware through innovative circuit design and device multiplexing on the premise of not obviously increasing hardware cost, and further realize a power conversion function in a battery mode. The system structure is simplified, the cost is reduced, and the power density is improved. According to the design, the multifunctionality of the existing device is fully utilized, and the problems of hardware redundancy and cost increase are avoided. Meanwhile, as the number of devices and the circuit complexity are reduced, the reliability of the system is improved, and the maintenance difficulty is reduced. Besides, due to the improvement of the power density, the whole power conversion circuit can support higher power output under the same size, or more compact design can be realized under the same power requirement, and powerful support is provided for integration and miniaturization of medium-power UPS power supply equipment.

Methods, error correction circuits, and circuit modules using error correction circuits are provided for performing co-bit calculations for error correction by means of circuit complexity reduction. Methods and related devices for co-bit computations for error correction by means of circuit complexity reduction are provided. The method comprises: in an error correction circuit using a predetermined error correction code, configuring a first group of XOR operational circuits in a plurality of XOR operational circuits corresponding to a predetermined codeword length, rather than all XOR operational circuits in the plurality of XOR operational circuits, so as to reduce the circuit complexity of the error correction circuit and improve the error correction efficiency of the error correction circuit. Wherein the first set of XOR operational circuits may be a set of optimized XOR operational circuits implemented based on co-located bit coverage reduction; and performing the co-bit calculation using the first set of XOR operational circuits for error correction corresponding to a shorter codeword length, where a smaller XOR operand and a shorter critical path length can be achieved.

The invention relates to the technical field of integrated circuits and electronic circuits, in particular to a multi-mode multiplexing differential driving circuit based on a CMOS (complementary metal oxide semiconductor) process, which comprises an auxiliary current control circuit and a core current control circuit, and is characterized in that the auxiliary current control circuit comprises a first auxiliary circuit and a second auxiliary circuit; the first auxiliary circuit and the second auxiliary circuit have the same structure and are symmetrically arranged on the left and right sides of the core current control circuit. The problems of large output parasitic capacitance, limited circuit speed, high power consumption and large circuit complexity caused by multi-mode multiplexing realized through module parallel connection in the prior art are solved.

The invention discloses an analog-to-digital converter with a voltage monitoring function. The analog-to-digital converter comprises a voltage comparator and a control logic circuit. The control logic circuit is used for switching the working modes of the analog-to-digital converter, and the working modes comprise a data acquisition mode and a real-time monitoring mode. When working in a data acquisition mode, the voltage comparator is used for converting an analog electric signal input into the analog-to-digital converter into a discrete digital logic level signal so as to output a digital signal according to the digital logic level signal. When working in a real-time monitoring mode, the voltage comparator is used for comparing an input analog electric signal with a threshold setting electric signal and outputting a monitoring result signal obtained through comparison. By means of the working mode switching mode, the voltage comparator of the analog-to-digital converter is fully applied, so that the circuit complexity of a signal acquisition chip in a scene where the analog signal subjected to analog-to-digital conversion is limited by a voltage value is simplified, and the cost is reduced.

The application discloses a linearization calibration circuit and method applied to a pipeline ADC without a sampling and holding structure, and the circuit comprises a signal generation module, a pipeline ADC quantization module and a linear calibration module. The signal generation module is used for generating a pseudo-random signal, and the pseudo-random signal is converted into a dithering signal and then input into the pipeline ADC quantization module. The dithering signal comprises a first dithering signal and a second dithering signal. The pipeline ADC quantization module is used for superimposing the first dithering signal and the second dithering signal on an input signal respectively after the first dithering signal and the second dithering signal are processed through different paths, generating a to-be-calibrated signal, and quantizing the to-be-calibrated signal to obtain an output digital code. The linear calibration module is used for calibrating the to-be-calibrated signal based on a preset weight coefficient, the output digital code and the pseudo-random signal, and obtaining a calibrated signal. The application does not affect the main function of the circuit during calibration, is suitable for the pipeline ADC without the sampling and holding structure, can be operated in the background, has low circuit complexity, and has important significance for improving the linearity of the ADC applied to various communication systems.

Ultra-Wideband (UWB) technology is a wireless technology supporting the transmission of large amounts of digital data over short distances using coded impulses over a wide frequency spectrum with very low power. Enhanced link performance and functionality of such UWB systems is presented exploiting multiple directive antennas for spatially filtering undesired signals and increasing signal strength whilst circuit complexity is reduced by eliminating baluns in prior art solutions. Further enhancements support payloads with flexible encoding schemes, improved channel utilization, reduced processing logic, improved robustness in correlation techniques, versatile synchronization techniques, improved ranging, as well as providing for improved inter-symbol interference tolerance and detection.

This invention discloses a power amplifier and its design method: replacing the microstrip lines in a power divider with lumped elements; merging the lumped elements in at least one input circuit and / or the output matching circuit connected to the same node with the lumped elements in the power divider. This invention achieves circuit miniaturization, reduced circuit complexity, and lower material costs without increasing the complexity of the driver stage output matching circuit and the final stage input matching circuit, and without affecting the performance of the power amplifier link.

Embodiments of the present application provide a shift logic circuit optimization method, a computer device and a storage medium. The method comprises: obtaining a first shift logic circuit, the first shift logic circuit comprising a first shift sub-circuit; determining a minimum input signal set corresponding to the first shift logic circuit, the minimum input signal set comprising the least input signals driving all logic outputs of the first shift logic circuit; constructing a second shift sub-circuit based on the minimum input signal set; and replacing the first shift sub-circuit in the first shift logic circuit with the second shift sub-circuit to obtain a second shift logic circuit. The technical solution provided by the embodiments of the present application has the advantages that the number of combination logic blocks included in the second shift logic circuit is also less than the number of combination logic blocks included in the first shift logic circuit, the number of logic levels included in the second shift logic circuit is generally shallower, the circuit complexity is lower, and it is easier to implement further optimization of the second shift logic circuit by a subsequent synthesis tool.

The application discloses a TOF measurement circuit and a measurement method based on column-shared TDC, which comprises a pixel array, a time address detection circuit and a readout circuit; the pixel array detects photons and outputs avalanche signals; the time address detection circuit measures the time of flight of the photons and encodes the row address of the pixels responding to the photons; and the readout circuit sequentially reads out the time of flight data and the address data column by column; the time address detection circuit proposed by the application can avoid the problem of inaccurate measurement results caused by photon event collision to the greatest extent while quantizing the time of flight of the photons; on the other hand, the circuit can directly encode the row address and read out the time of flight data and the row address data of the photons through the readout circuit, without additional column address encoding and control logic circuit, thereby effectively reducing the circuit complexity and saving the chip area; in addition, the application has a simple structure and is easy to realize large-scale pixel array expansion integration.

The application relates to a high-linearity sample-and-hold circuit for an electric energy metering chip, and belongs to the technical field of integrated circuits. The circuit aims to solve the problem of serious deterioration of linearity caused by substrate bias effect and parasitic diode leakage of a traditional sample-and-hold switch under the condition of zero common-mode voltage input. The core of the technical scheme is to introduce a dynamic substrate bias module, so that the substrate potential of a sampling tube and a reset switch can change in real time along with the input signal, and the substrate and the source-drain end are always maintained in reverse bias, and a gate voltage self-boosting circuit is combined to stabilize the gate-source voltage of the sampling tube. The design effectively eliminates threshold voltage drift and substrate leakage current under the premise of almost no increase in circuit complexity, thereby realizing high-linearity signal sampling under the condition of zero common-mode input, and significantly improving the precision and reliability of the electric energy metering chip.

The embodiment of the invention provides an interpolation filter circuit, a circuit module and a chip, the interpolation filter circuit comprises a compensation filter and an integrator comb filter, the compensation filter is used for carrying out first interpolation processing on an input signal of the interpolation filter circuit, and the integrator comb filter is used for carrying out second interpolation processing on the input signal of the interpolation filter circuit; a first interpolation result is obtained and input to the integrator comb filter; and the integrator comb filter is used for performing second interpolation processing on the first interpolation result to obtain a second interpolation result, and taking the second interpolation result as an output signal of the interpolation filter circuit. Therefore, the circuit complexity and the cost can be reduced.

The application provides a current register and a control method thereof and an image sensor, and comprises a transmission module for obtaining a signal current; an operation register module comprising a first register transistor, a second register transistor and a switch control unit; by controlling the state of the switch control unit, the first register transistor and the second register transistor perform inverse, addition, subtraction or multiplication operation on the signal current to obtain a result current, and the result current is stored. Only by using one operation register module, inverse, addition, subtraction and accumulation operations can be realized, and positive and negative currents can be stored, so that the circuit complexity is greatly reduced while the operation function is ensured, and the circuit area consumption is reduced, the integration is improved, the hardware cost is saved, and the problem of large area overhead of the current register is solved.

The application belongs to the field of digital isolator design, and specifically provides a high-speed digital isolator to solve the problem of trade-off between bandwidth, power consumption, area and circuit complexity of the existing digital isolator under the demand of high data transmission rate. The application comprises a sending end circuit, an isolated coupling channel and a receiving end circuit, the isolated coupling channel adopts a distributed coupling transmission line structure, the near-differential response presented by the low-frequency differential zone is used to change the rising edge and falling edge differential changes of the input digital signal into positive and negative polarity pulse signals on the second transmission line structure, then the continuous digital output is recovered through the threshold judgment and state retention of the receiving end, so as to eliminate the speed bottleneck of the traditional pulse coding digital isolator; without high-frequency carrier generation and demodulation circuit, without dedicated edge detection and pulse generation link of the sending end, the isolated digital transmission with high speed, low complexity and low power consumption is realized.

The invention relates to the technical field of optical communication, in particular to a bias voltage automatic control circuit and method and a silicon-based optical modulator. Through cooperative adaptation of the control circuit, the drive circuit, the signal generation circuit and the signal detection circuit, differential sine disturbance signals are accurately coupled to the radio frequency modulation phase shifter of the silicon-based light modulator, and synchronous detection of average light current and the disturbance signals is achieved by means of a built-in light detector. And the control circuit is linked with the driving circuit to accurately adjust the driving current of the thermo-optic phase shifter and efficiently lock a bias working point. The problems that a traditional scheme is low in precision and complex in circuit are solved, the locking speed and stability are improved, meanwhile, hardware design is simplified, the number of components is reduced, the requirement for miniaturization of a high-speed silicon-based optical module is met, working point drifting caused by environment changes is effectively restrained, and the optical signal quality and the long-term working performance of a communication system are guaranteed.

The invention provides a generator ready signal detection device, and relates to the technical field of standby power supply automatic control. The detection device comprises a signal input end, a detection circuit, a driving circuit, an isolation module and a signal output circuit, the signal input end receives at least two types of ready signals and generates an input signal according to the ready signals; the detection circuit generates a corresponding detection signal according to the jump of the input signal; the driving circuit compares the detection signal with a reference signal and generates a driving signal according to a comparison result; a primary side excitation element of the isolation module responds to the driving signal, and a secondary side controlled element of the isolation module responds to the action of the primary side excitation element and outputs an isolation controlled signal; the signal output circuit responds to the isolation controlled signal, so that the output end of the signal output circuit jumps from the first level to the second level. The detection device not only can be compatible with various types of ready signals output by different generators, but also can simplify the circuit complexity and save the cost.

The application discloses a method for load and mutual inductance synchronization identification of a multi-frequency and multi-load wireless power transmission system. First, input impedance equation sets under different frequencies are established under system steady state to obtain a relationship expression of mutual inductance and load. Meanwhile, a sliding window DFT is used to extract a frequency component of a primary side multi-frequency superimposed current according to system working frequencies. Then, a particle swarm algorithm is designed by taking an error between an actual output voltage value and a theoretical value as a fitness function, a parameter identification problem is converted into an algorithm optimization problem, and an optimal solution search is performed on the parameter to be identified to replace a traditional calculation method, so that errors generated by the traditional equation are avoided. The application only needs to analyze a model of system input impedance, has a simple circuit structure, does not need an additional control circuit, and only needs to sample an input bus voltage, a primary side current and an output voltage, so that communication data volume can be effectively reduced, circuit complexity is reduced, system volume is reduced, and a working range of a wireless charging system is expanded.

The invention discloses an in-memory computing circuit based on a floating gate transistor, a computing array and a reading method. The in-memory calculation circuit comprises a selection tube array, a floating gate transistor array and a proportional capacitor array; wherein the selection tube array comprises a plurality of independent selection tubes; the floating gate transistor array comprises a plurality of independent floating gate transistors; the proportional capacitor array comprises a plurality of independent proportional capacitors; the drain electrode of each independent floating gate transistor is connected with the source electrode of one independent selection tube; the source electrode of each independent floating gate transistor comprises two branches, one branch is connected with a shared output bus through a switch, and the other branch is connected with an independent proportional capacitor. According to the invention, the calculation characteristic of the in-memory calculation circuit based on the floating gate memory is utilized, and the data stored in the floating gate transistor in the in-memory calculation circuit can be inversely deduced directly through the calculation result, so that a complex peripheral circuit sensitive amplifier is omitted, the circuit complexity is reduced, and the circuit area is also reduced.

This application provides an ADC pixel and column-level coarse and fine quantization readout circuit suitable for infrared arrays, relating to the field of integrated circuit technology. An oscillator is connected to the pixel infrared detector, counter, and pulse generation unit respectively; the counter and pulse generation unit are both connected to a memory unit; the memory unit is connected to a bus; each pixel is connected to the column-level decoding unit of its column via the bus; the input of the column-level decoding unit is connected to the bus. This application, by employing a pixel structure where the oscillator is directly driven by photocurrent for integration, reduces circuit complexity and area overhead without significantly increasing additional power consumption, which is beneficial for realizing highly integrated small pixel arrays. It eliminates the need for a highly complex ADC structure or additional analog modules, achieving an optimized trade-off between power consumption, area, and accuracy. Reducing the number of buses and wiring resources, lowering bus parasitic capacitance and dynamic power consumption of the readout switches, helps to reduce the layout area.

The application discloses an embedded device and a neural network operation device, and belongs to the technical field of convolution operation of embedded devices. The operation device comprises an operation control module, a convolution operation module, a global average pooling module and a full connection calculation module. The convolution operation module comprises a multi-channel convolution calculation circuit, which is used for sequentially executing second-layer to last-layer convolution calculation. In each layer of convolution calculation, a convolution kernel {c ij} m*m The convolution calculation process of image data {p ij} m*m under the convolution kernel sliding window of each channel comprises the following steps: the operation control module controls the intermediate result calculation circuit to continuously execute the sub-process of different pixels in the sliding window and continuously output different intermediate results in adjacent time sequences; and the accumulation circuit accumulates the newly input intermediate results at each time sequence to obtain the pixel corresponding to the sliding window position in the convolution result. The framework can realize the convolution neural network operation on the embedded device, and can improve the operation speed while reducing the circuit complexity.

The application provides an OTP balance protection circuit, and relates to the field of protection circuits.The OTP balance protection circuit comprises a flyback topology main circuit, a VCC power supply circuit, an OTP protection pin control circuit and an OTP balance control circuit.The utility model discloses a single point detection is realized to many devices balance protection, reduces circuit complexity and cost;the OTP protection point is adaptively adjusted, and the reliability under different input voltages and load conditions is ensured;the insulation problem of cross connection is avoided, and the design is simplified;the OTP function is closed when the load is light, and the risk of false triggering is reduced;the circuit can reliably protect various power devices under different input voltages and different load currents.

The application belongs to the field of analog integrated circuit design, and particularly relates to a redundant current range current steering DAC based on digital pre-distortion. The application carries out rotation correction through an improved DEM decoding circuit, measures and quantizes error codes corresponding to the static mismatch error of each current unit, and reduces the circuit area and the influence of additional circuit parasitic on the DAC speed without additional control circuit. A redundant current unit is introduced at the highest bit to expand the quantization range, and the error code and clipping problem introduced by DPD correction are solved. Only a simple algorithm of a 14-bit adder and a 14-bit subtractor is needed to directly operate on binary codes, and a secondary decoding is used to realize thermometer code addition operation compatible with DEM, so that the timing delay and circuit complexity of the thermometer code addition circuit are greatly reduced. The circuit timing delay of the application meets the speed requirement of high-speed and high-precision current steering DAC, and compared with DEM correction only, the application significantly improves the SFDR without raising the noise floor.