83results about How to "Increase slew rate" patented technology

Fully-buffered dual in-line memory modules (FB-DIMM) include advanced memory buffers (AMBs) having enhanced skew, slew rate and output impedance control. The AMB includes user accessible registers that can be programmed to carefully control the edge placement (or phase) of signals generated from the AMB to multiple DRAMs on the module. This control of edge placement, which may be performed independently for each group of signals: clock (CLK, CLK#), command (RAS, CAS, WE), address (including bank address), data (DQ) and data strobe (DQS), provides 360 degrees of control (or one period). This means that any group of signals can be moved independently by one complete period relatively to any other group.

The invention relates to power management technologies, solves the problem that generally voltage spike in output voltage is overcome for the existing low-dropout regulator at the costs of increased circuit complexity, decreased load capacity, increased output voltage noise and the like, and provides a High-PSR (high power supply rejection) low-dropout regulator with a slew rate enhancement circuit integrated thereto. According to the scheme, the regulator compared to the existing LDO regulators has the advantages that the slew rate enhancement circuit and a compensation capacitor are added, the positive phase input end of an error amplifier is connected with a reference voltage source, the negative phase input end of the error amplifier is connected with a resistance feedback circuit, the output end of the error amplifier is connected with the input end of the slew rate enhancement circuit, the output end of the slew rate enhancement circuit is connected with a gate of a pass transistor, one end of the compensation capacitor is connected with the negative phase input end of the error amplifier, and the other end of the compensation capacitor is connected with the output end of the error amplifier. The high-PSR low-dropout regulator has the advantages that transient response is enhanced and the scheme is applied to low-dropout regulators.

The invention belongs to the technical field of electronics and relates to the frequency compensation technology of operational amplifiers in analog integrated circuits. The split compensation two-stage operational amplifier comprises a two-stage operational amplifier. A first-stage operational amplifier is composed of N-channel metal oxide semiconductor (NMOS) tubes (M1N, M2N, M3 and M4) and P-channel metal oxide semiconductor (PMOS) tubes (M1P, M2P and M0). A second-stage operational amplifier is composed of a PMOS tube M5P and an NMOS tube M5N. A traditional Miller capacitor is divided into a Cm1 portion and a Cm2 portion to finish frequency compensation of the operational amplifier. A first frequency compensation capacitor Cm1 is connected with the position between the output end of the first operational amplifier and the output end of the whole two-stage operational amplifier. A second frequency compensation capacitor Cm2 is connected with the position between a connection point of a source of the NMOS tube M2N and a drain of the NMOS tube M4 in the first-stage operational amplifier and the output end of the whole two-stage operational amplifier. The split compensation two-stage operational amplifier has strong robustness and higher unit grain bandwidth and output slew rate due to the fact that non-dominant poles and stray parameter are not related.

The invention discloses a slew rate enhancement circuit applicable to LDO regulators (low dropout regulators). The slew rate enhancement circuit comprises PMOS (P-channel Metal Oxide Semiconductor) transistors M0, M2, M4, M6 and M8, NMOS (N-channel Metal Oxide Semiconductor) transistors M1, M3, M5, M7 and M9, a bias current source I0, and a capacitor Cf. On the premise of not significantly increasing static power consumption, when LDO load of an LDO regulator, which the slew rate enhancement circuit is integrated to, jumps, changes in output end voltage can be quickly detected and a gate of a power regulating tube is transiently regulated; accordingly, the slew rate of voltage in the gate of the power regulating tube is greatly increased, and transient response of the LDO circuit is improved.

The invention provides a fast transient response circuit applied to an LDO (low-dropout linear voltage stabilizer). An LDO circuit without out-of-chip bulk capacitor is adopted, the fast transient response capacity of the LDO can be enhanced by improving an internal circuit of the LDO, and other performances of the circuit cannot be weakened. The tail current of EA is divided into two parts: one part adopts fixed current bias, and the other part adopts the current from output load sampling; the static current of a chip cannot be increased in the circuit, and the response speed of the loop is also increased along with the increase of the bandwidth and the slew rate of the loop when the load is suddenly increased.

The invention relates to a power supply management technology, solves the problem that the output voltage spike of a conventional low dropout regulator is solved through increasing the circuit complexity, reducing the load capacity and increasing the output voltage, and provides a low dropout regulator (LDO) integrated with slew rate intensifier circuit. The technical scheme adopted by the invention is summarized as follows: compared with a conventional LDO, a slew rate intensifier circuit and a compensation capacitor are additionally arranged, the negative phase input end of an error amplifier is connected with a reference voltage source, the positive phase input end of the error amplifier is connected with a resistance feedback circuit, and the output end of the error amplifier is connected with the input end of the slew rate intensifier circuit; the output end of the slew rate intensifier circuit is connected with a grid electrode of a compensating pipe; one end of the compensation capacitor is connected with the positive phase input end of the error amplifier, and the other end of the compensation capacitor is connected with the output end. The LDO integrated with the slew rate intensifier circuit has the benefit that the transient response is improved, and is applicable to the low dropout regulator.

A regulator includes a first operational amplifier configured to receive a reference voltage and a feedback voltage and to output a node voltage based on a difference of the feedback voltage and the reference voltage; a first switch unit configured to receive the node voltage and to supply a recover current based on the node voltage; an output unit configured to output an output voltage and the feedback voltage according to a supply of the recover current; a comparison unit configured to receive the reference voltage and a feedback voltage and to sense a voltage drop of the output voltage; and a second switch unit configured to discharge the first switch unit according to the difference of the reference voltage and the feedback voltage.

The invention provides a pod-type water jet propulsion unit, which comprises an installation platform, a pod propeller bracket arranged at the lower end of the installation platform, a pod propeller cabin body arranged at the lower end of the pod propeller bracket, a pod propeller cabin body arranged at the pod propulsion The motor base in the cabin body, the motor installed on the motor base, the transmission shaft connected to the output end of the motor, the water jet propulsion pump installed on the transmission axis, the lower end of the pod propeller cabin is provided with an inlet, a side A spout is provided, a flow channel is formed between the inlet and the spout, and the spout is set facing the water jet propulsion pump, and the upper end of the installation platform is provided with a data transmitter and a hydraulic steering device. The present invention is on the basis of maintaining the advantages of the original water jet propeller, adding the bracket, cabin body, electric propulsion system and steering device of the pod propeller, thereby reducing the complicated mechanical transmission mechanism and reversing device of the water jet propeller, further The propulsion efficiency and operational performance of the thrusters are improved, the noise is reduced and the stealth performance is enhanced.

The invention provides a slew rate control device and method. The slew rate control device comprises a pre-driving module, a process tracking and compensating module, a current mirror module and a post-driving module, wherein the pre-driving module is used for applying a pre-driving voltage on the process tracking and compensating module, the process tracking and compensating module is used for compensating the slew rate according to the process condition of the post-driving module under the control of the pre-driving voltage, the current mirror module is used for keeping the rates of charging and discharging the post-driving module, and the post-driving module is used for generating an output voltage and feeding the output voltage to the pre-driving module to generate the pre-driving voltage. By utilizing the slew rate control device and method provided by the invention, the slew rate can be controlled better, and the influence of the input voltage and temperature on the slew rate can be avoided without the increasing of the circuit area.

The invention discloses an operational amplifier circuit which comprises a first level and a second level. The first level comprises 22 MOS transistors from the first MOS transistor to the twenty-second MOS transistor, a first current source, a second current source, a first capacitor and a second capacitor. The second level comprises a PMOS transistor and an NMOS transistor, wherein the drain electrode of the PMOS transistor and the drain electrode of the NMOS transistor are connected. The input level of an operational amplifier is of a cross coupling pair structure, a load of a cross coupling pair is a cascode current mirror so that an I-V curve of the operational amplifier can have an expansion character instead of an amplitude limiting character of a common differential pair, and therefore a high slew rate can also be obtained under the condition of low static current.

Disclosed herein is an amplifier including a voltage follower circuit having differential input terminals and an output terminal fed back to a first one of the differential input terminals, the voltage follower circuit being configured to amplify an input signal inputted to a second one of the differential input terminals and output the amplified signal from the output terminal; a first current source configured to supply a predetermined current to the voltage follower circuit; and a second current source configured to supply current to the voltage follower circuit when a potential difference between the second one of the differential input terminals and the output terminal is equal to or higher than a predetermined value.

The invention provides a clock driver circuit. The clock driver circuit comprises successively connected input stage, double-end-to-single-end stage and driving output stage, wherein the input stage includes differential amplifiers which are the load for each other and a common mode negative feedback loop; the differential amplifiers access differential clock signals for amplification to generatea common mode voltage; the common mode feedback loop is connected to the output ends of the differential amplifiers for stabilizing the output amplitude of the common mode voltage; the double-end-to-single-end stage converts a differential sinusoidal clock signal outputted by the double-end common mode voltage into a single-end square wave clock signal; and the driving output stage includes a multi-stage-cascaded push-pull inverter, so as to increase the driving capability of the square wave clock signal. The clock driver circuit adopts differential amplifiers which are the load for each other, and any one of the two differential amplifiers acts as the load for the other, thus expanding the amplitude range of the input stage, has the capability of inhaling and supplying a large current, and improves the slew rate, so that the clock driver circuit can receive input clock signals with large amplitude and high speed.

The invention relates to a transconductance amplifier adopting the signal attenuation technology and a method. The transconductance amplifier comprises differential input-stage input voltages Vin+ and Vin-, and differential input currents are generated. Power voltage VDD is accessed to a signal attenuation circuit, signal attenuation is carried out on the differential input currents, and a current attenuation signal is generated. The power voltage VDD has access to a bias current source, communication is carried out according to the current attenuation signal, and bias currents are output to a first current mirror and a second current mirror. The first current mirror and the second current mirror both copy the bias currents, and copied currents are generated to be transmitted to a third current mirror. The unity-gain bandwidth is increased through the third current mirror, gain amplification is carried out on the copied currents, and an amplifying signal Iout is output. Compared with the prior art, the influence between input and output voltages is low, no additional pole is introduced, and high linearity, high gain and high-precision amplification are achieved.

The invention discloses an adjustable amplification circuit, which comprises an operational amplifier, a simulation unit and a bias control unit, wherein the operational amplifier comprises a variable bias current source which is used for supplying a variable bias current to the operational amplifier; the simulation unit is used for simulating the operation characteristic of the operational amplifier and converting a simulation input voltage into a simulation output voltage; and the bias control unit is used for generating a bias control signal to the variable bias current source according to the simulation output voltage to adjust the size of the variable bias current.

The invention discloses a slew rate enhanced operational amplifier suitable for restraining electromagnetic interference. The operational amplifier consists of seventeen MOS (Metal Oxide Semiconductor) transistors, namely, first to eleventh PMOS (P-channel Metal Oxide Semiconductor) transistors M0, M1a, M1b, M2a, M2b, M5, M6, M7, M8, M9 and M10 and first to sixth NMOS (N-channel Metal Oxide Semiconductor) transistors M3a, M3b, M4a, M4b, M11 and M12, wherein differential-mode signals Vin+ and Vin- are input through gate electrode input ends Vp of the second to third PMOS transistors M1a and M1b, and gate electrode input ends Vn of the fourth to fifth PMOS transistors M2a and M2b respectively; spurious signals are filtered through amplification of a Recycling folded cascode amplification stage and an electromagnetic interference restraining stage; meanwhile, a slew rate is increased; and a signal is output through a high-gain output end Vout. Through adoption of the operational amplifier in a low-voltage and low-power-consumption mixed signal circuit, an electromagnetic interference restraining ability specific to signals can be enhanced while the slew rate is increased.

The invention relates to a large-scale integrated circuit, and discloses a low-power high-slew-rate operational amplifier suitable for ultra-wide band microwave detection, for realizing a high slew rate through simultaneously improving the PSRR and the CMRR of an amplifier. For this end, the technical scheme employed by the invention is as follows: the low-power high-slew-rate operational amplifier suitable for ultra-wide band microwave detection is composed of a Recycling folded cascade amplifying stage, a slew rate enhanced stage and a PSRR enhanced output stage. Differential mode signals Vin- and Vin+ are input by the Recycling folded cascade amplifying stage, and after being subjected to the slew rate enhancement effect of a cascade current mirror, finally reach to an output end Vout through the PSRR enhanced output stag. The low-power high-slew-rate operational amplifier is mainly applied to the design and manufacture of the large-scale integrated circuit.

The invention discloses a high-precision current-limiting load switch circuit, a current-limiting load switch is connected between a power supply and a load, and the current-limiting load switch circuit mainly solves the problems of low precision and the low response speed of the existing current-limiting load switch circuit. The current-limiting load switch circuit comprises a reference current unit (1), a current-limiting detection unit (2) and a load switch unit (3), the reference current unit is used for generating a stable reference current signal and setting a limiting current; the current-limiting detection unit is used for detecting load current and outputting bias voltage to drive an NMOS load switch. When the load switch unit works in a deep linear region, the conduction impedance is small, and the power supply utilization efficiency is higher. Besides, the operational amplifier for the current-limiting detection unit provided by the invention has the lower offset voltage andthe higher slew rate, so that the current-limiting load switch circuit has the characteristics of high precision and the high response speed, and can be used in an intelligent and integrated power supply management system.

The invention provides a slew rate enhancement type operational amplifier, which at least comprises a biasing circuit, a first-stage circuit, a second-stage circuit and a drive current regulating circuit, wherein the first-stage circuit is connected to the biasing circuit; the second-stage circuit is respectively connected to the biasing circuit and the first-stage circuit; and the drive current regulating circuit is respectively connected to the biasing circuit, the first-stage circuit and the second-stage circuit and is used for regulating the drive current of the slew rate enhancement type operational amplifier when the slew rate enhancement type operational amplifier drives a load in order to make the drive current of the slew rate enhancement type operational amplifier greater than the bias current to enhance the slew rate of the slew rate enhancement type operational amplifier. In comparison with the class-A operational amplifier in the existing technology, the magnitude of the drive current of the slew rate enhancement type operational amplifier is not decided by the bias current of an output stage, and the drive current can be much larger than the bias current, so that quick charge and discharge under the large capacitance load can be realized without improving the bias current of the output stage, and thus the slew rate is greatly improved.

The invention discloses a multistage amplifier which comprises a differential input stage, at least one intermediate amplification stage and an output stage. The differential input stage, the intermediate amplification stages and the output stage are sequentially in cascade connection with one another; the differential input stage comprises a first MOS (metal oxide semiconductor) transistor, a second MOS transistors, a third MOS transistor, a fourth MOS transistor, a first current mirror circuit, a second current mirror circuit, a first bias circuit and a first load circuit, source electrodes and grid electrodes of the first MOS transistor and the second MOS transistor are coupled with one another, and first voltages can be received by the grid electrodes of the first MOS transistor and the second MOS transistor; source electrodes and grid electrodes of the third MOS transistor and the fourth MOS transistor are coupled with one another, second voltages can be received by the grid electrodes of the third MOS transistor and the fourth MOS transistor, the source electrodes of the third MOS transistor and the second MOS transistor are coupled with each other, and first bias currents can be received by the source electrodes of the third MOS transistor and the second MOS transistor; a common grid electrode of the first current mirror circuit is coupled with a drain electrode of the third MOS transistor, and a first drain electrode of the first current mirror circuit is coupled with a drain electrode of the first MOS transistor; a common grid electrode of the second current mirror circuit is coupled with a drain electrode of the second MOS transistor, and a first drain electrode of the second current mirror circuit is coupled with a drain electrode of the fourth MOS transistor; the first bias circuit is suitable for providing bias circuits for the first current mirror circuit and the second current mirror circuit; the first load circuit is suitable for providing load for the differential input stage. According to the scheme, the multistage amplifier has the advantages of high gain and wide unity gain bandwidth.

Phase-dependent operational amplifiers (“op-amps”) employing phase-based frequency compensation, and related systems and methods are disclosed. A phase-dependent op-amp is provided configured to provide output voltage based on inputs switched by clock signal. The op-amp employs a frequency compensation system having multiple frequency compensation circuits. The frequency compensation circuit corresponding to the clock phase is selected by selection circuit and coupled to the voltage output node. The op-amp charges each frequency compensation circuit during the clock phase to store voltage approximately equal to output voltage. When transitioning to a clock phase, output voltage of op-amp does not have to charge frequency compensation circuit. Voltage of frequency compensation circuit stored during clock phase is approximately equal to output voltage of op-amp for clock phase. The op-amp need only provide a small amount of voltage to the frequency compensation circuit to slew it to its designed voltage during instances of its clock phase.

The invention discloses a voltage buffer amplifier. The voltage buffer amplifier comprises a main amplification circuit and a self-adaption circuit. The size of the working current of the main amplification circuit is determined by a first current sink; the self-adaption circuit provides a mirror current to the first current sink and automatically adjusts the current size of the first current sink based on the working state of the main amplification circuit; when the voltages at the positive-phase and negative-phase input ends are equal, the self-adaption circuit enables the current of the first current sink to be as a first value; when the voltages at the positive-phase and negative-phase input ends are different, the self-adaption circuit enables the current of the first current sink to be as a second value; the first value is less than the second value; the power consumption of the voltage buffer amplifier is reduced through the relatively small first value; and the charging and discharging speed of the output end of the voltage buffer amplifier is increased through the relatively big second value, and the slew rate is accordingly increased. According to the voltage buffer amplifier, the slew rate and the building speed of the voltage buffer amplifier are increased, the stabilizing time of the voltage buffer amplifier can be reduced, and the power consumption also can be decreased.

The invention discloses a method for automatically controlling the power of an optical transceiver. An adopted operational amplifier has the characteristics of broad bandwidth, high slew rate and abundant steady-state current, a driver separately designed in a photodiode is replaced, and the automatic control on optical power is realized.