67 results about "Source structure" patented technology

This nitride semiconductor device (1) comprises a power FET (11), an ESD protection FET (12), a diode (13), and a resistor element (14). A gate structure (50G) of the power FET (11) includes a p-type semiconductor layer (52G) and a gate electrode (54G) that is Schottky-connected to the p-type semiconductor layer (52G). An anode structure (50A) of the diode (13) includes a p-type semiconductor layer (52A). The gate structure (50G), a drain structure (51D) of the ESD protection FET (12), and the anode structure (50A) are electrically connected to each other. A source structure (50S) of the power FET (11), a source structure (51S) of the ESD protection FET (12), and a terminal structure (50R) of the resistor element (14) are electrically connected to each other. A gate structure (51G) of the ESD protection FET (12), a cathode structure (50K) of the diode (13), and a terminal structure (51R) of the resistor element (14) are electrically connected to each other.

A multi-channel GaN HEMT structure and a preparation method thereof are provided. The structure comprises a substrate, a multi-channel region, a source, a drain, an ohmic connection unit, a multi-unit layer and a passivation layer. A buffer layer is formed on the substrate; the multi-channel region is formed on the buffer layer and comprises a plurality of groups of stacked heterojunction units; the source is formed on one side of the GaN HEMT structure and is configured as a hybrid source structure comprising a Schottky metal and an ohmic metal; the drain is formed on the other side of the GaN HEMT structure; the ohmic connection unit is made of an ohmic metal and is connected between all the heterojunction units except the lowermost heterojunction unit; the multi-unit layer is formed on the multi-channel region and comprises at least two unit structures in the same plane; wherein a gate metal is prepared on the surface of the first unit structure to form a gate together; the second unit structure is connected with the source to form a bridge-shaped structure; the other unit structures between the second unit structure and the drain are in the form of floating islands; and the passivation layer is formed on the multi-channel region.

The application discloses a ring gate transistor and a manufacturing method thereof, and relates to the technical field of semiconductors, which is used for effectively inhibiting the parasitic channel leakage of the ring gate transistor, preventing the band tunneling problem, improving the working performance of the ring gate transistor, and reducing the manufacturing difficulty of the ring gate transistor. The ring gate transistor comprises a semiconductor substrate, an active structure, a heavily doped epitaxial structure, and a gate stack structure. The active structure is formed on the semiconductor substrate. The active structure comprises a source region, a drain region, and a channel region between the source region and the drain region. A first recess is formed in the part of the semiconductor substrate below the channel region and is inwardly recessed. The heavily doped epitaxial structure fills the first recess. The conductive type of the heavily doped epitaxial structure is opposite to the conductive type of the source region and the drain region. The gate stack structure surrounds the outer periphery of the channel region. The part of the gate stack structure below the channel region is formed between the heavily doped epitaxial structure and the channel region.

The application discloses a kind of ultra-low voltage wideband low noise amplifiers, it is related to radio frequency signal transceiver technical field.Solve the high-frequency gain attenuation problem in the design of current low power supply voltage wideband low noise amplifier, including two-stage common-source amplifier connected in turn;The input stage amplifier is composed of input matching network, source sense asymmetric current sharing structure, cascaded matching network;The output stage amplifier is composed of MOS single-layer common-source structure, output matching network.The application improves the conventional source degeneration inductance structure, proposes a kind of source sense asymmetric current sharing structure, on the one hand, gain compensation of high frequency band is realized under the premise of not increasing power consumption, on the other hand, circuit uses peak inductance technology to realize wideband matching, gain compensation and reduce noise.In addition, the circuit uses active substrate noise reduction technology, adds high output impedance gate ground MOS tube to improve substrate resistance, reduce the noise change due to power consumption reduction.

This application relates to integrating a FinFET and a Schottky barrier diode on a substrate. A first fin structure and a second fin structure are formed on the substrate. The first fin structure includes a channel portion extending to two pressure source portions on two opposite sides of the channel portion, and the second fin structure includes a junction portion. The source and drain structures of the FinFET are respectively formed on the two pressure source portions of the first fin structure. A source metal material, a drain metal material, and a first metal material are formed to be electrically coupled to the source structure, the drain structure, and the junction portion of the second fin structure, respectively, thereby providing a Schottky junction between the junction portion of the second fin structure and the first metal material.

Embodiments of the present application provide a chip, a preparation method thereof and an electronic device, and relate to the technical field of semiconductors, and are used to improve the storage density of embedded memories. The chip comprises a plurality of memory cell groups. A memory cell group comprises a first transistor and two memory cells. A memory cell comprises a second transistor and a storage element, and the first transistor and the second transistor each comprise an active structure, and the active structure of the first transistor is located between the active structures of the second transistors of the two memory cells. The active structure comprises a channel region, a first contact region and a second contact region. The first contact region of the first transistor is connected to the first contact region of the second transistor of one memory cell, and the second contact region of the first transistor is connected to the first contact region of the second transistor of the other memory cell; wherein in the same memory cell group, when the memory cells are in a working state, the first transistor is in an off state. The above chip is applied to an electronic device, thereby improving the performance of the electronic device.

The embodiments of this application describe a base station and a cleaning system. The base station comprises a ramp assembly, a base station body, and a power supply structure, wherein the power supply structure includes a female connector assembly, a male connector assembly, and a first sealing component. The power supply structure is particularly suitable for electrical connection between two modules that must be frequently detached and attached. [Fig. 1]

The present application relates to semiconductor devices and methods of manufacturing the same. A semiconductor device includes at least one channel structure extending through a gate structure, a contact plug extending through a stack, a source structure on the gate structure to connect to the at least one channel structure and extending onto the stack, an interlayer insulating layer on the source structure, a first contact via extending through the interlayer insulating layer and connected to the source structure, and a second contact via including a first portion having a first width in the source structure and connected to the contact plug and a second portion having a second width and extending through the interlayer insulating layer to connect to the first portion.

The utility model provides a kind of micro heat source structure, atomization core and electronic equipment, it is related to electronic component technical field, can improve the connection reliability of micro heat source structure, improve the installation efficiency of micro heat source structure.Micro heat source structure includes: substrate, with opposite first surface and second surface;First impedance body, is arranged in first surface;First electrode, with first impedance body electric connection;Second impedance body, is arranged in second surface;Second electrode, with second impedance body electric connection;Through hole, through first surface and second surface, first impedance body and second impedance body are electrically connected by through hole;The orthographic projection of first electrode in first surface is identical with the orthographic projection of second electrode in first surface at least partially coincident.

Embodiments of the present application provide a semiconductor device, comprising: a substrate; a first well and a second well disposed in the substrate and adjacent to each other; an isolation structure disposed on the first well; a first field plate disposed on the isolation structure; a gate structure across the first well and the second well, and an opening between the first field plate and the gate structure, the opening exposing an edge of the isolation structure close to the gate structure; a drain structure disposed in the first well; and a source structure disposed in the second well, reducing or preventing hot carrier effect.

The application discloses a dual-frequency millimeter wave high-gain low-profile transmission-reflection integrated antenna, and relates to the technical field of wireless communication. The application realizes the functions of selective electromagnetic wave high-gain transmission and reflection of two frequencies by using one feed source structure, and reduces the profile height of the antenna to one half of the profile height of a conventional design only by using one metal layer and two dielectric layers, so that the overall size of the antenna is greatly reduced. In addition, the application can realize the functions realized by other prior arts only by using two dielectric layers, so that the overall processing complexity and manufacturing cost of the antenna are greatly reduced, and the application has high cost and processing advantages.

The application provides a light source angle adjusting mechanism and concentricity detection device, and relates to the technical field of concentricity detection.The adjusting structure is arranged, the first hand screw bolt is loosened, the light source support arm can be rotated around the first hand screw bolt as the center, the light source support arm can be lifted, the angle and the height of the light source structure can be adjusted, the second hand screw bolt is loosened, the light source structure can be rotated around the second hand screw bolt as the center, the angle between the light source structure and the light source support arm can be adjusted, the adjusting range is improved, the adjusting process can be operated by hand, the device is convenient to use, and the light source structure can be rotated in the containing groove before the adjusting structure and the light source structure are installed and used, so that the adjusting structure and the light source structure are more compact, and the adjusting structure can also play a part of the protection role for the light source structure.

Method for manufacturing a photonic device This description relates to a method for manufacturing a photonic device comprising the following steps: - providing on a structure comprising a basic substrate (110) covered by mesas (120) (Al,In,Ga)N / (Al,In,Ga)N, a first mesa (120a) being entirely porosified and having flanks covered by a protective layer (140), a second mesa (120b) being non-porified and a third mesa (120c) comprising porosified flanks (121) and a non-porified central part (122), - carrying out an epitaxy of an active structure (130) comprising InGaN-based quantum wells (132) simultaneously on the first mesa (120a), the second mesa (120b) and the third mesa (120c), to form respectively a first active structure (130a) emitting at a first wavelength,a second active structure (130b) emitting at a second wavelength and a third active structure (130c) emitting at a third wavelength. Figure for the abstract: Fig. 1B,

A method of generating a passive structure design includes receiving, by processing circuitry of a computing device, a set of performance metrics; providing, by the processing circuitry, the set of performance metrics to a trained generator network; receiving, by the processing circuitry, a passive structure design from the generator network; and outputting, by the processing circuitry, via a communication interface, the passive structure design.

The present disclosure provides a semiconductor device including an epitaxial structure, a first pad, a first contact electrode and a first barrier structure. The epitaxial structure includes a first semiconductor structure, a second semiconductor structure, and an active structure located between the first semiconductor structure and the second semiconductor structure. The first pad is located on the second semiconductor structure. The first contact electrode is located between the second semiconductor structure and the first pad. The first barrier structure is located between the first contact electrode and the first pad and includes a first metal layer and a second metal layer. The first metal layer has a first reflectivity for a light with a wavelength ranging from 950 nm to 1200 nm, and the second metal layer has a second reflectivity for the light with the wavelength ranging from 950 nm to 1200 nm, and the second reflectivity is larger than the first reflectivity. The first metal layer includes a first thickness, the second metal layer includes a second thickness, and the first thickness is larger than the second thickness.

A microelectronic device comprises lateral contact structures overlying a source structure and comprising conductive material, a cap material overlying the lateral contact structures and comprising implant regions therein, a stack structure overlying the cap material and comprising a vertically alternating sequence of insulative structures and conductive structures arranged in tiers, and pillars vertically extending through the stack structure and into the source structure. The pillars individually comprise semiconductive channel material in physical contact with the lateral contact structures. The microelectronic device comprises filled slot structures vertically extending at least through the stack structure and the cap material. The filled slot structures are positioned within horizontal areas of the implant regions of the cap material. Related memory devices, electronic systems, and methods of forming the microelectronic devices are also described.

Embodiments of the present disclosure provide a semiconductor structure and a manufacturing method thereof, and an electronic device. The manufacturing method comprises: providing an initial structure, the initial structure comprising: a substrate, a stack structure on the substrate, the stack structure comprising first semiconductor layers and first isolation layers stacked alternately, isolation grooves arranged in an array in the stack structure, second isolation layers filling the isolation grooves, and first openings between adjacent isolation grooves; removing part of the first semiconductor layers from the first openings to form capacitor grooves; filling the capacitor grooves and the first openings with first sacrificial structures; removing the second isolation layers to open the isolation grooves, and etching the first semiconductor layers from the isolation grooves to form a plurality of active structures; forming third isolation layers to fill at least the isolation grooves; removing the first sacrificial structures to open the first openings and the capacitor grooves; and forming a capacitor structure, the capacitor structure comprising a first electrode layer covering inner walls of the capacitor grooves and electrically connected to the active structures.

The present disclosure relates to a semiconductor device having a plurality of replica cells and a plurality of resistors and a method of manufacturing the same. Embodiments include a semiconductor device comprising a gate node, a drain node, a source node, and a gate bus, wherein the gate bus is connected to the gate node, a source structure, and a drain structure, wherein the source structure is coupled to the source node, and wherein the drain structure is coupled to the drain node, a plurality of replica cells, wherein a respective replica cell of the plurality of replica cells comprises a gate finger; wherein the gate finger, the source structure, and the drain structure are arranged to form a transistor structure and a plurality of resistors, wherein each resistor connects one of the gate fingers to the gate bus. Furthermore, a method for manufacturing a semiconductor device is disclosed.

The application discloses an ultra-wideband GaAs amplitude-phase control transceiver front-end chip, which is applied to the field of phased array radars, and aims at the fact that high-low pass type phase shifters adopted in existing transceiver front-end chips are only applicable to low-frequency phase shift units, and are limited by the problem of filter order; the application proposes a novel phase shift structure based on a magnetic coupling all-pass network and an active complementary dual-mode amplification circuit, the structure can realize a great expansion of available frequency on the premise of ensuring phase shift precision, and a 180-degree phase shift network based on an active structure can effectively provide transmission gain, reduce the number of used link amplifiers, further reduce the noise coefficient of a receiving link and assist in improving the power characteristics of a transmitting link. The application of the technology helps to realize good phase shift precision, input and output return loss and lower phase shift error of the chip in an ultra-wideband range of 2-18GHz.

Storage device (100A; 100B; 100C; 100D), comprising: a channel layer (110); a gate structure (154) on a first side of the channel layer (110), wherein the gate structure (154) has a top surface (TS154) facing the channel layer (110); a drain structure (140) on a second side of the channel layer (110) opposite the first side, wherein the drain structure (140) has a first bottom surface (BS140) in contact with the channel layer (110) and the first bottom surface (BS140) overlaps the top surface (TS154) of the gate structure (154) over a first lateral direction (X);and a source structure (142) on the second side of the channel layer (110) and adjacent to the drain structure (140) along the first lateral direction (X), wherein the source structure (142) has a second underside (BS142) facing the channel layer (110), and the second underside (BS142) overlaps the top side (TS154) of the gate structure (154) across the first lateral direction (X); wherein: the drain structure (140) has a first length along a second lateral direction (Y) perpendicular to the first lateral direction (X) in a top view of the storage device (100A; 100B; 100C; 100D); the source structure (142) has a second length along the second lateral direction (Y); and the first length is smaller than the second length.

This application provides a stacked transistor and its fabrication method, a semiconductor device, and an electronic device. The method includes: forming a stacked structure on a substrate; the stacked structure includes a front active layer, a first sacrificial layer, a back active layer, a second sacrificial layer, and a third sacrificial layer stacked sequentially in a first direction; etching the stacked structure to form an active structure; depositing an insulating material on the substrate to form a shallow trench isolation layer; forming a first gate oxide layer on the active structure by thermal oxidation; forming a dummy gate structure; performing a first wafer flip and thinning the substrate to expose the shallow trench isolation layer; forming a back transistor; performing a second wafer flip; forming a front transistor; before or after the first wafer flip, the method further includes: exposing a first surface of the back active structure that is away from the front active structure; performing a thermal oxidation treatment on the first surface to form a second gate oxide layer; the second gate oxide layer and the first gate oxide layer jointly encapsulate the active structure.

Gate-all-around integrated circuit structures having electrostatic discharge (ESD) clamps are described. For example, an integrated circuit structure includes a p channel device having a source structure and a drain structure. An n channel device is vertically stacked with the p channel device, the n channel device having a source structure and a drain structure. The source structure of the n channel device is electrically connected to the source structure of the p channel device. The drain structure of the n channel device is electrically connected to the drain structure of the p channel device.

A switching power supply structure includes a housing, a base and circuit boards, where the housing and the base enclose a cavity for accommodating the circuit boards, and a first heat dissipation channel is formed at an opening of the cavity; the housing consists of a top plate and two side plates, and a plurality of heat dissipation holes, including polygonal holes, are reserved in the housing in an array form, which forms a second heat dissipation channel. The first and second heat dissipation channels are provided, with the heat dissipation holes of the second heat dissipation channel having polygonal structures, which enlarges the heat dissipation area, achieving simple structure and good heat dissipation effect. Furthermore, due to the structural optimization of the housing and the base, the automation degree of product assembly is improved, thus lowering the cost of materials for the entire power supply housing structure.

The present invention relates to a single photon light source capable of generating single photons with a high repetition rate and a high collection efficiency by positioning an emitter in a nanogap of a nano-antenna including a metal nanoparticle and a metal layer, and by controlling Purcell enhancement in the nanogap. The single photon light source of the present invention is easy to manufacture with low manufacturing costs due to its simple structure and has excellent light collection efficiency by emitting single photons vertically upward through an optical antenna structure of a nano-antenna. In addition, single photons may be generated by applying various emitters to a nano-antenna, a high production yield is obtained due to the wide bandwidth, and operation may be possible at room temperature at various wavelengths.

The application provides a trench power device with a back source structure and a preparation method thereof. The preparation method comprises the following steps: forming a P-type body region and an N-type drift region on a surface layer of an N-type substrate; forming a trench, wherein the trench extends from the P-type body region to the N-type substrate; forming a gate dielectric layer on a surface of the trench, and filling a gate layer in the trench; forming an isolation layer, and forming a drain through hole in the isolation layer; performing N-type ion implantation on the drain through hole to form an N-type drain region in the N-type drift region; forming a drain electrode; etching a back surface of the N-type substrate to form a source through hole, wherein the source through hole exposes the P-type body region; and depositing a source electrode on the back surface of the N-type substrate and in the source through hole, wherein the source electrode is connected with the N-type substrate and the P-type body region. The drain electrode and the gate electrode are integrated on the front surface of the device, the trench gate structure is adopted to improve the unit density and the channel control ability, and the source electrode is connected with the P-type body region through the back surface deep groove contact, so that the source contact resistance is effectively reduced, and the heat dissipation capacity is improved.

A semiconductor device includes an active structure on a substrate, the active structure including a silicon germanium pattern and a silicon pattern alternately and repeatedly stacked in a vertical direction perpendicular to an upper surface of the substrate; a semiconductor layer on a sidewall of the active structure facing in a first direction parallel to the upper surface of the substrate, the semiconductor layer being a source / drain region; and a gate structure on a surface of the active structure and the substrate, the gate structure extending in a second direction perpendicular to the first direction, wherein the silicon germanium pattern is silicon-rich silicon germanium.

This application provides a complementary field-effect transistor (CFPT) and its fabrication method, as well as an electronic device. The fabrication method includes: forming a first active structure and a second active structure stacked sequentially on a substrate; depositing a first dummy gate structure and a second dummy gate structure stacked sequentially on the substrate; removing the first active structure and the second active structure located in the source / drain region; forming a bottom source / drain structure based on the second active structure in the gate region, and forming a top source / drain structure above the bottom source / drain structure based on the first active structure in the gate region; removing the first dummy gate structure and depositing a first metal material above the second dummy gate structure to form a top metal gate; flipping the top transistor and removing the substrate to expose the second dummy gate structure; removing the second dummy gate structure and depositing a second metal material above the top metal gate to form a bottom metal gate; the work function value of the top metal gate and the work function value of the bottom metal gate are different.

The present application relates to a kind of flexible audio sensor and the manufacturing method of flexible audio sensor.Flexible audio sensor includes support, first component and second component.Support has opening, first component includes the organic film attached on the support and the first electrode attached on the surface of the organic film towards the support, at least in the region corresponding to the opening, first component is formed with hollow hole array, second component includes the ultra-thin paper film attached on the surface of the organic film away from the support and the second electrode attached on the surface of the ultra-thin paper film towards the organic film, at least in the region corresponding to the opening, second component is formed with micropore array.The technical scheme of the present application, by the dual effect of triboelectricity and electrostatic induction, without additional power supply, simple structure and easy to make, can effectively realize the detection or collection of audio signal under the excitation of external sound, and application scenario is wide.

There is provided a semiconductor memory device. The semiconductor memory device includes a metal pattern including a first line part extending in a first direction and a second line part which is connected to the first line part and extends in a second direction to intersect with the first line part, and a source structure which has a trench. The metal pattern is formed in the trench and the source structure is in contact with a sidewall of the metal pattern.