416 results about "Source structure" patented technology

The invention relates to the technical field of semiconductors, in particular to a source heterojunction contact semiconductor structure and device and a manufacturing method, the semiconductor structure comprises a gate structure, a body region structure, a source structure and a drain structure, and the source structure comprises a polycrystalline silicon source contact layer; the semiconductor structure comprises a body region structure and a polycrystalline silicon source contact layer, the body region structure is surrounded by the gate structure, a source contact region is arranged in the body region structure, the polycrystalline silicon source contact layer is in contact with the source structure through the source contact region so as to form a heterojunction diode with the source structure, and the heterojunction diode is a freewheeling diode of the semiconductor structure. The drain electrode structure is located on one side, back to the gate electrode structure, of the body region structure; the semiconductor structure can be a SiC MOSFET structure, reverse conduction voltage drop during follow current of the SiC MOSFET can be greatly reduced, and conduction loss and loss caused during switching are reduced.

An alternating stack of insulating layers and spacer material layers is formed over a substrate. The spacer material layer is formed as a conductive layer or subsequently replaced by a conductive layer. Memory openings are formed through the alternating stack. A memory material layer, a semiconductor source structure, a vertical semiconductor channel, a dielectric core, and a drain region are formed in the memory opening. The dopant in the semiconductor source structure is activated after the drain region is formed. Subsequently, the substrate and a bottom portion of the memory film are removed, and a metal source layer is formed on the semiconductor source structure.

The semiconductor structure includes a transistor region and a step region, the transistor region includes a word line region, the word line region directly faces and is connected to the step region, and the manufacturing method includes: providing a base and forming sacrificial layers and active layers on the base; forming first isolation layers in the transistor region, wherein the first isolation layers divide a part of the active layers into a plurality of active structures; removing a part of the first isolation layers and a part of the sacrificial layers in the word line region; forming word lines and dielectric layers in the word line region, wherein the step region includes a first region and second regions located on two sides of the first region.

Embodiments of the present disclosure relate to the field of semiconductors, and provide a semiconductor structure and a manufacturing method thereof. The semiconductor structure includes: a base and a bit line that extends along a first direction; active structures, wherein the active structure includes at least two active layers arranged at intervals, the active layer includes a first source-drain region, a channel region, a second source-drain region, and a support region, and the bit line is connected to the first source-drain region; a word line extending along a second direction, wherein the word line is connected to an adjacent active structure, and the word line surrounds at least two channel regions included in the connected active structure; and a memory structure perpendicularly stacked on the base, where the memory structure is connected to the second source-drain region, and the memory structure surrounds the support region.

The application discloses a transistor and a manufacturing method of a semiconductor device, and relates to the technical field of semiconductors, and aims to solve the problem of poor compatibility between a ring-gate transistor and another transistor with a thicker gate dielectric layer and / or gate, and to reduce the integration difficulty of the two transistors. The manufacturing method of the transistor comprises the following steps: providing a semiconductor substrate; forming an active structure and an isolation layer on the semiconductor substrate; the active structure comprises a source region, a drain region, and at least two channel layers located between the source region and the drain region; the at least two channel layers are in contact with the source region and the drain region respectively; the adjacent two channel layers have a first gap; the isolation layer comprises at least a first isolation layer; the first isolation layer at least fills the first gap; the at least two channel layers and the isolation layer form a first fin structure; and a gate stack structure is formed across the first fin structure.

Provided in the present disclosure are a preparation method for a semiconductor device, the semiconductor device and an electronic apparatus. The preparation method for a semiconductor device comprises: forming an active structure on a substrate; forming a first semiconductor structure; bonding the first semiconductor structure and a first carrier wafer and flipping same over; removing the substrate to expose a second active structure; forming a second semiconductor structure; bonding the second semiconductor structure and a second carrier wafer and flipping same over; removing the first carrier wafer to expose the first semiconductor structure; forming a first gate structure in the first semiconductor structure; forming first source-drain metal on a first source-drain structure; forming a first metal interconnect structure on a first transistor; bonding the first metal interconnect structure and a third carrier wafer and flipping same over; removing the second carrier wafer to expose the second semiconductor structure; and forming a second metal interconnect structure.

A semiconductor device includes a first contact plug penetrating a source structure, the first contact plug having a first portion having a first width and a second portion having a second width that is larger than the first width, a stack formed on the source structure and the first contact plug, a second contact plug penetrating the stack, the second contact plug connected to the first contact plug, a first spacer surrounding the first portion and the second portion of the first contact plug, and a second spacer surrounding the first spacer to surround the second portion of the first contact plug.

A light-emitting diode (LED) chip with reflective layers having high reflectivity is disclosed. The LED chip may include an active LED structure including an active layer between an n-type layer and a p-type layer. A first reflective layer is adjacent the active LED structure and comprises a plurality of dielectric layers with varying optical thicknesses. The plurality of dielectric layers may include a plurality of first dielectric layers and a plurality of second dielectric layers of varying thicknesses and compositions. The LED chip may further include a second reflective layer that includes an electrically conductive path through the first reflective layer. An adhesion layer may be provided between the first reflective layer and the second reflective layer. The adhesion layer may comprise a metal oxide that promotes improved adhesion with reduced optical losses.

The invention provides a power semiconductor device and a preparation method of the power semiconductor device. The power semiconductor device comprises a substrate; the epitaxial layer is located on one side of the substrate; the gate structure is at least partially located in the epitaxial layer, and at least partial structure of the gate structure is hemispherical; the Schottky contact region is located in the epitaxial layer and is located between two adjacent gate structures; the source structure is located at one side of the epitaxial layer away from the substrate; the drain structure is located on one side of the substrate away from the epitaxial layer. The reliability of the power semiconductor device can be improved.

This nitride semiconductor device (1) comprises a power FET (11), an ESD protection FET (12), a diode (13), and a resistor element (14). A gate structure (50G) of the power FET (11) includes a p-type semiconductor layer (52G) and a gate electrode (54G) that is Schottky-connected to the p-type semiconductor layer (52G). An anode structure (50A) of the diode (13) includes a p-type semiconductor layer (52A). The gate structure (50G), a drain structure (51D) of the ESD protection FET (12), and the anode structure (50A) are electrically connected to each other. A source structure (50S) of the power FET (11), a source structure (51S) of the ESD protection FET (12), and a terminal structure (50R) of the resistor element (14) are electrically connected to each other. A gate structure (51G) of the ESD protection FET (12), a cathode structure (50K) of the diode (13), and a terminal structure (51R) of the resistor element (14) are electrically connected to each other.

The present disclosure relates to a semiconductor device and a fabricating method thereof, which includes a substrate and a plurality of word lines. The substrate includes a shallow trench isolation and an active structure defined by the shallow trench isolation and the active structure includes a first active area and a second active area. The first active area includes a plurality of active area units being parallel extended along a first direction, and the second active area is disposed outside a periphery of the first active area, to surround all of the active area units. The word lines are disposed in the substrate to intersect the active area units and the shallow trench isolation. The word lines includes first word lines arranged by a first pitch and at least one second word line arranged by a second pitch, and the second pitch is greater than the first pitch.

A multi-channel GaN HEMT structure and a preparation method thereof are provided. The structure comprises a substrate, a multi-channel region, a source, a drain, an ohmic connection unit, a multi-unit layer and a passivation layer. A buffer layer is formed on the substrate; the multi-channel region is formed on the buffer layer and comprises a plurality of groups of stacked heterojunction units; the source is formed on one side of the GaN HEMT structure and is configured as a hybrid source structure comprising a Schottky metal and an ohmic metal; the drain is formed on the other side of the GaN HEMT structure; the ohmic connection unit is made of an ohmic metal and is connected between all the heterojunction units except the lowermost heterojunction unit; the multi-unit layer is formed on the multi-channel region and comprises at least two unit structures in the same plane; wherein a gate metal is prepared on the surface of the first unit structure to form a gate together; the second unit structure is connected with the source to form a bridge-shaped structure; the other unit structures between the second unit structure and the drain are in the form of floating islands; and the passivation layer is formed on the multi-channel region.

The invention provides a semiconductor device. The semiconductor device includes a substrate, a gate structure, a first interlayer dielectric layer, a source structure, a drain structure, a dielectric pattern, a first field plate, and a second field plate. The gate structure is disposed on the substrate. The first interlayer dielectric layer is disposed on the substrate and partially covers the gate structure. The source electrode structure and the drain electrode structure are arranged on the substrate and located on the two sides of the gate electrode structure. The dielectric pattern is disposed on the first interlayer dielectric layer between the gate structure and the drain structure. The first field plate is arranged on the substrate and covers the first interlayer dielectric layer between the gate structure and the dielectric pattern and the dielectric pattern. The second field plate is disposed over the first field plate and the dielectric pattern and extends toward the drain structure.

The invention provides a packaging structure and a manufacturing method thereof. The packaging structure comprises an embedded component circuit structure layer, a signal interconnection structure layer, a power supply structure layer and an electronic component layer. The embedded component circuit structure layer comprises at least one embedded component and is provided with a first surface and a second surface which are opposite to each other. The signal interconnection structure layer is arranged on the first surface of the embedded component circuit structure layer and is electrically connected with the embedded component circuit structure layer. The power supply structure layer is arranged on the signal interconnection structure layer and is electrically connected with the signal interconnection structure layer. The electronic component layer comprises a plurality of electronic components, is configured on the second surface of the embedded component circuit structure layer, and is electrically connected with the embedded component circuit structure layer. The thermal expansion coefficient of the signal interconnection structure layer is higher than the thermal expansion coefficient of the electronic component layer and the thermal expansion coefficient of the power supply structure layer.

A semiconductor device is provided. The semiconductor device includes a first semiconductor structure, a second semiconductor structure on the first semiconductor structure and an active structure between the first semiconductor structure and the second semiconductor structure. The first semiconductor structure includes a first waveguiding layer having a first band gap, and a first interlayer directly contacting the first waveguiding layer and having a first thickness and a second bandgap lager than the first band gap. The first thickness is 5 nm-35 nm.

The present disclosure provides a semiconductor structure and a manufacturing method thereof. The semiconductor structure includes a substrate and a contact structure. The substrate includes a shallow trench isolation (STI) structure and active structures separated by the STI structure. The contact structure includes a first contact structure and a second contact structure that are laminated, where the first contact structure covers a part of a top surface and a part of a side wall of the active structure.

A package structure includes an embedded component circuit structure layer, a signal interconnection structure layer, a power structure layer, and an electronic component layer. The embedded component circuit structure layer includes at least one embedded component and has a first surface and a second surface opposite to each other. The signal interconnection structure layer is disposed on the first surface and is electrically connected to the embedded component circuit structure layer. The power structure layer is disposed on and electrically connected to the signal interconnection structure layer. The electronic component layer includes a plurality of electronic components, is disposed on the second surface, and is electrically connected to the embedded component circuit structure layer. A coefficient of thermal expansion of the signal interconnection structure layer is higher than a coefficient of thermal expansion of the electronic component layer and a coefficient of thermal expansion of the power structure layer.

The application discloses a ring gate transistor and a manufacturing method thereof, and relates to the technical field of semiconductors, which is used for effectively inhibiting the parasitic channel leakage of the ring gate transistor, preventing the band tunneling problem, improving the working performance of the ring gate transistor, and reducing the manufacturing difficulty of the ring gate transistor. The ring gate transistor comprises a semiconductor substrate, an active structure, a heavily doped epitaxial structure, and a gate stack structure. The active structure is formed on the semiconductor substrate. The active structure comprises a source region, a drain region, and a channel region between the source region and the drain region. A first recess is formed in the part of the semiconductor substrate below the channel region and is inwardly recessed. The heavily doped epitaxial structure fills the first recess. The conductive type of the heavily doped epitaxial structure is opposite to the conductive type of the source region and the drain region. The gate stack structure surrounds the outer periphery of the channel region. The part of the gate stack structure below the channel region is formed between the heavily doped epitaxial structure and the channel region.

The present disclosure provides a preparation method for a stacked transistor, a stacked transistor, and a semiconductor device. The preparation method comprises: on a semiconductor substrate, forming a first sacrificial layer, and active structures located on the first sacrificial layer, the active structures comprising a first active structure and a second active structure; depositing an oxide material on the semiconductor substrate to form a shallow trench isolation structure, the shallow trench isolation structure wrapping around the second active structure and the first sacrificial layer, and the first active structure being exposed out of the shallow trench isolation structure; forming a first transistor on the basis of the first active structure; inverting the entire structure and removing the semiconductor substrate, to expose the shallow trench isolation structure and the first sacrificial layer; removing the first sacrificial layer, and forming a hard mask structure at the position of the removed first sacrificial layer; using the hard mask structure as a hard mask, thinning the shallow trench isolation structure, so that the second active structure is exposed out of the shallow trench isolation structure; and, after removing the hard mask structure, forming a second transistor on the basis of the second active structure.

The application discloses an optical mode demultiplexer based on a cascaded silica multimode interferometer structure, and belongs to the technical field of silica integrated optics. The optical mode demultiplexer is composed of a substrate, a lower cladding layer, a core layer and an upper cladding layer from bottom to top, the core layer and the upper cladding layer are located above the lower cladding layer, the core layer is completely covered in the upper cladding layer, the materials of the upper cladding layer and the lower cladding layer are silica, the material of the core layer is germanium-doped silica, and the material of the substrate is silicon. The core layer is composed of three parts in cascade, the first part is two-stage Y-branch waveguides in cascade, the second part is a 4*4 multimode interferometer, and the third part is two straight waveguides and a 2*2 multimode interferometer. The device can output TE0 mode from four different ports when TE0, TE1, TE2 and TE3 modes are input respectively, thereby realizing the mode demultiplexing function. The device adopts a passive structure, and the phase of an optical signal in a waveguide is adjusted through a waveguide phase shifter, so that the mode demultiplexing function is realized.

To provide a method of manufacturing a semiconductor device having a three dimensional stacked structure, and a storage device.SOLUTION: A storage device 1000 includes a substrate 200 including an insulating surface 210 and a plurality of storage cells 100 arranged on the insulating surface, and includes a storage cell array in which the plurality of storage cells are repeatedly arranged along first and second horizontal directions and a vertical direction, and one transistor included in each storage cell includes a gate insulating layer 1112, a gate structure 1113, and an active layer 1111 parallel to the insulating surface. The gate structure includes a gate body portion side 1113A, the gate body portion includes a first gate 11131, the first gate extends along a sidewall of the active layer, the gate insulating layer is located between the first gate and the active layer and includes a common source structure including a common source 110 and a bit line structure 120, the bit line structure includes a plurality of bit lines extending along a first direction, and the active layer includes source terminals 11111 connected to the common source structure and drain terminals 11113 connected to the bit lines.SELECTED DRAWING: Figure 1

The invention discloses an anti-fraud early warning and intercepting system based on a light guide interaction layer, and relates to the field of intelligent terminal safety protection. The system comprises a light guide interaction layer, a coordinate mapping unit, a manager decision terminal and an early warning interception unit, and the light guide interaction layer is of a pure passive optical structure, does not contain electronic elements and comprises an array type light-induced deformation unit and an optical coding storage area; the optical coding storage area is of a pure passive structure and supports one-time storage or reconfigurable updating; the coordinate mapping unit realizes accurate mapping of screen coordinates and array indexes, and the whole process is pure optical logic and does not depend on electronic calculation; an encrypted fraud feature library is arranged in the supervisor decision-making terminal, interface recognition, fraud matching and instruction issuing are achieved, and system authority of the protected terminal and the Internet are not needed; the early warning interception unit drives the array type light-induced deformation unit to complete submillimeter-level accurate clicking, the response time is less than 5 ms, and fraud interception can be completed within 3 seconds. The method solves the problem that the existing fraud prevention technology depends on authority, is networked and is high in interception delay, adapts to fraud groups such as old people, can still realize real-time physical-level interception in an environment without network and authority, is safe in storage, is high in crowd adaptability, and can be widely applied to various terminal devices.

The embodiment of the present disclosure relates to the semiconductor field, and provides a manufacturing method of a semiconductor structure and the semiconductor structure, the manufacturing method comprising: providing a substrate, forming a plurality of active layers and a plurality of sacrificial layers on the substrate, the active layers and the sacrificial layers being arranged alternately; two adjacent active layers constituting an active group; the active layers in the active group having a first interval, adjacent active groups having a second interval, the first interval being greater than the second interval; forming an isolation layer, the isolation layer penetrating all the active layers and all the sacrificial layers, and each active layer being divided into a plurality of active structures; removing the isolation layer and the sacrificial layer in a word line region; forming a first dielectric layer in the word line region, the first dielectric layer covering the surface of the active layer and also being located between the active structures in the same layer and between the active groups; forming a word line in the word line region, the word line being located between the active layers in the active group, and each word line crossing the active structures in the same layer. The embodiment of the present disclosure can at least improve the performance of the semiconductor structure.

In some implementations, a photonic transmission structure includes a first cladding structure; a first active structure disposed over the first cladding structure; and a second cladding structure disposed over the first active structure. The first active structure includes a non-alkali, oxide solution that includes a cation that is niobium.

The application discloses a kind of ultra-low voltage wideband low noise amplifiers, it is related to radio frequency signal transceiver technical field.Solve the high-frequency gain attenuation problem in the design of current low power supply voltage wideband low noise amplifier, including two-stage common-source amplifier connected in turn;The input stage amplifier is composed of input matching network, source sense asymmetric current sharing structure, cascaded matching network;The output stage amplifier is composed of MOS single-layer common-source structure, output matching network.The application improves the conventional source degeneration inductance structure, proposes a kind of source sense asymmetric current sharing structure, on the one hand, gain compensation of high frequency band is realized under the premise of not increasing power consumption, on the other hand, circuit uses peak inductance technology to realize wideband matching, gain compensation and reduce noise.In addition, the circuit uses active substrate noise reduction technology, adds high output impedance gate ground MOS tube to improve substrate resistance, reduce the noise change due to power consumption reduction.

This application relates to integrating a FinFET and a Schottky barrier diode on a substrate. A first fin structure and a second fin structure are formed on the substrate. The first fin structure includes a channel portion extending to two pressure source portions on two opposite sides of the channel portion, and the second fin structure includes a junction portion. The source and drain structures of the FinFET are respectively formed on the two pressure source portions of the first fin structure. A source metal material, a drain metal material, and a first metal material are formed to be electrically coupled to the source structure, the drain structure, and the junction portion of the second fin structure, respectively, thereby providing a Schottky junction between the junction portion of the second fin structure and the first metal material.

Embodiments of the present application provide a chip, a preparation method thereof and an electronic device, and relate to the technical field of semiconductors, and are used to improve the storage density of embedded memories. The chip comprises a plurality of memory cell groups. A memory cell group comprises a first transistor and two memory cells. A memory cell comprises a second transistor and a storage element, and the first transistor and the second transistor each comprise an active structure, and the active structure of the first transistor is located between the active structures of the second transistors of the two memory cells. The active structure comprises a channel region, a first contact region and a second contact region. The first contact region of the first transistor is connected to the first contact region of the second transistor of one memory cell, and the second contact region of the first transistor is connected to the first contact region of the second transistor of the other memory cell; wherein in the same memory cell group, when the memory cells are in a working state, the first transistor is in an off state. The above chip is applied to an electronic device, thereby improving the performance of the electronic device.

A semiconductor device may include a gate structure, a source structure that is disposed on the gate structure, channel structures that extend into the source structure through the gate structure and include a channel layer and a memory layer surrounding the channel layer, the memory layer including a cut area that exposes the channel layer, and a slit structure that extends into the source structure through the gate structure between the channel structures, an upper surface of the slit structure being disposed at a lower level than the cut area.

A device comprises: a substrate having a first side and a second side; a first transistor and a second transistor formed in a first layer on the first side; a third transistor, a fourth transistor, a fifth transistor, and a sixth transistor formed in a second layer on the first side; a first interconnect structure, a second interconnect structure, a third interconnect structure, and a fourth interconnect structure formed on the second side, wherein the first and second interconnect structures are each configured to carry a supply voltage, and the third and fourth interconnect structures are each configured to carry a ground voltage;and a power supply structure extending vertically through the first and second levels and configured to electrically couple a source / drain terminal of the third transistor and a source / drain terminal of the fourth transistor to the third interconnect structure and the fourth interconnect structure, respectively.

The invention provides a preparation method of a memory, the memory and a semiconductor device. The method comprises the steps that a plurality of stacked structures are formed on a substrate, each stacked structure comprises a first active structure and a second active structure which are sequentially stacked in the first direction, the first active structure is far away from the substrate compared with the second active structure, and the first active structure and the second active structure are self-aligned in the first direction; metal materials are deposited on the first active structures and the second active structures respectively, so that front WL structures and back WL structures are formed, and the two adjacent first active structures in the second direction are communicated through the front WL structures; the two adjacent second active structures in the second direction are communicated through the back WL structures; the second direction is perpendicular to the first direction; forming a first memory based on a first active structure connected with the front WL structure; carrying out chip reversing on the first memory and removing the substrate; a second memory is formed based on a second active structure connected to the backside WL structure.