987 results about "Source structure" patented technology

The invention provides a preparation method of a stacked transistor, the stacked transistor and a semiconductor device. The method comprises the steps of performing primary etching on a semiconductor substrate to form a stack structure, wherein the stack structure comprises an active structure and a first sacrificial layer; forming a pseudo gate structure covering the stacked structure in the gate region; etching the stack structure which is not covered by the pseudo gate structure to form a first deep groove; epitaxially growing a first source drain structure in the first deep groove based on the first active structure in the gate region; removing the pseudo gate structure and the first sacrificial layer to expose the active structure in the gate region; depositing a gate dielectric material on the exposed active structure to form a gate dielectric layer; depositing a metal material on the first gate dielectric layer to form a first gate electrode layer; reversing and removing the semiconductor substrate; epitaxially growing a second source drain structure in the first deep groove based on a second active structure in the gate region; and depositing a metal material on the second gate dielectric layer to form a second gate electrode layer.

The invention provides a high-reliability trench gate silicon carbide VDMOS and a preparation method thereof, and the method comprises the steps: depositing metal on the lower side surface of a silicon carbide substrate to form a drain metal layer, and carrying out the epitaxial growth on the upper side surface of the silicon carbide substrate to form a drift layer; a barrier layer is formed on the drift layer, etching and ion implantation are carried out, a first P-type well region, a protruding part, a first low-resistance region, a second low-resistance region and a third low-resistance region are formed, and the low-resistance region comprises the first low-resistance region, the second low-resistance region and the third low-resistance region; a barrier layer is formed again, etching and ion implantation are carried out, and a P-type source region, an N-type source region, a conductive region and a protection region are formed; a barrier layer is formed again, an insulating medium layer is formed through etching and oxidation, and a groove is formed in the insulating medium layer; and forming a barrier layer again, etching, depositing metal, forming a gate metal layer and a source metal layer, and removing the barrier layer to complete preparation. Through optimization design of the gate structure and the source structure, the purpose of improving the reliability of the device is achieved.

The invention provides a preparation method of an inverted stacked transistor, a transistor, a device and equipment, and the method comprises the steps: forming an active structure on a substrate, the active structure is provided with a first part and a second part, and the first part is closer to the substrate than the second part; the active structure in the source-drain region is etched, the first source-drain region is filled with an insulating material to form a filling structure, the source-drain region comprises a first source-drain region and a second source-drain region, the first source-drain region corresponds to the first part, and the second source-drain region corresponds to the second part; forming a first source-drain structure and first source-drain metal of the first transistor based on the second source-drain region; reversing the first transistor and removing the substrate; selectively etching the filling structure through the material so as to expose the first source-drain region; and forming a second source-drain structure and second source-drain metal of the second transistor based on the first source-drain region. Complete self-alignment of the front and back transistors can be realized.

A semiconductor structure includes an alternating stack of insulating layers and electrically conductive layers located on a semiconductor layer, a memory opening vertically extending through the alternating stack and the semiconductor layer, a memory opening fill structure located in the memory opening and containing a memory film and a vertical semiconductor channel, and a backside semiconductor source structure including a doped semiconductor material. The backside semiconductor source structure may be polycrystalline or single crystalline.

The utility model discloses an LED packaging structure and a backlight source, the LED packaging structure comprises an LED chip and a support, the support is provided with a cup cavity, the bottom of the cup cavity is provided with a metal bonding pad, the LED chip is arranged on the metal bonding pad, and the cup cavity is filled with fluorescent glue to cover the LED chip; wherein a cup opening of the cup cavity is covered with a light-emitting adjusting structure layer, and the light-emitting adjusting structure layer is used for adjusting the divergence angle of first emergent light rays of the LED chip, so that the divergence angle of the first emergent light rays is converted into a second angle from a first angle. The backlight source structure can be simplified, and the cost is reduced.

The invention discloses a semiconductor device, a power module, a conversion circuit, a vehicle and a device preparation method, and the semiconductor device comprises a semiconductor body which comprises a substrate, an epitaxial layer, a well region, a first region and a second region, and is provided with a gate trench and a source trench, the gate trench and the source trench extend into the epitaxial layer from the first surface; the second region is arranged on one side, far away from or close to the gate trench, of the source trench; the first region and the epitaxial layer are of a first doping type, and the well region and the second region are of a second doping type; the gate structure is located in the gate trench; the source electrode structure is located in the source electrode groove; the drain is located on one side, away from the epitaxial layer, of the substrate. According to the semiconductor device provided by the invention, the reverse conduction voltage drop of the semiconductor device is reduced, the discharge speed during reverse connection of the semiconductor device is improved, and the performance stability and safety of the semiconductor device are improved.

The invention provides a preparation method of a stacked transistor, the stacked transistor and a semiconductor device. The method comprises the following steps: removing the second pseudo gate structure to expose the second active structure and the gate isolation layer; coating photoresist on the second active structure and the gate isolation layer in the first semiconductor unit, and at least removing the gate isolation layer in the second semiconductor unit through a photoetching process; sequentially removing the first pseudo gate structure and the photoresist to expose the first active structure, the gate isolation layer and the second active structure in the first semiconductor unit and the first active structure and the second active structure in the second semiconductor unit; and forming a first gate structure and a second gate structure based on the first active structure, the gate isolation layer and the second active structure in the first semiconductor unit, and simultaneously forming a third gate structure and a fourth gate structure based on the first active structure and the second active structure in the second semiconductor unit.

The invention relates to the technical field of semiconductors, in particular to a source heterojunction contact semiconductor structure and device and a manufacturing method, the semiconductor structure comprises a gate structure, a body region structure, a source structure and a drain structure, and the source structure comprises a polycrystalline silicon source contact layer; the semiconductor structure comprises a body region structure and a polycrystalline silicon source contact layer, the body region structure is surrounded by the gate structure, a source contact region is arranged in the body region structure, the polycrystalline silicon source contact layer is in contact with the source structure through the source contact region so as to form a heterojunction diode with the source structure, and the heterojunction diode is a freewheeling diode of the semiconductor structure. The drain electrode structure is located on one side, back to the gate electrode structure, of the body region structure; the semiconductor structure can be a SiC MOSFET structure, reverse conduction voltage drop during follow current of the SiC MOSFET can be greatly reduced, and conduction loss and loss caused during switching are reduced.

The invention provides a preparation method of a stacked transistor, the stacked transistor and a semiconductor device. The method comprises the steps that an active structure is formed on a semiconductor substrate, the active structure comprises a first part and a second part, and the second part is close to the semiconductor substrate relative to the first part; based on the first part, forming a front vertical stacked transistor, the front vertical stacked transistor comprising: a first transistor and a second transistor, the first transistor and the second transistor having different polarities, the first transistor and the second transistor being self-aligned in a first direction, the first direction being a direction perpendicular to the semiconductor substrate; reversing and removing the semiconductor substrate; on the basis of the second part, a reverse side vertical stacking transistor is formed, the reverse side vertical stacking transistor comprises a third transistor and a fourth transistor, the polarities of the third transistor and the fourth transistor are different, and the third transistor and the fourth transistor are self-aligned in the first direction.

The invention discloses a millimeter wave broadband high-gain low-noise amplifier based on a CMOS (Complementary Metal Oxide Semiconductor) process. The millimeter wave broadband high-gain low-noise amplifier comprises an input broadband balun transformer network, a first-stage gain circuit, a symmetric MCR interstage matching network, a second-stage linearization circuit and an output broadband transformer network, the first-stage gain circuit provides large gain for the whole amplifier and inhibits noise by using a differential common-source structure, and a source degeneration inductor uses an 8-shaped drawing scheme to reduce parasitic parameters; a derivative overlapping technology is used in a second-stage linearization circuit, so that the signal linearity is improved, and the signal is gained to a certain extent; the input broadband balun transformer network, the symmetric MCR inter-stage matching network and the output broadband transformer network all use an MCR broadband impedance matching method to carry out matching network design, so that the broadband characteristic of the circuit is ensured; the antenna can normally work in a temperature range from low temperature (-40 DEG C) to high temperature (125 DEG C), and achieves high gain and broadband characteristics in a working frequency band.

The invention provides a preparation method of a stacked transistor, the stacked transistor and a semiconductor device. The method comprises the steps of performing primary etching on a semiconductor substrate to form a stack structure, wherein the stack structure comprises a first active structure and a second active structure; forming an oxide layer covering the stacked structure on the semiconductor substrate; forming a pseudo gate structure covering the oxide layer; the pseudo gate structure comprises a first pseudo gate structure and a second pseudo gate structure; forming a first transistor based on the first active structure covered with the oxide layer; reversing and removing the semiconductor substrate; forming a second transistor based on the second active structure covered with the oxide layer; performing oxidation treatment on the first part of the first pseudo gate structure so as to form a first gate isolation structure between the first gate structure and the second gate structure; and / or performing oxidation treatment on the first part of the second pseudo gate structure so as to form a second gate isolation structure between the first gate structure and the second gate structure.

This semiconductor device includes: a chip that has a main face; a first conductivity-type semiconductor region that is formed in a surface layer portion of the main face; a trench-type source structure that is formed on the main face and is located in the semiconductor region; and a second conductivity-type impurity region that is formed in a region directly below the source structure in the chip and that forms a pn junction portion with the semiconductor region.

The invention discloses a photon antenna working at 275-296 GHz, and belongs to the field of photoelectron and terahertz communication. The UTC-PD comprises two UTC-PD bodies and a passive structure. The UTC-PD body adopts a double-mesa structure, each structure leads out an electrode by electroplating a small bonding pad, a metal bump is processed on the small bonding pad, and the UTC-PD body is electrically connected with a passive structure through flip-chip bonding. The passive structure comprises an impedance matching circuit, a power combiner circuit and a vivaldi antenna; the UTC-PD body generates a signal, and a built-in electric field is introduced by using the gradient doped absorption layer; a cliff layer is arranged between the absorbing layer and the collecting layer; and then, after the signal passes through an impedance matching circuit, the output impedance is close to 50 ohms, two combined output signals are superposed to the feed end of the Vivaldi antenna through a power combiner, and finally, the two combined output signals are converted into high-frequency electromagnetic waves with the frequency band of 275-296 GHz for radiation. Electromagnetic waves within the terahertz frequency range are generated and emitted, and the technical performance of high bandwidth, high gain and low insertion loss is achieved.

A semiconductor package may include a first redistribution layer, a passive device disposed on a top surface of the first redistribution layer, a bridge structure disposed on the top surface of the first redistribution layer and laterally spaced apart from the passive device, a second redistribution layer disposed on and electrically connected to the passive device and the bridge structure, conductive structures disposed between the first redistribution layer and the second redistribution layer and laterally spaced apart from the passive device and the bridge structure, a first semiconductor chip mounted on a top surface of the second redistribution layer, and a second semiconductor chip mounted on the top surface of the second redistribution layer. The conductive structures may include a signal structure and a ground / power structure, which is laterally spaced apart from the signal structure and has a width larger than the signal structure.

A transistor includes a first channel layer over a second channel layer, an epitaxial source structure coupled to a first end of the first and second channel layers and an epitaxial drain structure coupled to a second end of the first and second channel layers. The transistor includes a gate between the epitaxial source structure and the epitaxial drain structure, where the gate is above the first channel layer and between the first channel layer and the second channel layer. The transistor includes a first spacer of a first material, between the first and second channel layers includes. The first spacer has at least one convex sidewall that is between the gate and the epitaxial source structure and between the gate and the epitaxial drain structure. The transistor also includes a second spacer of a second material having substantially vertical sidewalls above the first channel layer.

Fabrication methods and structures for forming integrated circuit (IC) porous semiconductor (π-Semi) isolation structures such as shallow trench isolation (STI) and / or deep trench isolation (DTI) structures. The methods speed up IC front-end-of-line processing and decrease the cost of IC fabrication. In general, exposed portions of a semiconductor layer are subjected to an electrochemical etching to form π-Semi isolation structures; in essence, the in situ semiconductor is restructured to π-Semi. The characteristics of π-Semi, particularly mesoporous π-Semi and microporous π-Semi, include good electrical insulation as well as hole trapping capability. Accordingly, π-Semi used for STI and / or DTI structures provides excellent electrical isolation. A first embodiment comprises a “pre-FET”π-Semi isolation structure, fabricated before formation of gate, drain, and source structures or regions of a field-effect transistor (FET). A second embodiment comprises a “post-FET”π-Semi isolation structure, fabricated after formation of gate, drain, and source structures or regions of a FET.

The invention provides a preparation method of a semiconductor structure, the semiconductor structure, a device and equipment, the semiconductor structure comprises a first semiconductor structure and a second semiconductor structure which are stacked in a first direction, the first semiconductor structure is a complementary metal oxide semiconductor (CMOS), and the second semiconductor structure is a CMOS image sensor; the method comprises the following steps: forming an active structure on a substrate; the active structure comprises a first active structure and a second active structure; forming a first semiconductor structure based on the first active structure; the first semiconductor structure comprises a first transistor with a first polarity and a second transistor with a second polarity; reversing and thinning the substrate until the second active structure is exposed; forming a second semiconductor structure based on the second active structure; the second semiconductor structure comprises a third transistor of the first polarity and an image sensor unit; the third transistor and the image sensor unit are arranged side by side in the second direction.

The invention provides a memory preparation method, a memory, a device and equipment, and the method comprises the steps: forming a first semiconductor structure and a first active structure which are sequentially stacked on a substrate, and enabling the doping concentration of the first semiconductor structure to be the same as the doping concentration of a second active structure; ion implantation is carried out in the area, close to the first active structure, of the first semiconductor structure to form a BL structure located between the first semiconductor structure and the first active structure, and the first semiconductor structure, the BL structure and the first active structure are self-aligned in the BL area; forming a first memory based on the first active structure; reversing the first memory and removing the substrate to expose the first semiconductor structure; etching the first semiconductor structure in the BL region to form a second active structure; and forming a second memory based on the second active structure, the first source drain structure of the first memory and the second source drain structure of the second memory sharing the BL structure. The integration level of the memory can be improved.

The invention discloses a gate-all-around transistor and a manufacturing method thereof, relates to the technical field of semiconductors, and is used for controlling electric leakage between a parasitic channel and a source / drain region and improving the electrical performance of the gate-all-around transistor. The ring gate transistor comprises a semiconductor substrate, an active structure, a gate stack structure and a dielectric isolation structure. The active structure is disposed on the semiconductor substrate. The active structure comprises source / drain regions and a channel region located between the source / drain regions. The channel region includes at least one layer of nanostructure disposed over the semiconductor substrate. And the gate stack structure surrounds the periphery of each layer of nano structure. The dielectric isolation structure is arranged between the source / drain region and the semiconductor substrate, and the dielectric isolation structure extends to the part between the gate stack structure and the semiconductor substrate along the distribution direction of the source / drain region. The manufacturing method of the gate-all-around transistor is used for manufacturing the gate-all-around transistor.

Solid-state lighting devices including light-emitting diodes (LEDs) and more particularly current injection structures for LED chips are disclosed. Current injection structures include integrated layers or materials with high work functions as part of contact structures for epitaxial layers of active LED structures. Exemplary structures provide high work function contact layers for p-type epitaxial layers to enhance hole mobility and transport. Further contact structures include combinations of high work function layers with other current spreading layers. Exemplary materials for high work function layers include transition metal oxides.

A microelectronic device may include a source structure and a stack structure. The stack structure may include a vertically alternating sequence of insulative structures and conductive structures. Filled slits may extend through the stack structure and into the source structure, the slits dividing the stack structure into multiple blocks. Memory cell pillars may extend through the stack structure and into the source structure, the memory cell pillars and the filled slits terminated at substantially the same depth within the source structure as one another.

A semiconductor device includes a first substrate, a second substrate bonded to the first substrate, and at least one thermally conductive structure that extends through a portion of the first substrate and a portion of the second substrate and is vertically aligned with an active region of the first substrate. The at least one thermally conductive structure is electrically insulated from electrically active structures in the semiconductor device. The thermally conductive structure acts as a heat sink to transfer heat from the active region.

A semiconductor structure is disclosed, the semiconductor structure comprising: an alternating stack of insulating layers and conductive layers, the alternating stack on a semiconductor layer; a memory opening extending vertically through the alternating stack of layers and the semiconductor layer; a memory opening filling structure in the memory opening and including a memory film and a vertical semiconductor channel; and a backside semiconductor source structure, the backside semiconductor source structure comprising a doped semiconductor material. The backside semiconductor source structure may be polycrystalline or single crystal.

A transistor and a manufacturing method. The transistor includes a semiconductor base substrate, an active structure, a dielectric structure, and a gate stack structure. The active structure is formed on the semiconductor base substrate. The active structure includes a source region, a drain region, and a channel region located between the source region and the drain region. The channel region includes at least two nanostructures stacked in a thickness direction of the semiconductor base substrate. In the channel region, a bottom nanostructure has a greater width than other nanostructures. The dielectric structure is formed between the semiconductor base substrate and the active structure. The dielectric structure is in contact with the bottom nanostructure. The gate stack structure is formed on a surface of the bottom nanostructure not in contact with the dielectric structure, and the gate stack surrounds a periphery of the other nanostructures.

The invention discloses a semiconductor structure and a preparation method thereof. The preparation method of the semiconductor structure comprises the following steps: forming a laminated structure on a substrate; a first isolation structure, a sacrificial structure and a filling layer are formed in the laminated structure, the first semiconductor layer is patterned to form initial active patterns arranged in an array, the first isolation structure comprises a first isolation part and a second isolation part, and the size of the first isolation part in the second direction is larger than that of the second isolation part in the second direction; the adjacent first isolation parts in the second direction are in contact; removing part of the filling layer and forming an initial word line layer; removing the sacrificial structure to respectively form a bit line slot and a capacitance slot, patterning the initial active pattern as an active structure, and patterning the initial word line layer as a word line structure; bit line structures and capacitor structures are formed in the bit line grooves and the capacitor grooves respectively, and the bit line structures and the capacitor structures are alternately arranged in the first direction and the second direction. According to the preparation method of the semiconductor structure, the manufacturing process difficulty of the word line structure is simplified.

The present invention provides a multi-layer doping source structure, and a high-quality emitter and a controllable preparation method therefor. The multi-layer doping source structure comprises a dielectric layer, a nitrogen silicide layer and a doping source layer, which are stacked on the front surface of a crystalline silicon substrate, wherein the dielectric layer is a silicon oxide film or a silicon oxynitride film, the doping source layer is boron-doped amorphous silicon doped with functional elements or phosphorus-doped amorphous silicon doped with functional elements, and the functional elements doped in the doping source layer are carbon and / or nitrogen. In the present invention, the doping source structure is composed of the dielectric layer, a nitrogen silicide and boron- / phosphorus-doped amorphous silicon doped with functional elements; the multi-layer doping source structure has both a strong laser absorption capability and a high boron or phosphorus doping concentration, thereby facilitating a reduction in the laser power and the illumination time required by a laser selective emitter technique; moreover, such a multi-layer doping source structure is favorable for reducing the surface boron concentration, decreasing defects and improving the passivation effect of an emitter, and therefore an improvement in battery efficiency can be promoted.

The invention belongs to the technical field of power semiconductors, and relates to a 1200V SiC trench-type MOSFET (Metal-Oxide-Semiconductor Field Effect Transistor) integrated with a super junction and shield gate technology, which comprises an N + substrate layer, a drift region positioned above the N + substrate layer, and a trench gate structure and a source structure positioned above the drift region, compared with a conventional SiC trench type MOSFET with a P-type shielding layer, the SiC trench type MOSFET with the P-type shielding layer has the advantages that the peak electric field of the gate oxide layer is reduced, and the reliability of the device is ensured; the drift region adopts a super-junction structure, so that the electric field distribution is optimized, the blocking capability of the device is improved, the high doping concentration of the drift region can be adopted while the high breakdown voltage is maintained, the specific on-resistance of the device is remarkably reduced, and the conduction loss of the device is reduced; a shield gate structure is adopted, and the overlapping area of the gate and the drain is reduced, so that the gate-drain capacitance and the gate-drain charge are reduced, the switching speed of the device is improved, and the dynamic loss of the device is reduced. The performance is excellent in the high-voltage and high-frequency field.

An antifuse-type one time programming memory includes a first memory cell. The first memory cell includes an antifuse transistor. The antifuse transistor includes a first nanowire, a first gate structure, a first drain / source structure and a second drain / source structure. The first nanowire is surrounded by the first gate structure. The first gate structure includes a first spacer, a second spacer, a first gate dielectric layer and a first gate layer. The first drain / source structure is electrically contacted with the first terminal of the first nanowire. The second drain / source structure is electrically contacted with the second terminal of the first nanowire.

An alternating stack of insulating layers and spacer material layers is formed over a substrate. The spacer material layer is formed as a conductive layer or subsequently replaced by a conductive layer. Memory openings are formed through the alternating stack. A memory material layer, a semiconductor source structure, a vertical semiconductor channel, a dielectric core, and a drain region are formed in the memory opening. The dopant in the semiconductor source structure is activated after the drain region is formed. Subsequently, the substrate and a bottom portion of the memory film are removed, and a metal source layer is formed on the semiconductor source structure.

The invention discloses a gate-all-around transistor and a manufacturing method thereof, relates to the technical field of semiconductors, and aims to suppress parasitic channel electric leakage and improve the working performance of the gate-all-around transistor. The ring gate transistor comprises a semiconductor substrate, an active structure, a gate stack structure, an inner side wall and a dielectric isolation structure. The active structure is disposed on the semiconductor substrate. The active structure comprises a source region, a drain region and a channel region located between the source region and the drain region, and the two ends, in the length direction, of the channel region make contact with the source region and the drain region respectively. The gate stack structure surrounds the periphery of the channel region. The inner side walls are arranged between the gate stack structure and the source region and between the gate stack structure and the drain region. And the dielectric isolation structure is arranged below the active structure and is used for isolating the semiconductor substrate from the source region, the drain region and part of the gate stack structure. At least the part, located below the channel region, in the dielectric isolation structure is integrally continuous with the inner side wall located at the bottom layer. The manufacturing method of the gate-all-around transistor is used for manufacturing the gate-all-around transistor.