578 results about "Source structure" patented technology

The utility model discloses an LED packaging structure and a backlight source, the LED packaging structure comprises an LED chip and a support, the support is provided with a cup cavity, the bottom of the cup cavity is provided with a metal bonding pad, the LED chip is arranged on the metal bonding pad, and the cup cavity is filled with fluorescent glue to cover the LED chip; wherein a cup opening of the cup cavity is covered with a light-emitting adjusting structure layer, and the light-emitting adjusting structure layer is used for adjusting the divergence angle of first emergent light rays of the LED chip, so that the divergence angle of the first emergent light rays is converted into a second angle from a first angle. The backlight source structure can be simplified, and the cost is reduced.

The invention relates to the technical field of semiconductors, in particular to a source heterojunction contact semiconductor structure and device and a manufacturing method, the semiconductor structure comprises a gate structure, a body region structure, a source structure and a drain structure, and the source structure comprises a polycrystalline silicon source contact layer; the semiconductor structure comprises a body region structure and a polycrystalline silicon source contact layer, the body region structure is surrounded by the gate structure, a source contact region is arranged in the body region structure, the polycrystalline silicon source contact layer is in contact with the source structure through the source contact region so as to form a heterojunction diode with the source structure, and the heterojunction diode is a freewheeling diode of the semiconductor structure. The drain electrode structure is located on one side, back to the gate electrode structure, of the body region structure; the semiconductor structure can be a SiC MOSFET structure, reverse conduction voltage drop during follow current of the SiC MOSFET can be greatly reduced, and conduction loss and loss caused during switching are reduced.

A semiconductor structure is disclosed, the semiconductor structure comprising: an alternating stack of insulating layers and conductive layers, the alternating stack on a semiconductor layer; a memory opening extending vertically through the alternating stack of layers and the semiconductor layer; a memory opening filling structure in the memory opening and including a memory film and a vertical semiconductor channel; and a backside semiconductor source structure, the backside semiconductor source structure comprising a doped semiconductor material. The backside semiconductor source structure may be polycrystalline or single crystal.

The present invention provides a multi-layer doping source structure, and a high-quality emitter and a controllable preparation method therefor. The multi-layer doping source structure comprises a dielectric layer, a nitrogen silicide layer and a doping source layer, which are stacked on the front surface of a crystalline silicon substrate, wherein the dielectric layer is a silicon oxide film or a silicon oxynitride film, the doping source layer is boron-doped amorphous silicon doped with functional elements or phosphorus-doped amorphous silicon doped with functional elements, and the functional elements doped in the doping source layer are carbon and / or nitrogen. In the present invention, the doping source structure is composed of the dielectric layer, a nitrogen silicide and boron- / phosphorus-doped amorphous silicon doped with functional elements; the multi-layer doping source structure has both a strong laser absorption capability and a high boron or phosphorus doping concentration, thereby facilitating a reduction in the laser power and the illumination time required by a laser selective emitter technique; moreover, such a multi-layer doping source structure is favorable for reducing the surface boron concentration, decreasing defects and improving the passivation effect of an emitter, and therefore an improvement in battery efficiency can be promoted.

The invention belongs to the technical field of power semiconductors, and relates to a 1200V SiC trench-type MOSFET (Metal-Oxide-Semiconductor Field Effect Transistor) integrated with a super junction and shield gate technology, which comprises an N + substrate layer, a drift region positioned above the N + substrate layer, and a trench gate structure and a source structure positioned above the drift region, compared with a conventional SiC trench type MOSFET with a P-type shielding layer, the SiC trench type MOSFET with the P-type shielding layer has the advantages that the peak electric field of the gate oxide layer is reduced, and the reliability of the device is ensured; the drift region adopts a super-junction structure, so that the electric field distribution is optimized, the blocking capability of the device is improved, the high doping concentration of the drift region can be adopted while the high breakdown voltage is maintained, the specific on-resistance of the device is remarkably reduced, and the conduction loss of the device is reduced; a shield gate structure is adopted, and the overlapping area of the gate and the drain is reduced, so that the gate-drain capacitance and the gate-drain charge are reduced, the switching speed of the device is improved, and the dynamic loss of the device is reduced. The performance is excellent in the high-voltage and high-frequency field.

An alternating stack of insulating layers and spacer material layers is formed over a substrate. The spacer material layer is formed as a conductive layer or subsequently replaced by a conductive layer. Memory openings are formed through the alternating stack. A memory material layer, a semiconductor source structure, a vertical semiconductor channel, a dielectric core, and a drain region are formed in the memory opening. The dopant in the semiconductor source structure is activated after the drain region is formed. Subsequently, the substrate and a bottom portion of the memory film are removed, and a metal source layer is formed on the semiconductor source structure.

A memory device includes a semiconductor source line layer containing silicon and electrical dopants, an alternating stack of insulating layers and electrically conductive layers located over the semiconductor source line layer, a memory opening vertically extending through the alternating stack, and a memory opening fill structure located in the memory opening. The memory opening fill structure includes a memory film, a vertical semiconductor channel including silicon that is laterally surrounded by the memory film, and a silicon-germanium structure contacting an end portion of the vertical semiconductor channel and contacting the semiconductor source line.

The semiconductor structure includes a transistor region and a step region, the transistor region includes a word line region, the word line region directly faces and is connected to the step region, and the manufacturing method includes: providing a base and forming sacrificial layers and active layers on the base; forming first isolation layers in the transistor region, wherein the first isolation layers divide a part of the active layers into a plurality of active structures; removing a part of the first isolation layers and a part of the sacrificial layers in the word line region; forming word lines and dielectric layers in the word line region, wherein the step region includes a first region and second regions located on two sides of the first region.

An antifuse-type one time programming memory includes a first memory cell. The first memory cell includes at least one antifuse transistor. The antifuse transistor is forksheet transistor. The antifuse transistor includes a first nanowire, a first gate structure, a first drain / source structure and a second drain / source structure. A first-portion surface of the first nanowire is contacted with the isolation wall. A second-portion surface of the first nanowire is contacted with the first gate structure. The first gate structure includes a first spacer, a second spacer, a first gate dielectric layer and a first gate layer. The first drain / source structure is electrically contacted with a first terminal of the first nanowire. The second drain / source structure is electrically contacted with a second terminal of the first nanowire.

The invention discloses a semiconductor structure manufacturing method, a semiconductor structure, an electronic device and electronic equipment, and aims to solve the technical problem that the resistance between a channel layer and a source electrode structure and the resistance between the channel layer and a drain electrode structure are relatively large. When the first groove is formed, the thickness of the channel layer corresponding to the gap is reduced, and when the second groove is formed, the part of the channel layer corresponding to the gap is removed, that is, the part of the channel layer with the smaller thickness is removed, so that the contact area between the channel layer and the electrode structure is increased, and the resistance between the channel layer and the electrode structure is reduced.

The present invention relates to the technical field of semiconductors, and provides a semiconductor device and a manufacturing method for the semiconductor device. The semiconductor device comprises an epitaxial layer, a P-type ion implantation layer, an N-type ion implantation layer, a gate structure and a source structure. The manufacturing method comprises: forming the P-type ion implantation layer in the epitaxial layer; partially etching the P-type ion implantation layer to form a trench, a side wall area of the trench forming a cap layer structure; and then forming the N-type ion implantation layer in the P-type ion implantation layer, the N-type ion implantation layer being configured to be buried in the trench and to extend to the cap layer structure. Compared with the prior art, the present invention configures a first channel as a longitudinal conductive channel, so as to use the characteristic of high mobility of the longitudinal channel to increase turn-on current density in the case of a fixed size of unit cells, thereby achieving the purpose of improving performance. In addition, there is no need to use a trench type buried gate structure, achieving a simple process and being compatible with existing planar gate processes.

Embodiments of the present disclosure relate to the field of semiconductors, and provide a semiconductor structure and a manufacturing method thereof. The semiconductor structure includes: a base and a bit line that extends along a first direction; active structures, wherein the active structure includes at least two active layers arranged at intervals, the active layer includes a first source-drain region, a channel region, a second source-drain region, and a support region, and the bit line is connected to the first source-drain region; a word line extending along a second direction, wherein the word line is connected to an adjacent active structure, and the word line surrounds at least two channel regions included in the connected active structure; and a memory structure perpendicularly stacked on the base, where the memory structure is connected to the second source-drain region, and the memory structure surrounds the support region.

The application discloses a transistor and a manufacturing method of a semiconductor device, and relates to the technical field of semiconductors, and aims to solve the problem of poor compatibility between a ring-gate transistor and another transistor with a thicker gate dielectric layer and / or gate, and to reduce the integration difficulty of the two transistors. The manufacturing method of the transistor comprises the following steps: providing a semiconductor substrate; forming an active structure and an isolation layer on the semiconductor substrate; the active structure comprises a source region, a drain region, and at least two channel layers located between the source region and the drain region; the at least two channel layers are in contact with the source region and the drain region respectively; the adjacent two channel layers have a first gap; the isolation layer comprises at least a first isolation layer; the first isolation layer at least fills the first gap; the at least two channel layers and the isolation layer form a first fin structure; and a gate stack structure is formed across the first fin structure.

The present application relates to integrated assemblies and methods of forming the same. Some embodiments include an integrated assembly having a first memory region, a second memory region offset from the first memory region, and an intermediate region between the first and second memory regions. Channel material pillars are arranged in the first and second memory regions. Conductive pillars are arranged in the intermediate region. A panel extends across the first memory region, the intermediate region, and the second memory region. The panel is between a first memory block region and a second memory block region. Doped semiconductor material is within the first memory region, the second memory region, and the intermediate region and is adjacent to the panel. The doped semiconductor material is at least part of a conductive source structure within the first and second memory regions. An insulating ring surrounds a lower region of the conductive pillars and between the conductive pillars and the doped semiconductor material. Some embodiments include methods of forming the integrated assembly.

The invention discloses a semiconductor device and a manufacturing method thereof, relates to the technical field of semiconductors, and is used for increasing the contact area between a first contact structure and a source region and / or a drain region, reducing contact resistance, improving contact performance, enabling the semiconductor device to have high switching rate and reliability and reducing power consumption. The semiconductor device comprises a semiconductor substrate, an active structure, a gate stack structure and a first contact structure. The active structure is disposed on the semiconductor substrate. The active structure comprises a source region, a drain region and a channel region located between the source region and the drain region. And a first gap is formed between the source region and / or the drain region and the semiconductor substrate. The gate stack structure is arranged on the semiconductor substrate and located on the periphery of the channel region. The first contact structure is arranged on the semiconductor substrate and surrounds the periphery of the source region and / or the drain region through the first gap. The manufacturing method of the semiconductor device is used for manufacturing the semiconductor device.

Provided in the present disclosure are a preparation method for a semiconductor device, the semiconductor device and an electronic apparatus. The preparation method for a semiconductor device comprises: forming an active structure on a substrate; forming a first semiconductor structure; bonding the first semiconductor structure and a first carrier wafer and flipping same over; removing the substrate to expose a second active structure; forming a second semiconductor structure; bonding the second semiconductor structure and a second carrier wafer and flipping same over; removing the first carrier wafer to expose the first semiconductor structure; forming a first gate structure in the first semiconductor structure; forming first source-drain metal on a first source-drain structure; forming a first metal interconnect structure on a first transistor; bonding the first metal interconnect structure and a third carrier wafer and flipping same over; removing the second carrier wafer to expose the second semiconductor structure; and forming a second metal interconnect structure.

A semiconductor device includes a first contact plug penetrating a source structure, the first contact plug having a first portion having a first width and a second portion having a second width that is larger than the first width, a stack formed on the source structure and the first contact plug, a second contact plug penetrating the stack, the second contact plug connected to the first contact plug, a first spacer surrounding the first portion and the second portion of the first contact plug, and a second spacer surrounding the first spacer to surround the second portion of the first contact plug.

A light-emitting diode (LED) chip with reflective layers having high reflectivity is disclosed. The LED chip may include an active LED structure including an active layer between an n-type layer and a p-type layer. A first reflective layer is adjacent the active LED structure and comprises a plurality of dielectric layers with varying optical thicknesses. The plurality of dielectric layers may include a plurality of first dielectric layers and a plurality of second dielectric layers of varying thicknesses and compositions. The LED chip may further include a second reflective layer that includes an electrically conductive path through the first reflective layer. An adhesion layer may be provided between the first reflective layer and the second reflective layer. The adhesion layer may comprise a metal oxide that promotes improved adhesion with reduced optical losses.

The present invention relates to a radiation-resistant bandgap reference circuit, comprising a bandgap reference structure circuit for generating a reference voltage and a compensation current generating circuit for current compensation of transistors within the bandgap reference structure circuit. By performing current compensation on the transistors within the bandgap reference structure, the present invention reduces the impact of radiation effects on the transistor's current gain. While achieving radiation resistance, the present invention eliminates the need for high bias currents, effectively reducing system power consumption.

The invention provides a power semiconductor device and a preparation method of the power semiconductor device. The power semiconductor device comprises a substrate; the epitaxial layer is located on one side of the substrate; the gate structure is at least partially located in the epitaxial layer, and at least partial structure of the gate structure is hemispherical; the Schottky contact region is located in the epitaxial layer and is located between two adjacent gate structures; the source structure is located at one side of the epitaxial layer away from the substrate; the drain structure is located on one side of the substrate away from the epitaxial layer. The reliability of the power semiconductor device can be improved.

This nitride semiconductor device (1) comprises a power FET (11), an ESD protection FET (12), a diode (13), and a resistor element (14). A gate structure (50G) of the power FET (11) includes a p-type semiconductor layer (52G) and a gate electrode (54G) that is Schottky-connected to the p-type semiconductor layer (52G). An anode structure (50A) of the diode (13) includes a p-type semiconductor layer (52A). The gate structure (50G), a drain structure (51D) of the ESD protection FET (12), and the anode structure (50A) are electrically connected to each other. A source structure (50S) of the power FET (11), a source structure (51S) of the ESD protection FET (12), and a terminal structure (50R) of the resistor element (14) are electrically connected to each other. A gate structure (51G) of the ESD protection FET (12), a cathode structure (50K) of the diode (13), and a terminal structure (51R) of the resistor element (14) are electrically connected to each other.

The present invention provides a semiconductor device comprising: at least one transistor, a shallow well region, a guard ring, and a plurality of first doped regions and a plurality of second doped regions. The at least one transistor is located on a substrate, and the at least one transistor comprises a source structure, a gate structure, and a drain structure. The shallow well region surrounds the at least one transistor. The shallow well region has a first conductivity type. The guard ring surrounds the shallow well region. The guard ring has a first conductivity type. The first doped region and the second doped region are arranged within the guard ring and surround the shallow well region. The first doped region and the second doped region are alternately arranged to form a ring. Each of the first doped regions and each of the second doped regions have opposite conductivity types.

The present disclosure relates to a semiconductor device and a fabricating method thereof, which includes a substrate and a plurality of word lines. The substrate includes a shallow trench isolation and an active structure defined by the shallow trench isolation and the active structure includes a first active area and a second active area. The first active area includes a plurality of active area units being parallel extended along a first direction, and the second active area is disposed outside a periphery of the first active area, to surround all of the active area units. The word lines are disposed in the substrate to intersect the active area units and the shallow trench isolation. The word lines includes first word lines arranged by a first pitch and at least one second word line arranged by a second pitch, and the second pitch is greater than the first pitch.

A memory cell includes first through fifth gate structures that each extend along a first lateral direction, a first active structure extending along a second lateral direction and overlaid by respective first portions of the first to fourth gate structures, a second active structure extending along the second lateral direction and overlaid by respective second portions of the first to fourth gate structures, and a third active structure extending along the second lateral direction and overlaid by respective third portions of the third and fifth gate structures. In some embodiments, the first and second gate structures are aligned with each other, with the fourth and fifth gate structures aligned with a first segment and a second segment of the third gate structure, respectively. In some embodiments, the second lateral direction perpendicular to the first lateral direction.

A multi-channel GaN HEMT structure and a preparation method thereof are provided. The structure comprises a substrate, a multi-channel region, a source, a drain, an ohmic connection unit, a multi-unit layer and a passivation layer. A buffer layer is formed on the substrate; the multi-channel region is formed on the buffer layer and comprises a plurality of groups of stacked heterojunction units; the source is formed on one side of the GaN HEMT structure and is configured as a hybrid source structure comprising a Schottky metal and an ohmic metal; the drain is formed on the other side of the GaN HEMT structure; the ohmic connection unit is made of an ohmic metal and is connected between all the heterojunction units except the lowermost heterojunction unit; the multi-unit layer is formed on the multi-channel region and comprises at least two unit structures in the same plane; wherein a gate metal is prepared on the surface of the first unit structure to form a gate together; the second unit structure is connected with the source to form a bridge-shaped structure; the other unit structures between the second unit structure and the drain are in the form of floating islands; and the passivation layer is formed on the multi-channel region.

The invention provides a semiconductor device. The semiconductor device includes a substrate, a gate structure, a first interlayer dielectric layer, a source structure, a drain structure, a dielectric pattern, a first field plate, and a second field plate. The gate structure is disposed on the substrate. The first interlayer dielectric layer is disposed on the substrate and partially covers the gate structure. The source electrode structure and the drain electrode structure are arranged on the substrate and located on the two sides of the gate electrode structure. The dielectric pattern is disposed on the first interlayer dielectric layer between the gate structure and the drain structure. The first field plate is arranged on the substrate and covers the first interlayer dielectric layer between the gate structure and the dielectric pattern and the dielectric pattern. The second field plate is disposed over the first field plate and the dielectric pattern and extends toward the drain structure.

The invention provides a packaging structure and a manufacturing method thereof. The packaging structure comprises an embedded component circuit structure layer, a signal interconnection structure layer, a power supply structure layer and an electronic component layer. The embedded component circuit structure layer comprises at least one embedded component and is provided with a first surface and a second surface which are opposite to each other. The signal interconnection structure layer is arranged on the first surface of the embedded component circuit structure layer and is electrically connected with the embedded component circuit structure layer. The power supply structure layer is arranged on the signal interconnection structure layer and is electrically connected with the signal interconnection structure layer. The electronic component layer comprises a plurality of electronic components, is configured on the second surface of the embedded component circuit structure layer, and is electrically connected with the embedded component circuit structure layer. The thermal expansion coefficient of the signal interconnection structure layer is higher than the thermal expansion coefficient of the electronic component layer and the thermal expansion coefficient of the power supply structure layer.

A semiconductor device is provided. The semiconductor device includes a first semiconductor structure, a second semiconductor structure on the first semiconductor structure and an active structure between the first semiconductor structure and the second semiconductor structure. The first semiconductor structure includes a first waveguiding layer having a first band gap, and a first interlayer directly contacting the first waveguiding layer and having a first thickness and a second bandgap lager than the first band gap. The first thickness is 5 nm-35 nm.

The present disclosure provides a semiconductor structure and a manufacturing method thereof. The semiconductor structure includes a substrate and a contact structure. The substrate includes a shallow trench isolation (STI) structure and active structures separated by the STI structure. The contact structure includes a first contact structure and a second contact structure that are laminated, where the first contact structure covers a part of a top surface and a part of a side wall of the active structure.

A package structure includes an embedded component circuit structure layer, a signal interconnection structure layer, a power structure layer, and an electronic component layer. The embedded component circuit structure layer includes at least one embedded component and has a first surface and a second surface opposite to each other. The signal interconnection structure layer is disposed on the first surface and is electrically connected to the embedded component circuit structure layer. The power structure layer is disposed on and electrically connected to the signal interconnection structure layer. The electronic component layer includes a plurality of electronic components, is disposed on the second surface, and is electrically connected to the embedded component circuit structure layer. A coefficient of thermal expansion of the signal interconnection structure layer is higher than a coefficient of thermal expansion of the electronic component layer and a coefficient of thermal expansion of the power structure layer.