65 results about "Trench gate" patented technology

The present disclosure provides a trench gate semiconductor device and a manufacturing method therefor. Compared with the related art in which a gate oxide layer is formed by oxidizing a first epitaxial layer, in the embodiments of the present disclosure, the gate oxide layer is formed by oxidizing a prefabricated epitaxial layer, so as to address the problem of high roughness of trench sidewalls caused by the etching process during the forming the trench by means of etching on the first epitaxial layer, thereby reducing the influence of surface roughness scattering of the trench on channel mobility. Further, a shielding layer is arranged between the gate oxide layer on the outer bottom wall of the trench and the first epitaxial layer, so as to reduce the peak electric field at the bottom corners of the trench, thereby improving the breakdown voltage.

The present disclosure provides a trench gate semiconductor device and a preparation method thereof. The trench gate semiconductor device comprises a substrate, a drift region and a body region. The drift region is arranged on the surface of the substrate and has a first conductivity type. The body region is epitaxially formed on the surface of the drift region away from the substrate and is an in-situ doped region with a second conductivity type. In the embodiment of the present disclosure, the body region is directly epitaxially formed, which can reduce the lattice damage in the body region, thereby reducing the interface defects between the body region and the gate oxide layer, and further improving the channel mobility. In addition, the tailing effect of the channel caused by ion implantation can be avoided, thereby improving the threshold voltage stability.

The present application belongs to the technical field of semiconductor, and particularly relates to a trench gate SiC MOSFET and a preparation method thereof. The preparation method of the trench gate SiC MOSFET forms a relatively thick N-type doping layer below the groove bottom of the gate groove. In the subsequent gate oxide process, the relatively thick N-type doping layer generates more electrons, which accelerates the oxidation of SiC. After the gate oxide process, the thickness of the gate oxide formed at the bottom of the gate groove is obviously thicker than that at the channel sidewall position. The relatively thick gate oxide enhances the tolerance of the device to high voltage, and reduces Qgd (the charge amount of the gate-drain), thereby improving the switching speed of the device.

The application discloses a trench Schottky contact area wet etching control method, which comprises the following steps: depositing an anti-etching layer on the surface of a wafer with a poly etching trench gate structure; depositing an oxidation layer on the anti-etching layer; performing contact area photoetching on the wafer; placing the wafer into an etching device to etch and remove the oxidation layer on the anti-etching layer in the contact area; and placing the wafer into a dry etching machine to etch the anti-etching layer and the gate oxide structure. The method can effectively control the etching amount in the wet etching process, realizes the control of the gate oxide height when etching the contact area oxidation layer of the trench Schottky structure, and further guarantees the high-voltage stability and high-speed switching performance of the device.

The present invention relates to the technical field of semiconductors, and provides a MOSFET device and a manufacturing method therefor, and a layout arrangement structure. A P-type buried layer is disposed within an N-type voltage-withstanding layer between the bottom of a trench and a substrate, and the P-type buried layer is electrically connected to a source, thereby solving the problem of insufficient electric field protection at the bottom of a trench gate and achieving effective protection of a gate dielectric layer under a high drain voltage. In addition, because a gap exists between the P-type buried layer and the bottom of a channel, current can still flow between the bottom of the trench and the P-type buried layer, and the design of the P-type buried layer does not hinder current flow, thereby comprehensively improving the operational performance of the MOSFET device.

The application provides a semiconductor structure and a forming method thereof, and the semiconductor structure comprises: a silicon carbide substrate, a silicon carbide epitaxial layer is formed on the surface of the silicon carbide substrate; a trench gate structure is located in the silicon carbide epitaxial layer; a shielding structure is located in the silicon carbide epitaxial layer on both sides of the trench gate structure; and a thermistor structure is located in the shielding structure. The application provides a semiconductor structure and a forming method thereof, and the thermistor structure for detecting temperature is formed in the shielding structure on both sides of the trench gate structure, so that an accurate and rapid chip temperature detection technical scheme is provided.

This application provides a trench gate field-effect transistor with low Ron, comprising: an N+ substrate, an N-type epitaxial layer, a first dielectric layer, an upper gate, a p-type substrate region, a source region, a drain, and a source. The N-type epitaxial layer and the p-type substrate region are sequentially disposed above the N+ substrate, and the drain is disposed below the N+ substrate. The first dielectric layer is located on the N-type epitaxial layer and passes through the p-type substrate region. The upper gate is disposed within the first dielectric layer and connected to the gate. The p-type substrate region, the source region, and the source are connected. The trench gate field-effect transistor further includes a lower gate and a first connecting portion. The lower gate and the first connecting portion are located within the first dielectric layer. The lower gate is located below the upper gate and is electrically connected to the upper gate through the first connecting portion. Embodiments of this application also provide a method for manufacturing a trench gate field-effect transistor and a smart electronic switch.

The application discloses a manufacturing method of super-junction trench gate MOSFET, which utilizes a photo mask for etching a top metal layer and a second mask layer; after the top metal layer is etched clean, the second mask layer is not removed, and etching is continuously performed on exposed metal tungsten in a source contact hole of a source region; the exposed metal tungsten in the source contact hole of the source region is etched and removed clean, and then the second mask layer is removed; and then a second dielectric layer is formed, so that the manufacturing cost can be reduced due to the reduction of mask layers, the exposed metal tungsten in the source contact hole of the source region can be avoided from being short-circuited to other conductors, the exposed metal tungsten can be avoided in the case of saving one mask layer, and the process risk is reduced.

An improved reverse field-effect transistor semiconductor device and its fabrication method may include a source layer at the bottom and a drain at the top of a semiconductor substrate, and a vertical conduction channel between the source layer and the drain region, the trench being controlled by a trench gate electrode disposed in a gate trench lined with insulating material. A heavily doped drain region is disposed near the top of the substrate surrounding the upper portion of the shielding trench and the gate trench. A doped body contact region is disposed in the substrate and surrounding the lower portion of the shielding trench. A shielding electrode extends upward from the source layer in the shielding trench for electrically short-circuiting the source layer and the body region, wherein the shielding structure extends upward to the heavily doped drain region and is insulated from the heavily doped drain region to serve as a shielding electrode.

The present application relates to a trench gate insulated gate bipolar transistor (IGBT) and a manufacturing method therefor. The trench gate IGBT comprises: a collector region; a drift region; a body region; an emitter region; a trench gate structure, comprising a gate dielectric layer located on an inner surface of a first trench, and a gate electrode located in the first trench and surrounded by the gate dielectric layer; a target trench structure, comprising an insulating dielectric layer located on a side wall of a second trench, and doped polysilicon located in the second trench and surrounded by the insulating dielectric layer from a side surface, wherein the doped polysilicon is P-type doped polysilicon; a first P-type doped region which is located in the drift region below the second trench, surrounds the bottom of the second trench, and is electrically connected to the doped polysilicon; and a target metal interconnect, which is located above the body region and is configured to be connected to an emitter potential, and is electrically connected to the doped polysilicon, the emitter region, and the body region by means of a target contact hole and an emitter contact hole below. The present invention can shorten the time of a tail current, thereby shortening the turn-off time of the IGBT.

A Metal Oxide Semiconductor (MOS) transistor cell design has multiple trench recesses embedding trench gate electrodes longitudinally extending in a third dimension, with interconnected first base layer, source regions, and a second base layer covering portions of the regions between adjacent trench recesses and longitudinally extending in the same third dimension. When a control voltage greater than a threshold value is applied on the trench gate electrodes, no vertical MOS channels are formable on the trench walls because each of trench recesses abuts at least one source regions and a connected highly doped second base layer. Instead, the charge carriers flow from a singular point within the source region, into a radial MOS channel formed only on the lateral walls of those trench regions abutting the first base layer, but not the higher doped second base layer.

The application relates to a trench type semiconductor field effect tube and a preparation method thereof, which comprises the following steps: a substrate with a first conductive type; a drift region located on the substrate and having the first conductive type; a first well region located on a side of the drift region away from the substrate and having a second conductive type; a second well region located on a side of the drift region away from the substrate and arranged in a spaced mode with the first well region and having the second conductive type; a trench gate located between the first well region and the second well region; a carrier extraction structure penetrating the trench gate in a first direction and covering at least part of a surface of the trench gate on a side close to the substrate and having the second conductive type; the first direction is along the thickness direction of the substrate; and a source metal layer covering the first well region, the second well region, the trench gate and the carrier extraction structure. The trench type semiconductor field effect tube provided by the application has high SEE resistance.

This switching element includes a semiconductor substrate, a trench, a gate insulating film, a gate electrode, and an upper electrode. The semiconductor substrate has an upper n-type region in contact with the gate insulating film, a p-type body contact region adjacent to the upper n-type region, a p-type body region in contact with the gate insulating film below the upper n-type region, and an n-type drift region in contact with the gate insulating film below the body region. The distance from a bottom end of the trench in the thickness direction of the semiconductor substrate to an interface between the upper n-type region and the body region is defined as L1, and the shortest distance, in a plane along a top surface of the semiconductor substrate, from the position farthest from the body contact region within a range where the upper n-type region contacts the gate insulating film to the body contact region is defined as L2, and the relationship L2 ≤ 0.429L1 − 0.318 is satisfied.

The application discloses a trench gate structure silicon carbide power semiconductor device and a preparation method thereof. The device adopts a trench gate structure, hexagonal boron nitride as a first gate dielectric buffer layer, alpha-Bi2SeO5 two-dimensional ferroelectric material as a second gate dielectric layer, both of which together form a silicon carbide gate dielectric layer, and TiN as a gate electrode. At the same time, the bottom of the trench gate adopts a new structure, which uses a deep P well region to wrap the corners on both sides of the bottom of the trench, and the rest of the bottom area not covered by the deep P well region is covered by a current spreading layer (CSL) for further optimizing the current spreading capability. The device prepared by the application has the advantages of excellent gate dielectric stability, outstanding withstand voltage capability, good conduction characteristics, excellent interface quality and the like, and is suitable for high-voltage and high-power power electronic application fields.

The silicon carbide device comprises a silicon carbide substrate layer and an epitaxial layer arranged on the silicon carbide substrate layer, a trench gate structure is arranged on the side of the epitaxial layer away from the silicon carbide substrate layer, shielding structures are arranged on both sides of the trench gate structure, a first shielding area of the shielding structure extends to the side of the first surface of the silicon carbide substrate layer, a second shielding area of the shielding structure is arranged on the side of the first surface of the silicon carbide substrate layer, facing the first shielding area, along a first direction, the gap between two adjacent second shielding areas is smaller than the gap between two adjacent first shielding areas; the size of the first shielding area is smaller than the size of the second shielding area, and in the projection of the epitaxial layer, the second shielding area covers the first shielding area completely, along a second direction, the depth of the trench gate structure is greater than the depth of the first shielding area. The silicon carbide transistor has high reliability and low on-resistance.

The application provides a SiC MOSFET and a preparation method of the SiC MOSFET, which comprises, from bottom to top, a drain metallization layer, an N+ substrate layer, an N-drift region, a current spreading region, a P-well region, a second N+ source region, a second P-base region, a first P-base region, a first N+ source region, a gate oxide, a polysilicon gate, an isolation oxide, and a source metallization layer; the first N+ source region, the second N+ source region, and the P-well region are in contact with the source metallization layer; the second N+ source region surrounds the bottom, two corners, and one sidewall of a trench gate oxide; the second N+ source region is shielded by the P-well region and the second P-base region, and is isolated from the current spreading region and the N-drift region. The application effectively suppresses a strong electric field of the gate oxide caused by high-energy charged particle radiation, and greatly improves the anti-single-particle gate punch-through capability of the trench type SiC MOSFET.

The invention provides a trench gate device and a preparation method thereof, the trench gate device comprises a semiconductor layer, a trench gate structure, a first shielding layer, a second shielding layer, a source electrode, a gate electrode and a drain electrode, the semiconductor layer comprises a drift region, a body region located on the upper surface layer of the drift region and a plurality of source regions arranged at intervals and located on the upper surface layer of the body region; the trench gate structure penetrates through the source region and the body region, and the bottom of the trench gate structure extends into the drift region; the first shielding layer is located in the drift region under the trench gate structure and is adjacent to the bottom of the trench gate structure; the second shielding layer is located in the semiconductor layer on the same side of each trench gate structure, the top of the second shielding layer is adjacent to the source region, and the bottom of the second shielding layer is adjacent to the first shielding layer; the source electrode, the grid electrode and the drain electrode are electrically connected with the corresponding areas respectively. The first shielding layer is arranged at the bottom of the groove, and the second shielding layer is arranged in the semiconductor layer on the same side of each groove, so that the channel density and reliability of the device are improved, and the on resistance of the device is reduced.

The utility model provides a kind of low drive voltage trench gate silicon carbide VDMOS, comprising: drift layer is connected to silicon carbide substrate;Drift layer is equipped with protruding part, and recess is equipped in protruding part;P-type trap area is connected to drift layer, and P-type trap area is connected to protruding part;P-type base area is connected to P-type trap area, and P-type base area is connected to protruding part;P-type source area is connected to P-type base area;N-type source area is connected to P-type base area, and N-type source area is connected to P-type source area, and N-type source area is connected to protruding part;Mask layer is located in recess;Insulating medium layer is located in recess, and insulating medium layer is connected to mask layer;Insulating medium layer protrudes from recess, and groove is equipped in insulating medium layer;Gate metal layer is located in groove;Source metal layer is connected protruding part, P-type source area and N-type source area respectively;Drain metal layer is connected to silicon carbide substrate, reduce device drive voltage, reduce device drive loss. Improve device reliability.

A semiconductor device includes a semiconductor element. The semiconductor element has a semiconductor layer (1), a first conductive type layer (2), a saturation current suppression layer (3, 4), a current diffusion layer (6), a base region (7), a source region (8), a trench gate structure, an interlayer insulating film (13), a source electrode (14), a drain electrode (15), and a second deep layer (5). The first conductive type layer is provided above the semiconductor layer. The saturation current suppression layer provided above the first conductive type layer includes a first deep layer (4) and a JFET portion (3). The base region is provided above the saturation current suppression layer. The source region and the contact region are provided above the regions. Each trench gate structure has a gate trench (10), a gate insulating film (11), and a gate electrode (12). The second deep layer is provided between the trench gate structures and connected to the first deep layer.

The application provides a trench power device with a back source structure and a preparation method thereof. The preparation method comprises the following steps: forming a P-type body region and an N-type drift region on a surface layer of an N-type substrate; forming a trench, wherein the trench extends from the P-type body region to the N-type substrate; forming a gate dielectric layer on a surface of the trench, and filling a gate layer in the trench; forming an isolation layer, and forming a drain through hole in the isolation layer; performing N-type ion implantation on the drain through hole to form an N-type drain region in the N-type drift region; forming a drain electrode; etching a back surface of the N-type substrate to form a source through hole, wherein the source through hole exposes the P-type body region; and depositing a source electrode on the back surface of the N-type substrate and in the source through hole, wherein the source electrode is connected with the N-type substrate and the P-type body region. The drain electrode and the gate electrode are integrated on the front surface of the device, the trench gate structure is adopted to improve the unit density and the channel control ability, and the source electrode is connected with the P-type body region through the back surface deep groove contact, so that the source contact resistance is effectively reduced, and the heat dissipation capacity is improved.

The present application relates to a trench-gate insulated gate bipolar transistor (IGBT) and a manufacturing method therefor. The IGBT comprises: a collector region; a drift region; a body region; an emitter region; trench gate structures, which extend from the body region into the drift region, the trench gate structures being arranged in a grid pattern resembling the Chinese character "田" in a plan view; target trench structures, which extend from the body region into the drift region, wherein each target trench structure is located in each "inner square" section of the trench gate structures arranged in the grid pattern resembling the Chinese character "田" and is surrounded by the four sides of each "inner square" section, and the depth of each first trench is less than the depth of each second trench; a voltage-withstanding region of a second electrical conductivity type, wherein the voltage-withstanding region is located in the drift region below each second trench and surrounds the bottom of each second trench; and a target metal interconnect located above the body region and configured to connect to an emitter potential, wherein the target metal interconnect is connected to polysilicon, the emitter region and the body region by means of a contact hole therebelow. The trench gate structures in the present invention are arranged in a grid pattern resembling the Chinese character "田" in the plan view; therefore, the density of the trench gate structures per unit of area is relatively high, and thus a device can obtain a relatively high current density.

The semiconductor device of the present application has a bipolar transistor. The bipolar transistor includes a semiconductor substrate having a first surface and a second surface, and a first electrode provided on the first surface. The semiconductor substrate includes a drift layer, a body layer located on the first surface side than the drift layer, a charge accumulation region located on the body layer, and a source region and a contact region formed on the first surface and electrically connected to the first electrode. The bipolar transistor further includes at least one first trench gate extending from the first surface toward the second surface, and a plurality of second trench gates. The plurality of second trench gates each has a depth from the first surface shallower than a depth of the at least one first trench gate from the first surface. The semiconductor substrate includes, between mutually adjacent ones of the plurality of second trench gates, the body layer, the contact region, and a first region located between the body layer and the contact region and having an impurity density lower than the body layer.

The application discloses a high-mobility silicon carbide N-type LDMOS device with reduced on-resistance, which comprises an N-type substrate, a P-type epitaxial layer arranged on the N-type substrate, an N-type well region, a first P-type heavily doped region, a first N-type heavily doped region, a second P-type heavily doped region connected to a source, a second N-type heavily doped region connected to a drain arranged in the N-type well region, the first P-type heavily doped region, the first N-type heavily doped region and the second P-type heavily doped region being connected, an oxide layer arranged on the surface of the second N-type heavily doped region, the N-type well region, the first P-type heavily doped region, the first N-type heavily doped region, the second P-type heavily doped region and the P-type epitaxial layer, a polycrystalline silicon trench gate serving as a gate of the device and extending into the P-type epitaxial layer, and an N-type buried layer arranged in the P-type epitaxial layer, one end of the N-type buried layer being connected to a channel of the device and the other end being connected to the N-type well region.

A semiconductor die includes: a silicon substrate; a trench gate NMOS transistor formed in a first device region of the silicon substrate; a trench gate PMOS transistor formed in a second device region of the silicon substrate and electrically connected to the trench gate NMOS transistor; and an isolation structure interposed between the first device region and the second device region. Methods of monolithically integrating the trench gate NMOS transistor and the trench gate PMOS transistor in the same semiconductor die are also described.

This invention discloses a trench gate IGBT device and its manufacturing method. The device uses a thin second portion of a first oxide layer as an insulator between the first gate and the P-type body region, and a thicker first portion of the first oxide layer as the dielectric for the sidewalls and bottom of the first gate. This reduces the electric field concentration effect at the bottom of the trench and improves the device's avalanche resistance. At the same time, the thicker first portion of the first oxide layer reduces the capacitance between the gate and collector, optimizing the device's turn-on speed and reducing losses during the turn-on process. In addition, the bottoms of the first and second oxide layers are respectively connected to the corresponding P-floating layer regions, solving the problem of direct contact between the bottom gate oxide layer and the drift region in traditional trench gate IGBTs, which increases the Miller capacitance of the IGBT device, affects the switching losses during operation, and easily induces false turn-on.

The present invention provides a trench gate device and a manufacturing method therefor. The trench gate device comprises: a semiconductor structure, first and second interlayer dielectric layers, first and second lead-out layers, and a source / drain / gate, wherein the semiconductor structure comprises a semiconductor layer and at least one trench gate structure extending in an X direction, the semiconductor layer comprises a drift region, a well region, and a source region, and the trench gate structure passes through the source region and the well region; the first interlayer dielectric layer covers the upper surface of the semiconductor structure; the first lead-out layer passes through the first interlayer dielectric layer and is electrically connected to the source region; the second lead-out layer passes through the first interlayer dielectric layer and extends its bottom into a gate conductive layer; the second interlayer dielectric layer covers the upper surface of the first interlayer dielectric layer; the source is electrically connected to the first lead-out layer, and the size of the second lead-out layer in the X direction is not less than the size of the source; the gate is electrically connected to the second lead-out layer; and the drain is electrically connected to the bottom surface of the semiconductor layer. In the present invention, by forming, in the device, the second lead-out layer embedded in the gate conductive layer, gate resistance and switching loss are reduced.

The application provides a trench gate MOSFET and a forming method, which comprises the following steps: forming a first trench in an epitaxial layer of a cell region and forming a second trench in an epitaxial layer of a gate lead-out region; forming a first gate dielectric layer and a first control gate in the first trench and the second trench; forming a third trench on both sides of the first control gate in the cell region and forming a fourth trench on both sides of the first control gate in the gate lead-out region; forming a second gate dielectric layer and a second control gate in the third trench and the fourth trench, the second control gate is separated from the first control gate by the second gate dielectric layer, and the thickness of the second gate dielectric layer is smaller than that of the first gate dielectric layer; forming a well region in the epitaxial layer close to the surface of the epitaxial layer; forming a source-drain terminal in the well region close to the surface of the epitaxial layer in the cell region; forming an interlayer dielectric layer on the surface of the epitaxial layer; forming a first contact hole in the cell region and forming a second contact hole in the gate lead-out region, and the first control gate and the second control gate are communicated.

A semiconductor device is provided. The semiconductor device includes a semiconductor substrate; a N type drift layer, a P-channel layer and a N+ layer sequentially stacked on the semiconductor substrate; a trench gate in the N+ layer, the P− channel layer and the N type drift layer; a P type ultra-wide bandgap epitaxial layer below the trench gate; and a gate insulating layer surrounding a bottom and a sidewall of the trench gate, and between the trench gate and the P type ultra-wide bandgap epitaxial layer.