860 results about "Trench gate" patented technology

The disclosure relates to a π type trench gate silicon carbide MOSFET device and a fabrication method thereof. To protect a trench gate oxide layer without increasing a channel resistance and process complexity, a second conductivity type of heavily doped deep well inserted with double gate trenches along the sidewalls of deep well is designed. The deep well is connected to the source metal directly. The electric potential is clamped to the source during the voltage blocking and turn-off state, which reduces the electric field in the gate oxide and reduces the miller capacitance. An interlayer dielectric layer is deposited above the conductive dielectric polysilicon layers and extends outward separately to cover a part of the source region. A smaller cell pitch can be achieved by controlling the spacing between the first and the second trench gate, thereby increasing the channel density and reducing the channel resistance.

The invention provides a high-reliability trench gate silicon carbide VDMOS and a preparation method thereof, and the method comprises the steps: depositing metal on the lower side surface of a silicon carbide substrate to form a drain metal layer, and carrying out the epitaxial growth on the upper side surface of the silicon carbide substrate to form a drift layer; a barrier layer is formed on the drift layer, etching and ion implantation are carried out, a first P-type well region, a protruding part, a first low-resistance region, a second low-resistance region and a third low-resistance region are formed, and the low-resistance region comprises the first low-resistance region, the second low-resistance region and the third low-resistance region; a barrier layer is formed again, etching and ion implantation are carried out, and a P-type source region, an N-type source region, a conductive region and a protection region are formed; a barrier layer is formed again, an insulating medium layer is formed through etching and oxidation, and a groove is formed in the insulating medium layer; and forming a barrier layer again, etching, depositing metal, forming a gate metal layer and a source metal layer, and removing the barrier layer to complete preparation. Through optimization design of the gate structure and the source structure, the purpose of improving the reliability of the device is achieved.

The invention discloses an SJ-MOSFET device. The SJ-MOSFET device comprises a first conductive type substrate; a first conductive type epitaxial layer; a source region; a body region; a second conductive type doped column; the trench gate is arranged on the side surface of the second conductive type doped column and penetrates through the source region and the body region; and the trench pseudo gate is arranged on the side surface of the second conductive type doped column and penetrates through the source region and the body region. On the other hand, the invention discloses a manufacturing method. According to the invention, the grid electrode and the grid electrode groove are arranged on the side surface of the doped column, and a part of the grid electrode groove is arranged in the doped column, so that the area of the grid electrode groove occupying the MESA is small, and the grid electrode groove is arranged towards the interior of the doped column, so that the cell size and the pitch between two source electrode contact holes can be reduced to the greatest extent, and the performance of the MESA is improved. And meanwhile, no JFET resistor exists, so that the optimization of the on-resistance is realized.

The invention provides a low-resistance separation trench gate silicon carbide VDMOS and a preparation method thereof, and the method comprises the steps: depositing metal on the lower side surface of a silicon carbide substrate, and forming a drain metal layer; epitaxially growing on the upper side surface of the silicon carbide substrate to form a drift layer; forming a barrier layer, etching, performing ion implantation, and forming a P-type source region, a low-resistance region, a P-type well region and an N-type source region; a barrier layer is formed again, and a first insulating medium layer and a second insulating medium layer are formed through etching and deposition; re-forming a barrier layer, etching and depositing metal, and respectively forming a first gate metal layer and a second gate metal layer; forming a barrier layer again, etching and depositing metal, and forming a first source metal layer; and forming a barrier layer again, etching, depositing metal, forming a second source metal layer, and removing the barrier layer to complete preparation. And the driving loss and the body diode loss of the device are reduced.

The invention provides a left-right shielding trench gate silicon carbide VDMOS and a preparation method thereof, and the method comprises the steps: depositing metal on the lower side surface of a silicon carbide substrate, and forming a drain metal layer; epitaxially growing on the upper side surface of the silicon carbide substrate to form a drift layer; forming a barrier layer above the drift layer, and performing etching and ion implantation to form a P-type source region, a low-resistance region, a P-type well region and an N-type source region; forming a barrier layer again, etching to form a first groove, and depositing to form an insulating dielectric layer; forming a barrier layer again, etching and depositing metal, and forming a first gate metal layer and a second gate metal layer; forming a barrier layer again, etching and depositing metal, and forming a first source metal layer; and a barrier layer is formed again, the barrier layer is etched to form a through hole, the low-resistance region, the P-type source region and the N-type source region are etched, metal is deposited, a second source electrode metal layer is formed, the barrier layer is removed, and preparation is completed.

The invention provides an asymmetric trench gate silicon carbide VDMOS and a preparation method thereof, and the method comprises the steps: depositing metal on the lower side surface of a silicon carbide substrate, and forming a drain metal layer; epitaxially growing on the silicon carbide substrate to form a drift layer; performing ion implantation to form a freewheeling region; forming a barrier layer, etching, carrying out ion implantation, and forming a masking layer, a P-type well region and an N-type source region; re-forming a barrier layer, etching, etching the drift layer and the masking layer to form a groove, and oxidizing to form an insulating dielectric layer; forming a barrier layer again, etching and depositing metal, and forming a gate metal layer; a barrier layer is formed again, the barrier layer is etched to form a through hole, the drift layer is etched to the upper side face of the follow current region, metal is deposited, and a source electrode metal layer is formed; according to the invention, the body diode conduction loss of the device can be effectively reduced, the reverse recovery speed of the device can be improved, and the gate reliability and the source large current impact reliability of the device can be improved.

The invention discloses a semiconductor device and a manufacturing method thereof, a power module, a power conversion circuit, and a vehicle. The semiconductor device includes: a semiconductor body; the semiconductor body comprises a well region and a first region; the first surface is provided with a gate trench; the gate trench comprises a first gate trench and a second gate trench which are communicated, and the second gate trench is located at one side, far away from the first surface, of the first gate trench; the first gate trench extends into the first region and the well region from the first surface, and the second gate trench is located at one side, far away from the first region, of the well region; the semiconductor body further comprises a first insulating layer and a second insulating layer, the first insulating layer is located on the side wall of the first gate trench, the second gate trench is filled with the second insulating layer, and the thickness of the second insulating layer is larger than or equal to that of the first insulating layer; and a trench gate located in the first gate trench. According to the technical scheme, the breakdown voltage of the semiconductor device is improved, and the device performance is improved.

The present application discloses a structure of a trench-gate power MOSFET and a manufacturing method thereof. The structure includes: a second epitaxial layer; a strip-shaped P pillar, the length direction of the strip-shaped P pillar being parallel to the projection direction of the crystal orientation with the most obvious channel effect on the surface of the epitaxial material; a trench gate, including a trench, the trench being parallel to the length direction of the strip-shaped P pillar or perpendicular to the length direction of the strip-shaped P pillar, and filling a filler into the trench to manufacture the trench gate. When the length direction of the trench is parallel to the length direction of the strip-shaped P pillar, the trench is located directly above the strip-shaped P pillar and has the same width as the strip-shaped P pillar. When the length direction of the trench is perpendicular to the length direction of the strip-shaped P pillar, the width of the trench is not related to the strip-shaped P pillar; a surface source region. The advantage of the present application is that it can reduce the manufacturing steps and simplify the processing technology.

The invention provides a quasi-super junction trench gate silicon carbide VDMOS and a preparation method thereof, and the method comprises the steps: depositing metal on the lower side surface of a silicon carbide substrate, and forming a drain metal layer; epitaxially growing on the upper side surface of the silicon carbide substrate to form a drift layer; a barrier layer is formed above the drift layer, etching and ion implantation are carried out, a plurality of N-type regions, a plurality of P-type masking regions, a P-type well region, an N-type source region and a P-type source region are formed, the barrier layer is formed again, etching and oxidation are carried out to form a gate dielectric layer, and a groove is formed in the gate dielectric layer; and forming a barrier layer again, etching, depositing metal, forming a gate metal layer and a source metal layer, and removing the barrier layer to complete preparation. An N-type region and a masking region are constructed in the device, so that a transverse and longitudinal combined quasi super junction voltage-withstanding structure is formed to improve the voltage-withstanding capability of the device, and meanwhile, the N-type region can reduce the on resistance of the device.

The invention provides a semiconductor device and a manufacturing method thereof, the semiconductor device comprises a semiconductor layer and a trench gate, the trench gate is located in a trench of a first surface of the semiconductor layer, and the semiconductor layer comprises a body region, a source region and a drift region; the first buried layer is located at the bottom of the trench gate and connected with the trench gate, the third buried layer is connected with a part of the first buried layer in the width direction of the trench gate, and the third buried layer is further connected with a part of the body region. The first buried layer is arranged at the bottom of the trench gate, the voltage endurance capability is improved, and the first buried layer is electrically connected with the source region through the third buried layer, the body region and the source region in sequence, so that the electric field shielding function of the first buried layer to the bottom of the trench gate is more stable.

On a single semiconductor substrate, a main semiconductor device is provided in an active-region operating region and a current sensing portion for detecting overcurrent flowing through the main semiconductor device is provided in a sensing region. The main semiconductor device and the current sensing portion are vertical IGBTs with a trench gate structure. All cells of the main semiconductor device have a CS region. Some of the cells of the current sensing portion have the same structure as the structure of the cells of the main semiconductor device while some of the cells have a structure that is free of CS regions but otherwise the same as the structure of the cells of the main semiconductor device. An average carrier concentration of the CS regions per unit area of the sensing region is less than that of the CS regions per unit area of the active-region operating region.

The invention provides an MOSFET and a manufacturing method thereof. The MOSFET includes a substrate; the epitaxial layer is arranged on the substrate; the trench gate group comprises a first trench gate and a plurality of second trench gates, the first trench gate extends into the epitaxial layer from the surface of the side, away from the substrate, of the epitaxial layer, the first trench gate extends in the first direction on the plane where the epitaxial layer is located, and the second trench gates are arranged at intervals in the first direction; the orthographic projection of the second trench gate on the substrate is located in the orthographic projection range of the first trench gate on the substrate, the top of the second trench gate is in contact with the bottom of the first trench gate, and a gate layer in the second trench gate is connected with a gate layer in the first trench gate; each shielding region wraps the bottom and all the side walls of the second trench gate and extends towards the surface of the side, away from the substrate, of the epitaxial layer so as to cover the side wall of the first trench gate, and the multiple shielding regions are arranged at intervals. The shielding region has a three-dimensional structure, so that the stress of a trench gate oxide electric field can be reduced, the cell size of the MOSFET can be reduced, and the current density of the MOSFET can be improved.

The invention provides a trench gate silicon carbide MOSFET device integrated with a FinFET structure and a manufacturing method. The device structurally comprises an N + substrate, an N-epitaxial layer, an N + buffer layer, a P-type well region, a carrier expansion layer (CSL layer), an N + source region, a P + shielding region, a polycrystalline silicon gate, a source trench, source metal and drain metal. According to the invention, the FinFET structure with the fin width less than 300nm is integrated into the gate trench of the trench gate silicon carbide MOSFET. The integrated FinFET increases the channel density of the device, meanwhile, the carrier distribution is more uniform due to the extremely narrow Fin-shaped table top, the influence of interface scattering on the carriers is weakened, and the channel mobility is increased. Therefore, after the FinFET structure is integrated, the specific on-resistance of the trench gate silicon carbide MOSFET is obviously reduced. Meanwhile, the device is provided with a source trench which is deep and is wrapped by a P + shielding region, and the P + shielding region prevents the oxide layer at the corner of the trench from being broken down in advance.

The utility model provides a trench gate silicon carbide VDMOS with low on-resistance. The trench gate silicon carbide VDMOS is characterized in that the lower side surface of a drift layer is connected to the upper side surface of a silicon carbide substrate; the lower side of the P-type source region is connected to the upper side of the drift layer; the freewheeling region is connected to the drift layer, and the freewheeling region is connected to the P-type source region; a groove is formed in the follow current area, and a masking layer is arranged at the bottom of the groove; a P-type well region and an N-type source region are arranged in the follow current region, and the upper side surface of the P-type well region is connected to the lower side surface of the N-type source region; the lower portion of the gate dielectric layer is arranged in the groove, the outer side of the gate dielectric layer is connected with the N-type source region and the P-type well region, and the lower side face of the gate dielectric layer is connected to the upper side face of the masking layer; a groove is formed in the gate dielectric layer; the gate metal layer is arranged in the groove; the source electrode metal layer is respectively connected with the P-type source region, the follow current region and the N-type source region; the drain metal layer is connected to the lower side surface of the silicon carbide substrate; the on-resistance of the device can be effectively reduced, the body diode conduction loss of the device is reduced, and the switching speed of the device is improved.

The embodiment of the invention discloses a semiconductor device, a manufacturing method, a power module, a power conversion circuit and a vehicle. The semiconductor device comprises a semiconductor body, and the semiconductor body comprises a first surface, a second surface, a well region and a first region; the first surface is provided with a gate trench and a source trench; the first insulating layer is located on the bottom surface and the side wall of the gate trench; the trench gate is located on the side, away from the semiconductor body, of the first insulating layer in the gate trench; the source trench structure comprises a filling layer located in the source trench; the barrier layer is located on the side, away from the semiconductor body, of the filling layer and located in the source trench; the ohmic contact metal layer is located on the first surface and provided with an opening; the source electrode is located on one side, away from the first surface, of the ohmic contact metal layer and contacts the barrier layer through the opening; the drain is located on the second surface. According to the technical scheme of the embodiment of the invention, the surface of the source trench can be flat, no abnormal morphology such as holes or grooves exists, and the reliability of the semiconductor device is improved.

The invention provides a low-loss trench gate silicon carbide MOSFET device and a manufacturing method. The device structurally comprises an N + substrate, an N-epitaxial layer, an N + buffer layer, a P-type well region, an N + source region, a P + shielding region, a polycrystalline silicon gate, source metal and drain metal. According to the silicon carbide MOSFET device based on the asymmetric trench gate, a channel is formed in one side of a silicon carbide trench, and the other side of the silicon carbide trench is wrapped by P +. The integrated FinFET structure increases the channel density, and meanwhile, the extremely narrow Fin-shaped mesa weakens the electric field intensity and interface scattering at the channel, so that the mobility of the channel in the Fin-shaped mesa is increased. In addition, the P + structure wrapping the gate trench reduces the electric field of the gate oxide layer at the corner of the trench, so that the electric field intensity of the gate oxide layer of the device is within a safe working range after the FinFET structure is introduced.

The embodiment of the invention discloses a semiconductor device, a manufacturing method, a power module, a power conversion circuit and a vehicle. The semiconductor device includes a semiconductor body including a first surface, a second surface, a first device region, and a second device region; the first device region comprises a well region, a first region and a channel layer, and the first region is in contact with the channel layer; a gate trench; a first insulating layer; a first trench located in the second device region; the second device region further comprises a second insulating layer and a filling layer; a trench gate; an interlayer insulating layer; a Schottky metal layer; a drain electrode; and a source electrode. According to the technical scheme of the embodiment of the invention, the depletion type semiconductor device is formed and is in a conducting state and a cut-off state in a normal state, negative voltage needs to be applied between the grid electrode and the source electrode to cut off the channel, the response can be faster, the current circulation can be controlled, and the conducting loss is smaller. And a Schottky structure is integrated, so that the forward conduction voltage drop of the device is reduced, and the energy loss of the device in a reverse follow current state is reduced.

The invention provides a high-reliability super-junction trench gate silicon carbide VDMOS (Vertical Double-diffused Metal Oxide Semiconductor) with voltage higher than 3kV and a preparation method thereof. The method comprises the following steps: depositing metal on the lower side surface of a silicon carbide substrate to form a drain metal layer, and epitaxially growing on the upper side surface of the silicon carbide substrate to form a buffer region; performing epitaxial growth on the buffer region to obtain a first drift region; performing ion implantation to form a P-type region; removing the barrier layer, and performing epitaxial growth on the first drift region to obtain a second drift region; forming a barrier layer, and performing etching and ion implantation to form a P-type well region, a P + region and an N-type source region; etching the P-type well region and the N-type source region to form a first groove; etching the N-type source region, and then depositing metal to form a source metal layer; oxidizing to form an insulating dielectric layer, wherein a groove is formed in the insulating dielectric layer; and depositing metal, forming a gate metal layer, removing the barrier layer, and completing preparation. The voltage endurance capability and reliability of the device are improved by constructing a device gate and a source which are comprehensively wrapped by a P-type well region and a P-type region.

The invention discloses a semiconductor device which comprises a cellular structure, and the cellular structure comprises an N + substrate, an N-drift layer and a functional area. The N-drift layer is located on the N + substrate; the functional region is embedded into one side, away from the N + substrate, of the N-drift layer, the functional region comprises two subunits and a second N + source region, and each subunit comprises a P + contact region, a P-type body region, a first N + source region and a first trench gate structure; the first N + source region is located on the P-type body region, the first groove is located between the P-type body region and the P + contact region, the first gate oxide layer covers the inner wall of the first groove, a first filling groove is formed in the inner wall of the first gate oxide layer, the first gate is filled in the first filling groove, and the P + shielding region of the P + contact region covers the bottom of the first gate oxide layer; and a second N + source region is arranged between the first trench gate structures of the two subunits. According to the device, the effective utilization rate of a channel can be improved, the specific on-resistance is further reduced, and the problem of long reverse recovery time is solved.

The invention provides a trench gate silicon carbide VDMOS of a trench source electrode and a preparation method, and the method comprises the steps: depositing metal on the lower side surface of a silicon carbide substrate, and forming a drain electrode metal layer; epitaxially growing on the upper side surface of the silicon carbide substrate to form a drift layer; forming a barrier layer, etching, performing ion implantation, and forming a low-resistance region and a first lug boss; a barrier layer is formed again, etching and ion implantation are carried out, and a first well region and a second protruding part are formed; a barrier layer is formed again, etching and ion implantation are carried out, and a P-type source region and a P-type well region are formed; a barrier layer is formed again, an insulating medium layer is formed through etching and oxidation, and a groove is formed in the insulating medium layer; and forming a barrier layer again, etching, depositing metal, forming a gate metal layer and a source metal layer, and removing the barrier layer to complete preparation. The gate reliability problem of the trench gate is solved, extra electrodes do not need to be led out, the follow current capability of the body diode is improved, and the on-resistance of the device is reduced.

The invention belongs to the technical field of power semiconductors, and relates to a 1200V SiC trench-type MOSFET (Metal-Oxide-Semiconductor Field Effect Transistor) integrated with a super junction and shield gate technology, which comprises an N + substrate layer, a drift region positioned above the N + substrate layer, and a trench gate structure and a source structure positioned above the drift region, compared with a conventional SiC trench type MOSFET with a P-type shielding layer, the SiC trench type MOSFET with the P-type shielding layer has the advantages that the peak electric field of the gate oxide layer is reduced, and the reliability of the device is ensured; the drift region adopts a super-junction structure, so that the electric field distribution is optimized, the blocking capability of the device is improved, the high doping concentration of the drift region can be adopted while the high breakdown voltage is maintained, the specific on-resistance of the device is remarkably reduced, and the conduction loss of the device is reduced; a shield gate structure is adopted, and the overlapping area of the gate and the drain is reduced, so that the gate-drain capacitance and the gate-drain charge are reduced, the switching speed of the device is improved, and the dynamic loss of the device is reduced. The performance is excellent in the high-voltage and high-frequency field.

The invention discloses an IGBT structure and a manufacturing method thereof, and a semiconductor device, and the IGBT structure comprises a substrate, a drift region of a first conduction type, a field cut-off region of the first conduction type, a collector region of a second conduction type, a plurality of trench gates, a body region of the second conduction type, an emitter region of the first conduction type, and a protection ring of the first conduction type. The substrate comprises an active region and a terminal region located on the outer side of the active region, the field cut-off region is arranged on the side, facing the first surface, of the drift region, the collector region is arranged on the side, facing the first surface, of the field cut-off region, and the field cut-off region comprises a first field cut-off region located in the active region and a second field cut-off region located in the terminal region; and the doping concentration of at least partial region of the second field stop region is greater than that of the first field stop region. According to the IGBT structure, the manufacturing method thereof and the semiconductor device, the turn-off loss can be effectively reduced, and the conduction voltage drop cannot be influenced.

The invention discloses a semiconductor device which comprises a semiconductor layer and a trench gate structure, the semiconductor layer is provided with a first surface and a second surface which are opposite to each other, at least part of the trench gate structure is located in a trench extending from the first surface to the second surface of the semiconductor layer, and the semiconductor layer comprises a shielding layer extending along a second direction, the bottom interval of the trench gate structure which is located between the trench gate structure and the second surface of the semiconductor layer and extends along the first direction is adjacent to the shielding layer, the first direction and the second direction are parallel to the first surface of the semiconductor layer, and an included angle which is not zero is formed between the first direction and the second direction. According to the semiconductor device provided by the invention, the shielding layer which is provided with the plurality of beam-shaped structures and extends along the second direction is formed below the groove extending along the first direction, and the width of the interval region between the adjacent beam-shaped structures along the first direction and the width of the beam-shaped structures are controlled, so that the electric field optimization of the corner at the bottom of the groove gate is realized; and meanwhile, the on-resistance is reduced.

The invention discloses a trench separation gate field effect transistor. The trench separation gate field effect transistor comprises a multi-stage step trench structure. The first-stage groove structure comprises a gate dielectric layer formed on the side face of the gate groove, a first dielectric layer on the surface of the bottom and a filled gate conductive material layer. The second-stage groove structure comprises a plurality of source electrode grooves, source dielectric layers and source electrode conductive material layers, wherein the source dielectric layers and the source electrode conductive material layers are formed in the source electrode grooves. First spacer regions are arranged among the source trenches, and the sum of the widths of all the source trenches and the first spacer regions is smaller than the width of the gate trench. A first buried layer and a second buried layer doped with a first conductive type and a second conductive type are formed at the top and the bottom of the first spacer region, and the second buried layer further wraps the bottom corners of the adjacent source trenches on the two sides. The gate conductive material layer is connected to the gate. Each source conductive material layer, the first buried layer and the second buried layer are connected to a source. The invention further discloses a manufacturing method of the trench separation gate field effect transistor. The invention can reduce the electric field intensity at the bottom of the gate trench.

The present application provides a semiconductor device and a manufacturing method thereof, wherein the device comprises: a body region, adjacent to the sidewall of the trench gate; an epitaxial layer, at least a portion of the epitaxial layer is located between the body region and the second surface, and adjacent to the trench gate and the body region, wherein the trench comprises a first trench extending from the first surface of the semiconductor layer to the second surface and a second trench located at the bottom of the first trench and connected to the first trench, the cross-sectional shape of the second trench is circular or elliptical, and at least a portion of the sidewall of the second trench is adjacent to the body region. The semiconductor device and the manufacturing method thereof of the present application increase the length of the channel by forming a second trench with a circular or elliptical cross-sectional shape at the bottom of the first trench and making the second trench at least partially adjacent to the body region.

To provide a semiconductor device capable of reducing on-resistance.SOLUTION: A semiconductor device 1 according to one embodiment includes: a semiconductor substrate 11 of a first conductivity type; and a semiconductor layer 12 of the first conductivity type, and the semiconductor layer includes: a trench gate 14, a source region 15 of the first conductivity type; a contact region 16 of a second conductivity type, and a column region 17 of the second conductivity type. In the semiconductor layer, a plurality of trench gates 14 are discretely formed along a first direction X and a second direction Y; the source region 15 is in contact with the trench gates 14 and surrounds the trench gates 14; the contact region 16 is located between the source regions adjacent in the second direction Y; and the column region 17 extends from an end 16a of the contact region 16 closer to the semiconductor substrate toward the semiconductor substrate 11.SELECTED DRAWING: Figure 3

The invention relates to a semiconductor device and a forming method thereof, a vehicle-mounted chip and a vehicle. The semiconductor device includes a semiconductor layer, a first gate trench in the semiconductor layer, and a first trench gate structure. The semiconductor layer is provided with a first surface and a second surface which are oppositely arranged in a first direction. The first gate trench is recessed from the first surface to the second surface. The first trench gate structure is located in the first gate trench and comprises a first gate portion and a first shielding portion. The first gate portions and the first shielding portions are arranged at intervals in the second direction, and the first direction intersects with the second direction. The grid electrode in the first grid electrode groove is split into the first grid electrode part and the first shielding part which are arranged at intervals in the second direction, and stray capacitance between the first grid electrode part and the drain electrode is small. In addition, the first shielding part plays a role in shielding lateral parasitic capacitance between the first gate part and the drain, and the gate-drain capacitance can also be reduced. The small gate-drain capacitance can reduce the switching loss of the semiconductor device.

The invention provides a low-driving-voltage trench gate silicon carbide VDMOS and a preparation method thereof, and the method comprises the steps: depositing metal on the lower side surface of a silicon carbide substrate, and forming a drain metal layer; epitaxially growing on the upper side surface of the silicon carbide substrate to form a drift layer; forming a barrier layer, etching, performing ion implantation, and forming a masking layer, a P-type well region, a P-type base region, a P-type source region and an N-type source region; a barrier layer is formed again, the barrier layer is etched to form a through hole, the drift layer is etched to the upper side face of the N-type source region, metal is deposited, and a source electrode metal layer is formed; re-forming a barrier layer, etching the barrier layer to form a through hole, etching the drift layer to the upper side surface of the masking layer, and depositing to form an insulating dielectric layer; and forming a barrier layer again, etching the barrier layer to form a through hole, etching the insulating dielectric layer to form a groove, depositing metal, forming a gate metal layer, removing the barrier layer, completing preparation, reducing the driving voltage of the device, and reducing the driving loss of the device. The device reliability is improved.

A method of manufacturing an electronic device, comprising the steps of: forming, on a first side (102a) of a solid body (101, 102) of Silicon, a first covering layer (104a) of SiO2; forming, on the first covering layer (104a), a second covering layer (104b) of SiN; forming, on the second covering layer (104b), a third covering layer (104c) of TEOS; forming a passing opening through the first, second and third covering layers (104a-104c); forming a trench (106) at the portion of the solid body exposed through the opening; grow a sacrificial layer (114), of said first oxide, within the trench (106); and perform in the order: selectively etch part of the second covering layer (104b), completely remove the sacrificial layer (114) and the third covering layer (104c) in one or more contextual etching steps.

The invention provides a semiconductor device with a trench gate and a forming method thereof, and the method comprises the steps: firstly executing a first exposure process and a first etching process to form a bottom gate oxide of a trench, then forming a monocrystalline silicon layer, executing a second exposure process and a second etching process to form a trench, exposing the top surface of the bottom gate oxide through the trench, and then forming the trench gate, the trench gate is located in the trench and located on the bottom gate oxide, the first exposure process and the second exposure process adopt the same mask, and the polarity of the second photoresist layer is opposite to that of the first photoresist layer. The unexpected effects of the invention are that the thickness of the bottom gate oxide of the groove can be more conveniently controlled, the bottom gate oxide of the groove is firstly formed, and then the monocrystalline silicon layer and the groove are formed, so that the problem that the bottom gate oxide is easy to seal in advance due to a high-density plasma process after the groove is formed is avoided, the process difficulty can be simplified, and the production efficiency is improved. And meanwhile, the possibility of thick bottom gate oxide is provided for the MOS device with a small critical size, and the density of the device can be improved.