1188 results about "Trench gate" patented technology

The invention provides a low-on-resistance trench gate silicon carbide VDMOS and a preparation method thereof, and the method comprises the steps: depositing metal on the lower side surface of a silicon carbide substrate, and forming a drain metal layer; epitaxially growing on the upper side surface of the silicon carbide substrate to form a drift layer; performing ion implantation to form a low-resistance region; forming a barrier layer, etching, performing ion implantation, and forming a P + well region, a P-type well region and an N-type source region; a barrier layer is formed again, and the insulating medium is etched and deposited; forming a barrier layer again, etching and depositing metal, and forming a suspension gate; forming a barrier layer again, etching the barrier layer, and depositing to form an insulating medium layer; forming a barrier layer again, etching and depositing metal, and forming a gate metal layer; the barrier layer is re-formed, the barrier layer is etched to form a through hole, the drift layer is etched to the upper side face of the P-type well region, metal is deposited, a source electrode metal layer is formed, the barrier layer is removed, preparation is completed, gate-drain capacitance is reduced, the switching speed of the device is increased, and switching loss is reduced.

The disclosure relates to a π type trench gate silicon carbide MOSFET device and a fabrication method thereof. To protect a trench gate oxide layer without increasing a channel resistance and process complexity, a second conductivity type of heavily doped deep well inserted with double gate trenches along the sidewalls of deep well is designed. The deep well is connected to the source metal directly. The electric potential is clamped to the source during the voltage blocking and turn-off state, which reduces the electric field in the gate oxide and reduces the miller capacitance. An interlayer dielectric layer is deposited above the conductive dielectric polysilicon layers and extends outward separately to cover a part of the source region. A smaller cell pitch can be achieved by controlling the spacing between the first and the second trench gate, thereby increasing the channel density and reducing the channel resistance.

The invention provides a high-reliability trench gate silicon carbide VDMOS and a preparation method thereof, and the method comprises the steps: depositing metal on the lower side surface of a silicon carbide substrate to form a drain metal layer, and carrying out the epitaxial growth on the upper side surface of the silicon carbide substrate to form a drift layer; a barrier layer is formed on the drift layer, etching and ion implantation are carried out, a first P-type well region, a protruding part, a first low-resistance region, a second low-resistance region and a third low-resistance region are formed, and the low-resistance region comprises the first low-resistance region, the second low-resistance region and the third low-resistance region; a barrier layer is formed again, etching and ion implantation are carried out, and a P-type source region, an N-type source region, a conductive region and a protection region are formed; a barrier layer is formed again, an insulating medium layer is formed through etching and oxidation, and a groove is formed in the insulating medium layer; and forming a barrier layer again, etching, depositing metal, forming a gate metal layer and a source metal layer, and removing the barrier layer to complete preparation. Through optimization design of the gate structure and the source structure, the purpose of improving the reliability of the device is achieved.

The invention discloses an SJ-MOSFET device. The SJ-MOSFET device comprises a first conductive type substrate; a first conductive type epitaxial layer; a source region; a body region; a second conductive type doped column; the trench gate is arranged on the side surface of the second conductive type doped column and penetrates through the source region and the body region; and the trench pseudo gate is arranged on the side surface of the second conductive type doped column and penetrates through the source region and the body region. On the other hand, the invention discloses a manufacturing method. According to the invention, the grid electrode and the grid electrode groove are arranged on the side surface of the doped column, and a part of the grid electrode groove is arranged in the doped column, so that the area of the grid electrode groove occupying the MESA is small, and the grid electrode groove is arranged towards the interior of the doped column, so that the cell size and the pitch between two source electrode contact holes can be reduced to the greatest extent, and the performance of the MESA is improved. And meanwhile, no JFET resistor exists, so that the optimization of the on-resistance is realized.

The invention discloses a semiconductor device and a manufacturing method thereof, a power module, a power conversion circuit, and a vehicle. The semiconductor device includes a semiconductor body including a well region, a first region, and a second region; the well region is located on the side, away from the first surface, of the first region; the first surface is also provided with a gate trench and a source trench; the second region surrounds the bottom surface and the side wall of the source trench; the trench gate is positioned on one side, far away from the semiconductor body, of the insulating layer in the gate trench; the source trench structure comprises a filling layer located in a source trench; the ohmic contact resistance between the ohmic contact layer and the semiconductor body is smaller than the ohmic contact resistance when the metal titanium and the semiconductor body form ohmic contact; and no chemical reaction intermediate product exists between the filling layer and the ohmic contact layer at the annealing temperature of the ohmic contact layer. According to the technical scheme provided by the embodiment of the invention, the electrical performance of the semiconductor device is improved.

The invention provides a heterogeneous trench gate silicon carbide VDMOS and a preparation method thereof, and the method comprises the steps: depositing metal on the lower side surface of a silicon carbide substrate, and forming a drain metal layer; epitaxially growing on the upper side surface of the silicon carbide substrate to form a drift layer; forming a barrier layer above the drift layer, and performing etching and ion implantation to form a P-type well region, an N-type source region and a masking region; forming a barrier layer again, and etching and depositing the insulating medium to form a first insulating medium region; forming a barrier layer again, and etching to form a groove; forming a barrier layer again, etching and depositing metal, and forming a suspension gate; forming a barrier layer again, and etching and depositing the insulating medium to form a second insulating medium region; forming a barrier layer again, etching and depositing metal, and forming a gate metal layer; the preparation method comprises the following steps: preparing a source electrode metal layer, re-forming a barrier layer, etching, depositing metal, forming a source electrode metal layer, removing the barrier layer, and completing the preparation, thereby realizing the characteristics of low switching loss, high switching speed and low on-resistance.

The invention provides a low-resistance separation trench gate silicon carbide VDMOS and a preparation method thereof, and the method comprises the steps: depositing metal on the lower side surface of a silicon carbide substrate, and forming a drain metal layer; epitaxially growing on the upper side surface of the silicon carbide substrate to form a drift layer; forming a barrier layer, etching, performing ion implantation, and forming a P-type source region, a low-resistance region, a P-type well region and an N-type source region; a barrier layer is formed again, and a first insulating medium layer and a second insulating medium layer are formed through etching and deposition; re-forming a barrier layer, etching and depositing metal, and respectively forming a first gate metal layer and a second gate metal layer; forming a barrier layer again, etching and depositing metal, and forming a first source metal layer; and forming a barrier layer again, etching, depositing metal, forming a second source metal layer, and removing the barrier layer to complete preparation. And the driving loss and the body diode loss of the device are reduced.

The invention provides a left-right shielding trench gate silicon carbide VDMOS and a preparation method thereof, and the method comprises the steps: depositing metal on the lower side surface of a silicon carbide substrate, and forming a drain metal layer; epitaxially growing on the upper side surface of the silicon carbide substrate to form a drift layer; forming a barrier layer above the drift layer, and performing etching and ion implantation to form a P-type source region, a low-resistance region, a P-type well region and an N-type source region; forming a barrier layer again, etching to form a first groove, and depositing to form an insulating dielectric layer; forming a barrier layer again, etching and depositing metal, and forming a first gate metal layer and a second gate metal layer; forming a barrier layer again, etching and depositing metal, and forming a first source metal layer; and a barrier layer is formed again, the barrier layer is etched to form a through hole, the low-resistance region, the P-type source region and the N-type source region are etched, metal is deposited, a second source electrode metal layer is formed, the barrier layer is removed, and preparation is completed.

The invention provides an asymmetric trench gate silicon carbide VDMOS and a preparation method thereof, and the method comprises the steps: depositing metal on the lower side surface of a silicon carbide substrate, and forming a drain metal layer; epitaxially growing on the silicon carbide substrate to form a drift layer; performing ion implantation to form a freewheeling region; forming a barrier layer, etching, carrying out ion implantation, and forming a masking layer, a P-type well region and an N-type source region; re-forming a barrier layer, etching, etching the drift layer and the masking layer to form a groove, and oxidizing to form an insulating dielectric layer; forming a barrier layer again, etching and depositing metal, and forming a gate metal layer; a barrier layer is formed again, the barrier layer is etched to form a through hole, the drift layer is etched to the upper side face of the follow current region, metal is deposited, and a source electrode metal layer is formed; according to the invention, the body diode conduction loss of the device can be effectively reduced, the reverse recovery speed of the device can be improved, and the gate reliability and the source large current impact reliability of the device can be improved.

A semiconductor device includes a chip with a main surface, featuring a first conductivity type base region. A trench gate structure penetrates the base region, while a second conductivity type emitter region is formed along the trench gate structure on the surface. Between the bottom of the base region and the emitter region, a higher impurity concentration in-base region is present. An insulating film covers the main surface, featuring a connection hole that exposes part of the emitter region at a distance from the in-base region. A connection electrode is positioned in the connection hole, electrically connecting the base and emitter regions.

The invention discloses a semiconductor device and a preparation method thereof, a power module, a power conversion circuit and a vehicle, and relates to the technical field of semiconductors, a semiconductor body of the semiconductor device is set as a first conductive type, a first surface of the semiconductor body is provided with a gate trench, and a trench gate structure is located in the gate trench. The semiconductor body further comprises a first region of the first conduction type, a well region of the second conduction type and a second region of the second conduction type, and the second region and at least part of the first surface are connected with a source electrode of the semiconductor device to form Schottky contact. The Schottky contact reduces the conduction voltage drop, reverse recovery time and reverse recovery energy consumption of the semiconductor device, enhances the conduction performance and surge current resistance of the body diode, avoids the problem that holes enter a drift layer in the follow current process, reduces the risk of double-click degradation of the device, avoids an external follow current diode, and improves the reliability of the device. Therefore, the circuit design complexity and the system cost are reduced.

The invention provides a semiconductor structure and a semiconductor device. The semiconductor structure comprises a substrate; the first semiconductor voltage-withstanding layer is located on the substrate, and the conduction type of the first semiconductor voltage-withstanding layer is identical to that of the substrate; the second semiconductor voltage-withstanding layer is located on the side, away from the substrate, of the first semiconductor voltage-withstanding layer, and the conduction type of the second semiconductor voltage-withstanding layer is different from that of the substrate; the first injection region is located in the second semiconductor voltage-withstanding layer, and the conduction type of the first injection region is different from that of the substrate; the second injection region is located in the second semiconductor voltage-withstanding layer and located on one side of the first injection region, the surface, close to the substrate, of the second injection region makes contact with the first semiconductor voltage-withstanding layer, and the conduction type of the second injection region is the same as that of the substrate; the third injection region is located in the second injection region, the conduction type is the same as that of the substrate, and the doping concentration is the same as that of the substrate; and the first trench gate structure is located in the first semiconductor voltage-withstanding layer and the second semiconductor voltage-withstanding layer and is in contact with the first injection region, the second injection region and the third injection region respectively. According to the invention, the problem that the latch-up effect is easy to occur in the groove-type MOS is solved.

The invention discloses a semiconductor device and a manufacturing method thereof, a power module, a power conversion circuit, and a vehicle. The semiconductor device includes: a semiconductor body; the semiconductor body comprises a well region and a first region; the first surface is provided with a gate trench; the gate trench comprises a first gate trench and a second gate trench which are communicated, and the second gate trench is located at one side, far away from the first surface, of the first gate trench; the first gate trench extends into the first region and the well region from the first surface, and the second gate trench is located at one side, far away from the first region, of the well region; the semiconductor body further comprises a first insulating layer and a second insulating layer, the first insulating layer is located on the side wall of the first gate trench, the second gate trench is filled with the second insulating layer, and the thickness of the second insulating layer is larger than or equal to that of the first insulating layer; and a trench gate located in the first gate trench. According to the technical scheme, the breakdown voltage of the semiconductor device is improved, and the device performance is improved.

The present application discloses a structure of a trench-gate power MOSFET and a manufacturing method thereof. The structure includes: a second epitaxial layer; a strip-shaped P pillar, the length direction of the strip-shaped P pillar being parallel to the projection direction of the crystal orientation with the most obvious channel effect on the surface of the epitaxial material; a trench gate, including a trench, the trench being parallel to the length direction of the strip-shaped P pillar or perpendicular to the length direction of the strip-shaped P pillar, and filling a filler into the trench to manufacture the trench gate. When the length direction of the trench is parallel to the length direction of the strip-shaped P pillar, the trench is located directly above the strip-shaped P pillar and has the same width as the strip-shaped P pillar. When the length direction of the trench is perpendicular to the length direction of the strip-shaped P pillar, the width of the trench is not related to the strip-shaped P pillar; a surface source region. The advantage of the present application is that it can reduce the manufacturing steps and simplify the processing technology.

The invention provides a quasi-super junction trench gate silicon carbide VDMOS and a preparation method thereof, and the method comprises the steps: depositing metal on the lower side surface of a silicon carbide substrate, and forming a drain metal layer; epitaxially growing on the upper side surface of the silicon carbide substrate to form a drift layer; a barrier layer is formed above the drift layer, etching and ion implantation are carried out, a plurality of N-type regions, a plurality of P-type masking regions, a P-type well region, an N-type source region and a P-type source region are formed, the barrier layer is formed again, etching and oxidation are carried out to form a gate dielectric layer, and a groove is formed in the gate dielectric layer; and forming a barrier layer again, etching, depositing metal, forming a gate metal layer and a source metal layer, and removing the barrier layer to complete preparation. An N-type region and a masking region are constructed in the device, so that a transverse and longitudinal combined quasi super junction voltage-withstanding structure is formed to improve the voltage-withstanding capability of the device, and meanwhile, the N-type region can reduce the on resistance of the device.

The invention relates to a novel asymmetric groove SiC MOSFET device with low resistance and Miller capacitance, and belongs to the technical field of semiconductor devices. The device comprises a substrate; the drift region is formed on one surface of the substrate; the N-CSL is formed on the surface of the drift region; the low-barrier diode is formed on one side of the surface of the N-CSL; the second P-well is formed on the other side of the surface of the N-CSL; the trench gate and the auxiliary trench gate are formed on the surface of the low-barrier diode and located on the two sides of the low-barrier diode; the P-base is formed on the surface of the N-CSL and is positioned between the second P-well and the trench gate; the source N + region is formed on the surface of the P-base and is positioned between the second P-well and the trench gate; a source electrode formed on the top of the device; and the drain electrode is formed on the other surface of the substrate. The specific on-resistance of the device can be reduced, the Miller capacitance and the gate charge of the device are reduced, and the switching speed of the device is improved.

The invention provides a semiconductor device and a manufacturing method thereof, the semiconductor device comprises a semiconductor layer and a trench gate, the trench gate is located in a trench of a first surface of the semiconductor layer, and the semiconductor layer comprises a body region, a source region and a drift region; the first buried layer is located at the bottom of the trench gate and connected with the trench gate, the third buried layer is connected with a part of the first buried layer in the width direction of the trench gate, and the third buried layer is further connected with a part of the body region. The first buried layer is arranged at the bottom of the trench gate, the voltage endurance capability is improved, and the first buried layer is electrically connected with the source region through the third buried layer, the body region and the source region in sequence, so that the electric field shielding function of the first buried layer to the bottom of the trench gate is more stable.

On a single semiconductor substrate, a main semiconductor device is provided in an active-region operating region and a current sensing portion for detecting overcurrent flowing through the main semiconductor device is provided in a sensing region. The main semiconductor device and the current sensing portion are vertical IGBTs with a trench gate structure. All cells of the main semiconductor device have a CS region. Some of the cells of the current sensing portion have the same structure as the structure of the cells of the main semiconductor device while some of the cells have a structure that is free of CS regions but otherwise the same as the structure of the cells of the main semiconductor device. An average carrier concentration of the CS regions per unit area of the sensing region is less than that of the CS regions per unit area of the active-region operating region.

The invention provides an MOSFET and a manufacturing method thereof. The MOSFET includes a substrate; the epitaxial layer is arranged on the substrate; the trench gate group comprises a first trench gate and a plurality of second trench gates, the first trench gate extends into the epitaxial layer from the surface of the side, away from the substrate, of the epitaxial layer, the first trench gate extends in the first direction on the plane where the epitaxial layer is located, and the second trench gates are arranged at intervals in the first direction; the orthographic projection of the second trench gate on the substrate is located in the orthographic projection range of the first trench gate on the substrate, the top of the second trench gate is in contact with the bottom of the first trench gate, and a gate layer in the second trench gate is connected with a gate layer in the first trench gate; each shielding region wraps the bottom and all the side walls of the second trench gate and extends towards the surface of the side, away from the substrate, of the epitaxial layer so as to cover the side wall of the first trench gate, and the multiple shielding regions are arranged at intervals. The shielding region has a three-dimensional structure, so that the stress of a trench gate oxide electric field can be reduced, the cell size of the MOSFET can be reduced, and the current density of the MOSFET can be improved.

The present invention discloses a trench gate IGBT device, comprising a collector metal layer, a collector region, a field stop layer, a drift region, a trench structure and an emitter metal layer stacked in sequence from bottom to top; the trench structure comprises a dummy gate structure and a gate structure, wherein the dummy gate structure is located on the upper side of the drift region, and the gate structure is located in the upper middle of the drift region; the dummy gate structure comprises a narrow portion and a wide portion, and the wide portion is located below the narrow portion; a carrier storage layer is provided above the drift region between the gate structure and the narrow portion, and a P-type base region is provided above the carrier storage layer; a P+ emitter region and an N+ emitter region are provided above the P-type base region, and the P+ emitter region and the N+ emitter region are electrically connected to the emitter metal layer respectively. The present invention effectively reduces Miller capacitance, improves IGBT switching speed, reduces IGBT switching loss and reduces device on-state voltage drop, while taking into account the improvement of various performances of the IGBT.

The invention provides a trench gate silicon carbide MOSFET device integrated with a FinFET structure and a manufacturing method. The device structurally comprises an N + substrate, an N-epitaxial layer, an N + buffer layer, a P-type well region, a carrier expansion layer (CSL layer), an N + source region, a P + shielding region, a polycrystalline silicon gate, a source trench, source metal and drain metal. According to the invention, the FinFET structure with the fin width less than 300nm is integrated into the gate trench of the trench gate silicon carbide MOSFET. The integrated FinFET increases the channel density of the device, meanwhile, the carrier distribution is more uniform due to the extremely narrow Fin-shaped table top, the influence of interface scattering on the carriers is weakened, and the channel mobility is increased. Therefore, after the FinFET structure is integrated, the specific on-resistance of the trench gate silicon carbide MOSFET is obviously reduced. Meanwhile, the device is provided with a source trench which is deep and is wrapped by a P + shielding region, and the P + shielding region prevents the oxide layer at the corner of the trench from being broken down in advance.

The utility model provides a trench gate silicon carbide VDMOS with low on-resistance. The trench gate silicon carbide VDMOS is characterized in that the lower side surface of a drift layer is connected to the upper side surface of a silicon carbide substrate; the lower side of the P-type source region is connected to the upper side of the drift layer; the freewheeling region is connected to the drift layer, and the freewheeling region is connected to the P-type source region; a groove is formed in the follow current area, and a masking layer is arranged at the bottom of the groove; a P-type well region and an N-type source region are arranged in the follow current region, and the upper side surface of the P-type well region is connected to the lower side surface of the N-type source region; the lower portion of the gate dielectric layer is arranged in the groove, the outer side of the gate dielectric layer is connected with the N-type source region and the P-type well region, and the lower side face of the gate dielectric layer is connected to the upper side face of the masking layer; a groove is formed in the gate dielectric layer; the gate metal layer is arranged in the groove; the source electrode metal layer is respectively connected with the P-type source region, the follow current region and the N-type source region; the drain metal layer is connected to the lower side surface of the silicon carbide substrate; the on-resistance of the device can be effectively reduced, the body diode conduction loss of the device is reduced, and the switching speed of the device is improved.

The embodiment of the invention discloses a semiconductor device, a manufacturing method, a power module, a power conversion circuit and a vehicle. The semiconductor device comprises a semiconductor body, and the semiconductor body comprises a first surface, a second surface, a well region and a first region; the first surface is provided with a gate trench and a source trench; the first insulating layer is located on the bottom surface and the side wall of the gate trench; the trench gate is located on the side, away from the semiconductor body, of the first insulating layer in the gate trench; the source trench structure comprises a filling layer located in the source trench; the barrier layer is located on the side, away from the semiconductor body, of the filling layer and located in the source trench; the ohmic contact metal layer is located on the first surface and provided with an opening; the source electrode is located on one side, away from the first surface, of the ohmic contact metal layer and contacts the barrier layer through the opening; the drain is located on the second surface. According to the technical scheme of the embodiment of the invention, the surface of the source trench can be flat, no abnormal morphology such as holes or grooves exists, and the reliability of the semiconductor device is improved.

The invention provides a low-loss trench gate silicon carbide MOSFET device and a manufacturing method. The device structurally comprises an N + substrate, an N-epitaxial layer, an N + buffer layer, a P-type well region, an N + source region, a P + shielding region, a polycrystalline silicon gate, source metal and drain metal. According to the silicon carbide MOSFET device based on the asymmetric trench gate, a channel is formed in one side of a silicon carbide trench, and the other side of the silicon carbide trench is wrapped by P +. The integrated FinFET structure increases the channel density, and meanwhile, the extremely narrow Fin-shaped mesa weakens the electric field intensity and interface scattering at the channel, so that the mobility of the channel in the Fin-shaped mesa is increased. In addition, the P + structure wrapping the gate trench reduces the electric field of the gate oxide layer at the corner of the trench, so that the electric field intensity of the gate oxide layer of the device is within a safe working range after the FinFET structure is introduced.

The embodiment of the invention discloses a semiconductor device, a manufacturing method, a power module, a power conversion circuit and a vehicle. The semiconductor device includes a semiconductor body including a first surface, a second surface, a first device region, and a second device region; the first device region comprises a well region, a first region and a channel layer, and the first region is in contact with the channel layer; a gate trench; a first insulating layer; a first trench located in the second device region; the second device region further comprises a second insulating layer and a filling layer; a trench gate; an interlayer insulating layer; a Schottky metal layer; a drain electrode; and a source electrode. According to the technical scheme of the embodiment of the invention, the depletion type semiconductor device is formed and is in a conducting state and a cut-off state in a normal state, negative voltage needs to be applied between the grid electrode and the source electrode to cut off the channel, the response can be faster, the current circulation can be controlled, and the conducting loss is smaller. And a Schottky structure is integrated, so that the forward conduction voltage drop of the device is reduced, and the energy loss of the device in a reverse follow current state is reduced.

The invention provides a high-reliability super-junction trench gate silicon carbide VDMOS (Vertical Double-diffused Metal Oxide Semiconductor) with voltage higher than 3kV and a preparation method thereof. The method comprises the following steps: depositing metal on the lower side surface of a silicon carbide substrate to form a drain metal layer, and epitaxially growing on the upper side surface of the silicon carbide substrate to form a buffer region; performing epitaxial growth on the buffer region to obtain a first drift region; performing ion implantation to form a P-type region; removing the barrier layer, and performing epitaxial growth on the first drift region to obtain a second drift region; forming a barrier layer, and performing etching and ion implantation to form a P-type well region, a P + region and an N-type source region; etching the P-type well region and the N-type source region to form a first groove; etching the N-type source region, and then depositing metal to form a source metal layer; oxidizing to form an insulating dielectric layer, wherein a groove is formed in the insulating dielectric layer; and depositing metal, forming a gate metal layer, removing the barrier layer, and completing preparation. The voltage endurance capability and reliability of the device are improved by constructing a device gate and a source which are comprehensively wrapped by a P-type well region and a P-type region.

Wide bandgap trench gate semiconductor devices are provided. In one example, a semiconductor device includes a wide bandgap semiconductor structure. The wide bandgap semiconductor structure includes a drift region of a first conductivity type and a well region of a second conductivity type. The semiconductor device includes a gate trench in the wide bandgap semiconductor structure. The gate trench extends through the well region into the drift region. The semiconductor device includes a buried gate structure in the gate trench. The buried gate structure includes a gate polysilicon layer and a gate silicide layer.

The invention discloses a semiconductor device which comprises a cellular structure, and the cellular structure comprises an N + substrate, an N-drift layer and a functional area. The N-drift layer is located on the N + substrate; the functional region is embedded into one side, away from the N + substrate, of the N-drift layer, the functional region comprises two subunits and a second N + source region, and each subunit comprises a P + contact region, a P-type body region, a first N + source region and a first trench gate structure; the first N + source region is located on the P-type body region, the first groove is located between the P-type body region and the P + contact region, the first gate oxide layer covers the inner wall of the first groove, a first filling groove is formed in the inner wall of the first gate oxide layer, the first gate is filled in the first filling groove, and the P + shielding region of the P + contact region covers the bottom of the first gate oxide layer; and a second N + source region is arranged between the first trench gate structures of the two subunits. According to the device, the effective utilization rate of a channel can be improved, the specific on-resistance is further reduced, and the problem of long reverse recovery time is solved.

The invention provides a trench gate silicon carbide transistor structure and a preparation method thereof. According to the invention, the sacrificial oxide layer with a thin film layer grows and is formed on the surface of the polycrystalline silicon layer of the trench gate structure and the surface of the polycrystalline silicon layer of the driving gate structure, so that sputtering metal can be prevented from reacting with polycrystalline silicon when an ohmic contact structure is formed; therefore, the condition that the photoetching and etching processes of the source contact hole and the gate contact hole can use the same photomask can be met; and meanwhile, the sacrificial oxide layer is thin, so that the sacrificial oxide layer can be conveniently removed together when the first metal layer which does not react is removed, and the influence on other film layers is small. The source contact hole and the gate contact hole are simultaneously formed through photoetching and etching by adopting the same photomask, so that the number of layers of the photomask is reduced, the photoetching and etching process time can be saved on one hand, the process manufacturing cost can be reduced, the parameter abnormity caused by external defects can be reduced on the other hand, the process stability is improved, and the production efficiency is improved. Therefore, the production efficiency is improved, and the productivity is increased.

The invention provides a longitudinal compact trench gate silicon carbide VDMOS and a preparation method thereof, and the method comprises the steps: depositing metal on the lower side surface of a silicon carbide substrate, and forming a drain metal layer; performing epitaxial growth on the upper side surface of the silicon carbide substrate to form a drift layer; performing ion implantation on the drift layer to form a low-resistance region, a P-type source region, a P-type well region and an N-type source region; a barrier layer is formed again, the barrier layer is etched to form a through hole, the drift layer and the P-type well region are etched to form a groove, an insulating medium layer is formed through oxidation, and a groove is formed in the insulating medium layer; a barrier layer is formed again, the barrier layer is etched to form a through hole, metal is deposited, and a gate metal layer is formed; re-forming a barrier layer, etching the barrier layer to form a through hole, etching the drift layer to the upper side surface of the P-type well region, depositing a metal layer, forming a source metal layer, removing the barrier layer, and completing the preparation. The compact design of the gate structure of the device is realized, the gate thickness of the device is reduced, and the power density of the device is improved.