652 results about "Trench gate" patented technology

The invention discloses a semiconductor device and a manufacturing method thereof, a power module, a power conversion circuit, and a vehicle. The semiconductor device includes: a semiconductor body; the semiconductor body comprises a well region and a first region; the first surface is provided with a gate trench; the gate trench comprises a first gate trench and a second gate trench which are communicated, and the second gate trench is located at one side, far away from the first surface, of the first gate trench; the first gate trench extends into the first region and the well region from the first surface, and the second gate trench is located at one side, far away from the first region, of the well region; the semiconductor body further comprises a first insulating layer and a second insulating layer, the first insulating layer is located on the side wall of the first gate trench, the second gate trench is filled with the second insulating layer, and the thickness of the second insulating layer is larger than or equal to that of the first insulating layer; and a trench gate located in the first gate trench. According to the technical scheme, the breakdown voltage of the semiconductor device is improved, and the device performance is improved.

The present application discloses a structure of a trench-gate power MOSFET and a manufacturing method thereof. The structure includes: a second epitaxial layer; a strip-shaped P pillar, the length direction of the strip-shaped P pillar being parallel to the projection direction of the crystal orientation with the most obvious channel effect on the surface of the epitaxial material; a trench gate, including a trench, the trench being parallel to the length direction of the strip-shaped P pillar or perpendicular to the length direction of the strip-shaped P pillar, and filling a filler into the trench to manufacture the trench gate. When the length direction of the trench is parallel to the length direction of the strip-shaped P pillar, the trench is located directly above the strip-shaped P pillar and has the same width as the strip-shaped P pillar. When the length direction of the trench is perpendicular to the length direction of the strip-shaped P pillar, the width of the trench is not related to the strip-shaped P pillar; a surface source region. The advantage of the present application is that it can reduce the manufacturing steps and simplify the processing technology.

The invention provides an MOSFET and a manufacturing method thereof. The MOSFET includes a substrate; the epitaxial layer is arranged on the substrate; the trench gate group comprises a first trench gate and a plurality of second trench gates, the first trench gate extends into the epitaxial layer from the surface of the side, away from the substrate, of the epitaxial layer, the first trench gate extends in the first direction on the plane where the epitaxial layer is located, and the second trench gates are arranged at intervals in the first direction; the orthographic projection of the second trench gate on the substrate is located in the orthographic projection range of the first trench gate on the substrate, the top of the second trench gate is in contact with the bottom of the first trench gate, and a gate layer in the second trench gate is connected with a gate layer in the first trench gate; each shielding region wraps the bottom and all the side walls of the second trench gate and extends towards the surface of the side, away from the substrate, of the epitaxial layer so as to cover the side wall of the first trench gate, and the multiple shielding regions are arranged at intervals. The shielding region has a three-dimensional structure, so that the stress of a trench gate oxide electric field can be reduced, the cell size of the MOSFET can be reduced, and the current density of the MOSFET can be improved.

The utility model provides a trench gate silicon carbide VDMOS with low on-resistance. The trench gate silicon carbide VDMOS is characterized in that the lower side surface of a drift layer is connected to the upper side surface of a silicon carbide substrate; the lower side of the P-type source region is connected to the upper side of the drift layer; the freewheeling region is connected to the drift layer, and the freewheeling region is connected to the P-type source region; a groove is formed in the follow current area, and a masking layer is arranged at the bottom of the groove; a P-type well region and an N-type source region are arranged in the follow current region, and the upper side surface of the P-type well region is connected to the lower side surface of the N-type source region; the lower portion of the gate dielectric layer is arranged in the groove, the outer side of the gate dielectric layer is connected with the N-type source region and the P-type well region, and the lower side face of the gate dielectric layer is connected to the upper side face of the masking layer; a groove is formed in the gate dielectric layer; the gate metal layer is arranged in the groove; the source electrode metal layer is respectively connected with the P-type source region, the follow current region and the N-type source region; the drain metal layer is connected to the lower side surface of the silicon carbide substrate; the on-resistance of the device can be effectively reduced, the body diode conduction loss of the device is reduced, and the switching speed of the device is improved.

The embodiment of the invention discloses a semiconductor device, a manufacturing method, a power module, a power conversion circuit and a vehicle. The semiconductor device includes a semiconductor body including a first surface, a second surface, a first device region, and a second device region; the first device region comprises a well region, a first region and a channel layer, and the first region is in contact with the channel layer; a gate trench; a first insulating layer; a first trench located in the second device region; the second device region further comprises a second insulating layer and a filling layer; a trench gate; an interlayer insulating layer; a Schottky metal layer; a drain electrode; and a source electrode. According to the technical scheme of the embodiment of the invention, the depletion type semiconductor device is formed and is in a conducting state and a cut-off state in a normal state, negative voltage needs to be applied between the grid electrode and the source electrode to cut off the channel, the response can be faster, the current circulation can be controlled, and the conducting loss is smaller. And a Schottky structure is integrated, so that the forward conduction voltage drop of the device is reduced, and the energy loss of the device in a reverse follow current state is reduced.

The invention provides a high-reliability super-junction trench gate silicon carbide VDMOS (Vertical Double-diffused Metal Oxide Semiconductor) with voltage higher than 3kV and a preparation method thereof. The method comprises the following steps: depositing metal on the lower side surface of a silicon carbide substrate to form a drain metal layer, and epitaxially growing on the upper side surface of the silicon carbide substrate to form a buffer region; performing epitaxial growth on the buffer region to obtain a first drift region; performing ion implantation to form a P-type region; removing the barrier layer, and performing epitaxial growth on the first drift region to obtain a second drift region; forming a barrier layer, and performing etching and ion implantation to form a P-type well region, a P + region and an N-type source region; etching the P-type well region and the N-type source region to form a first groove; etching the N-type source region, and then depositing metal to form a source metal layer; oxidizing to form an insulating dielectric layer, wherein a groove is formed in the insulating dielectric layer; and depositing metal, forming a gate metal layer, removing the barrier layer, and completing preparation. The voltage endurance capability and reliability of the device are improved by constructing a device gate and a source which are comprehensively wrapped by a P-type well region and a P-type region.

The invention discloses a semiconductor device which comprises a cellular structure, and the cellular structure comprises an N + substrate, an N-drift layer and a functional area. The N-drift layer is located on the N + substrate; the functional region is embedded into one side, away from the N + substrate, of the N-drift layer, the functional region comprises two subunits and a second N + source region, and each subunit comprises a P + contact region, a P-type body region, a first N + source region and a first trench gate structure; the first N + source region is located on the P-type body region, the first groove is located between the P-type body region and the P + contact region, the first gate oxide layer covers the inner wall of the first groove, a first filling groove is formed in the inner wall of the first gate oxide layer, the first gate is filled in the first filling groove, and the P + shielding region of the P + contact region covers the bottom of the first gate oxide layer; and a second N + source region is arranged between the first trench gate structures of the two subunits. According to the device, the effective utilization rate of a channel can be improved, the specific on-resistance is further reduced, and the problem of long reverse recovery time is solved.

The invention belongs to the technical field of power semiconductors, and relates to a 1200V SiC trench-type MOSFET (Metal-Oxide-Semiconductor Field Effect Transistor) integrated with a super junction and shield gate technology, which comprises an N + substrate layer, a drift region positioned above the N + substrate layer, and a trench gate structure and a source structure positioned above the drift region, compared with a conventional SiC trench type MOSFET with a P-type shielding layer, the SiC trench type MOSFET with the P-type shielding layer has the advantages that the peak electric field of the gate oxide layer is reduced, and the reliability of the device is ensured; the drift region adopts a super-junction structure, so that the electric field distribution is optimized, the blocking capability of the device is improved, the high doping concentration of the drift region can be adopted while the high breakdown voltage is maintained, the specific on-resistance of the device is remarkably reduced, and the conduction loss of the device is reduced; a shield gate structure is adopted, and the overlapping area of the gate and the drain is reduced, so that the gate-drain capacitance and the gate-drain charge are reduced, the switching speed of the device is improved, and the dynamic loss of the device is reduced. The performance is excellent in the high-voltage and high-frequency field.

The invention discloses a trench separation gate field effect transistor. The trench separation gate field effect transistor comprises a multi-stage step trench structure. The first-stage groove structure comprises a gate dielectric layer formed on the side face of the gate groove, a first dielectric layer on the surface of the bottom and a filled gate conductive material layer. The second-stage groove structure comprises a plurality of source electrode grooves, source dielectric layers and source electrode conductive material layers, wherein the source dielectric layers and the source electrode conductive material layers are formed in the source electrode grooves. First spacer regions are arranged among the source trenches, and the sum of the widths of all the source trenches and the first spacer regions is smaller than the width of the gate trench. A first buried layer and a second buried layer doped with a first conductive type and a second conductive type are formed at the top and the bottom of the first spacer region, and the second buried layer further wraps the bottom corners of the adjacent source trenches on the two sides. The gate conductive material layer is connected to the gate. Each source conductive material layer, the first buried layer and the second buried layer are connected to a source. The invention further discloses a manufacturing method of the trench separation gate field effect transistor. The invention can reduce the electric field intensity at the bottom of the gate trench.

To provide a semiconductor device capable of reducing on-resistance.SOLUTION: A semiconductor device 1 according to one embodiment includes: a semiconductor substrate 11 of a first conductivity type; and a semiconductor layer 12 of the first conductivity type, and the semiconductor layer includes: a trench gate 14, a source region 15 of the first conductivity type; a contact region 16 of a second conductivity type, and a column region 17 of the second conductivity type. In the semiconductor layer, a plurality of trench gates 14 are discretely formed along a first direction X and a second direction Y; the source region 15 is in contact with the trench gates 14 and surrounds the trench gates 14; the contact region 16 is located between the source regions adjacent in the second direction Y; and the column region 17 extends from an end 16a of the contact region 16 closer to the semiconductor substrate toward the semiconductor substrate 11.SELECTED DRAWING: Figure 3

The invention provides a low-driving-voltage trench gate silicon carbide VDMOS and a preparation method thereof, and the method comprises the steps: depositing metal on the lower side surface of a silicon carbide substrate, and forming a drain metal layer; epitaxially growing on the upper side surface of the silicon carbide substrate to form a drift layer; forming a barrier layer, etching, performing ion implantation, and forming a masking layer, a P-type well region, a P-type base region, a P-type source region and an N-type source region; a barrier layer is formed again, the barrier layer is etched to form a through hole, the drift layer is etched to the upper side face of the N-type source region, metal is deposited, and a source electrode metal layer is formed; re-forming a barrier layer, etching the barrier layer to form a through hole, etching the drift layer to the upper side surface of the masking layer, and depositing to form an insulating dielectric layer; and forming a barrier layer again, etching the barrier layer to form a through hole, etching the insulating dielectric layer to form a groove, depositing metal, forming a gate metal layer, removing the barrier layer, completing preparation, reducing the driving voltage of the device, and reducing the driving loss of the device. The device reliability is improved.

A method of manufacturing an electronic device, comprising the steps of: forming, on a first side (102a) of a solid body (101, 102) of Silicon, a first covering layer (104a) of SiO2; forming, on the first covering layer (104a), a second covering layer (104b) of SiN; forming, on the second covering layer (104b), a third covering layer (104c) of TEOS; forming a passing opening through the first, second and third covering layers (104a-104c); forming a trench (106) at the portion of the solid body exposed through the opening; grow a sacrificial layer (114), of said first oxide, within the trench (106); and perform in the order: selectively etch part of the second covering layer (104b), completely remove the sacrificial layer (114) and the third covering layer (104c) in one or more contextual etching steps.

The invention provides a semiconductor device with a trench gate and a forming method thereof, and the method comprises the steps: firstly executing a first exposure process and a first etching process to form a bottom gate oxide of a trench, then forming a monocrystalline silicon layer, executing a second exposure process and a second etching process to form a trench, exposing the top surface of the bottom gate oxide through the trench, and then forming the trench gate, the trench gate is located in the trench and located on the bottom gate oxide, the first exposure process and the second exposure process adopt the same mask, and the polarity of the second photoresist layer is opposite to that of the first photoresist layer. The unexpected effects of the invention are that the thickness of the bottom gate oxide of the groove can be more conveniently controlled, the bottom gate oxide of the groove is firstly formed, and then the monocrystalline silicon layer and the groove are formed, so that the problem that the bottom gate oxide is easy to seal in advance due to a high-density plasma process after the groove is formed is avoided, the process difficulty can be simplified, and the production efficiency is improved. And meanwhile, the possibility of thick bottom gate oxide is provided for the MOS device with a small critical size, and the density of the device can be improved.

The invention provides a 5KV high-reliability trench gate silicon carbide VDMOS and a preparation method thereof, and the method comprises the steps: depositing metal, and forming a drain metal layer; performing epitaxial growth to form a buffer layer and a drift layer; forming a barrier layer above the drift layer, and performing etching and ion implantation to form a P-type region; performing epitaxial growth to form an epitaxial layer; forming a barrier layer, etching, performing ion implantation, and forming a P + region, a P-type well region, an N-type region, a P-type shielding layer and an N-type source region; etching the epitaxial layer, the masking layer and the N-type region to form a groove and a lug boss, then oxidizing to form an insulating dielectric layer, and forming a trench in the insulating dielectric layer; depositing metal to form a gate metal layer; etching the N-type source region and the P + region, depositing metal to form a source metal layer, and removing the barrier layer to complete preparation; by constructing an L-shaped grid control structure, a multi-layer P-type protection structure from a drain electrode to a source electrode is formed, the source electrode and the grid electrode are protected, and the low-resistance characteristic of the device is ensured by double conductive channels.

The utility model provides a low-on-resistance trench gate silicon carbide VDMOS. The low-on-resistance trench gate silicon carbide VDMOS is characterized in that the lower side surface of a drift layer is connected to the upper side surface of a silicon carbide substrate; a second P-type well region, a groove and a shielding layer are arranged in the drift layer, and a second N-type source region is arranged in the second P-type well region; the lower side surface of the first P-type well region is connected to the drift layer, the second P-type well region and the second N-type source region; the lower side surface of the first N-type source region is connected to the upper side surface of the first P-type well region; the lower portion of the gate dielectric layer is arranged in the groove, the outer side wall of the gate dielectric layer is connected with the first N-type source region, the first P-type well region and the drift layer, and a groove is formed in the gate dielectric layer; the source metal layer is respectively connected with the first N-type source region, the first P-type well region, the drift layer, the second P-type well region and the second N-type source region; the gate metal layer is arranged in the groove; and the drain metal layer is connected to the lower side surface of the silicon carbide substrate to construct a second N-type source region and a second P-type well region for providing a large number of electrons in the drift layer and reducing the on-resistance of the device.

The invention discloses a manufacturing method of a trench gate semiconductor power device. The manufacturing method comprises the following steps: forming a first hard mask layer on a first epitaxial layer; and performing graphical etching on the first hard mask layer to open the forming region of the gate trench. And etching the first epitaxial layer to form a gate trench. And after the first hard mask layer is removed, performing a first thermal oxidation process to form a first field oxide layer on the inner side surface of the gate trench and the outer surface of the gate trench. And performing a first CVD growth process to form a second field oxide layer, and overlapping the first field oxide layer and the second field oxide layer to form a third field oxide layer. And performing a first CMP process to remove the third field oxide layer outside the gate trench. And forming a first polycrystalline silicon layer to completely fill the gate trench and extend out of the gate trench. And performing a second CMP process to flatten the first polycrystalline silicon layer. The structure consistency of the gate trench region and the platform region can be improved at the same time, and the performance and the yield of the device can be comprehensively improved.

The invention provides a manufacturing method of a separation gate semiconductor device, which comprises the following steps of: providing a wafer with a back sealing layer, and the back sealing layer comprises an inner polycrystalline silicon layer, a middle oxide layer and an outer polycrystalline silicon layer which are superposed in sequence; forming a groove from the front surface of the wafer; forming a sacrificial oxide layer on the inner wall of the groove, and removing the sacrificial oxide layer by wet etching; a trench gate structure is formed in the trench, the trench gate structure comprises a shield gate oxide layer, shield gate polycrystalline silicon, a gate oxide layer and gate polycrystalline silicon which are formed in sequence, a first oxide layer, a first polycrystalline silicon layer, a second oxide layer and a second polycrystalline silicon layer are accumulated on the back face of the wafer in sequence, and the first oxide layer is combined on the surface of the outer polycrystalline silicon layer. According to the invention, the back sealing layer with a sandwich structure of polycrystalline silicon, an oxide layer and polycrystalline silicon is adopted, the oxide layer on the back surface is retained due to the blocking of the polycrystalline silicon on the outer layer in the subsequent wet etching process, the warping degree of the wafer in the technological process is integrally improved, and various risks caused by warping in the measurement / technological process are reduced.

The invention discloses a semiconductor device and a manufacturing method thereof, a power module, a power conversion circuit, and a vehicle. The semiconductor device comprises a semiconductor body, wherein the semiconductor body further comprises a well region and a first region; the ion concentration of the well region is smaller than that of the first region; the first surface is also provided with a gate trench, and the gate trench extends into the semiconductor body from the first surface; the semiconductor body further comprises a first insulating layer which is located on the side wall of the gate trench. The two-dimensional conductive layer is located on the side wall of the gate trench; the two-dimensional conductive layer is at least located between the well region and the first insulating layer; and the trench gate is positioned on one side, far away from the semiconductor body, of the first insulating layer in the gate trench. According to the technical scheme, the on-resistance of the semiconductor device is reduced.

A semiconductor device includes: a plurality of first active trench gates extending in a first direction and facing a source layer and a base layer via a trench-gate insulating film; and a second active trench gate extending in a second direction that intersects the first direction and connecting the adjacent first active trench gates to each other. A gate wiring electrode is connected to a wide portion in the first active trench gate. The second active trench gate is disposed below the gate wiring electrode. A connection portion between the first active trench gate and the second active trench gate is T-shaped in plan view.

The invention discloses an insulated gate bipolar transistor device and a preparation process thereof, and the device comprises a substrate, a drain electrode which is formed below the substrate, a dielectric layer which is formed above the substrate, a source electrode which is formed above the dielectric layer, and a plurality of grooves which are formed in the substrate in a downward etching and sinking manner and are independently arranged, independent trench gates are deposited in the trenches, the cross section of the plurality of trenches is of a circular or annular or polygonal closed structure, and the trench gates are insulated and isolated from the side walls of the trenches and the source electrodes through dielectric layers. The novel groove type IGBT structure is achieved through the groove gates arranged in a circular layout mode, the structure has the advantages of being high in channel density, large in current density, simple in process and the like, and the chip area and the cost can be reduced while the current capacity is kept; or the current density and the power density of the device are improved while the chip area is maintained, and the on-state loss is reduced.

A semiconductor device includes a trench emitter electrode located at a boundary between one end of an active cell region and an inactive cell region, a trench gate electrode located at a boundary between the other end of the active cell region and the inactive cell region, an end trench gate electrode connected to one end of the trench gate electrode, and an end trench emitter electrode connected to one end of the trench emitter electrode. A hole barrier region of a first conductivity type is provided under a body region of a second conductivity type between the end trench gate electrode and the end trench emitter electrode in a plan view. A body region in the active cell region and a body region in the inactive cell region are connected to each other by a body region between the end trench gate electrode and the end trench emitter electrode.

The invention provides a silicon carbide device and a forming method thereof, the silicon carbide device comprises a silicon carbide substrate, a silicon carbide epitaxial layer is formed on the surface of the silicon carbide substrate, a plurality of buried doped regions are formed in the silicon carbide epitaxial layer, and the top surfaces of the buried doped regions are flush with the top surface of the silicon carbide epitaxial layer; the protection doped regions are located on the two sides of the buried doped region and connected with the buried doped region, and the doping type of the protection doped regions is opposite to the doping type of the silicon carbide epitaxial layer; the body doping layer is located on the surface of the silicon carbide epitaxial layer; the trench gate structures are located in the body doping layer and the silicon carbide epitaxial layer, the trench gate structures are located at the positions, connected with the protective doping region, of the two sides of the buried doping region, and the bottoms of the trench gate structures are wrapped by the buried doping region and the protective doping region respectively.

The invention discloses a groove SiC MOSFET device and a preparation method thereof. The preparation method comprises the following steps: epitaxial growth; performing P-type ion implantation for the first time; performing first-stage groove etching; performing N-type ion implantation; implanting P-type ions for the second time; carrying out second-stage groove etching; growing gate oxide, polycrystalline silicon and an interlayer insulating layer; carrying out metal deposition; the beneficial effects of the invention are that the multi-stage trench structure is combined with the plane gate and the trench gate, so that the channel density is increased, the current capability is provided, and the conduction loss is reduced; the MPS diode structure is integrated, the forward voltage drop of the body diode is reduced, the discharge capacity is improved when inrush current occurs in the circuit, the reverse follow current capacity can be improved through the parallel Schottky diode structure, and electronic elements needed by a peripheral circuit are reduced; by integrating the built-in field plate structure, the electric field concentration effect at the bottom of the trench gate is effectively relieved.

The present disclosure provides a trench gate semiconductor device and a manufacturing method therefor. Compared with the related art in which a gate oxide layer is formed by oxidizing a first epitaxial layer, in the embodiments of the present disclosure, the gate oxide layer is formed by oxidizing a prefabricated epitaxial layer, so as to address the problem of high roughness of trench sidewalls caused by the etching process during the forming the trench by means of etching on the first epitaxial layer, thereby reducing the influence of surface roughness scattering of the trench on channel mobility. Further, a shielding layer is arranged between the gate oxide layer on the outer bottom wall of the trench and the first epitaxial layer, so as to reduce the peak electric field at the bottom corners of the trench, thereby improving the breakdown voltage.

Provided is a semiconductor device in which on-resistance can be further reduced. This semiconductor device comprises a gate electrode, a contact region of a first conductivity type, and a drift layer having a super junction structure. The drift layer has a first stripe pattern in which first column layers of the first conductivity type and second column layers of a second conductivity type extending in a first direction are alternately arranged in a second direction. The gate electrode has a second stripe pattern in which a plurality of trench gates extending in the second direction are arranged in the first direction. The first stripe pattern and the second stripe pattern intersect in plan view. When the period of repetition of the first column layers or the second column layers is regarded as a first period, and the period of repetition of the trench gates is regarded as a second period, the second period is shorter than the first period. The contact region has a higher concentration of the first conductivity type than the first column layers and has a greater second-direction width than the first column layers.

In a trench gate type semiconductor device, a bottom layer is deepened while the space between adjacent trenches is suppressed from being blocked by the bottom layer. A semiconductor device is provided with: a plurality of trenches (51, 52) formed in a first main surface of a semiconductor substrate; and insulating films (11b, 12b, 21b, 72b) and electrodes (11a, 12a, 21a, 72a) formed in the plurality of trenches (51, 52). The plurality of trenches (51, 52) include a first trench (51) and a second trench (52), the depth of the second trench (52) being deeper than that of the first trench (51), and the width of the second trench (52) being wider than that of the first trench (51). A bottom layer (60) of a second conductivity type is disposed below the second trench (52), and the bottom layer (60) of the second conductivity type is in contact with the bottom of the second trench (52) and is not in contact with the first trench (51).

The invention discloses a trench gate silicon carbide MOSFET (Metal-Oxide-Semiconductor Field Effect Transistor). The top surface of a second conductive type doped first buried layer formed in a first conductive type doped silicon carbide epitaxial layer is lower than the bottom surface of a gate trench; and a heterojunction polycrystalline silicon layer filled in the second groove is formed on the outer side of the first side surface of the channel region. A lateral current path is made up of the silicon carbide epitaxial layer located over the top surface of the first buried layer, and a longitudinal current path is made up of the silicon carbide epitaxial layer located between the second side of the first buried layer and the bottom of the gate trench and forms a current path of the heterojunction diode together with the lateral current path. A plurality of first connecting layers are formed in a partial region where the first buried layer and the channel region are overlapped, intervals are formed between the first connecting layers in the length direction of the first buried layer, and interval regions are constituent parts of a transverse current path. The invention further discloses a manufacturing method of the trench gate silicon carbide MOSFET. According to the invention, the heterojunction diode can be integrated.

The invention discloses an anti-radiation reinforced IGBT (Insulated Gate Bipolar Translator) structure and a preparation method thereof, and relates to the technical field of power semiconductor devices. The IGBT structure comprises a collector electrode, a semiconductor layer, a trench gate and an emitter electrode, a P-type collector region of the semiconductor layer is provided with a plurality of deep doped regions, the deep doped regions are embedded into an N-type buffer region in the direction perpendicular to the interface of the N-type buffer region and extend into an N-type drift region, and the doping concentration of the deep doped regions is higher than that of other regions of the P-type collector region. According to the invention, the electron-hole recombination efficiency of the bottom region of the N-type drift region is enhanced through the arrangement of the deep doping region, and the number of deposited charges in the region is reduced, so that the radiation resistance of the IGBT device can be effectively improved, and the IGBT device is suitable for high-voltage direct-current power transmission requirements in high-altitude regions.

The invention belongs to the technical field of power semiconductor devices, and relates to a super-junction IGBT device with a split gate structure and a preparation method of the super-junction IGBT device. The device comprises collector metal, a P-type collector, an N-type field stop layer, a super junction N column, a super junction P column, a P-type buried layer, a trench gate structure and a trench emitter structure which are sequentially stacked from bottom to top, and the trench gate structure and the trench emitter structure are connected with an N-type charge storage layer, a P-type base region and an N + emitter region. The P columns / N columns of the device are alternately arranged in the Y direction, the cell width is reduced, meanwhile, the parasitic PMOS introduced by only adding one photoetching plate acts, and the device has high channel density and a wide short-circuit safe working area. In addition, the Miller capacitance of the super-junction IGBT is reduced, the negative gate capacitance effect is suppressed, the surge current of the device is reduced, and the control capability of the gate of the device on dv / dt is improved. According to the invention, an extra path is provided for redundant holes stored in the drift region, the turn-off speed of the device is obviously improved, and the switching loss is reduced.

The present disclosure provides a trench gate semiconductor device and a preparation method thereof. The trench gate semiconductor device comprises a substrate, a drift region and a body region. The drift region is arranged on the surface of the substrate and has a first conductivity type. The body region is epitaxially formed on the surface of the drift region away from the substrate and is an in-situ doped region with a second conductivity type. In the embodiment of the present disclosure, the body region is directly epitaxially formed, which can reduce the lattice damage in the body region, thereby reducing the interface defects between the body region and the gate oxide layer, and further improving the channel mobility. In addition, the tailing effect of the channel caused by ion implantation can be avoided, thereby improving the threshold voltage stability.