461 results about "Trench gate" patented technology

The invention provides a high-reliability super-junction trench gate silicon carbide VDMOS (Vertical Double-diffused Metal Oxide Semiconductor) with voltage higher than 3kV and a preparation method thereof. The method comprises the following steps: depositing metal on the lower side surface of a silicon carbide substrate to form a drain metal layer, and epitaxially growing on the upper side surface of the silicon carbide substrate to form a buffer region; performing epitaxial growth on the buffer region to obtain a first drift region; performing ion implantation to form a P-type region; removing the barrier layer, and performing epitaxial growth on the first drift region to obtain a second drift region; forming a barrier layer, and performing etching and ion implantation to form a P-type well region, a P + region and an N-type source region; etching the P-type well region and the N-type source region to form a first groove; etching the N-type source region, and then depositing metal to form a source metal layer; oxidizing to form an insulating dielectric layer, wherein a groove is formed in the insulating dielectric layer; and depositing metal, forming a gate metal layer, removing the barrier layer, and completing preparation. The voltage endurance capability and reliability of the device are improved by constructing a device gate and a source which are comprehensively wrapped by a P-type well region and a P-type region.

The invention discloses a semiconductor device which comprises a cellular structure, and the cellular structure comprises an N + substrate, an N-drift layer and a functional area. The N-drift layer is located on the N + substrate; the functional region is embedded into one side, away from the N + substrate, of the N-drift layer, the functional region comprises two subunits and a second N + source region, and each subunit comprises a P + contact region, a P-type body region, a first N + source region and a first trench gate structure; the first N + source region is located on the P-type body region, the first groove is located between the P-type body region and the P + contact region, the first gate oxide layer covers the inner wall of the first groove, a first filling groove is formed in the inner wall of the first gate oxide layer, the first gate is filled in the first filling groove, and the P + shielding region of the P + contact region covers the bottom of the first gate oxide layer; and a second N + source region is arranged between the first trench gate structures of the two subunits. According to the device, the effective utilization rate of a channel can be improved, the specific on-resistance is further reduced, and the problem of long reverse recovery time is solved.

The invention discloses a trench separation gate field effect transistor. The trench separation gate field effect transistor comprises a multi-stage step trench structure. The first-stage groove structure comprises a gate dielectric layer formed on the side face of the gate groove, a first dielectric layer on the surface of the bottom and a filled gate conductive material layer. The second-stage groove structure comprises a plurality of source electrode grooves, source dielectric layers and source electrode conductive material layers, wherein the source dielectric layers and the source electrode conductive material layers are formed in the source electrode grooves. First spacer regions are arranged among the source trenches, and the sum of the widths of all the source trenches and the first spacer regions is smaller than the width of the gate trench. A first buried layer and a second buried layer doped with a first conductive type and a second conductive type are formed at the top and the bottom of the first spacer region, and the second buried layer further wraps the bottom corners of the adjacent source trenches on the two sides. The gate conductive material layer is connected to the gate. Each source conductive material layer, the first buried layer and the second buried layer are connected to a source. The invention further discloses a manufacturing method of the trench separation gate field effect transistor. The invention can reduce the electric field intensity at the bottom of the gate trench.

To provide a semiconductor device capable of reducing on-resistance.SOLUTION: A semiconductor device 1 according to one embodiment includes: a semiconductor substrate 11 of a first conductivity type; and a semiconductor layer 12 of the first conductivity type, and the semiconductor layer includes: a trench gate 14, a source region 15 of the first conductivity type; a contact region 16 of a second conductivity type, and a column region 17 of the second conductivity type. In the semiconductor layer, a plurality of trench gates 14 are discretely formed along a first direction X and a second direction Y; the source region 15 is in contact with the trench gates 14 and surrounds the trench gates 14; the contact region 16 is located between the source regions adjacent in the second direction Y; and the column region 17 extends from an end 16a of the contact region 16 closer to the semiconductor substrate toward the semiconductor substrate 11.SELECTED DRAWING: Figure 3

The invention provides a semiconductor device with a trench gate and a forming method thereof, and the method comprises the steps: firstly executing a first exposure process and a first etching process to form a bottom gate oxide of a trench, then forming a monocrystalline silicon layer, executing a second exposure process and a second etching process to form a trench, exposing the top surface of the bottom gate oxide through the trench, and then forming the trench gate, the trench gate is located in the trench and located on the bottom gate oxide, the first exposure process and the second exposure process adopt the same mask, and the polarity of the second photoresist layer is opposite to that of the first photoresist layer. The unexpected effects of the invention are that the thickness of the bottom gate oxide of the groove can be more conveniently controlled, the bottom gate oxide of the groove is firstly formed, and then the monocrystalline silicon layer and the groove are formed, so that the problem that the bottom gate oxide is easy to seal in advance due to a high-density plasma process after the groove is formed is avoided, the process difficulty can be simplified, and the production efficiency is improved. And meanwhile, the possibility of thick bottom gate oxide is provided for the MOS device with a small critical size, and the density of the device can be improved.

The invention provides a 5KV high-reliability trench gate silicon carbide VDMOS and a preparation method thereof, and the method comprises the steps: depositing metal, and forming a drain metal layer; performing epitaxial growth to form a buffer layer and a drift layer; forming a barrier layer above the drift layer, and performing etching and ion implantation to form a P-type region; performing epitaxial growth to form an epitaxial layer; forming a barrier layer, etching, performing ion implantation, and forming a P + region, a P-type well region, an N-type region, a P-type shielding layer and an N-type source region; etching the epitaxial layer, the masking layer and the N-type region to form a groove and a lug boss, then oxidizing to form an insulating dielectric layer, and forming a trench in the insulating dielectric layer; depositing metal to form a gate metal layer; etching the N-type source region and the P + region, depositing metal to form a source metal layer, and removing the barrier layer to complete preparation; by constructing an L-shaped grid control structure, a multi-layer P-type protection structure from a drain electrode to a source electrode is formed, the source electrode and the grid electrode are protected, and the low-resistance characteristic of the device is ensured by double conductive channels.

The invention discloses a manufacturing method of a trench gate semiconductor power device. The manufacturing method comprises the following steps: forming a first hard mask layer on a first epitaxial layer; and performing graphical etching on the first hard mask layer to open the forming region of the gate trench. And etching the first epitaxial layer to form a gate trench. And after the first hard mask layer is removed, performing a first thermal oxidation process to form a first field oxide layer on the inner side surface of the gate trench and the outer surface of the gate trench. And performing a first CVD growth process to form a second field oxide layer, and overlapping the first field oxide layer and the second field oxide layer to form a third field oxide layer. And performing a first CMP process to remove the third field oxide layer outside the gate trench. And forming a first polycrystalline silicon layer to completely fill the gate trench and extend out of the gate trench. And performing a second CMP process to flatten the first polycrystalline silicon layer. The structure consistency of the gate trench region and the platform region can be improved at the same time, and the performance and the yield of the device can be comprehensively improved.

The invention discloses a groove SiC MOSFET device and a preparation method thereof. The preparation method comprises the following steps: epitaxial growth; performing P-type ion implantation for the first time; performing first-stage groove etching; performing N-type ion implantation; implanting P-type ions for the second time; carrying out second-stage groove etching; growing gate oxide, polycrystalline silicon and an interlayer insulating layer; carrying out metal deposition; the beneficial effects of the invention are that the multi-stage trench structure is combined with the plane gate and the trench gate, so that the channel density is increased, the current capability is provided, and the conduction loss is reduced; the MPS diode structure is integrated, the forward voltage drop of the body diode is reduced, the discharge capacity is improved when inrush current occurs in the circuit, the reverse follow current capacity can be improved through the parallel Schottky diode structure, and electronic elements needed by a peripheral circuit are reduced; by integrating the built-in field plate structure, the electric field concentration effect at the bottom of the trench gate is effectively relieved.

The present disclosure provides a trench gate semiconductor device and a manufacturing method therefor. Compared with the related art in which a gate oxide layer is formed by oxidizing a first epitaxial layer, in the embodiments of the present disclosure, the gate oxide layer is formed by oxidizing a prefabricated epitaxial layer, so as to address the problem of high roughness of trench sidewalls caused by the etching process during the forming the trench by means of etching on the first epitaxial layer, thereby reducing the influence of surface roughness scattering of the trench on channel mobility. Further, a shielding layer is arranged between the gate oxide layer on the outer bottom wall of the trench and the first epitaxial layer, so as to reduce the peak electric field at the bottom corners of the trench, thereby improving the breakdown voltage.

In a trench gate type semiconductor device, a bottom layer is deepened while the space between adjacent trenches is suppressed from being blocked by the bottom layer. A semiconductor device is provided with: a plurality of trenches (51, 52) formed in a first main surface of a semiconductor substrate; and insulating films (11b, 12b, 21b, 72b) and electrodes (11a, 12a, 21a, 72a) formed in the plurality of trenches (51, 52). The plurality of trenches (51, 52) include a first trench (51) and a second trench (52), the depth of the second trench (52) being deeper than that of the first trench (51), and the width of the second trench (52) being wider than that of the first trench (51). A bottom layer (60) of a second conductivity type is disposed below the second trench (52), and the bottom layer (60) of the second conductivity type is in contact with the bottom of the second trench (52) and is not in contact with the first trench (51).

The invention discloses a trench gate silicon carbide MOSFET (Metal-Oxide-Semiconductor Field Effect Transistor). The top surface of a second conductive type doped first buried layer formed in a first conductive type doped silicon carbide epitaxial layer is lower than the bottom surface of a gate trench; and a heterojunction polycrystalline silicon layer filled in the second groove is formed on the outer side of the first side surface of the channel region. A lateral current path is made up of the silicon carbide epitaxial layer located over the top surface of the first buried layer, and a longitudinal current path is made up of the silicon carbide epitaxial layer located between the second side of the first buried layer and the bottom of the gate trench and forms a current path of the heterojunction diode together with the lateral current path. A plurality of first connecting layers are formed in a partial region where the first buried layer and the channel region are overlapped, intervals are formed between the first connecting layers in the length direction of the first buried layer, and interval regions are constituent parts of a transverse current path. The invention further discloses a manufacturing method of the trench gate silicon carbide MOSFET. According to the invention, the heterojunction diode can be integrated.

The invention discloses an anti-radiation reinforced IGBT (Insulated Gate Bipolar Translator) structure and a preparation method thereof, and relates to the technical field of power semiconductor devices. The IGBT structure comprises a collector electrode, a semiconductor layer, a trench gate and an emitter electrode, a P-type collector region of the semiconductor layer is provided with a plurality of deep doped regions, the deep doped regions are embedded into an N-type buffer region in the direction perpendicular to the interface of the N-type buffer region and extend into an N-type drift region, and the doping concentration of the deep doped regions is higher than that of other regions of the P-type collector region. According to the invention, the electron-hole recombination efficiency of the bottom region of the N-type drift region is enhanced through the arrangement of the deep doping region, and the number of deposited charges in the region is reduced, so that the radiation resistance of the IGBT device can be effectively improved, and the IGBT device is suitable for high-voltage direct-current power transmission requirements in high-altitude regions.

The present disclosure provides a trench gate semiconductor device and a preparation method thereof. The trench gate semiconductor device comprises a substrate, a drift region and a body region. The drift region is arranged on the surface of the substrate and has a first conductivity type. The body region is epitaxially formed on the surface of the drift region away from the substrate and is an in-situ doped region with a second conductivity type. In the embodiment of the present disclosure, the body region is directly epitaxially formed, which can reduce the lattice damage in the body region, thereby reducing the interface defects between the body region and the gate oxide layer, and further improving the channel mobility. In addition, the tailing effect of the channel caused by ion implantation can be avoided, thereby improving the threshold voltage stability.

The present application belongs to the technical field of semiconductor, and particularly relates to a trench gate SiC MOSFET and a preparation method thereof. The preparation method of the trench gate SiC MOSFET forms a relatively thick N-type doping layer below the groove bottom of the gate groove. In the subsequent gate oxide process, the relatively thick N-type doping layer generates more electrons, which accelerates the oxidation of SiC. After the gate oxide process, the thickness of the gate oxide formed at the bottom of the gate groove is obviously thicker than that at the channel sidewall position. The relatively thick gate oxide enhances the tolerance of the device to high voltage, and reduces Qgd (the charge amount of the gate-drain), thereby improving the switching speed of the device.

The utility model provides an IGBT device, which comprises a semiconductor structure, a collector region, a second trench gate structure, an emitter, a first gate, a second gate and a collector, and is characterized in that the semiconductor structure comprises a base region, an emitter region, a first trench gate structure, a field stop layer and a drift region; the collector region is located on the lower surface of the field stop layer; the second trench gate structure penetrates through the collector region and comprises a back gate trench, a first dielectric layer, a second dielectric layer, a shielding gate layer, an isolation layer and a back gate conductive layer, the back gate trench penetrates through the collector region, the first dielectric layer covers the inner wall and the bottom surface of the bottom of the back gate trench, the shielding gate layer fills the bottom of the back gate trench, the isolation layer covers the bottom surface of the shielding gate layer, and the back gate conductive layer covers the bottom surface of the shielding gate layer. The second dielectric layer covers the inner wall of the remaining back gate groove, and the remaining back gate groove is filled with the back gate conductive layer; and each electrode is electrically connected with the corresponding area. According to the utility model, through the arrangement of the second trench gate structure, the voltage turn-back phenomenon during the forward conduction of the device is avoided, and the turn-off loss of the device is reduced.

To provide a semiconductor device that installs a plurality of recesses in a first surface of a semiconductor layer to increase the contact area of the conductive layer with a source region per unit area, and thereby reduces source contact resistance.SOLUTION: A semiconductor device includes a semiconductor layer, a trench gate structure including a gate dielectric layer 151 and a gate conductor 152, and a conductive layer 170. The semiconductor layer has a first surface 10 and a second surface 20 facing each other, and includes a source region 130, a body region 110, and a drift region 101. At least part of the trench gate structure is located on a trench of the first surface of the semiconductor layer. The source region extends toward a direction from the first surface to the second surface. The first surface of the semiconductor layer has a plurality of recesses. The conductive layer is adjacent to the first surface and extends to the plurality of recesses.SELECTED DRAWING: Figure 3

The invention relates to the technical field of semiconductors, and provides an MOS (Metal Oxide Semiconductor) device and a preparation method thereof. The epitaxial layer is arranged on the substrate and has a first doping type; the current adjusting layer is arranged in the epitaxial layer and has a first doping type, the doping concentration of the current adjusting layer is larger than that of the epitaxial layer, and the current adjusting layer comprises a plurality of first current adjusting parts which are arranged at intervals in the direction parallel to the substrate; the base regions are of a second doping type, the second doping type is opposite to the first doping type, and the multiple base regions are arranged in the epitaxial layer at intervals and located on the side, away from the substrate, of the current adjusting layer; the well region with the second doping type and the source region with the first doping type are arranged in the base region; and the trench gate structure is at least partially arranged in the interval between the adjacent base regions, and the trench gate structure extends into the current adjusting layer and is in contact with the first current adjusting part.

The application discloses a trench gate semiconductor device and a manufacturing method thereof, and is used for improving the reliability of the trench gate semiconductor. The trench gate semiconductor comprises a substrate with a first conductive type; an epitaxial layer with the first conductive type, which is grown on the substrate; a well region with a second conductive type, which is formed on a surface layer of the epitaxial layer; a source region with the first conductive type, which is formed on a surface layer of the well region; a first trench, which extends from a surface of the source region to the epitaxial layer through the well region; a gate, which is formed in the first trench through a gate insulating film; and an amorphous semiconductor layer, which is formed in the first trench and wraps an outer bottom wall of the gate and corner portions on both sides of the outer bottom wall through the gate insulating film, and the amorphous semiconductor layer is composed of a low dielectric constant material.

A semiconductor device including a semiconductor layer and a trench gate structure is provided. The semiconductor layer includes: a source region, a drift region, and a body region. The first part of the body region is located between the source region and the drift region, the first part of the body region and the source region both adjoin a first sidewall of the trench gate structure. The third part of the body region is located between a bottom surface of the trench gate structure and the second surface, at least part of the bottom surface of the trench gate structure is separated from the third part of the body region by the drift region. By separating the third part of the body region from the bottom surface along a vertical direction, electric field distribution at a bottom of a trench and near corner is adjusted.

The invention discloses a micro trench gate IGBT device structure and a preparation method thereof, the device structure comprises a wafer substrate, a gate oxide layer, a polycrystalline silicon layer, a dielectric layer and a metal layer, trenches are formed on the wafer substrate, and the trenches comprise a gate trench and a virtual gate trench; the gate oxide layer covers the surface of the wafer substrate; the polycrystalline silicon layer is filled in the groove; the dielectric layer covers the gate oxide layer and the polycrystalline silicon layer; a contact hole is formed in the dielectric layer and extends into the wafer substrate and the polycrystalline silicon layer; the coverage area of the contact hole comprises a part of the virtual gate trench, a part of the wafer substrate and a gate oxide layer at the junction; the metal layer is stacked on the surface of the dielectric layer and fills the contact hole. According to the invention, the short circuit of the virtual gate and the source electrode is realized through one contact hole, and the requirement on the photoetching line width is reduced, so that photoetching can be carried out by using an I-line photoetching machine, the preparation cost is reduced, and the compatibility of wafer flatness and warping degree can be improved by using the I-line photoetching machine process.

The invention discloses a preparation method of a silicon carbide trench gate type MOSFET (Metal-Oxide-Semiconductor Field Effect Transistor) power device. The preparation method comprises six steps of substrate buffer layer deposition, gate oxide layer preparation, trench etching, gate metal layer deposition, source and drain region ion implantation and source and drain metal layer deposition and annealing. In the preparation process, a multi-physics field coupling dynamic thermal resistance model, a multi-working-condition thermal reliability boundary algorithm, a full-working-area variable temperature parameter fitting model and a power device multi-parameter calibration platform are integrated, technological parameters of all steps are set through model calculation and algorithm analysis, and key performance parameters of the device are detected in real time and dynamically adjusted by means of the calibration platform. According to the method, the problems of non-uniform heat distribution, stress concentration, insufficient parameter fitting and calibration deficiency in traditional preparation are solved, the interface bonding quality of the buffer layer and the metal layer and the electrical property consistency of the device are improved, the thermal reliability and the working efficiency of the device are enhanced, and the application requirement of a high-voltage high-power power electronic system for a core device is met.

The invention belongs to the technical field of semiconductors, and particularly relates to an IGBT device which comprises a device cell unit. The device cellular unit comprises a collector electrode, a P + region arranged on the collector electrode, a buffer region arranged on the P + region, a drift region arranged on the buffer region, a P-base arranged on the drift region, an N + region arranged in the P-base, and an emitter electrode arranged on the N + region and the P-base. When the device is conducted, the N-type region provides a low-resistance path for electrons to enter the drift region from a channel, the electron concentration of the drift region is increased, a large number of injected electrons attract more holes to be injected into the drift region from a collector electrode, the resistance of the drift region under high blocking voltage is remarkably reduced, and compared with a traditional plane gate IGBT or even a standard trench gate IGBT, the IGBT has the advantages that the reliability is high, and the reliability is high. According to the structure, lower conduction voltage drop can be realized, so that power loss and heating in a conduction state are reduced.

The disclosure relates to a π type trench gate silicon carbide MOSFET device and a fabrication method thereof. To protect a trench gate oxide layer without increasing a channel resistance and process complexity, a second conductivity type of heavily doped deep well inserted with double gate trenches along the sidewalls of deep well is designed. The deep well is connected to the source metal directly. The electric potential is clamped to the source during the voltage blocking and turn-off state, which reduces the electric field in the gate oxide and reduces the miller capacitance. An interlayer dielectric layer is deposited above the conductive dielectric polysilicon layers and extends outward separately to cover a part of the source region. A smaller cell pitch can be achieved by controlling the spacing between the first and the second trench gate, thereby increasing the channel density and reducing the channel resistance.

The utility model provides a trench gate silicon carbide VDMOS of a trench source electrode. The trench gate silicon carbide VDMOS comprises a drift layer connected to a silicon carbide substrate; the drift layer is provided with a first protruding part, the first protruding part is provided with a second protruding part, and the second protruding part is provided with a groove; the low-resistance region is connected to the drift layer, and the low-resistance region is connected to the first lug boss; the P-type well region is connected to the low-resistance region, the drift layer, the first lug boss and the second lug boss; an N-type source region is arranged on the P-type well region; the P-type source region is connected to the P-type well region; the lower part of the insulating dielectric layer is arranged in the groove, and the insulating dielectric layer is respectively connected with the P-type well region and the N-type source region; a groove is formed in the insulating medium layer; the gate metal layer is arranged in the groove; the source metal layer is respectively connected with the P-type source region, the P-type well region and the N-type source region; the drain metal layer is connected to the silicon carbide substrate; the gate reliability problem of the trench gate is solved, extra electrodes do not need to be led out, the follow current capability of the body diode is improved, and the on-resistance of the device is reduced.

The application discloses a trench gate power MOSFET device with anti-single event burnout reinforcement and a preparation method thereof, which comprises the following steps: etching a deep trench at a center position of the device and forming a P-type shielding area and depositing N-type polysilicon; forming a current expansion layer between a boron-doped area and an N-type drift area by means of ion implantation; and forming a P-type high-concentration doped area and an N-type high-concentration source area above the boron-doped area by means of ion implantation. According to the technical scheme, the internal electric field of the device can be modulated, the electric field distribution on the heavy ion incident track is smoother, the instantaneous power density of the device is reduced, the local high temperature is reduced, the trench oxide layer is protected from high temperature, the forward conduction capability of the device is improved, and the anti-single event burnout capability of the device can be remarkably improved without sacrificing the basic electrical characteristics of the device.

The invention relates to a semiconductor component (500) having a gate structure (150) which extends from a first surface (101) into a silicon carbide body (100), a width (w1) of the gate structure (150) in a first horizontal direction (191) parallel to the first surface (101) being smaller than a vertical extension (v1) of the gate structure (150) perpendicular to the first surface (101). Contact structures (315) extend from the first surface (101) into the silicon carbide body (100), wherein the gate structures (150) and the contact structures (315) alternate in a first horizontal direction (191). A shielding region (160) in the silicon carbide body (100) abuts a bottom of the contact structure (315) and is spaced apart from the gate structure (150) along a first horizontal direction (191).

The application discloses a trench Schottky contact area wet etching control method, which comprises the following steps: depositing an anti-etching layer on the surface of a wafer with a poly etching trench gate structure; depositing an oxidation layer on the anti-etching layer; performing contact area photoetching on the wafer; placing the wafer into an etching device to etch and remove the oxidation layer on the anti-etching layer in the contact area; and placing the wafer into a dry etching machine to etch the anti-etching layer and the gate oxide structure. The method can effectively control the etching amount in the wet etching process, realizes the control of the gate oxide height when etching the contact area oxidation layer of the trench Schottky structure, and further guarantees the high-voltage stability and high-speed switching performance of the device.

The invention discloses a semiconductor device and a manufacturing method thereof, a power module, a power conversion circuit and a vehicle. The manufacturing method comprises the following steps: providing a semiconductor body which comprises a first surface and a second surface which are oppositely arranged; a well region and a first region are formed on the semiconductor body, the first region is located on the first surface, and the well region is located on one side of the first region away from the first surface; forming a gate trench on the first surface; performing primary ion implantation on the semiconductor body to form a third sub-region, and then performing secondary ion implantation to form a second region; the second region and the third sub-region are located at the bottom of the gate trench, the position of the second region is the same as the position of the third sub-region, and the implanted ion conduction type of the primary ion implantation is opposite to the implanted ion conduction type of the secondary ion implantation; and forming a grid electrode in the grid electrode groove. According to the embodiment of the invention, the voltage endurance capability of the gate oxide layer of the trench gate can be improved, and the reliability of the semiconductor device is improved.

The present invention relates to the technical field of semiconductors, and provides a MOSFET device and a manufacturing method therefor, and a layout arrangement structure. A P-type buried layer is disposed within an N-type voltage-withstanding layer between the bottom of a trench and a substrate, and the P-type buried layer is electrically connected to a source, thereby solving the problem of insufficient electric field protection at the bottom of a trench gate and achieving effective protection of a gate dielectric layer under a high drain voltage. In addition, because a gap exists between the P-type buried layer and the bottom of a channel, current can still flow between the bottom of the trench and the P-type buried layer, and the design of the P-type buried layer does not hinder current flow, thereby comprehensively improving the operational performance of the MOSFET device.

Provided is a semiconductor device that improves control of dV / dt and reduces on-state loss. A transistor and a diode are formed on a common semiconductor substrate, and the semiconductor substrate has a transistor region and a diode region. The diode region has: a first semiconductor layer of an n type provided on a second main surface side of the semiconductor substrate; a second semiconductor layer of an n type provided on the first semiconductor layer; a third semiconductor layer of a p type provided on a first main surface side of the semiconductor substrate compared to the second semiconductor layer; a first main electrode that applies a first potential to the diode; a second main electrode that applies a second potential to the diode; and a dummy active trench gate provided so as to reach the second semiconductor layer from the first main surface of the semiconductor substrate. The dummy active trench gate has the third semiconductor layer, which is not applied with the first potential but is in a floating state, on at least one of both side surfaces, and a gate potential of the transistor is applied to the dummy active trench gate.