Semiconductor device and a method of manufacturing the same

Abstract

A technology is provided to reduce ON-resistance, and the prevention of punch through is achieved with respect to a trench gate type power MISFET. Input capacitance and a feedback capacitance are reduced by forming a groove in which a gate electrode is formed so as to have a depth as shallow as about 1 μm or less, a p−type semiconductor region is formed to a depth so as not to cover the bottom of the groove, and a p-type semiconductor region higher in impurity concentration than the p−type semiconductor region is formed under a n+type semiconductor region serving as a source region of the trench gate type power MISFET, causing the p-type semiconductor region to serve as a punch-through stopper layer of the trench gate type power MISFET.

Description

CROSS-REFERENCE TO RELATED APPLICATION The present application claims priority from Japanese Patent application JP 2003-286142 filed on Aug. 4, 2003, the content of which is hereby incorporated by reference as if set forth in the entirety herein. FIELD OF THE INVENTION The invention relates to a semiconductor device and for a method of manufacturing the same, and in particular, to a semiconductor device and method employing power MISFETs (Metal Insulator Semiconductor Field Effect Transistors). BACKGROUND OF THE INVENTION In the case of a trench (groove) gate type power MOSFET (Metal Oxide Semiconductor Field Effect Transistor) formed in a structure incorporating, for example, a p-type epitaxial layer as an upper layer of an n+type substrate, it is known to reduce the risk of punch-through breakdown of the trench gate by forming an n-type drain region extended between the n+type substrate and the bottom of a trench, and by forming a junction of the n-type drain region and the p-t...

AI Technical Summary

Benefits of technology

"The patent text describes a power MISFET that is used in a DC-DC converter. The text discusses the problem of reducing capacitance in the power MISFET to minimize switching loss and drive loss in the converter. The text proposes a solution to reduce the input capacitance and feedback capacitance of the power MISFET by narrowing the width of the groove in which the gate is formed and reducing the distance of the portion of the groove extending from the p-type semiconductor region towards the n-type single crystal silicon layer. The technical effect of this solution is to improve the performance and efficiency of the DC-DC converter."

Problems solved by technology

Accordingly, there is a trend for a DC-DC converter towards higher frequency, and as the DC-DC converter operates higher in frequency, an increase in switching loss and drive loss may occur in a power MISFET.

Images