182 results about "Power MOSFET" patented technology

An apparatus includes a drain and a source on opposing sides of an epitaxial layer, a body region and a plurality of gates formed in the epitaxial layer, an interlayer dielectric layer over the epitaxial layer, a gate-source electrostatic discharge (ESD) diode in the interlayer dielectric layer, a source contact connected to the source and a first terminal of the gate-source ESD diode structure, a gate contact connected to the plurality of gates and a second terminal of the gate-source ESD diode structure, a drain contact on opposing sides of the epitaxial layer of the source contact, a breakdown voltage enhancement and leakage prevention structure formed underneath the gate-source ESD diode structure, wherein the breakdown voltage enhancement and leakage prevention structure comprises a body ring structure.

A power inverter is provided. The power inverter includes: first, second and third legs configured to output alternating voltages having different phases. Each the first leg, the second leg, and the third leg includes: a first power metal oxide semiconductor field effect transistor (MOSFET) on a SiC substrate, and connected between a power terminal of direct current voltage and an output terminal configured to output a voltage of a corresponding phase among the first phase, the second phase and the third phase; a second power MOSFET on the SiC substrate, and connected between the output terminal and a ground terminal; and a redundancy circuit including a redundancy power transistor configured to replace the first power MOSFET based on the first power MOSFET failing and replace the second power MOSFET based on the second power MOSFET failing.

A system and a method for controlling a power MOSFET for limiting electromagnetic interference from a load is provided. The system and method include a pulse-width-modulated (PWM) control voltage to operate the power MOSFET in accordance with its Ohmic region (linear mode). By operating the power MOSFET in its Ohmic region, the electromagnetic field generated by the load is reduced, without requiring a dedicated DC / DC converter that would otherwise increase the cost, size, and weight of the power electronics.

The invention relates to a low-power-consumption high-performance D-type power amplifier modulation method and circuit and a D-type audio power amplifier, and the method comprises the steps: separating a pair of BD mode modulated signals outputted by a PWM modulation module in the D-type audio power amplifier circuit into a common mode component and a differential mode component, and outputting the common mode component and the differential mode component; feeding back the common-mode component and the differential-mode component to a differential input end through a common-mode feedback link and a differential-mode feedback link respectively; wherein the common-mode component and the common-mode feedback link are completely arranged in the chip; the differential mode component and the differential mode feedback link are realized by a power MOSFET (Metal-Oxide-Semiconductor Field Effect Transistor) integrated inside the chip or an external power MOSFET; and outputting the differential mode component to a to-be-driven object through the power output stage. According to the method, after two feedback links are separated, in a zero-input mute state, no common-mode signal is sent to an output stage for amplification, and power consumption is not caused at the output stage, so that the overall efficiency is greatly improved; and meanwhile, static bottom noise is almost eliminated.

The inventive concepts provide a bidirectional switching converter including a first power metal oxide semiconductor field effect transistor (MOSFET) connecting an input voltage node to a switching node, a second power MOSFET connecting the switching node to a ground node, and a zero current detection (ZCD) auto-calibration circuit configured to perform one of an operation of generating a first offset for varying a turn-on time of the first power MOSFET according to an operation mode and an operation of generating a second offset for varying a turn-on time of the second power MOSFET according to the operation mode.

The utility model provides a switching device. The switching device comprises a tube shell, an MOSFET tube core and a TVS tube core group, wherein the MOSFET tube core and the TVS tube core group are arranged in the tube shell; the tube shell comprises a tube seat, a plurality of leading-out ends and an accommodating groove; a first metalized region, a second metalized region and a third metalized region are arranged at the bottom of the accommodating groove at intervals and are respectively connected with the leading-out end; the MOSFET tube core is attached to the first metallization region, the drain electrode is electrically connected with the first metallization region, and the source electrode and the grid electrode are electrically connected with the second metallization region and the third metallization region through bonding wires respectively; and the TVS tube core group comprises two TVS tube cores of which the cathodes are connected, and the anodes of the two TVS tube cores are electrically connected with the second metallization region and the third metallization region through bonding wires respectively. The two TVS chips are integrated between the grid electrode and the source electrode of the MOSFET through the design of the tube socket and the metallization area in the tube socket, so that a good electrostatic protection effect on the grid electrode of the power MOSFET is achieved, and the purpose of improving the ESD resistance of the power MOSFET device is achieved.

This invention belongs to the field of power semiconductor technology, specifically relating to a silicon carbide power MOSFET and its fabrication method. The silicon carbide power MOSFET provided by this invention includes a substrate, a first epitaxial layer, a first CSL layer, a first P-body region, a second epitaxial layer, a second CSL layer, and a second P-body region. A trench region is provided between the two P-body regions, with P+ regions injected at the bottom of the trench and N+ regions distributed on the sidewalls. Specifically, the on-resistance is reduced by the double CSL layer and P-body structure, while the JFET region length is extended to limit short-circuit current, significantly improving short-circuit withstand time. This makes it suitable for high-power, high-reliability power electronic devices.

The utility model discloses a high-power MOSFET device structure with low on-resistance, which relates to the technical field of MOSFET devices, and comprises a device main body, heat dissipation assemblies and a protection assembly, the lower side of the device main body is connected with pins, the left side and the right side of the device main body are provided with the heat dissipation assemblies, the outer side of the device main body is provided with the protection assembly, and the protection assembly is connected with the pins. And the protection assembly comprises a protection cover frame, ventilation grooves, a fixed connecting frame and a magnetic suction plate, the ventilation grooves are formed in the protection cover frame at equal intervals, and the fixed connecting frame is integrally fixed to the lower side of the protection cover frame. According to the high-power MOSFET device structure with the low on-resistance, the device body and the pins form the high-power MOSFET device structure with the low on-resistance, the protective cover frame can be arranged on the outer side of the device body in an upward sliding mode when not in use, a certain protection effect is achieved on the device body, the protective cover frame and the fixed connecting frame can slide downwards when in use, the protective cover frame and the fixed connecting frame are made to be located on the outer sides of the pins, and therefore the protective cover frame and the fixed connecting frame can be prevented from being damaged. And the pins are prevented from being bent and damaged.

A bidirectional isolated high voltage DC-DC converter includes a primary three-level circuit, a capacitor-inductor-inductor-capacitor (CLLC) resonant tank network connected to the primary three-level circuit, a secondary three-level circuit connected to the CLLC resonant tank network, and a controller that controls one or more of the components of the bidirectional isolated high voltage DC-DC converter. The primary three-level circuit and the secondary three-level circuit include capacitor middle points having respective voltages that are actively controlled by the controller. The controller implements a novel space vector PWM (SVPWM). The secondary capacitor middle point is chassis grounded to provide an optimal system level partial discharge hazard management for aircraft. vehicle and vessel applications. GaN power MOSFETs are used for high frequency operation of the power switches.

The application provides a single-point detection device and method for a safe working area of a power MOSFET, and relates to the technical field of semiconductor device testing. The single-point detection device comprises a pulse trigger circuit, a sampling feedback circuit, a driving amplification circuit, a capacitor energy storage circuit and a data collector. The pulse trigger circuit is used for outputting a pulse signal with a preset width according to a conduction time corresponding to a specific test point. The sampling feedback circuit is used for collecting a drain current of the power MOSFET and generating a feedback signal. The driving amplification circuit drives the power MOSFET to be turned on or turned off according to the feedback signal and the pulse signal. The capacitor energy storage circuit provides a target drain-source voltage for the power MOSFET according to a drain-source voltage corresponding to the specific test point. The data collector records waveforms of the drain-source voltage and the drain current of the power MOSFET. The single-point detection device does not need to increase an additional circuit, parameter matching is realized by adjusting devices in the single-point detection device, the test efficiency is improved, and the single-point detection device has the advantages of high efficiency, flexibility, high precision and the like.

The invention provides a power MOSFET (Metal-Oxide-Semiconductor Field Effect Transistor) wide SOA (Silicon On Architecture) structure preparation process and a chip, a well region is arranged among a plurality of first grooves, a first injection region is arranged in the well region, and a plurality of second injection regions are correspondingly arranged below a part of the well region, so that an MOSFET device with a wider safe working region can be realized; moreover, a proper threshold voltage value is obtained, the overcurrent capability of the SOA can be improved by nearly 2-3 times, and the thermal stability is synchronously reduced.

To provide a power metal oxide semiconductor field effect transistor (MOSFET) having a gate source electrostatic discharge (ESD) diode structure and a high voltage resistance and leakage prevention structure.SOLUTION: A power MOSFET 100 includes a substrate 102, an epitaxial layer 104, a plurality of gates 702, 704, 706, a body having first and second body regions 802, 804, a source having first and second source regions 912, 914, an interlayer insulating layer 920, a plurality of source contact plugs 951, 952, 953, a gate contact plug 954, a gate source ESD diode structure 929 connected between the gate contact and the source contact, a source contact 962, a gate contact 964, a drain contact 966, and a body ring structure 820 formed under the gate source ESD diode structure, functioning as a high voltage resistance and leakage prevention structure.SELECTED DRAWING: Figure 1

A power MOSFET driver circuit includes a feedback circuit configured to supply a feedback signal that signals when a gate voltage of the power MOSFET crosses a plateau value and the power MOSFET switches conduction state. The feedback circuit includes a comparator with a replica MOSFET of the power MOSFET, with scaled down dimensions, whose gate is coupled to the gate electrode of the power MOSFET. A bistable circuit has an input coupled to an output of the replica MOSFET and is configured to change a logic state of the feedback signal following the transition of the switching signal when the gate voltage of the power MOSFET crosses the plateau value and the power MOSFET switches conduction state.

A charge recycling circuit in an integrated circuit DC-DC converter having two power MOSFETs, the charge recycling circuit comprising a single inductor and recycling MOSFET switches arranged and sized such that when one of the two power MOSFETs is turning off, its gate capacitance charges are transferred to the single inductor, stored in the single inductor and then transferred directly to the gate of the other power MOSFET to turn it on.

The application discloses a trench gate power MOSFET device with anti-single event burnout reinforcement and a preparation method thereof, which comprises the following steps: etching a deep trench at a center position of the device and forming a P-type shielding area and depositing N-type polysilicon; forming a current expansion layer between a boron-doped area and an N-type drift area by means of ion implantation; and forming a P-type high-concentration doped area and an N-type high-concentration source area above the boron-doped area by means of ion implantation. According to the technical scheme, the internal electric field of the device can be modulated, the electric field distribution on the heavy ion incident track is smoother, the instantaneous power density of the device is reduced, the local high temperature is reduced, the trench oxide layer is protected from high temperature, the forward conduction capability of the device is improved, and the anti-single event burnout capability of the device can be remarkably improved without sacrificing the basic electrical characteristics of the device.

A circuit (21) can be used as part of an electric drive system having a direct current (DC) voltage source (18), a DC link capacitor (17) and an inverter circuit (11) for powering an electric machine (12). The circuit (21) comprises a driver circuit (15) connected to a gate terminal of a power switch (20), such as a silicon carbide power metal oxide semiconductor field effect transistor (SiC power MOSFET). The power switch (20) has a gate-to-source voltage responsive to the drive voltage (VDR), a degradation interval during which the gate-to-source voltage increases from a relatively low voltage level below the threshold voltage toward a relatively high voltage level above the threshold voltage. The drive circuit (15) is operable to shape a trajectory of the drive voltage (VDR) over a degradation interval such that the drive voltage (VDR) is non-linear over an entire duration of the degradation interval.

The present invention provides a super-junction power MOSFET structure with optimized linear output and a preparation method thereof, which are used to solve the technical problem that the output signal of the traditional SJMOS device structure is distorted or generates unnecessary harmonics, resulting in the inability of the power management system to output stably. The present invention provides multiple pillar regions within the silicon drift region, and is provided with a guard ring and a surface guard ring on the outside thereof; the width and doping concentration of the pillar regions and the guard rings are both distributed in a gradient decreasing from top to bottom; the upper surfaces of the multiple pillar regions are sequentially provided with a shield region and a base region from bottom to top, and the shield region is wider than the base region; JFET regions are provided on both sides of the shield region and the base region, and the doping concentration of the shield region and the JFET region is distributed in an inverse gradient, and the corresponding depth of the doping peak concentration is located at the bottom of the base region; the doping concentration of the shield region is higher than that of the base region, and the doping concentration of the JFET region is higher than that of the silicon drift region; the base region is provided with a source region and a source electrode contact region, and the source electrode is conductively connected to the source electrode contact region.

The invention provides a CLIP packaging process for a power MOSFET, and belongs to the technical field of packaging, the CLIP packaging process comprises three axial movement mechanisms, each axial movement mechanism comprises an inner rail and an outer rail which are nested with each other, a magnetic suspension driving assembly is arranged between the inner rail and the outer rail, and the magnetic suspension driving assembly is arranged between the inner rail and the outer rail. The magnetic suspension driving assembly comprises permanent magnet arrays distributed in the length direction of the inner rail at intervals, and electromagnetic coil sets arranged on the inner side of the outer rail and arranged corresponding to the permanent magnet arrays. The precision of a magnetic suspension driving assembly and a grating ruler is 0.1 micrometer, non-contact linear motion of an inner rail is achieved, closed-loop control is matched, the motion positioning precision is greatly improved, the precise control requirement of power MOSFETTCLIP packaging for the tiny dispensing amount is met, the three axial motion mechanisms are connected through an angle-adjustable connecting base, the relative angle can be flexibly adjusted, and the relative angle can be adjusted. Therefore, the spatial posture of the dispensing execution assembly is changed, and the requirements for different dispensing positions and angles in different packaging processes are met.

The application discloses a partial feedback push-pull type driving power MOSFET circuit, which comprises branch A, branch B and branch C; the branch A comprises a first PMOS transistor MP1, a second PMOS transistor MP2, a first NMOS transistor MN1 and a second NMOS transistor MN2; the branch B comprises a third PMOS transistor MP3, a third NMOS transistor MN3, a first resistor R1 and a second resistor R2; and the branch C comprises a power MOS transistor M0. The partial feedback push-pull type driving power MOSFET circuit can effectively reduce di / dt through local feedback.

This invention relates to the field of semiconductor device technology, specifically to an integrated SGT power MOSFET, comprising: in the operation of the integrated SGT power MOSFET, firstly, adaptively adjusting the gate voltage control signal, then dividing the process into at least two gate drive cycles, defining a current build-up phase within each gate drive cycle, and based on the magnitude of the source current and gate voltage during the current build-up phase, obtaining the degree of gate voltage rate anomaly during the current build-up phase of the current gate drive cycle, thereby adjusting the voltage change rate during the current build-up phase of the current gate drive cycle, and obtaining a corrected voltage change rate for the current build-up phase of the next gate drive cycle. This invention enables precise control of the power device conduction process under different loads and thermal conditions, providing a reliable foundation for subsequent power device protection, lifespan extension, and system stability.

The invention discloses a surface-mounted metal ceramic packaging structure suitable for a power MOSFET (Metal-Oxide-Semiconductor Field Effect Transistor) and a power MOSFET device, and the surface-mounted metal ceramic packaging structure comprises a metal ceramic tube shell. The chip is arranged in a sintering area on the bottom surface of the inner cavity of the metal ceramic tube shell; the source electrode bonding finger and the grid electrode bonding finger are arranged on the bottom surface of the inner cavity of the metal ceramic tube shell, insulating layers are arranged among the sintering region, the source electrode bonding finger and the grid electrode bonding finger for isolation, and the area of the source electrode bonding finger is larger than that of the grid electrode bonding finger; the plurality of bonding wires are respectively connected between the chip and the source electrode bonding finger and between the chip and the grid electrode bonding finger. According to the invention, the effective area of the source electrode bonding finger is enlarged, so that the total area of the source electrode bonding finger is larger than that of the grid electrode bonding finger, and a space is provided for welding more source electrode bonding wires, so that the through-current capability of the power MOSFET device can be improved by increasing the number of the source electrode bonding wires; therefore, the high-frequency advantage of the device can be fully exerted when the material is applied to silicon carbide and gallium nitride power MOSFET devices.

The invention discloses a power supply starting and constant current logic circuit and a control method thereof. The circuit comprises a constant-current power supply management chip U1, a starting branch and a constant-current control branch. The starting branch comprises a triode Q1 and a clamping / biasing network thereof, and a preset level Vpre is provided for the FB in a power-on stage so as to meet the starting condition of the U1; and along with the rise of the OUT, when the VBE of the Q1 is reduced to a cut-off threshold VBEOFF, the starting branch automatically quits. The constant-current control branch is composed of an operational amplifier U2, a sampling resistor Rs and a reference source Vref, the U2 compares voltages at the two ends of the Rs with the Vref and applies the voltages to the FB through a one-way coupling network, and closed-loop constant-current control over the output current after starting is achieved. Furthermore, a conflict detection and power consumption suppression sub-circuit is provided, when external trigger inputs A and B are effective at the same time, VINDET is pulled down to be lower than an undervoltage locking threshold VUVLO of U1, a grid electrode of a power MOSFET M1 is pulled down, and the retention time Thold is larger than or equal to Trestartmin, so that repeated starting is suppressed. The power-on success rate is improved, the handover oscillation is suppressed, and the system power consumption is reduced.

The invention belongs to the technical field of power semiconductors, and particularly relates to a silicon carbide power MOSFET and a manufacturing method thereof. The silicon carbide power MOSFET provided by the invention comprises a substrate, a first epitaxial layer, a first CSL layer, a first P body region, a second epitaxial layer, a second CSL layer and a second P body region, a groove region is arranged between the two P body regions, a P + region is injected into the bottom of the groove, and an N + region is distributed on the side wall of the groove; specifically, the on-resistance is reduced through the double-layer CSL layer and the P body structure, the length of the JFET region is prolonged to limit the short-circuit current, the short-circuit tolerance time is remarkably prolonged, and the structure is suitable for the field of high-power and high-reliability power electronic devices.

Embodiments of this disclosure relate to a split-gate trench power MOSFET with self-aligned polycrystalline-to-polycrystalline isolation. A semiconductor substrate has a trench extending from a front surface, the trench including a lower portion and an upper portion. A first insulating layer is arranged along the lower portion of the trench, and a first conductive material in the lower portion is insulated from the semiconductor substrate through the first insulating layer to form a field plate electrode of a transistor. A second insulating layer is arranged along the sidewalls of the upper portion of the trench. A third insulating layer liner is applied to the top surface of the first conductive material at the bottom of the upper portion of the trench. A second conductive material fills the upper portion of the trench. The second conductive material forms the gate electrode of the transistor, which is insulated from the semiconductor substrate through a second insulating layer and further insulated from the first conductive material through a third insulating layer.

The invention provides a current source resonance type inter-line direct current power flow controller topology and a frequency conversion control method. The current source resonance type inter-line direct current power flow controller topology comprises a first current source type H bridge, a second current source type H bridge, an isolation transformer and a resonance capacitor, each H bridge serves as a port and is composed of four bidirectional switches, and each bidirectional switch comprises two power MOSFETs with common source electrodes connected in series; the turn ratio of the primary side to the secondary side of the isolation transformer is 1: 1; the two resonant capacitors and the leakage inductor of the isolation transformer form a CLC resonant circuit; wherein the direct current side of the first current source type H bridge is connected with a first direct current line, and the alternating current side is connected with the primary side of the isolation transformer through the CLC resonance circuit; the direct-current side of the second current source type H bridge is connected with a second direct-current line, and the alternating-current side is connected with the secondary side of the isolation transformer through the CLC resonance circuit; during operation, the first current source type H bridge and the second current source type H bridge invert direct current of a direct current line into alternating current in a square wave form and inject the alternating current into the CLC resonance circuit.

The invention discloses a gate drive circuit with an ideal diode circuit as a bootstrap diode. The gate drive circuit comprises an input logic circuit, a high-side drive circuit HSD, the ideal diode circuit, a low-side drive circuit LSD and a power supply circuit. The input logic circuit is used for performing level shift processing on a high-side input signal HI to generate a first control signal and performing level shift processing on a low-side input signal LI to generate a second control signal; the high-side driving circuit HSD is used for generating a high-side driving signal HO according to the first control signal; the ideal diode circuit is used for bootstrap boost of the high-side driving circuit; the low-side driving circuit LSD is used for generating a low-side driving signal LO according to the second control signal; and the power supply circuit is used for providing reference voltage and reference current for each module. During high-frequency work, electric leakage to ground is small, chip power consumption is low, chip temperature is low, high-side output voltage is high when VDD voltage is low, the driving capacity is high, and a high-side power MOSFET is not prone to being burnt out.

To provide a method for forming an edge ring that at least partially surrounds an active area of an electronic device by obtaining an edge ring implant in a self-aligned manner.SOLUTION: A method includes disposing an N-type semiconductor body 50 having a lattice structure with spatial symmetry, forming damaged regions 80a to 80c in the semiconductor body having an amorphous lattice structure or a lattice structure without spatial symmetry, and forming a P-type edge termination region 68 in the semiconductor body, and the forming of the P-type edge termination region includes performing a channeling implant of a P-type doping species in the damaged region and in portions of the semiconductor body adjacent to each side of the damaged region.SELECTED DRAWING: Figure 3

The application relates to an automatic testing device and method for power MOSFET performance evaluation, and belongs to the technical field of power electronic power device testing. The automatic testing device comprises an upper computer, a power module, a controller module, a driving module, a load module and a detection module. Based on the device, MOSFET opening voltage testing, gate-source limit voltage testing, thermal resistance testing, short circuit testing, opening and closing waveform testing can be realized, and related working parameters of the MOSFET can be calculated according to the testing data, the performance of the MOSFET is comprehensively evaluated in actual application, the device architecture has high feasibility, the testing condition is easy to change, the device is easy to replace, and the testing efficiency is high; in addition, the device is convenient to use in data acquisition, has high application value, and is of great significance for guiding the selection of power MOSFET.

A method of manufacturing a semiconductor device is provided. The method may include implanting a silicon-rich layer on a surface of a silicon carbide substrate, and growing a gate oxide layer on the silicon-rich layer on the surface of the silicon carbide substrate.

A trench metal-oxide-semiconductor field-effect transistor (MOSFET) device comprises an active cell area including a plurality of superjunction trench power MOSFETs formed in an epitaxial layer. Each MOSFET includes source and body regions and a contact trench formed between first and second gate trenches. A region of the epitaxial layer between the gate trenches extends to the top surface of the epitaxial layer. An insulated gate electrode is formed in each gate trench. At least a portion of the contact trench extends from a top surface of the epitaxial layer to a depth that is shallower than the bottom of the body region.