99 results about "Power MOSFET" patented technology

The inventive concepts provide a bidirectional switching converter including a first power metal oxide semiconductor field effect transistor (MOSFET) connecting an input voltage node to a switching node, a second power MOSFET connecting the switching node to a ground node, and a zero current detection (ZCD) auto-calibration circuit configured to perform one of an operation of generating a first offset for varying a turn-on time of the first power MOSFET according to an operation mode and an operation of generating a second offset for varying a turn-on time of the second power MOSFET according to the operation mode.

The utility model discloses a high-power MOSFET device structure with low on-resistance, which relates to the technical field of MOSFET devices, and comprises a device main body, heat dissipation assemblies and a protection assembly, the lower side of the device main body is connected with pins, the left side and the right side of the device main body are provided with the heat dissipation assemblies, the outer side of the device main body is provided with the protection assembly, and the protection assembly is connected with the pins. And the protection assembly comprises a protection cover frame, ventilation grooves, a fixed connecting frame and a magnetic suction plate, the ventilation grooves are formed in the protection cover frame at equal intervals, and the fixed connecting frame is integrally fixed to the lower side of the protection cover frame. According to the high-power MOSFET device structure with the low on-resistance, the device body and the pins form the high-power MOSFET device structure with the low on-resistance, the protective cover frame can be arranged on the outer side of the device body in an upward sliding mode when not in use, a certain protection effect is achieved on the device body, the protective cover frame and the fixed connecting frame can slide downwards when in use, the protective cover frame and the fixed connecting frame are made to be located on the outer sides of the pins, and therefore the protective cover frame and the fixed connecting frame can be prevented from being damaged. And the pins are prevented from being bent and damaged.

A bidirectional isolated high voltage DC-DC converter includes a primary three-level circuit, a capacitor-inductor-inductor-capacitor (CLLC) resonant tank network connected to the primary three-level circuit, a secondary three-level circuit connected to the CLLC resonant tank network, and a controller that controls one or more of the components of the bidirectional isolated high voltage DC-DC converter. The primary three-level circuit and the secondary three-level circuit include capacitor middle points having respective voltages that are actively controlled by the controller. The controller implements a novel space vector PWM (SVPWM). The secondary capacitor middle point is chassis grounded to provide an optimal system level partial discharge hazard management for aircraft. vehicle and vessel applications. GaN power MOSFETs are used for high frequency operation of the power switches.

A power MOSFET driver circuit includes a feedback circuit configured to supply a feedback signal that signals when a gate voltage of the power MOSFET crosses a plateau value and the power MOSFET switches conduction state. The feedback circuit includes a comparator with a replica MOSFET of the power MOSFET, with scaled down dimensions, whose gate is coupled to the gate electrode of the power MOSFET. A bistable circuit has an input coupled to an output of the replica MOSFET and is configured to change a logic state of the feedback signal following the transition of the switching signal when the gate voltage of the power MOSFET crosses the plateau value and the power MOSFET switches conduction state.

A charge recycling circuit in an integrated circuit DC-DC converter having two power MOSFETs, the charge recycling circuit comprising a single inductor and recycling MOSFET switches arranged and sized such that when one of the two power MOSFETs is turning off, its gate capacitance charges are transferred to the single inductor, stored in the single inductor and then transferred directly to the gate of the other power MOSFET to turn it on.

The application discloses a trench gate power MOSFET device with anti-single event burnout reinforcement and a preparation method thereof, which comprises the following steps: etching a deep trench at a center position of the device and forming a P-type shielding area and depositing N-type polysilicon; forming a current expansion layer between a boron-doped area and an N-type drift area by means of ion implantation; and forming a P-type high-concentration doped area and an N-type high-concentration source area above the boron-doped area by means of ion implantation. According to the technical scheme, the internal electric field of the device can be modulated, the electric field distribution on the heavy ion incident track is smoother, the instantaneous power density of the device is reduced, the local high temperature is reduced, the trench oxide layer is protected from high temperature, the forward conduction capability of the device is improved, and the anti-single event burnout capability of the device can be remarkably improved without sacrificing the basic electrical characteristics of the device.

A circuit (21) can be used as part of an electric drive system having a direct current (DC) voltage source (18), a DC link capacitor (17) and an inverter circuit (11) for powering an electric machine (12). The circuit (21) comprises a driver circuit (15) connected to a gate terminal of a power switch (20), such as a silicon carbide power metal oxide semiconductor field effect transistor (SiC power MOSFET). The power switch (20) has a gate-to-source voltage responsive to the drive voltage (VDR), a degradation interval during which the gate-to-source voltage increases from a relatively low voltage level below the threshold voltage toward a relatively high voltage level above the threshold voltage. The drive circuit (15) is operable to shape a trajectory of the drive voltage (VDR) over a degradation interval such that the drive voltage (VDR) is non-linear over an entire duration of the degradation interval.

This invention relates to the field of semiconductor device technology, specifically to an integrated SGT power MOSFET, comprising: in the operation of the integrated SGT power MOSFET, firstly, adaptively adjusting the gate voltage control signal, then dividing the process into at least two gate drive cycles, defining a current build-up phase within each gate drive cycle, and based on the magnitude of the source current and gate voltage during the current build-up phase, obtaining the degree of gate voltage rate anomaly during the current build-up phase of the current gate drive cycle, thereby adjusting the voltage change rate during the current build-up phase of the current gate drive cycle, and obtaining a corrected voltage change rate for the current build-up phase of the next gate drive cycle. This invention enables precise control of the power device conduction process under different loads and thermal conditions, providing a reliable foundation for subsequent power device protection, lifespan extension, and system stability.

The invention provides a current source resonance type inter-line direct current power flow controller topology and a frequency conversion control method. The current source resonance type inter-line direct current power flow controller topology comprises a first current source type H bridge, a second current source type H bridge, an isolation transformer and a resonance capacitor, each H bridge serves as a port and is composed of four bidirectional switches, and each bidirectional switch comprises two power MOSFETs with common source electrodes connected in series; the turn ratio of the primary side to the secondary side of the isolation transformer is 1: 1; the two resonant capacitors and the leakage inductor of the isolation transformer form a CLC resonant circuit; wherein the direct current side of the first current source type H bridge is connected with a first direct current line, and the alternating current side is connected with the primary side of the isolation transformer through the CLC resonance circuit; the direct-current side of the second current source type H bridge is connected with a second direct-current line, and the alternating-current side is connected with the secondary side of the isolation transformer through the CLC resonance circuit; during operation, the first current source type H bridge and the second current source type H bridge invert direct current of a direct current line into alternating current in a square wave form and inject the alternating current into the CLC resonance circuit.

The invention discloses a gate drive circuit with an ideal diode circuit as a bootstrap diode. The gate drive circuit comprises an input logic circuit, a high-side drive circuit HSD, the ideal diode circuit, a low-side drive circuit LSD and a power supply circuit. The input logic circuit is used for performing level shift processing on a high-side input signal HI to generate a first control signal and performing level shift processing on a low-side input signal LI to generate a second control signal; the high-side driving circuit HSD is used for generating a high-side driving signal HO according to the first control signal; the ideal diode circuit is used for bootstrap boost of the high-side driving circuit; the low-side driving circuit LSD is used for generating a low-side driving signal LO according to the second control signal; and the power supply circuit is used for providing reference voltage and reference current for each module. During high-frequency work, electric leakage to ground is small, chip power consumption is low, chip temperature is low, high-side output voltage is high when VDD voltage is low, the driving capacity is high, and a high-side power MOSFET is not prone to being burnt out.

A method of manufacturing a semiconductor device is provided. The method may include implanting a silicon-rich layer on a surface of a silicon carbide substrate, and growing a gate oxide layer on the silicon-rich layer on the surface of the silicon carbide substrate.

A trench metal-oxide-semiconductor field-effect transistor (MOSFET) device comprises an active cell area including a plurality of superjunction trench power MOSFETs formed in an epitaxial layer. Each MOSFET includes source and body regions and a contact trench formed between first and second gate trenches. A region of the epitaxial layer between the gate trenches extends to the top surface of the epitaxial layer. An insulated gate electrode is formed in each gate trench. At least a portion of the contact trench extends from a top surface of the epitaxial layer to a depth that is shallower than the bottom of the body region.

The application provides a semiconductor structure and a forming method thereof. The semiconductor structure comprises: a semiconductor substrate, the semiconductor substrate comprises a plurality of first regions and second regions which are alternately arranged, a surface of the semiconductor substrate comprises an epitaxial layer, and a surface of the epitaxial layer comprises a current dispersion layer; a first doped region is located in the current dispersion layer of the first region; a second doped region is located in the first doped region; a third doped region is located in the current dispersion layer and crosses the first region and an adjacent second region, one end of the third doped region is connected to the second doped region in the first region, and the other end of the third doped region extends into the second region; and an electric field buffer region is located in the current dispersion layer of the second region and between adjacent third doped regions. The technical scheme of the application can avoid the occurrence of secondary degradation in a power MOSFET device, and improve the performance and reliability of the device.

The invention discloses a shield gate trench power MOSFET and a preparation method thereof, the shield gate trench power MOSFET comprises a first epitaxial layer, a plurality of trench structures, a first doped region, a second epitaxial layer, a second doped region, a dielectric layer, a metal layer and at least two third doped regions, the trench structures are arranged and distributed in the first epitaxial layer; the first doped region is located in the first epitaxial layer between the adjacent groove structures, and the two sides of the first doped region are in contact with the outer side surfaces of the groove structures; the second epitaxial layer is located in the first doped region, and the bottom surface of the second epitaxial layer is in contact with the upper surface of the first epitaxial layer; the second doped region is located on the upper surface of the first doped region, and the at least two third doped regions are arranged in the first epitaxial layer right below the second epitaxial layer from top to bottom and located in the middle positions of the adjacent groove structures. According to the invention, two additional third doped regions are introduced into the first epitaxial layer between two traditional groove structures, so that the electric field of the middle section can be further pulled up to improve the breakdown voltage of the device.

The invention relates to a power MOSFET (Metal Oxide Semiconductor Field Effect Transistor) device, in particular to a high-reliability MOS (Metal Oxide Semiconductor) device structure with three buffer layers and a preparation method thereof, and the preparation method comprises the following steps: sequentially growing an N drift layer and a second buffer layer on an N substrate layer; forming a first deep groove in the middle of the cell through etching, and injecting ions into the bottom of the first deep groove to form a third buffer layer; depositing an oxide layer in the first deep groove to fill the first deep groove, and then forming a first buffer layer around the first deep groove in the second buffer layer by injecting ions; growing a P-type well region on the surface of the second buffer layer; and etching the P-type well region to form a second deep groove, and arranging a first polycrystalline silicon layer and a second polycrystalline silicon layer in the second deep groove. The contradiction between performance improvement and anti-radiation reliability of a current power device is solved, high performance of a shield gate device is considered, electric field distribution of the device is optimized, and the single particle and total dose radiation resistance of the device is improved.

The utility model discloses a drive circuit with low propagation delay and high isolation voltage, which relates to the technical field of power electronics, and comprises a signal input branch, an isolation device, a signal output branch, a power amplification circuit and a drive output branch, the signal input branch comprises a PWM (Pulse Width Modulation) input end and a filter circuit; the isolation device is a TLP152, a pin 1 and a pin 3 of the input end of the isolation device receive filtered PWM signals, a pin 5 of the output end of the isolation device outputs isolated signals, and the isolation device is connected to the output end of the filter circuit and used for achieving electrical isolation between input signals and output signals; the signal output branch circuit comprises a vibration damping branch circuit and a parasitic parameter removing branch circuit. And the power amplification circuit comprises a high-power tube Q1 which is a high-power MOSFET (Metal-Oxide-Semiconductor Field Effect Transistor), so that the driving circuit has the characteristics of low propagation delay and high isolation voltage.

The utility model relates to the technical field of detection equipment, in particular to a power MOS (Metal Oxide Semiconductor) tube fault detection assembly, which is characterized in that the input end of a bearing platform is lapped with a linkage frame, the output end of the linkage frame is detachably connected to a cylinder, the output end of the linkage frame is rotatably connected with a rotating wheel, and the rotating wheel is lapped on the input end part of the bearing platform. The air cylinder pushes the fixing frame to move, the linkage frame and the push plate which are connected with the fixing frame can move, the push plate can move towards the position of the conveying belt, the linkage frame pushes the support, the support enables the sliding base to move, and therefore the bearing platform on the sliding base moves towards the interior of the inner groove, and bearing of the MOS tube is achieved. In the process, the MOS tube does not need to be taken down from the conveyor belt by a person, so that the taking and placing efficiency is improved, and detection is facilitated.

The invention relates to the technical field of semiconductor devices, in particular to an integrated SGT power MOSFET which comprises the steps that in the working state of the integrated SGT power MOSFET, self-adaptive adjustment is carried out on a grid voltage control signal, then at least two grid driving periods are divided, current establishing stages in the grid driving periods are divided, and the grid voltage control signal is output; and according to the magnitude of the source current and the grid voltage in the current establishment stage in the grid driving period, the grid voltage rate abnormal degree of the current establishment stage in the current grid driving period is obtained so as to adjust the voltage change rate of the current establishment stage in the current grid driving period. And obtaining the correction voltage change rate of the current establishment stage in the next gate driving period in the future. According to the invention, fine regulation and control of the conduction process of the power device can be realized under different load and thermal working conditions, and a reliable basis is provided for subsequent power device protection, service life prolonging and system stability.

The invention relates to the technical field of intelligent voltage regulation and control, and discloses an intelligent regulation and control method and device for threshold voltage of a gallium nitride power MOSFET (Metal-Oxide-Semiconductor Field Effect Transistor). The method comprises the following steps: performing deep energy level transient spectrum measurement on a silicon nitride charge trapping layer of the gallium nitride power MOSFET to obtain calibrated trap density, calibrated energy level depth and calibrated barrier thickness; creating a pulse parameter mapping table; collecting the drain current of the gallium nitride power MOSFET and calculating the threshold deviation; querying a pulse parameter mapping table according to the threshold deviation to obtain a first pulse parameter, and performing temperature compensation on the first pulse parameter to obtain a second pulse parameter; and converting the second pulse parameter into a grid injection pulse, applying the grid injection pulse to the charge trapping layer, driving the electron tunneling injection trap to adjust the two-dimensional electron gas concentration, and outputting a regulated threshold voltage. According to the invention, high-precision stable regulation and control of the threshold voltage in a wide working range are realized, and the reliability and switching performance of the gallium nitride power MOSFET are improved.

A voltage transient protection utilizes Zener diodes, resisters, and a power MOSFET to clamp down the DC spike or surged voltage at the input and prevent damage to the inverter's DC power and control section. The input reverse polarity protection utilizes blocking diodes and a switch to cut off reverse voltage and prevent damage to the DC power and control section of the inverter. Once the surge voltage and / or reverse voltage conditions have been removed, the inverter will automatically recover and power on. In addition, an AC output interlock protection circuit is in place to provide safety protection to the external load. The AC output interlock protection circuit utilizes interlock jumpers on the mating connectors, which when detected (or in response to a control signal), it will activate the internal power relays and enable the AC output voltage to the terminals coupled to the external load.

Fabrication method for a SiC integrated circuit which allows multiple power MOSFETs or LDMOSs to exist in the same piece of semiconductor substrate and still function as individual devices which form the components of a given circuit architecture, for example, and not by limitation, in a half-bridge module. In one example, a deep isolation trench is etched into the silicon carbide substrate surrounding each individual LDMOS device. The trench is filled with an insulating material. The depth of the trench may be deeper than the thickness of an epitaxial layer to ensure electrical isolation between the individual epitaxial layer regions housing the individual LDMOSs. The width of the trench may be selected to withstand the potential difference between the bias levels of the body regions of neighboring power LDMOS devices.

The application discloses a fast recovery power device with embedded tunnel diode structure and a production method thereof, wherein the power device has a plurality of uniformly arrayed heavy doped regions with opposite doped types under a neutral body region, and the heavy doped regions form a tunnel PN junction structure with the doped regions with opposite doped types in the neutral body region; the tunnel PN junction structure can provide an additional minority carrier leakage conduction channel when the power MOSFET device is switched from a conducting state to a closed state, reduces the tail current when the device is closed, makes the power device quickly closed from an open state, and thus improves the working speed of the device and expands the frequency band range of the power device. The application realizes the fast recovery characteristic of the device through the process steps of adding the arrayed opposite heavy doped regions and rapid thermal annealing, makes the power device have the advantages of low cost and fast recovery, and breaks the barrier that the VDMOS power device can only be used in the medium and low frequency field applications.

The invention discloses a power-on and power-off circuit for a power switch in a meter reading terminal. The circuit comprises a power input end, a power output end, a light touch key, a power MOSFET, a first triode, a second triode, a plurality of diodes, a plurality of resistors and a plurality of capacitors. The power MOSFET serves as a high-side power switch, is arranged between the power input end and the power output end in series, and is used for controlling the on-off of the master control power supply branch. A self-locking loop which is triggered by lightly touching a key and is formed by feedback of a power supply output end is combined, so that single-key power-on and automatic power supply keeping after power-on are realized; and when the main control MCU detects a shutdown condition, the second triode is controlled to release self-locking, so that the power MOSFET is turned off, and controllable power-off is realized. An RC maintaining network is arranged in the circuit to ensure that the shutdown process is stable and reliable, an external forced shutdown interface is provided, and hardware-level outage can still be achieved under the condition that a master control is abnormal. And meanwhile, the power supply is kept continuous in the online upgrading or restarting process of the master control, so that accidental power failure is avoided.

This utility model relates to the field of pulse width modulation (PWM) technology and provides an output synchronous rectified PWM signal control and driving circuit, including an oscillation control circuit, a shaping drive circuit, an output drive circuit, and an interlock control circuit. The oscillation control circuit is electrically connected to the shaping drive circuit and is used to correct the waveform of the transformer signal. The interlock control circuit is also electrically connected to the shaping drive circuit and is used to control the cutoff and turn-on of the power MOSFETs at the positive and negative output terminals of the interlock transformer. The shaping drive circuit is electrically connected to the output drive circuit and is used to reduce the internal losses of the main power MOSFETs. The output drive circuit is also electrically connected to the shaping drive circuit and is used to improve the operating efficiency of the output synchronous rectifier circuit. This utility model reduces the internal losses of the main power MOSFETs, improves the operating efficiency of the output synchronous rectifier circuit, and enhances the overall power conversion efficiency and electrical performance of the rectifier module.

The present application relates to the technical field of power semiconductor device design, and particularly relates to a modeling method and system of shielded gate trench MOSFET. The method comprises the following steps: selecting characteristic point key positions of the shielded gate trench structure, wherein the characteristic point key positions comprise corners, edges and centers; calculating the electric field intensity of the characteristic point key positions through two-dimensional simulation to generate an electric field intensity distribution map; based on the electric field intensity distribution map, defining a set of trapezoidal angle parameters to design the shape of the shielded gate as a trapezoidal structure with the upper part being wide and the lower part being narrow; modeling and establishing a quantitative relationship between the side wall inclination angle and the electric field intensity of the trench corner; generating an angle-electric field response curve; and calculating the change of the overlapping area between the shielded gate and the control gate in the trench for different trapezoidal structures. The present application provides clear performance improvement indicators and optimization directions for power MOSFET design by analyzing the relationship between the trapezoidal angle and the gate overlapping area.

The invention relates to a vertical groove type power MOSFET (Metal-Oxide-Semiconductor Field Effect Transistor) structure of an integrated channel diode and a preparation method thereof, and belongs to the technical field of semiconductors, the vertical groove type power MOSFET structure comprises a drain metal layer, a substrate and an N-GaN drift region from bottom to top, a P +-shielding layer is formed at the top of the center of the N-GaN drift region through ion implantation, an NPN structure is arranged above the N-GaN drift region, and the P +-shielding layer is arranged above the N-GaN drift region. The NPN structure sequentially comprises an N-GaN CSL layer, a P < + >-GaN body region layer and an N < + >-GaN source region layer from bottom to top; a split gate structure is introduced, on the basis of the split gate structure, a channel diode is integrated to serve as a freewheel diode, a p-type region at the bottom of a groove serving as a part of the channel diode and an n-type drift region form a PN junction, and the breakdown voltage of the device is further improved by optimizing important structural parameters such as the thickness and the doping concentration of a p-type GaN layer and the width of a channel.

The utility model discloses an intelligent lithium ion / sodium ion battery group BMS management system, include: battery group, power MOSFET pipe circuit, AFE battery group voltage / current acquisition circuit, pre charge and discharge circuit, slave discharge circuit, main current sampling circuit, zero current calibration circuit, operational amplifier reference voltage source circuit, current and voltage sampling amplification circuit, central control circuit, charge and discharge current sampling circuit, power reference voltage source circuit, communication circuit, central control circuit corresponding end is respectively connected with AFE battery group voltage / current acquisition circuit, power MOSFET pipe circuit, current and voltage sampling amplification circuit, pre charge and discharge circuit, slave discharge circuit, charge and discharge current sampling circuit, power reference voltage source circuit, communication isolation module corresponding end electric connection. The utility model discloses a high -power MOSFET replaces traditional relay scheme, and the working current of all systems on BMS board is gathered, and the collection accuracy is better than 50uA, and the charge and discharge main loop current collection accuracy range is 1mA 3000A, ensures SOC correct when battery group long -term storage or working.

The application relates to a power MOSFET-based switching circuit, which comprises an input power supply, a switch and a power MOSFET, the power supply is connected to the source of the power MOSFET through the switch, the drain of the power MOSFET is an output end and is connected to a capacitor, the front end of the switch is provided with an external power supply pin, the power MOSFET is a P-type MOSFET, and the circuit further comprises: a first regulating sub-circuit, the first regulating sub-circuit controls the power MOSFET to work in a saturation region when the switch is closed and the output end voltage is lower than a set threshold value, and the capacitor is charged with a small current; and a second regulating sub-circuit, the second regulating sub-circuit controls the power MOSFET to work in a linear region when the switch is closed and the output end voltage is greater than the set threshold value, and the capacitor is charged with a large current. Compared with the prior art, the application avoids a large drop of the voltage of the external power supply pin, and guarantees the reliability of the power supply of the switching circuit.

An electrical circuit (21) can be used as part of an electrical control system comprising a direct current (DC) power supply (18), an intermediate circuit capacitor (17), and an inverter circuit (11) for powering an electric machine (12). The electrical circuit (21) includes a driver circuit (15) connected to a gate terminal of a power switch (20), e.g., a silicon carbide power metal oxide semiconductor field-effect transistor (SiC power MOSFET). The power switch (20) has a gate-source voltage that responds to a drive voltage (VDR) and a degradation interval during which the gate-source voltage rises from a relatively low voltage level below a threshold voltage to a relatively high voltage level above the threshold voltage.The driver circuit (15) can be operated to form a trajectory of the drive voltage (VDR) over the degradation interval such that the drive voltage (VDR) is non-linear over the entire duration of the degradation interval.

The invention belongs to the field of power electronics, and particularly relates to a floating photovoltaic-energy storage oriented power converter structure and a coordination control method. The converter is composed of a photovoltaic DC-DC boost conversion circuit and an energy storage bidirectional Buck-Boost circuit, the photovoltaic DC-DC boost conversion circuit takes a photovoltaic panel as an input, the energy storage bidirectional Buck-Boost circuit takes an energy storage battery as an energy unit, and outputs of the photovoltaic DC-DC boost conversion circuit and the energy storage bidirectional Buck-Boost circuit are connected with the same DC bus to supply power to a DC ship body and a port DC load. The circuit adopts a power MOSFET as a switching device, the energy storage circuit is provided with an over-current and over-voltage protection module, and the inductor adopts a silicon steel sheet iron core with low magnetic hysteresis loss to reduce energy consumption. The coordination control method comprises the steps of obtaining photovoltaic parameters adaptive to a dynamic water environment through environmental data in combination with a correction coefficient, establishing an engineering mathematical model to derive output characteristics, screening photovoltaic maximum power through a niche algorithm, determining an energy storage working state according to a load demand, generating a charging and discharging instruction by calculating the end voltage and the charge state of a storage battery, and controlling the dynamic water environment according to the charging and discharging instruction. And cooperative operation is realized.