312 results about "Power MOSFET" patented technology

The invention relates to the technical field of MOS (Metal Oxide Semiconductor) semiconductors, and discloses a semiconductor device with an integrated heat dissipation function for a power MOSFET (Metal Oxide Semiconductor Field Effect Transistor). The single MOS cell comprises a drain electrode, a semiconductor epitaxial layer, a source electrode and a grid electrode, the semiconductor epitaxial layer comprises an N substrate layer, an N drift layer, a P + layer, an N well layer and a P well layer, the profile of the cross section of the grid electrode is in an H shape, and the grid electrode comprises two longitudinal parts and a transverse part used for bridging the two longitudinal parts. According to the invention, the H-shaped gate structure is in bridge connection with the double longitudinal grooves through the transverse part, so that the channel width is increased, and the on-resistance is reduced; a current path is further optimized by combining a metal deposition layer and a heavily doped N + layer in the bottom doping layer; and the metal layer is connected in parallel to conduct electricity, so that the resistance is reduced, and the heavily doped N + layer inhibits the JFET effect, so that the resistance is reduced by more than 10%.

The invention discloses a power MOSFET and a preparation method thereof, and belongs to the technical field of microelectronics. The power MOSFET comprises a substrate layer, an AlN buffer layer, a Ga2O3 buffer layer and a Ga2O3 epitaxial layer which are arranged from bottom to top, wherein the top surface of the Ga2O3 epitaxial layer is provided with a groove, and an oxide isolation layer is arranged in the groove; the drain electrode is arranged on one side of the Ga2O3 epitaxial layer and is adjacent to the oxide isolation layer; the source electrode is arranged in the middle area of the other side of the Ga2O3 epitaxial layer; second grooves are formed in the two sides of the source electrode; a NiO layer and an insulated gate dielectric layer are arranged on the second groove from bottom to top; a gate electrode with a non-planar gate structure is arranged on the insulated gate dielectric layer; and a gap part around the second groove and the gate electrode is filled with a first oxide isolation layer. Through structural design and material selection, the problems of serious heat dissipation and gate electrode electric leakage of existing similar devices are solved, and the voltage withstanding performance of the device is improved.

Disclosed is a power metal-oxide-semiconductor field-effect transistor (MOSFET) diagnostic and lifetime estimation system and method, including the steps of: acquiring degradation data by conducting a degradation test; measuring potential failure precursors to provide early warning of failure; inspecting and diagnosing health condition of internal structure of the power MOSFET device using thermal transient measurement and scanning acoustic microscopy (SAM) images; repeating power cycling test and the measurements of potential failure precursors until the precursors reach a corresponding failure threshold; and estimating remaining lifetime of the power MOSFET device using an artificial intelligence (AI) algorithm.

The present application discloses a structure of a trench-gate power MOSFET and a manufacturing method thereof. The structure includes: a second epitaxial layer; a strip-shaped P pillar, the length direction of the strip-shaped P pillar being parallel to the projection direction of the crystal orientation with the most obvious channel effect on the surface of the epitaxial material; a trench gate, including a trench, the trench being parallel to the length direction of the strip-shaped P pillar or perpendicular to the length direction of the strip-shaped P pillar, and filling a filler into the trench to manufacture the trench gate. When the length direction of the trench is parallel to the length direction of the strip-shaped P pillar, the trench is located directly above the strip-shaped P pillar and has the same width as the strip-shaped P pillar. When the length direction of the trench is perpendicular to the length direction of the strip-shaped P pillar, the width of the trench is not related to the strip-shaped P pillar; a surface source region. The advantage of the present application is that it can reduce the manufacturing steps and simplify the processing technology.

A semiconductor device has a first substrate and a first semiconductor layer formed over the first substrate. A second substrate is disposed over a surface of the first semiconductor layer opposite the first substrate. The first semiconductor layer and second semiconductor layer can be silicon carbide or cubic silicon carbide. The first substrate and a portion of the first semiconductor layer are removed to reduce defects in the first semiconductor layer. A second semiconductor layer is formed over a remaining portion of the first semiconductor layer. A third semiconductor layer is disposed over the second semiconductor layer. The third semiconductor layer can be silicon. The third semiconductor layer can be disposed over the second semiconductor layer by direct wafer bonding. An electrical component is formed within the third semiconductor layer. The electrical component can be a power MOSFET, IGBT, CTIGBT, diode, and thyristor.

An apparatus includes a drain and a source on opposing sides of an epitaxial layer, a body region and a plurality of gates formed in the epitaxial layer, an interlayer dielectric layer over the epitaxial layer, a gate-source electrostatic discharge (ESD) diode in the interlayer dielectric layer, a source contact connected to the source and a first terminal of the gate-source ESD diode structure, a gate contact connected to the plurality of gates and a second terminal of the gate-source ESD diode structure, a drain contact on opposing sides of the epitaxial layer of the source contact, a breakdown voltage enhancement and leakage prevention structure formed underneath the gate-source ESD diode structure, wherein the breakdown voltage enhancement and leakage prevention structure comprises a body ring structure.

The invention discloses an adjustable wide-adaptation MOSFET turn-off gate drive circuit and a drive method, and relates to the field of power electronics, and the drive circuit matches parasitic parameters of a to-be-controlled power MOSFET through parameter configuration so as to improve the applicability. In the turn-off process of the to-be-controlled power MOSFET, the circuit controls the grid voltage to be rapidly decreased at the stage higher than the Miller platform, to be kept at the Miller platform voltage during the Miller platform, to be linearly decreased at the stage from the Miller platform to the threshold voltage, and to be rapidly decreased below the threshold voltage. Through continuous fine control of grid voltage, drain-source side voltage and current track regulation and control are realized. The problems that according to an existing turn-off driving circuit, grid voltage is difficult to finely regulate and control in the turn-off process of a power MOSFET device, voltage and current tracks on the drain side and the source side of the power MOSFET cannot be finely regulated and controlled independently, the targets of low voltage overshoot and low turn-off loss are difficult to meet in the turn-off process at the same time, limited application of the power MOSFET device is difficult to achieve, and the turn-off efficiency of the power MOSFET device is low are solved. And the high power density requirement of the power electronic device is difficult to meet.

An apparatus includes a drain and a source on opposing sides of an epitaxial layer, a body region and a plurality of gates formed in the epitaxial layer, an interlayer dielectric layer over the epitaxial layer, a gate-source electrostatic discharge (ESD) diode in the interlayer dielectric layer, a source contact connected to the source and a first terminal of the gate-source ESD diode structure, a gate contact connected to the plurality of gates and a second terminal of the gate-source ESD diode structure, a drain contact on opposing sides of the epitaxial layer of the source contact, a breakdown voltage enhancement and leakage prevention structure formed underneath the gate-source ESD diode structure, wherein the breakdown voltage enhancement and leakage prevention structure comprises a body ring structure.

The invention discloses a mixed function bridgeless topology circuit adopting a GaN device, which adopts a solution of combining totem-pole-like bridgeless and LLC (Logical Link Control), can simultaneously realize three functions of bridgeless rectification, power factor correction (PFC) and isolated direct current-direct current (DC / DC) conversion, and harmonic waves can meet the requirements of the industrial field. The topology circuit only needs four high-speed GaN power HEMT devices, two low-speed Si power MOSFET devices, two low-speed Si power thyristors and one auxiliary small inductor capable of correcting input current waveforms, does not need a rectifier bridge, only needs one-stage control to stabilize output voltage, and greatly simplifies the difficulty of system design.

A power inverter is provided. The power inverter includes: first, second and third legs configured to output alternating voltages having different phases. Each the first leg, the second leg, and the third leg includes: a first power metal oxide semiconductor field effect transistor (MOSFET) on a SiC substrate, and connected between a power terminal of direct current voltage and an output terminal configured to output a voltage of a corresponding phase among the first phase, the second phase and the third phase; a second power MOSFET on the SiC substrate, and connected between the output terminal and a ground terminal; and a redundancy circuit including a redundancy power transistor configured to replace the first power MOSFET based on the first power MOSFET failing and replace the second power MOSFET based on the second power MOSFET failing.

A trench gate power MOSFET, including: a substrate provided with a hexagonal wide bandgap semiconductor of a first conductivity type; an epitaxial layer grown on the substrate and of the first conductivity type; a body region formed on the epitaxial layer and of a second conductivity type; a trench formed in the body region by etching, where a length direction of the trench is parallel to a projection, on the surface of a wafer, of the C axis; a second conductivity-type pillar formed by implanting first ions into a bottom region of the trench along the C axis of the hexagonal wide bandgap semiconductor material, where the bottom region of the trench is located below the trench, and is connected to the bottom of the trench, and the longitudinal depth of the second conductivity-type pillar is at least not less than 50% of the thickness of the epitaxial layer located in the bottom region of the trench; and a trench gate formed by filling the trench with a filler.

A system and a method for controlling a power MOSFET for limiting electromagnetic interference from a load is provided. The system and method include a pulse-width-modulated (PWM) control voltage to operate the power MOSFET in accordance with its Ohmic region (linear mode). By operating the power MOSFET in its Ohmic region, the electromagnetic field generated by the load is reduced, without requiring a dedicated DC / DC converter that would otherwise increase the cost, size, and weight of the power electronics.

The invention discloses a structure of a trench gate power MOSFET (Metal-Oxide-Semiconductor Field Effect Transistor) and a manufacturing method of the trench gate power MOSFET. The structure comprises a second epitaxial layer; the length direction of the strip-shaped P column is parallel to the projection direction of the crystal orientation with the most obvious channel effect on the surface of the epitaxial material; the groove gate comprises a groove, the groove is parallel to the length direction of the strip-shaped P column or perpendicular to the length direction of the strip-shaped P column, the groove is filled with filler, and therefore the groove gate is manufactured, when the length direction of the groove is parallel to the length direction of the strip-shaped P column, the groove is located over the strip-shaped P column, and the width of the groove is consistent with the width of the strip-shaped P column; when the length direction of the groove is perpendicular to the length direction of the strip-shaped P column, the width of the groove is not related to the strip-shaped P column; and a surface source region. The method has the advantages that the manufacturing steps can be reduced, and the machining process is simplified.

The invention relates to a low-power-consumption high-performance D-type power amplifier modulation method and circuit and a D-type audio power amplifier, and the method comprises the steps: separating a pair of BD mode modulated signals outputted by a PWM modulation module in the D-type audio power amplifier circuit into a common mode component and a differential mode component, and outputting the common mode component and the differential mode component; feeding back the common-mode component and the differential-mode component to a differential input end through a common-mode feedback link and a differential-mode feedback link respectively; wherein the common-mode component and the common-mode feedback link are completely arranged in the chip; the differential mode component and the differential mode feedback link are realized by a power MOSFET (Metal-Oxide-Semiconductor Field Effect Transistor) integrated inside the chip or an external power MOSFET; and outputting the differential mode component to a to-be-driven object through the power output stage. According to the method, after two feedback links are separated, in a zero-input mute state, no common-mode signal is sent to an output stage for amplification, and power consumption is not caused at the output stage, so that the overall efficiency is greatly improved; and meanwhile, static bottom noise is almost eliminated.

The inventive concepts provide a bidirectional switching converter including a first power metal oxide semiconductor field effect transistor (MOSFET) connecting an input voltage node to a switching node, a second power MOSFET connecting the switching node to a ground node, and a zero current detection (ZCD) auto-calibration circuit configured to perform one of an operation of generating a first offset for varying a turn-on time of the first power MOSFET according to an operation mode and an operation of generating a second offset for varying a turn-on time of the second power MOSFET according to the operation mode.

A battery pack charge and discharge control module and control method of the present invention include a main controller unit and a charge and discharge control module, wherein the charge and discharge control module includes a discharge control switch tube, a charge control switch tube, a discharge tube drive control circuit, and a charge tube drive control circuit; the discharge control switch tube and the charge control switch tube are both power MOSFETs, and a reverse-parallel parasitic diode is integrated between the drain and source; the charge control switch tube and the discharge control switch tube are connected in series with a common drain, the source of the discharge control switch tube is connected to the negative output terminal of the battery pack, and the source of the charge control switch tube is connected to the negative busbar; the positive electrode of the battery pack is connected to the positive busbar. The present invention can not only fully control the charge and discharge process of the battery pack, but also effectively solve the problem of load interruption caused by the inability of the battery to discharge in the event of a control unit failure, thereby greatly improving the reliability of the power supply of the battery backup power supply system.

The invention relates to the technical field of power semiconductor devices, in particular to a SiC power MOSFET (Metal-Oxide-Semiconductor Field Effect Transistor) device and a manufacturing method thereof, and the cellular structure of the device sequentially comprises a substrate, an N-epitaxial layer, a polysilicon gate layer, an isolation layer and a metal layer from bottom to top; two bilaterally symmetrical Pwell layers are arranged in the surface of the N-epitaxial layer; the N + layer is arranged on the Pwell layer; the P + layer is arranged on the N + layer; the surface of the N-epitaxial layer is internally provided with an alternating structure of a cross section A and a cross section B; the structure of the section A is as follows: the boundaries of the opposite sides of the two pwell layers are in the shapes of arcs bent inwards and straight bottom edge boundaries connected with the arcs; the structure of the section B is as follows: the boundaries of the two pwell layers are arc-shaped which are bent inwards; groove structures are arranged on the two sides of the cellular structure. The invention has a double-section alternating structure, can shorten the path of hole current passing through the lower part of the source region, and improves the dynamic latch-up resistance of the device.

A reliability prediction method for a power field effect transistor belongs to the technical field of power MOSFET reliability modeling. The present invention is to solve the problem of low work efficiency caused by manually adjusting model hyperparameters in the existing deep learning model for reliability prediction of power devices. It includes: S1, collecting sensor data as initial data and performing data processing on the initial data; S2, optimizing the hyperparameters of the Transformer model using a genetic algorithm to construct a GA-Transformer model; S3, transmitting the data obtained by S1 to the GA-Transformer model obtained by S2, evaluating the accuracy of the prediction based on performance indicators, predicting the remaining service life RUL, and outputting the reliability prediction result. The present invention is used for power MOSFET reliability prediction.

An apparatus includes a drain and a source on opposing sides of an epitaxial layer, a plurality of gates formed in the epitaxial layer, a source contact connected to the source, a gate contact connected to the plurality of gates, a gate-source electrostatic discharge (ESD) diode connected between the gate contact and the source contact, and a breakdown voltage enhancement and leakage prevention structure formed underneath the gate-source ESD diode structure.

The invention discloses a method for constructing a thermal resistance simulation model of a power MOSFET (Metal-Oxide-Semiconductor Field Effect Transistor) device, which comprises the following steps of: drawing a corresponding three-dimensional model according to a packaging structure of the power device, introducing the three-dimensional model on a thermal simulation analysis platform to simulate and analyze thermal distribution in the power device, and constructing a thermal resistance simulation model by utilizing a multi-layer equivalent simplification method. Equivalently simplifying a chip structure in the power device into five layers of thin films, setting equivalent characteristic parameters of each layer, and constructing a chip finite element simulation model serving as a heating source of the power device; building a thermal resistance test environment, simulating in a set temperature environment to obtain the temperature of each layer of film, and obtaining a temperature change model of the finite element simulation model of the chip; and obtaining a thermal resistance simulation model of the power device according to the temperature change model and the heat distribution in the power device. A finite element simulation method is adopted, influence factors such as an internal structure of a power device and packaging process parameters are systematically considered, and a multi-layer equivalent simplification method is utilized to construct a thermal resistance simulation model which accurately reflects internal thermal characteristics of the device.

The invention provides a power MOSFET (Metal-Oxide-Semiconductor Field Effect Transistor) device and a manufacturing method thereof. The device comprises a drain metal layer; the epitaxial structure is arranged on the drain electrode metal layer; the at least two grid electrode grooves are formed in one side, deviating from the drain electrode metal layer, of the epitaxial structure; gate polycrystalline silicon is arranged in the gate trench; the at least one source electrode groove is arranged between two adjacent grid electrode grooves, and source electrode polycrystalline silicon is arranged in the source electrode groove; and the source electrode metal layer is electrically connected with the source electrode polycrystalline silicon. According to the invention, under the condition that the channel density is not reduced, the source-drain capacitance can be increased, and the EMI characteristic of the device can be optimized by adjusting the resistance of the source polysilicon in the source trench.

The utility model provides a switching device. The switching device comprises a tube shell, an MOSFET tube core and a TVS tube core group, wherein the MOSFET tube core and the TVS tube core group are arranged in the tube shell; the tube shell comprises a tube seat, a plurality of leading-out ends and an accommodating groove; a first metalized region, a second metalized region and a third metalized region are arranged at the bottom of the accommodating groove at intervals and are respectively connected with the leading-out end; the MOSFET tube core is attached to the first metallization region, the drain electrode is electrically connected with the first metallization region, and the source electrode and the grid electrode are electrically connected with the second metallization region and the third metallization region through bonding wires respectively; and the TVS tube core group comprises two TVS tube cores of which the cathodes are connected, and the anodes of the two TVS tube cores are electrically connected with the second metallization region and the third metallization region through bonding wires respectively. The two TVS chips are integrated between the grid electrode and the source electrode of the MOSFET through the design of the tube socket and the metallization area in the tube socket, so that a good electrostatic protection effect on the grid electrode of the power MOSFET is achieved, and the purpose of improving the ESD resistance of the power MOSFET device is achieved.

This invention belongs to the field of power semiconductor technology, specifically relating to a silicon carbide power MOSFET and its fabrication method. The silicon carbide power MOSFET provided by this invention includes a substrate, a first epitaxial layer, a first CSL layer, a first P-body region, a second epitaxial layer, a second CSL layer, and a second P-body region. A trench region is provided between the two P-body regions, with P+ regions injected at the bottom of the trench and N+ regions distributed on the sidewalls. Specifically, the on-resistance is reduced by the double CSL layer and P-body structure, while the JFET region length is extended to limit short-circuit current, significantly improving short-circuit withstand time. This makes it suitable for high-power, high-reliability power electronic devices.

The utility model discloses a high-power MOSFET device structure with low on-resistance, which relates to the technical field of MOSFET devices, and comprises a device main body, heat dissipation assemblies and a protection assembly, the lower side of the device main body is connected with pins, the left side and the right side of the device main body are provided with the heat dissipation assemblies, the outer side of the device main body is provided with the protection assembly, and the protection assembly is connected with the pins. And the protection assembly comprises a protection cover frame, ventilation grooves, a fixed connecting frame and a magnetic suction plate, the ventilation grooves are formed in the protection cover frame at equal intervals, and the fixed connecting frame is integrally fixed to the lower side of the protection cover frame. According to the high-power MOSFET device structure with the low on-resistance, the device body and the pins form the high-power MOSFET device structure with the low on-resistance, the protective cover frame can be arranged on the outer side of the device body in an upward sliding mode when not in use, a certain protection effect is achieved on the device body, the protective cover frame and the fixed connecting frame can slide downwards when in use, the protective cover frame and the fixed connecting frame are made to be located on the outer sides of the pins, and therefore the protective cover frame and the fixed connecting frame can be prevented from being damaged. And the pins are prevented from being bent and damaged.

The invention discloses a low-on-resistance split-gate power MOSFET (Metal-Oxide-Semiconductor Field Effect Transistor) structure and a manufacturing method thereof. The MOSFET structure comprises a doped semiconductor layer of a first conductive type, a first metal oxide semiconductor layer and a second metal oxide semiconductor layer, wherein the doped semiconductor layer is arranged on a substrate; the two split gate trenches are arranged in the semiconductor layer in parallel, and trench corners are arranged between the bottoms and the side surfaces of the split gate trenches; the two doped transition regions are located in the semiconductor layer in a spaced mode and at least surround the groove corners of the two split gate grooves respectively; wherein the doping concentration of the first conductive type shown in the doped transition region is smaller than the doping concentration of the first conductive type of the semiconductor layer outside the doped transition region, so that the reverse withstand voltage is enhanced, and meanwhile, the on-resistance of the SGT device is further reduced.

A bidirectional isolated high voltage DC-DC converter includes a primary three-level circuit, a capacitor-inductor-inductor-capacitor (CLLC) resonant tank network connected to the primary three-level circuit, a secondary three-level circuit connected to the CLLC resonant tank network, and a controller that controls one or more of the components of the bidirectional isolated high voltage DC-DC converter. The primary three-level circuit and the secondary three-level circuit include capacitor middle points having respective voltages that are actively controlled by the controller. The controller implements a novel space vector PWM (SVPWM). The secondary capacitor middle point is chassis grounded to provide an optimal system level partial discharge hazard management for aircraft. vehicle and vessel applications. GaN power MOSFETs are used for high frequency operation of the power switches.

The application provides a single-point detection device and method for a safe working area of a power MOSFET, and relates to the technical field of semiconductor device testing. The single-point detection device comprises a pulse trigger circuit, a sampling feedback circuit, a driving amplification circuit, a capacitor energy storage circuit and a data collector. The pulse trigger circuit is used for outputting a pulse signal with a preset width according to a conduction time corresponding to a specific test point. The sampling feedback circuit is used for collecting a drain current of the power MOSFET and generating a feedback signal. The driving amplification circuit drives the power MOSFET to be turned on or turned off according to the feedback signal and the pulse signal. The capacitor energy storage circuit provides a target drain-source voltage for the power MOSFET according to a drain-source voltage corresponding to the specific test point. The data collector records waveforms of the drain-source voltage and the drain current of the power MOSFET. The single-point detection device does not need to increase an additional circuit, parameter matching is realized by adjusting devices in the single-point detection device, the test efficiency is improved, and the single-point detection device has the advantages of high efficiency, flexibility, high precision and the like.

The invention provides a power MOSFET (Metal-Oxide-Semiconductor Field Effect Transistor) wide SOA (Silicon On Architecture) structure preparation process and a chip, a well region is arranged among a plurality of first grooves, a first injection region is arranged in the well region, and a plurality of second injection regions are correspondingly arranged below a part of the well region, so that an MOSFET device with a wider safe working region can be realized; moreover, a proper threshold voltage value is obtained, the overcurrent capability of the SOA can be improved by nearly 2-3 times, and the thermal stability is synchronously reduced.

To provide a power metal oxide semiconductor field effect transistor (MOSFET) having a gate source electrostatic discharge (ESD) diode structure and a high voltage resistance and leakage prevention structure.SOLUTION: A power MOSFET 100 includes a substrate 102, an epitaxial layer 104, a plurality of gates 702, 704, 706, a body having first and second body regions 802, 804, a source having first and second source regions 912, 914, an interlayer insulating layer 920, a plurality of source contact plugs 951, 952, 953, a gate contact plug 954, a gate source ESD diode structure 929 connected between the gate contact and the source contact, a source contact 962, a gate contact 964, a drain contact 966, and a body ring structure 820 formed under the gate source ESD diode structure, functioning as a high voltage resistance and leakage prevention structure.SELECTED DRAWING: Figure 1

A power MOSFET driver circuit includes a feedback circuit configured to supply a feedback signal that signals when a gate voltage of the power MOSFET crosses a plateau value and the power MOSFET switches conduction state. The feedback circuit includes a comparator with a replica MOSFET of the power MOSFET, with scaled down dimensions, whose gate is coupled to the gate electrode of the power MOSFET. A bistable circuit has an input coupled to an output of the replica MOSFET and is configured to change a logic state of the feedback signal following the transition of the switching signal when the gate voltage of the power MOSFET crosses the plateau value and the power MOSFET switches conduction state.