251 results about "Power MOSFET" patented technology

The invention relates to the technical field of MOS (Metal Oxide Semiconductor) semiconductors, and discloses a semiconductor device with an integrated heat dissipation function for a power MOSFET (Metal Oxide Semiconductor Field Effect Transistor). The single MOS cell comprises a drain electrode, a semiconductor epitaxial layer, a source electrode and a grid electrode, the semiconductor epitaxial layer comprises an N substrate layer, an N drift layer, a P + layer, an N well layer and a P well layer, the profile of the cross section of the grid electrode is in an H shape, and the grid electrode comprises two longitudinal parts and a transverse part used for bridging the two longitudinal parts. According to the invention, the H-shaped gate structure is in bridge connection with the double longitudinal grooves through the transverse part, so that the channel width is increased, and the on-resistance is reduced; a current path is further optimized by combining a metal deposition layer and a heavily doped N + layer in the bottom doping layer; and the metal layer is connected in parallel to conduct electricity, so that the resistance is reduced, and the heavily doped N + layer inhibits the JFET effect, so that the resistance is reduced by more than 10%.

The present application discloses a structure of a trench-gate power MOSFET and a manufacturing method thereof. The structure includes: a second epitaxial layer; a strip-shaped P pillar, the length direction of the strip-shaped P pillar being parallel to the projection direction of the crystal orientation with the most obvious channel effect on the surface of the epitaxial material; a trench gate, including a trench, the trench being parallel to the length direction of the strip-shaped P pillar or perpendicular to the length direction of the strip-shaped P pillar, and filling a filler into the trench to manufacture the trench gate. When the length direction of the trench is parallel to the length direction of the strip-shaped P pillar, the trench is located directly above the strip-shaped P pillar and has the same width as the strip-shaped P pillar. When the length direction of the trench is perpendicular to the length direction of the strip-shaped P pillar, the width of the trench is not related to the strip-shaped P pillar; a surface source region. The advantage of the present application is that it can reduce the manufacturing steps and simplify the processing technology.

An apparatus includes a drain and a source on opposing sides of an epitaxial layer, a body region and a plurality of gates formed in the epitaxial layer, an interlayer dielectric layer over the epitaxial layer, a gate-source electrostatic discharge (ESD) diode in the interlayer dielectric layer, a source contact connected to the source and a first terminal of the gate-source ESD diode structure, a gate contact connected to the plurality of gates and a second terminal of the gate-source ESD diode structure, a drain contact on opposing sides of the epitaxial layer of the source contact, a breakdown voltage enhancement and leakage prevention structure formed underneath the gate-source ESD diode structure, wherein the breakdown voltage enhancement and leakage prevention structure comprises a body ring structure.

An apparatus includes a drain and a source on opposing sides of an epitaxial layer, a body region and a plurality of gates formed in the epitaxial layer, an interlayer dielectric layer over the epitaxial layer, a gate-source electrostatic discharge (ESD) diode in the interlayer dielectric layer, a source contact connected to the source and a first terminal of the gate-source ESD diode structure, a gate contact connected to the plurality of gates and a second terminal of the gate-source ESD diode structure, a drain contact on opposing sides of the epitaxial layer of the source contact, a breakdown voltage enhancement and leakage prevention structure formed underneath the gate-source ESD diode structure, wherein the breakdown voltage enhancement and leakage prevention structure comprises a body ring structure.

The invention discloses a mixed function bridgeless topology circuit adopting a GaN device, which adopts a solution of combining totem-pole-like bridgeless and LLC (Logical Link Control), can simultaneously realize three functions of bridgeless rectification, power factor correction (PFC) and isolated direct current-direct current (DC / DC) conversion, and harmonic waves can meet the requirements of the industrial field. The topology circuit only needs four high-speed GaN power HEMT devices, two low-speed Si power MOSFET devices, two low-speed Si power thyristors and one auxiliary small inductor capable of correcting input current waveforms, does not need a rectifier bridge, only needs one-stage control to stabilize output voltage, and greatly simplifies the difficulty of system design.

A power inverter is provided. The power inverter includes: first, second and third legs configured to output alternating voltages having different phases. Each the first leg, the second leg, and the third leg includes: a first power metal oxide semiconductor field effect transistor (MOSFET) on a SiC substrate, and connected between a power terminal of direct current voltage and an output terminal configured to output a voltage of a corresponding phase among the first phase, the second phase and the third phase; a second power MOSFET on the SiC substrate, and connected between the output terminal and a ground terminal; and a redundancy circuit including a redundancy power transistor configured to replace the first power MOSFET based on the first power MOSFET failing and replace the second power MOSFET based on the second power MOSFET failing.

A trench gate power MOSFET, including: a substrate provided with a hexagonal wide bandgap semiconductor of a first conductivity type; an epitaxial layer grown on the substrate and of the first conductivity type; a body region formed on the epitaxial layer and of a second conductivity type; a trench formed in the body region by etching, where a length direction of the trench is parallel to a projection, on the surface of a wafer, of the C axis; a second conductivity-type pillar formed by implanting first ions into a bottom region of the trench along the C axis of the hexagonal wide bandgap semiconductor material, where the bottom region of the trench is located below the trench, and is connected to the bottom of the trench, and the longitudinal depth of the second conductivity-type pillar is at least not less than 50% of the thickness of the epitaxial layer located in the bottom region of the trench; and a trench gate formed by filling the trench with a filler.

A system and a method for controlling a power MOSFET for limiting electromagnetic interference from a load is provided. The system and method include a pulse-width-modulated (PWM) control voltage to operate the power MOSFET in accordance with its Ohmic region (linear mode). By operating the power MOSFET in its Ohmic region, the electromagnetic field generated by the load is reduced, without requiring a dedicated DC / DC converter that would otherwise increase the cost, size, and weight of the power electronics.

The invention relates to a low-power-consumption high-performance D-type power amplifier modulation method and circuit and a D-type audio power amplifier, and the method comprises the steps: separating a pair of BD mode modulated signals outputted by a PWM modulation module in the D-type audio power amplifier circuit into a common mode component and a differential mode component, and outputting the common mode component and the differential mode component; feeding back the common-mode component and the differential-mode component to a differential input end through a common-mode feedback link and a differential-mode feedback link respectively; wherein the common-mode component and the common-mode feedback link are completely arranged in the chip; the differential mode component and the differential mode feedback link are realized by a power MOSFET (Metal-Oxide-Semiconductor Field Effect Transistor) integrated inside the chip or an external power MOSFET; and outputting the differential mode component to a to-be-driven object through the power output stage. According to the method, after two feedback links are separated, in a zero-input mute state, no common-mode signal is sent to an output stage for amplification, and power consumption is not caused at the output stage, so that the overall efficiency is greatly improved; and meanwhile, static bottom noise is almost eliminated.

The inventive concepts provide a bidirectional switching converter including a first power metal oxide semiconductor field effect transistor (MOSFET) connecting an input voltage node to a switching node, a second power MOSFET connecting the switching node to a ground node, and a zero current detection (ZCD) auto-calibration circuit configured to perform one of an operation of generating a first offset for varying a turn-on time of the first power MOSFET according to an operation mode and an operation of generating a second offset for varying a turn-on time of the second power MOSFET according to the operation mode.

An apparatus includes a drain and a source on opposing sides of an epitaxial layer, a plurality of gates formed in the epitaxial layer, a source contact connected to the source, a gate contact connected to the plurality of gates, a gate-source electrostatic discharge (ESD) diode connected between the gate contact and the source contact, and a breakdown voltage enhancement and leakage prevention structure formed underneath the gate-source ESD diode structure.

The invention provides a power MOSFET (Metal-Oxide-Semiconductor Field Effect Transistor) device and a manufacturing method thereof. The device comprises a drain metal layer; the epitaxial structure is arranged on the drain electrode metal layer; the at least two grid electrode grooves are formed in one side, deviating from the drain electrode metal layer, of the epitaxial structure; gate polycrystalline silicon is arranged in the gate trench; the at least one source electrode groove is arranged between two adjacent grid electrode grooves, and source electrode polycrystalline silicon is arranged in the source electrode groove; and the source electrode metal layer is electrically connected with the source electrode polycrystalline silicon. According to the invention, under the condition that the channel density is not reduced, the source-drain capacitance can be increased, and the EMI characteristic of the device can be optimized by adjusting the resistance of the source polysilicon in the source trench.

The utility model provides a switching device. The switching device comprises a tube shell, an MOSFET tube core and a TVS tube core group, wherein the MOSFET tube core and the TVS tube core group are arranged in the tube shell; the tube shell comprises a tube seat, a plurality of leading-out ends and an accommodating groove; a first metalized region, a second metalized region and a third metalized region are arranged at the bottom of the accommodating groove at intervals and are respectively connected with the leading-out end; the MOSFET tube core is attached to the first metallization region, the drain electrode is electrically connected with the first metallization region, and the source electrode and the grid electrode are electrically connected with the second metallization region and the third metallization region through bonding wires respectively; and the TVS tube core group comprises two TVS tube cores of which the cathodes are connected, and the anodes of the two TVS tube cores are electrically connected with the second metallization region and the third metallization region through bonding wires respectively. The two TVS chips are integrated between the grid electrode and the source electrode of the MOSFET through the design of the tube socket and the metallization area in the tube socket, so that a good electrostatic protection effect on the grid electrode of the power MOSFET is achieved, and the purpose of improving the ESD resistance of the power MOSFET device is achieved.

This invention belongs to the field of power semiconductor technology, specifically relating to a silicon carbide power MOSFET and its fabrication method. The silicon carbide power MOSFET provided by this invention includes a substrate, a first epitaxial layer, a first CSL layer, a first P-body region, a second epitaxial layer, a second CSL layer, and a second P-body region. A trench region is provided between the two P-body regions, with P+ regions injected at the bottom of the trench and N+ regions distributed on the sidewalls. Specifically, the on-resistance is reduced by the double CSL layer and P-body structure, while the JFET region length is extended to limit short-circuit current, significantly improving short-circuit withstand time. This makes it suitable for high-power, high-reliability power electronic devices.

The utility model discloses a high-power MOSFET device structure with low on-resistance, which relates to the technical field of MOSFET devices, and comprises a device main body, heat dissipation assemblies and a protection assembly, the lower side of the device main body is connected with pins, the left side and the right side of the device main body are provided with the heat dissipation assemblies, the outer side of the device main body is provided with the protection assembly, and the protection assembly is connected with the pins. And the protection assembly comprises a protection cover frame, ventilation grooves, a fixed connecting frame and a magnetic suction plate, the ventilation grooves are formed in the protection cover frame at equal intervals, and the fixed connecting frame is integrally fixed to the lower side of the protection cover frame. According to the high-power MOSFET device structure with the low on-resistance, the device body and the pins form the high-power MOSFET device structure with the low on-resistance, the protective cover frame can be arranged on the outer side of the device body in an upward sliding mode when not in use, a certain protection effect is achieved on the device body, the protective cover frame and the fixed connecting frame can slide downwards when in use, the protective cover frame and the fixed connecting frame are made to be located on the outer sides of the pins, and therefore the protective cover frame and the fixed connecting frame can be prevented from being damaged. And the pins are prevented from being bent and damaged.

A bidirectional isolated high voltage DC-DC converter includes a primary three-level circuit, a capacitor-inductor-inductor-capacitor (CLLC) resonant tank network connected to the primary three-level circuit, a secondary three-level circuit connected to the CLLC resonant tank network, and a controller that controls one or more of the components of the bidirectional isolated high voltage DC-DC converter. The primary three-level circuit and the secondary three-level circuit include capacitor middle points having respective voltages that are actively controlled by the controller. The controller implements a novel space vector PWM (SVPWM). The secondary capacitor middle point is chassis grounded to provide an optimal system level partial discharge hazard management for aircraft. vehicle and vessel applications. GaN power MOSFETs are used for high frequency operation of the power switches.

The application provides a single-point detection device and method for a safe working area of a power MOSFET, and relates to the technical field of semiconductor device testing. The single-point detection device comprises a pulse trigger circuit, a sampling feedback circuit, a driving amplification circuit, a capacitor energy storage circuit and a data collector. The pulse trigger circuit is used for outputting a pulse signal with a preset width according to a conduction time corresponding to a specific test point. The sampling feedback circuit is used for collecting a drain current of the power MOSFET and generating a feedback signal. The driving amplification circuit drives the power MOSFET to be turned on or turned off according to the feedback signal and the pulse signal. The capacitor energy storage circuit provides a target drain-source voltage for the power MOSFET according to a drain-source voltage corresponding to the specific test point. The data collector records waveforms of the drain-source voltage and the drain current of the power MOSFET. The single-point detection device does not need to increase an additional circuit, parameter matching is realized by adjusting devices in the single-point detection device, the test efficiency is improved, and the single-point detection device has the advantages of high efficiency, flexibility, high precision and the like.

The invention provides a power MOSFET (Metal-Oxide-Semiconductor Field Effect Transistor) wide SOA (Silicon On Architecture) structure preparation process and a chip, a well region is arranged among a plurality of first grooves, a first injection region is arranged in the well region, and a plurality of second injection regions are correspondingly arranged below a part of the well region, so that an MOSFET device with a wider safe working region can be realized; moreover, a proper threshold voltage value is obtained, the overcurrent capability of the SOA can be improved by nearly 2-3 times, and the thermal stability is synchronously reduced.

To provide a power metal oxide semiconductor field effect transistor (MOSFET) having a gate source electrostatic discharge (ESD) diode structure and a high voltage resistance and leakage prevention structure.SOLUTION: A power MOSFET 100 includes a substrate 102, an epitaxial layer 104, a plurality of gates 702, 704, 706, a body having first and second body regions 802, 804, a source having first and second source regions 912, 914, an interlayer insulating layer 920, a plurality of source contact plugs 951, 952, 953, a gate contact plug 954, a gate source ESD diode structure 929 connected between the gate contact and the source contact, a source contact 962, a gate contact 964, a drain contact 966, and a body ring structure 820 formed under the gate source ESD diode structure, functioning as a high voltage resistance and leakage prevention structure.SELECTED DRAWING: Figure 1

A power MOSFET driver circuit includes a feedback circuit configured to supply a feedback signal that signals when a gate voltage of the power MOSFET crosses a plateau value and the power MOSFET switches conduction state. The feedback circuit includes a comparator with a replica MOSFET of the power MOSFET, with scaled down dimensions, whose gate is coupled to the gate electrode of the power MOSFET. A bistable circuit has an input coupled to an output of the replica MOSFET and is configured to change a logic state of the feedback signal following the transition of the switching signal when the gate voltage of the power MOSFET crosses the plateau value and the power MOSFET switches conduction state.

A charge recycling circuit in an integrated circuit DC-DC converter having two power MOSFETs, the charge recycling circuit comprising a single inductor and recycling MOSFET switches arranged and sized such that when one of the two power MOSFETs is turning off, its gate capacitance charges are transferred to the single inductor, stored in the single inductor and then transferred directly to the gate of the other power MOSFET to turn it on.

According to the medium-high voltage shielding grid power MOSFET layout and the MOSFET provided by the embodiment of the invention, charge balance can be optimized and point discharge can be avoided by changing the space between the first groove region, closest to the cellular region, of the terminal region and the second groove region of the cellular region, so that IDSS is optimized and breakdown voltage is improved.

The application discloses a trench gate power MOSFET device with anti-single event burnout reinforcement and a preparation method thereof, which comprises the following steps: etching a deep trench at a center position of the device and forming a P-type shielding area and depositing N-type polysilicon; forming a current expansion layer between a boron-doped area and an N-type drift area by means of ion implantation; and forming a P-type high-concentration doped area and an N-type high-concentration source area above the boron-doped area by means of ion implantation. According to the technical scheme, the internal electric field of the device can be modulated, the electric field distribution on the heavy ion incident track is smoother, the instantaneous power density of the device is reduced, the local high temperature is reduced, the trench oxide layer is protected from high temperature, the forward conduction capability of the device is improved, and the anti-single event burnout capability of the device can be remarkably improved without sacrificing the basic electrical characteristics of the device.

A controllable wide-adaptation MOSFET turn-on gate drive circuit and drive method, which relates to the field of power electronics. In the design of this circuit, the drain-source side information of the power MOSFET to be controlled is not introduced. Only by finely controlling the gate voltage of the power MOSFET to be controlled, the regulation of the drain-source voltage and current trajectory of the power MOSFET to be controlled during the turn-on process is realized. This circuit matches the parasitic parameters of the power MOSFET to be controlled through parameter configuration to improve the applicability. During the turn-on process of the power MOSFET to be controlled, the voltage rising slope of the gate voltage in the stage higher than the threshold voltage is regulated, so as to realize the regulation of the drain-source voltage and current trajectory, and further regulate the electromagnetic noise generated by the drain-source current during the reverse recovery stage in the turn-on process according to the requirements of the power electronic device, solving the problems that the existing power MOSFET drive circuit is difficult to finely and continuously regulate the gate voltage during the turn-on process, unable to make the drain-source voltage and current meet both low electromagnetic interference and low loss during the turn-on process, and difficult to meet the high power density requirements of power electronic devices.

A circuit (21) can be used as part of an electric drive system having a direct current (DC) voltage source (18), a DC link capacitor (17) and an inverter circuit (11) for powering an electric machine (12). The circuit (21) comprises a driver circuit (15) connected to a gate terminal of a power switch (20), such as a silicon carbide power metal oxide semiconductor field effect transistor (SiC power MOSFET). The power switch (20) has a gate-to-source voltage responsive to the drive voltage (VDR), a degradation interval during which the gate-to-source voltage increases from a relatively low voltage level below the threshold voltage toward a relatively high voltage level above the threshold voltage. The drive circuit (15) is operable to shape a trajectory of the drive voltage (VDR) over a degradation interval such that the drive voltage (VDR) is non-linear over an entire duration of the degradation interval.

The present invention provides a super-junction power MOSFET structure with optimized linear output and a preparation method thereof, which are used to solve the technical problem that the output signal of the traditional SJMOS device structure is distorted or generates unnecessary harmonics, resulting in the inability of the power management system to output stably. The present invention provides multiple pillar regions within the silicon drift region, and is provided with a guard ring and a surface guard ring on the outside thereof; the width and doping concentration of the pillar regions and the guard rings are both distributed in a gradient decreasing from top to bottom; the upper surfaces of the multiple pillar regions are sequentially provided with a shield region and a base region from bottom to top, and the shield region is wider than the base region; JFET regions are provided on both sides of the shield region and the base region, and the doping concentration of the shield region and the JFET region is distributed in an inverse gradient, and the corresponding depth of the doping peak concentration is located at the bottom of the base region; the doping concentration of the shield region is higher than that of the base region, and the doping concentration of the JFET region is higher than that of the silicon drift region; the base region is provided with a source region and a source electrode contact region, and the source electrode is conductively connected to the source electrode contact region.

The invention provides a CLIP packaging process for a power MOSFET, and belongs to the technical field of packaging, the CLIP packaging process comprises three axial movement mechanisms, each axial movement mechanism comprises an inner rail and an outer rail which are nested with each other, a magnetic suspension driving assembly is arranged between the inner rail and the outer rail, and the magnetic suspension driving assembly is arranged between the inner rail and the outer rail. The magnetic suspension driving assembly comprises permanent magnet arrays distributed in the length direction of the inner rail at intervals, and electromagnetic coil sets arranged on the inner side of the outer rail and arranged corresponding to the permanent magnet arrays. The precision of a magnetic suspension driving assembly and a grating ruler is 0.1 micrometer, non-contact linear motion of an inner rail is achieved, closed-loop control is matched, the motion positioning precision is greatly improved, the precise control requirement of power MOSFETTCLIP packaging for the tiny dispensing amount is met, the three axial motion mechanisms are connected through an angle-adjustable connecting base, the relative angle can be flexibly adjusted, and the relative angle can be adjusted. Therefore, the spatial posture of the dispensing execution assembly is changed, and the requirements for different dispensing positions and angles in different packaging processes are met.

The application discloses a partial feedback push-pull type driving power MOSFET circuit, which comprises branch A, branch B and branch C; the branch A comprises a first PMOS transistor MP1, a second PMOS transistor MP2, a first NMOS transistor MN1 and a second NMOS transistor MN2; the branch B comprises a third PMOS transistor MP3, a third NMOS transistor MN3, a first resistor R1 and a second resistor R2; and the branch C comprises a power MOS transistor M0. The partial feedback push-pull type driving power MOSFET circuit can effectively reduce di / dt through local feedback.

A semiconductor device includes first to third electrodes, a semiconductor part, a control electrode and an insulating body. The second electrode is opposite to the first electrode. The semiconductor part is provided between the first electrode and the second electrode. The semiconductor part includes first and second trenches next to each other in a front side facing the second electrode. The second trench has a first width in a first direction directed from the first trench toward the second trench. The third electrode and the control electrode are provided inside the first trench. Another third electrode and the insulating body is provided inside the second trench. The insulating body is positioned in the second trench between said another third electrode and the second electrode. The insulating body has a second width in the first direction. The second width is equal to the first width of the second trench.

An electrical circuit (21) is usable as part of an electric drive system having a direct current (DC) voltage supply (18), a DC link capacitor (17), and an inverter circuit (11) for powering an electric machine (12). The electrical circuit (21) includes a driver circuit (15) connected to a gate terminal of a power switch (20), e.g., a silicon carbide power metal-oxide semiconductor field effect transistor (SiC power MOSFET). The power switch (20) has a gate-to-source voltage responsive to a driving voltage (VDR), and a degradation interval during which the gate-to-source voltage increases from a relatively low voltage level below a threshold voltage toward a relatively high voltage level above the threshold voltage. The driver circuit (15) is operable to shape a trajectory of the driving voltage (VDR) over the degradation interval such that the driving voltage (VDR) is non-linear across over a full duration of the degradation interval.