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1212 results about "Switch matrix" patented technology

FPGA with register-intensive architecture

Field programmable gate arrays (FPGA's) may be structured in accordance with the disclosure to have a register-intensive architecture that provides, for each of plural function-spawning LookUp Tables (e.g. a 4-input, base LUT's) within a logic block, a plurality of in-block accessible registers. A register-feeding multiplexer means may be provided for allowing each of the plural registers to equivalently capture and store a result signal output by the corresponding, base LUT of the plural registers. Registerable, primary and secondary feedthroughs may be provided for each base LUT so that locally-acquired input signals of the LUT may be fed-through to the corresponding, in-block registers for register-recovery purposes without fully consuming (wasting) the lookup resources of the associated, base LUT. A multi-stage, input switch matrix (ISM) may be further provided for acquiring and routing input signals from adjacent, block-interconnect lines (AIL's) and/or block-intra-connect lines (e.g., FB's) to the base LUT's and/or their respective, registerable feedthroughs. Techniques are disclosed for utilizing the many in-block registers and/or the registerable feedthroughs and/or the multi-stage ISM's for efficiently implementing various circuit designs by appropriately configuring such register-intensive FPGA's.
Owner:LATTICE SEMICON CORP

Method and system for communicating with and tracking RFID transponders

An RFID system and method for communicating between a host computer, one or more interrogators connected to the host computer, and a large body of transponders distributed within an area covered by the interrogators. Each transponder originally has a common identification code, and upon initialization by the host computer internally generates a unique identification code based upon an internally generated random number. The host, through the interrogators, reads each of the identification codes associated with each transponder by iteratively transmitting a read identification code command along with a controlled variable. Each transponder compares the received controlled variable to an internally generated random number, and selectively transmits its identification code based upon the outcome of this comparison. After the completion of each read identification code iteration, the host adjusts the controlled variable based upon the responses received in the previous iteration. Preferably, communications between the interrogators and the transponders are DSSS signals in TDMA format, and the transponders use the random number generator to assign a time slot for transmission of their response. Each interrogator includes an antenna system utilizing a switch matrix to connect multiple antennas having different polarizations, which ensures that all transponders within the range of the interrogator receive the signals from the interrogator. In a further aspect, the interrogators are arranged in groups, each group in nearest neighbor format, to reduce the time for reading the transponders and the emissions generated when more than one interrogator is active at the same time.
Owner:TERRESTRIAL COMMS LLC

Digital signal processor containing scalar processor and a plurality of vector processors operating from a single instruction

A digital data processor integrated circuit (1) includes a plurality of functionally identical first processor elements (6A) and a second processor element (5). The first processor elements are bidirectionally coupled to a first cache (12) via a crossbar switch matrix (8). The second processor element is coupled to a second cache (11). Each of the first cache and the second cache contain a two-way, set-associative cache memory that uses a least-recently-used (LRU) replacement algorithm and that operates with a use-as-fill mode to minimize a number of wait states said processor elements need experience before continuing execution after a cache-miss. An operation of each of the first processor elements and an operation of the second processor element are locked together during an execution of a single instruction read from the second cache. The instruction specifies, in a first portion that is coupled in common to each of the plurality of first processor elements, the operation of each of the plurality of first processor elements in parallel. A second portion of the instruction specifies the operation of the second processor element. Also included is a motion estimator (7) and an internal data bus coupling together a first parallel port (3A), a second parallel port (3B), a third parallel port (3C), an external memory interface (2), and a data input/output of the first cache and the second cache.
Owner:CUFER ASSET LTD LLC

Method and system for communicating with and tracking RFID transponders

An RFID system and method for communicating between a host computer, one or more interrogators connected to the host computer, and a large body of transponders distributed within an area covered by the interrogators. Each transponder originally has a common identification code, and upon initialization by the host computer internally generates a unique identification code based upon an internally generated random number. The host, through the interrogators, reads each of the identification codes associated with each transponder by iteratively transmitting a read identification code command along with a controlled variable. Each transponder compares the received controlled variable to an internally generated random number, and selectively transmits its identification code based upon the outcome of this comparison. After the completion of each read identification code iteration, the host adjusts the controlled variable based upon the responses received in the previous iteration. Preferably, communications between the interrogators and the transponders are DSSS signals in TDMA format, and the transponders use the random number generator to assign a time slot for transmission of their response. Each interrogator includes an antenna system utilizing a switch matrix to connect multiple antennas having different polarizations, which ensures that all transponders within the range of the interrogator receive the signals from the interrogator. In a further aspect, the interrogators are arranged in groups, each group in nearest neighbor format, to reduce the time for reading the transponders and the emissions generated when more than one interrogator is active at the same time.
Owner:TERRESTRIAL COMMS LLC
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