43 results about "Parallel port" patented technology

The invention discloses a power supply method for high-speed parallel port interconnection between large-scale Chiplets, and the method comprises the steps: in a Chiplet interconnection circuit, a TX end is connected with a plurality of drivers, each driver is connected with a transmission link, and a plurality of transmission links are formed; the number of the transmission links sharing one LDO is calculated through a preset algorithm, and the number and the distribution position of the required LDO are obtained according to the number and the distance of the transmission links, so that each transmission link supplements power supply charges in time. In a system in which a plurality of Chiplets work in parallel, the method can ensure that each Chiplet obtains accurate voltage, performance reduction or faults caused by power supply fluctuation are avoided, and therefore the overall reliability and stability of the system are improved. The LDO in the method is small in size and simple in design, required external elements (such as an inductor and a capacitor) can be effectively reduced, and then the overall size and cost of the system are reduced.

The present application relates to the field of integrated circuit technologies and provides a training system and method for a high-speed parallel port IP. The system includes: a high-speed transceiver for transmitting and receiving data and command signals; a delay and reference voltage regulator for performing delay adjustment and reference voltage adjustment; a multi-branch generator for separately generating command combinations, data sequences, and adjustment signals; a microprocessor for controlling the generation of the multi-branch generator based on a first instruction combination; and an instruction memory for storing the first instruction combination. The microprocessor is further configured to generate, based on the first instruction combination, a first scanning strategy including a first scanning object, which is determined based on a first high-speed parallel port IP. The microprocessor controls the generation of the multi-branch generator to utilize the delay and reference voltage regulator to implement the first scanning strategy for the first scanning object in the data and command signals so as to complete eye diagram adaptation. In this way, flexibility and compatibility are achieved.

The utility model discloses a track circuit reader test interface switching device, and relates to the field of track circuit equipment. The utility model aims to solve the problem that the traffic safety is influenced because the number of test items of TCR equipment is small. According to the track circuit reader test interface switching device of the utility model, a CAN signal input / output end of a CAN isolation transmit-receive module is used for being connected with a CAN bus of a DB15 connector, and a logic level input / output end of the CAN isolation transmit-receive module is connected with a logic level input / output end of an MCU. The parallel port information input and output end of the MCU is connected with the parallel port information input and output end of the optocoupler, and the optocoupler outputs or receives signals through the external input and output signal test interface module.

The invention discloses a parallel port type hexagonal frequency mixing solid-state transformer and a regulation and control method and device thereof, and the method comprises the steps: under the conditions that the direct-current active power and the alternating-current active power of the solid-state transformer are equal, and the instantaneous active power absorbed by each sub-bridge arm is 0, calculating the frequency of each sub-bridge arm in each sub-bridge arm; the stability relation between the fundamental frequency alternating current port current distribution coefficient and the intermediate frequency alternating current port current distribution coefficient is determined; and calculating a bridge arm circulation current through the stability relationship, thereby calculating to obtain a bridge arm circulation voltage reference value, calculating to obtain a sub-module capacitor voltage reference value of each sub-bridge arm, superposing each sub-module capacitor voltage correction component of each sub-bridge arm, obtaining a corresponding optimized sub-module capacitor voltage, and generating a corresponding modulation signal. By the adoption of the technical scheme, the multi-scene access requirement of the alternating current and direct current hybrid power distribution network is met, and inherent decoupling of three-frequency components including direct current, fundamental frequency and intermediate frequency can be achieved without an additional frequency selection network under the corresponding control method.

The invention belongs to the technical field of wired communication, and particularly discloses an autonomous controllable radio station access gateway device. The system comprises an Ethernet control module, a CPU module, an FPGA module, an audio digital-to-analog conversion module, a serial port interface module and a parallel port acquisition control module, wherein the Ethernet control module is used for realizing network transceiving of data; the CPU module is used for realizing encapsulation and de-encapsulation of audio media streams, serial port data and parallel port data; the FPGA module is used for realizing analysis, coding and decoding of audio, serial port and parallel port signals and network packing transmission work; the audio digital-to-analog conversion module is used for realizing sampling, transmitting and receiving of multiple paths of analog audio signals; the serial port interface module is used for realizing physical layer transmission of serial port signals; the parallel port acquisition control module is used for state acquisition of various input parallel port signals and state control of report and output parallel port signals; therefore, various radio stations and terminal equipment are accessed, differences of different equipment types and communication interfaces are shielded, and a unified network communication platform is established.

The invention provides a clock duty ratio calibration circuit and device applied to a high-speed interconnection parallel port. A duty ratio adjustment module is used for receiving an input clock signal and adjusting the duty ratio of the input clock signal according to a feedback signal; the single-ended to differential module is used for converting the adjusted clock signals into differential clock signals with opposite phases; the narrow-band low-pass filter is used for extracting a direct-current level component of the differential clock signal and outputting a filtering signal; the fully differential dynamic amplifier is used for carrying out differential amplification on the filtered signal and outputting an amplified signal; the integrating capacitor module is used for integrating the amplified signal to obtain an integral voltage; the comparator is used for comparing the first integral voltage with the second integral voltage and outputting a comparison result; and the feedback path is used for connecting the output end of the comparator to the feedback input end of the duty ratio adjusting module to form a closed-loop control loop, so that the duty ratio of the input clock signal is gradually converged to the target duty ratio.

The utility model provides a control circuit for managing a sample frame of a chemiluminescence instrument, and solves the technical problems that the existing detection sample frame needs to adopt a contact mode to obtain the state of the sample frame, and the requirements of large measurement and fast speed measurement of the chemiluminescence instrument cannot be met. The serial-to-parallel circuit and the parallel-to-serial circuit are connected with the controller, and parallel ports of the serial-to-parallel circuit are connected with a plurality of indicating lamps; a parallel port of the parallel-to-serial circuit is connected with a plurality of induction circuits; the plurality of sensing circuits comprise Hall sensors, and the Hall sensors are connected and output data acquired by the Hall sensors through a parallel-to-serial circuit; the controller is used for receiving a loading signal in the Hall sensor, a communication clock signal and serial data, and sending out a control instruction for reflecting the test state of the sample rack; and the serial-to-parallel circuit is used for receiving the control instruction and controlling the level to enable the plurality of indicator lamps to change light. The control circuit can be widely applied to the technical field of control circuits.

The invention relates to the technical field of serial / parallel port testing, in particular to a function testing jig for automatic switching detection of serial port modes. The system comprises an input instruction unit, a power supply unit, an MCU main control unit, a COM switching driving unit, a data transmission interface unit and an output unit, the MCU main control unit comprises an MCU and a determination module, the COM switching driving unit comprises an RS-232 test module, an RS-422 test module and an RS-485 test module, the MCU is connected with the determination module, and the determination module is connected with the COM switching driving unit. According to the tool, the instruction is sent to the MCU, the MCU is made to control the COM switching driving unit to be switched to the designated test module, the function of the product to be tested under the test module is detected through the corresponding instruction, full-automatic detection of the COM port of the product to be tested is achieved, and the test efficiency of the tool is greatly improved.

The invention provides an embedded chip system, a program execution method thereof and embedded equipment. The embedded chip system comprises: a master control module; the storage space of the expansion program memory is divided into a plurality of CPU address accessible spaces, and high-order addresses are selected through an expansion parallel port unit; the storage space of the extended data memory is divided into a plurality of CPU address accessible spaces, and high-order addresses are selected through an extended parallel port unit; the first CPLD unit can generate a chip selection signal of an external expansion chip according to an address signal of the main control module; and the second CPLD unit can finish the state conversion of the program memory and the high-order access address control of the program memory and the data memory according to the control signal of the main control module. According to the invention, the limitation of 64Kbytes of the access address of the CPU of the single-chip microcomputer is broken through, the program memory and the data memory are expanded to 512Kbytes at most, and the method is suitable for the requirements of a complex application system with relatively large program quantity and data memory quantity.

The invention relates to the technical field of integrated circuits and provides a training system and method for a high-speed parallel port IP. The system comprises a high-speed transceiver used for receiving and transmitting data and command signals; the delay and reference voltage regulator is used for executing delay regulation and reference voltage regulation; a multi-branch generator to generate a command combination, a data sequence, and an adjustment signal, respectively; a microprocessor to control generation of the multi-branch generator based on the first combination of instructions; and the instruction memory is used for storing the first instruction combination. The microprocessor is further configured to generate a first scan policy including a first scan object based on the first instruction combination, which is determined based on the first high-speed parallel port IP. The microprocessor controls generation of the multi-branch generator so as to utilize the delay and reference voltage regulator to implement execution of a first scanning strategy on a first scanning object in the data and command signals to complete eye pattern adaptation. Therefore, flexibility and compatibility are realized.

The utility model relates to the technical field of parallel port equipment testing, and discloses a parallel port equipment testing tool and a parallel port equipment testing system, and the testing tool comprises a testing device which is used for testing parallel port equipment; the testing device is provided with a testing interface, and the parallel port equipment is provided with an output interface; one end of the switching assembly is in communication connection with the test interface, and the other end of the switching assembly is in communication connection with the output interface; the line sequence definition of the transfer connection line of the transfer assembly corresponds to the interface definition of the output interface, and the interface definition of the output interface corresponds to the type of the parallel port equipment. According to the embodiment of the utility model, the switching assembly is arranged, so that a technician only needs to formulate corresponding switching wires for different parallel port devices, the whole testing device does not need to be customized independently, the parallel port devices of different types can be tested in a compatible manner, and the testing requirements of most parallel port devices are met.

The application discloses to the technical field of power supply control, specifically a bidirectional power supply controller, including bidirectional power supply controller main body, ARM control system and FPGA control system, ARM control system and FPGA control system are installed in bidirectional power supply controller main body, ARM control system includes: first power supply control module, communication control module, first parallel port control module and ADC acquisition module, the output of first power supply control module is connected with communication control module, first parallel port control module and ADC acquisition module respectively.The application adopts the control framework of ARM+FPGA, not only can guarantee the control system of bidirectional power supply, but also can make full use of the respective advantages of ARM and FPGA, realizes a kind of real-time control occasion that can be directly used in various bidirectional power supply such as bidirectional DC / DC, bidirectional AC / DC etc.;ARM and FPGA chip adopt 16-bit data parallel port communication, realizes high-speed data exchange between chips, to meet the real-time requirements of power supply control in algorithm, communication and protection.

The invention discloses a high-throughput electromyographic signal communication and protocol construction method based on a Type-C USB interface, and relates to the technical field of man-machine interface signal communication.The method comprises the steps that a physical layer data transmission channel is constructed, uplink data are transmitted through a parallel port data line, and downlink data are transmitted through a serial port data line; defining a data packet structure; designing a response detection mechanism: formulating a verification standard of a data packet, verifying the data packet by a receiving end according to the verification standard after the sending end sends the data packet, and sending a communication state packet of which the packet label is ACK or NAK; the sending end resends the data packet after receiving the data packet of which the packet label is NAK; a timeout retransmission mechanism is designed; if the sending end does not receive the confirmation signal of the receiving end within the preset time, the sending end retransmits the data packet; and designing a communication management mechanism which comprises a data path establishment mechanism, a communication detection mechanism and a communication restart mechanism. According to the invention, low-delay and high-stability communication is realized, real-time and reliable operation of the system is ensured, and the requirement of high synchronism is met.

The present invention belongs to the technical field of measuring instruments, and is specifically a USB to 25-pin parallel port converter. The USB to 25-pin parallel port converter of the present invention includes a Teensy 3.6 single-chip microcomputer, a parallel port adapter, and a 25-pin parallel port connector; the single-chip microcomputer receives a 16-bit trigger value sent from a computer as a USB serial port device, splits it into two 8-bit integers, and then sets the levels of the pre-set 8 pins in sequence to represent the 8 bits of each integer, and transmits them to the 25-pin parallel port connector through the parallel port adapter to achieve the transmission of 16-bit integers through 8 pins. The present invention is compatible with experimental instruments that can only receive 8-bit integer trigger signals, and can operate normally in desktop or laptop computers, Windows or Ubuntu environments. It solves the problem that modern computers no longer have 25-pin parallel ports and have a small capacity for 8-bit integer trigger information, and improves the possibility of portability in implementing brain science experiments.

This application discloses a neuroelectromodulation device and its control method for synchronous electroencephalogram (EEG) detection. The neuroelectromodulation device includes: an EEG acquisition module configured for multi-channel EEG acquisition via a common electrode; a neuroelectromodulation module configured for multi-channel neuroelectromodulation operation via the common electrode; and an isolation module including a high-speed USB isolation submodule and a parallel port isolation submodule. The EEG acquisition module and the neuroelectromodulation module communicate through the isolation module. In response to the neuroelectromodulation module determining that a modulation signal with a predetermined high voltage will be output via a predetermined modulation channel in the multi-channel configuration, the neuroelectromodulation module activates the modulation component corresponding to the predetermined modulation channel, and the EEG acquisition module synchronously deactivates the analog switch corresponding to the predetermined modulation channel.

The embodiment of the application provides a method for verifying a universal parallel port, which comprises: configuring a clock rollover interval in a comprehensive top layer, so that the clock signal frequency of the universal parallel port to be verified is a set frequency value; configuring a reset signal to be pulled high after a plurality of clock cycles, so that the universal parallel port ends the reset; reading the reset value of a register and a memory after the reset ends, and confirming that the reset value is correct; performing a write-first-read-later operation on the register and the memory, and detecting the read-write function; and verifying the sending and receiving function in a double-machine connection mode. The embodiment of the application utilizes the UVM characteristics, improves the reusability and standardization of the verification environment, realizes highly randomized testing of test cases, makes up for the test points that cannot be found by manpower of the verification personnel, improves the function coverage rate, and realizes comprehensive verification of the uPP module level.

The utility model provides a serial-parallel port device based on a PCIE16X slot. The serial-parallel port device comprises a mainboard, an adapter plate and a braid wire, the braid wire comprises a bus terminal, a parallel port terminal and at least one serial port terminal, wherein the parallel port terminal and the serial port terminal are connected with the bus terminal. The mainboard is provided with at least one PCIE (Peripheral Component Interface Express) X16 slot, and the PCIE X16 slot is connected with a main control chip on the mainboard; the adapter plate is provided with a PCIE (Peripheral Component Interface Express) X16 conversion interface, the PCIE X16 end of the PCIE X16 conversion interface is connected with the PCIE X16 slot, and the conversion end of the PCIE X16 conversion interface is connected with the bus terminal. The PCIE X16 slot connected with the main control chip is arranged on the main board, the adapter plate and the braid wire are combined, the multi-serial-port and parallel-port functions of the main board are achieved, the function selecting and matching requirements of a user for the multi-serial-port and parallel-port functions are met, the PCIE X16 slot and other interfaces such as a USB port and a network port on the main board are not squeezed, a large amount of space is saved, and the cost is reduced. And the appearance and configuration upgrading of the mainboard product is facilitated.

The invention provides a 16-path switching value acquisition circuit, and relates to the technical field of switching value output printed board testing. The circuit comprises an acquisition interface, a photoelectric isolation sub-circuit, a parallel port-to-serial port sub-circuit, an acquisition display sub-circuit, an output interface and a power supply interface, the acquisition interface is used for receiving external 16-path switching value signals, the photoelectric isolation sub-circuit is used for electrically isolating the 16-path switching value signals and outputting isolated acquisition signals, and the output interface is used for outputting the isolated acquisition signals. The parallel port to serial port sub-circuit is used for converting 16 paths of parallel acquisition signals into serial signals, the acquisition display sub-circuit is used for indicating the input state of each path of acquisition signals, the output interface is used for outputting the serial signals and introducing control signals, and the power supply interface is used for providing a working power supply for the whole circuit. The problem that the workload of repeated design and development of a traditional test method is large is solved, the electrical isolation and anti-electromagnetic interference capabilities are enhanced, the signal conversion efficiency is improved, and a real-time state display function is introduced.

The invention relates to a high-integration industrial personal computer main board with multiple expansion function interfaces, which comprises a circuit main board, a CPU (Central Processing Unit) and a PCH (Platform Controller Hub), wherein the CPU and the PCH are arranged on the circuit main board; a memory module, an ATX power supply, a battery element, a hard disk, a VGA interface, an HDMI interface, a network interface socket, an audio interface, a front audio interface, an expansion slot, an audio output interface, a bus slot, an external interface, an input and output interface, a COM6, a COM5, a COM4, a COM3, a parallel port, a first fan interface, a keyboard and mouse interface, a second fan interface, a front panel interface, a USB3 interface, an SATA interface and a USB2 interface are further arranged on the circuit mainboard. The requirements of more functional interfaces are met, so that the functions of the industrial personal computer are conveniently expanded, the high integration of the mainboard is ensured, the mainboard has the diversity of the expansion functions of the mainboard, the mainboard supports more expansion functions, and the applicability of the industrial personal computer is improved.

The invention provides a time sequence description method for an IO parallel port output control time sequence, namely, a universal control time sequence description method is provided by abstracting signal characteristics aiming at the function requirement of using the IO port output time sequence, the time sequence is divided into clock signals: mclk, scaclk and cdsclk according to the control requirement of scanning equipment, and the name of a signal structure for describing a clock type is clockDesc; and level signals: TE, R LED, GLED and BLED, and setting the name of a structural body for describing the level type signals as level Desc; clockDesc or level Desc is used for independently describing each IO port signal, and IO parallel port time sequence data is generated according to the independent description of each IO port.

The invention aims to provide a clock and a control method of a PLL (Phase Locked Loop) shared by multiple parallel port PHYs (Physical Layers). The method comprises an SOC (System On Chip) phase-locked loop, a plurality of PHYs and a plurality of memory controllers, and the SOC phase-locked loop is connected with the PHY and the memory controller and is used for providing a clock signal. According to the invention, a clock scheme that a plurality of parallel port PHYs share an external PLL is adopted, the number of PLLs in a chip is saved, the area and power consumption of the chip are reduced, and the method is particularly suitable for chips with small areas and ultra-low power consumption requirements, is not only suitable for a system with a single parallel port PHY, but also suitable for a system with a multi-parallel port PHY, and is suitable for a system with a high-power-consumption chip. And the integration mode of the parallel port PHY in the SoC system becomes more flexible and diversified.

The invention discloses a general power-up and control system and method for a radio frequency BGA packaging product, and the system comprises an upper computer which is configured to generate a low-frequency control signal and a power supply control signal; the low-frequency parallel port controller is configured to receive a low-frequency control signal output by the upper computer and transmit the low-frequency control signal to a radio frequency performance test clamp for testing a radio frequency BGA packaging product through a universal power-on control line, so that signal control of any path is realized; the array type electromagnetic relay switch is configured to receive a power supply control signal output by the upper computer; and the PXI case is configured to be connected to a power supply, receive a power supply control signal transmitted by the array type electromagnetic relay switch, transmit the power supply control signal to the radio frequency performance test clamp through a universal power-up control line, and realize power-up of any path through on-off control of the array type electromagnetic relay switch. According to the invention, control and power supply unified management of different types of radio frequency BGA packaging products can be realized.

The invention provides a timing sequence compression and decompression method for IO parallel port output control timing sequence, which comprises the following steps of: segmenting the timing sequence stored in a memory to compress the memory, and then outputting each segment by an MCU (Microprogrammed Control Unit). For a scene with a small available memory of the MCU, the compression method can effectively solve the problem that the time sequence data memory is too large. Comprising the following steps: S1, describing a period; s2, performing segmentation description; and S3, starting the MCU to carry out decompression output. The method can be applied to simulation printer scanning time sequence application, and a good effect is achieved.

The utility model relates to the technical field of data acquisition, in particular to a universal data acquisition preprocessing simulation control daughter card. Comprising a master control module, a power conversion unit, a clock unit and an interface unit. The system is used for controlling various ADC acquisition chips, the ZYNQ chip is adopted to realize the connection of the SPI, the LVTTL discrete line, the 16-bit parallel port, the LVDS interface and the JESD204B interface with the ADC chip of an external acquisition system, a main data acquisition system is assisted to carry out signal preprocessing and execute preliminary data processing or analysis, the function of the main acquisition system is enhanced, and the data acquisition efficiency is improved. And more accurate signal conditioning and faster data processing capability are provided.

The four-quadrant explosion-proof frequency converter control device comprises a main control board composed of a DSP chip and an FPGA chip, the DSP chip is connected with an FPGA through a parallel port bus and an SPI bus, and the four-quadrant explosion-proof frequency converter control device is characterized in that the main control board is connected with a rectification side sub-control board and an inversion side sub-control board through receiving and transmitting optical fibers; the rectification side sub-control board and the inversion side sub-control board respectively control the on-off states of IGBT devices in the rectification circuit part and the inversion circuit part of the frequency converter, and the rectification side sub-control board detects the input current of the frequency converter; the rectification side sub-control board and the inversion side sub-control board are connected with an interface board. According to the four-quadrant explosion-proof frequency converter control device provided by the utility model, the existing mode of adopting a rectification main control board and an inversion main control board is combined into one, so that the design of the frequency converter control device is simplified, the volume is reduced, and the cost is reduced.

The application provides an implementation method and system for controlling laser printing density by using high-frequency data lines. The method and system optimize the output of the raster data stage generated by the printing image, expand the SLCD data from 1 bit to N times, and increase the frequency by N times. Therefore, the duty cycle effect of PWM is simulated by adjusting the ratio of the effective data and the filling data of N bit data, so as to achieve the effect of adjusting the printing data density. The problem that the printing density cannot be controlled in the prior art using the SLCD parallel port to simulate laser printing is solved. By using the method, the effect of the PWM duty cycle can be simulated, and the function is realized.

The application discloses a power supply method for large-scale Chiplet high-speed parallel port interconnection, wherein in a Chiplet interconnection circuit, a plurality of drivers are connected to a TX end, each driver is connected to a transmission link, and a plurality of transmission links are formed; the number of transmission links sharing one LDO is calculated by using a preset algorithm, and the number and distribution positions of required LDOs are obtained according to the number and distance of the transmission links, so that each transmission link is timely supplemented with power charges. In a system in which a plurality of Chiplets work in parallel, the method can ensure that each Chiplet obtains accurate voltage, avoids performance degradation or failure caused by power fluctuations, and thus improves the overall reliability and stability of the system. The LDO in the method is small in size and simple in design, can effectively reduce required external components (such as inductors, capacitors and the like), and thus reduces the overall size and cost of the system.

The purpose of the present invention is to provide a method for quickly evaluating the power consumption of a parallel port IO analog circuit, the method comprising: configuring the circuit to a preset working mode for simulation, testing the internal DC power consumption of the circuit; configuring the circuit to a preset working mode for simulation, testing the internal flip power consumption of the circuit; obtaining the external DC power consumption of the circuit by calculation; obtaining the external switching power consumption of the circuit by calculation. The present invention can greatly reduce the computing resources and time required to obtain power consumption data, and provides a method for accurately evaluating the power consumption changes of IO analog circuits caused by process migration.

The invention provides a parallel port communication method of a printer, the printer and a storage medium thereof, and the method comprises the steps: determining the enabling setting of a feedback signal through responding to the feedback signal sent by a host and received from a control interface; when the enabling setting is represented as effective enabling and the data transmission of the state interface is controlled to be in a forward mode, sending a response signal to the host so as to notify the host to transmit a command word signal; in response to the command word signal received from the control interface, determining support setting of the command word signal in the printing processor according to the type of the command word signal; when the support setting is represented as support, data transmission of the state interface is controlled to be in a reverse mode, and a first acquisition signal is sent to the printing processor to acquire a feedback parameter corresponding to the printing processor; and when the feedback parameter is received, the feedback parameter is sent to the host through the state interface, so that bidirectional communication is realized based on the hardware-based parallel port controller, and the stability of a communication time sequence is improved while processing resources are saved.