FPGA (Field Programmable Gate Array)-based method for realizing multi-path I2C (Inter-Integrated Circuit) bus port expansion
A bus port and peripheral bus technology, which is applied in the field of multi-channel I2C bus port expansion based on FPGA, can solve the problems of reduced communication speed, waste of time, and I2C bus can not meet the communication between devices, and achieve the effect of improving communication speed.
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[0020] In order to understand the present invention more clearly, describe the present invention in detail in conjunction with accompanying drawing and embodiment:
[0021] When the FPGA extended I2C port is configured on the FPGA port, the level of the corresponding pin needs to be selected as the I2C level mode. The high-speed parallel port is used for communication between the MCU and the FPGA, and one Byte of data can be transmitted each time. The transfer rate depends on the system clock of the MCU.
[0022] The parallel ports of MCU and FPGA are defined as follows:
[0023] ADDR_BUS[15:0] : Address bus (represents the address of the register in the FPGA)
[0024] DATA_BUS[7:0] : bidirectional data bus
[0025] WRB: write control signal, active low
[0026] RDB: read control signal, active low
[0027] RD_IRQ: read interrupt signal, active low
[0028] Two types of registers are set in the FPGA to realize the interaction between the MCU and the FPGA.
[002...
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