1 results about "Fpga implementations" patented technology

The application discloses a method for quickly testing a plurality of FPGA implementation decoders, comprising: a host computer generates a data packet and sends, receives a decoding result of a lower computer, processes a block error rate and a bit error rate; the lower computer uses a state machine to control the whole test system; a read-write control block controls writing of to-be-decoded data into two RAMs and reading of a decoding result into a FIFO; a decoding control block controls starting, reading, ending and resetting of the decoder. The method follows the idea that when one RAM is storing data, the decoder reads data in the other RAM, and compared with a test structure following the idea of series connection of generating data, sending, decoding and receiving processing, the running time can be shortened.