425results about "Frequency to pulse train conversion" patented technology

The method includes steps: sampling AC current to be monitored; based on sampled values, looking up crossover points of the sampled waveform; calculating period T of AC current to be monitored based on crossover points; calculating frequency of AC current monitored. Crossover points are searched through software directly so as to reduce hardware spending. Averaging results of multiple times of calculation obtains final outcome in high precision. Anti-interference ability is high since questionable data including too large and too small data are thrown off. Advantages are: simple and reasonable, accurate and reliable data, and high practicability.

The invention provides a frequency measurement method based on an FPGA. A standard reference clock is adopted to count the number of pulses of a measured signal in a unit time (1s) and the number of the pulses of the measured signal in the unit time (1s) is the frequency of the signal. Due to the fact that the starting moment of a gate and the finishing moment of the gate are random for the signal, a pulse period quantization error can be produced, and measurement accuracy needs to be analyzed further: the pulse period of a signal to be measured is set to be Tx, the frequency is set to be Fx, and when the measuring time T equals to 1s, the measurement accuracy & meets the equation that &=Tx/T=1/Fx. The fact that measurement accuracy in a direct frequency measurement method is relevant to the frequency of the signal is known, the higher the frequency of the signal to be measured is, the higher the measurement accuracy is, and otherwise, the lower the frequency of the signal to be measured is, the lower the measurement accuracy is. The direct frequency measurement method is only suitable for measurement of the signal at the higher frequency and can not meet the demand that the measurement accuracy remains unchanged in the whole measurement frequency band. In order to overcome the defect of inaccuracy in low-frequency-band measurement, gating signals and the measured signal are used for carrying out dual control on enable signals of the counter, and therefore accuracy is improved.

A motor control system and method are provided for detecting current ripple in a commutated DC motor and further determining position and speed of the motor based on the detected ripple current. Ripples in the motor current are detected and a ripple frequency is calculated based on the time between successive ripples. A ripple count between successive frequencies is determined and the ripple count is compared to a threshold value, and an estimated ripple frequency is determined from a motor model when the ripple count exceeds the threshold value. A corrected ripple count is calculated from a ratio of the calculated ripple frequency and the estimated ripple frequency, and motor position and motor speed are determined based on the corrected ripple count.

An electrical circuit and method for measuring small variations in a high frequency signal is disclosed. The circuit generates a coarse measurement of the input signal frequency and a reference signal having the same frequency as the frequency represented by the coarse measurement. The circuit measures the difference in frequency between the input signal and the reference signal, and adds the coarse measurement and the difference measurement to determine the frequency of the input signal. The circuit may be used in conjunction with a piezoelectric acoustic wave device and oscillator to provide an apparatus for accurately measuring low concentrations of a gas.

Systems and methods for monitoring frequencies of periodic electrical signals are disclosed. According to one technique, a first and second counters are respectively clocked by a first periodic electrical signal to be monitored and a second periodic electrical, and a threshold detector resets one of the counters when a count of the other counter crosses a reset threshold and determines whether a frequency error has occurred based on whether a count of the one of the counters crosses an alarm threshold. Another technique according to an embodiment of the invention also involves clocking counters with respective periodic electrical signals, although error detection is based on whether the counts of the counters cross respective associated thresholds in other than a particular sequence with respect to each other.

A calibration unit and technique for calibrating A/D systems (e.g., data acquisition devices) using a pulse-width modulation (PWM) circuit to reduce nonlinearity. The calibration unit may be coupled to an analog-to-digital module (ADM) of the A/D system. The PWM circuit may generate a calibration signal with intentional ripple, which may exercise a region of a transfer curve of the ADM to reduce local nonlinearities in measurements associated with the calibration of the system. Pulse trains of varying frequency and duty cycle may be generated to sweep the PWM circuit through an ADM range and to calculate an ADM linearity correction function, which may be used to perform gain and offset correction with respect to a best-fit line through an ADM transfer curve to reduce large signal nonlinearities. The PWM circuit may include a resistor divider circuit including a plurality of taps to improve the ability to calibrate small input ranges.

The invention discloses a system for automatically testing the parameters of a quartz crystal oscillator, which comprises a master computer and a parameter test card connected with the main board of the master computer, wherein the parameter test card comprises a singlechip and a test circuit and a reference circuit which are connected with the singlechip respectively. The singlechip has a D/A module, an A/D module, a first counter, a second counter and a timer. The test circuit comprises a current amplification circuit, a voltage sampling resistor, a frequency dividing circuit, a first measurement gate control circuit and the crystal oscillator to be measured. The reference circuit comprises a reference frequency source, a frequency multiplication circuit, a second measurement gate control circuit and a frequency dividing and high-frequency signal latch circuit. In the invention, the test card integrates the functions of all apparatuses such as a frequency counter, a digital voltmeter and a digital oscillometer and can be directly inserted in the main board of the computer, and the fully automatic test of various parameters, such as working frequency, working current and start up time, of the quartz crystal oscillator can be realized by a control program.

The present invention relates to a quick frequency measurement system and its method, belonging to the field of communication technology. Said system includes frequency regulator, frequency measurer and control processor. Said invention utilizes the frequency regulator to regulate tested signal and reference signal, prolong testing time length of tested signal, raise frequency of reference signal so as to obtain high-frequency count pulse, then the frequency measurer can utilize the above-mentioned high-frequency count pulse to measure regulated tested signal.

An LSI test equipment can acquire output data of an LSI as a device under test by a clock signal output from the LSI to be measured and acquire measurement data synchronously with the output data having jitter. The LSI test equipment (10) includes a clock side time interpolator (20) for acquiring the clock output from the LSI (1) to be measured by a plurality of strobes having a predetermined timing interval and outputting it as encoded level data of time series, a data side time interpolator (20) for acquiring the output data output from the LSI (1) to be measured by a plurality of strobes having a predetermined timing interval and outputting it as level data of time series, and a selector (30) for receiving the level data from both of the time interpolators, selecting output data at the clock edge timing, and outputting it as data to be measured.

A frequency detector includes an error measurement unit measuring a time interval between zero-crossing points of an input signal that is modulated. An error conversion unit quantizes the measured time interval using one of modulation time intervals. An error calculation unit calculates a frequency error based upon a difference between the measured time interval and the quantized time interval. An error generation control unit controls whether to output the frequency error based upon the quantized time interval, the calculated frequency error, and a predetermined critical value.

The invention discloses a real-time calibration and frequency measurement method for time base frequency and a device thereof, wherein the method comprises the following steps: 1) calibration step: a frequency measurement device acquires an external high-accuracy standard-frequency signal with Fs of given frequency as a calibration signal; the actual frequency value measured by the frequency measurement device is Fs'; a calibration factor K which is equal to Fs/Fs' is calculated and stored, and the calibration factor K can not be updated until the next calibration step is finished; 2) measurement step: the frequency of the unknown signal measured by the frequency measurement device is Fx', and the calculated and revised frequency value of the unknown signal Fx is equal to K * Fx'; 3) the process returns to step 1). The method and the device can ensure that, the time base frequency can be as accurate as 5E-10 and the second gate time frequency measurement can be as accurate as 1E-9 when measuring frequency and the accuracy of the measured frequency can be determined, thereby solving the problems of undetermined frequency timing base frequency accuracy, low precision, and the like of the prior art.

The invention discloses an equal-precision frequency testing system and method based on an FPGA. According to the system, frequency demultiplication is carried out on outer standard clock signals, a preset gate signal is obtained, and then an actual gate signal is obtained. The rising edge of an outer signal to be tested and the rising edge of the standard clock signal are counted so that the periodicity of the outer signal to be tested and the standard clock signal in the actual gate signal can be obtained. The frequency of the signal to be tested is obtained according to the obtained periodicity and the frequency of the standard clock signal, and finally the frequency of the signal to be tested is sent to a nixie tube to be displayed. Through the method, high frequency measurement precision can be obtained, and the measurement precision of the frequency is almost equal.

A method and counter for reducing the background counting rate in gas-filled alpha particle counters wherein the counter is constructed in such a manner as to exaggerate the differences in the features in preamplifier pulses generated by collecting the charges in ionization tracks produced by alpha particles emanating from different regions within the counter and then using pulse feature analysis to recognize these differences and so discriminate between different regions of emanation. Thus alpha particles emitted from the sample can then be counted while those emitted from the counter components can be rejected, resulting in very low background counting rates even from large samples. In one embodiment, a multi-wire ionization chamber, different electric fields are created in different regions of the counter and the resultant difference in electron velocities during charge collection allow alpha particles from the sample and counter backwall to be distinguished. In a second embodiment, a parallel-plate ionization chamber, the counter dimensions are adjusted so that charge collection times are much longer for ionization tracks caused by sample source alpha particles than for those caused by anode source alpha particles. In both embodiments a guard electrode can be placed about the anode's perimeter and secondary pulse feature analysis performed on signal pulses output from a preamplifier attached to this guard electrode to further identify and reject alpha particles emanating from the counter's sidewalls in order to further lower the counter's background.

The invention discloses a reliable time scale pulse measurement method, which comprises the following steps: 1) converting a 10MHz frequency signal of a precise clock source, a standard 1PPS signal and 1PPS, 1PPM and 1PPH signals to be measured to pulse signals; 2) carrying out frequency doubling on the 10MHz frequency signal of the precise clock source for obtaining a 100MHz frequency signal, and taking the 100MHz frequency signal as the working frequency of an FPGA; simultaneously carrying out frequency division on the standard 1PPS signal and respectively obtaining a 1PPM reference signal and a 1PPH reference signal; and 3) measuring the precision of the 1PPS, the 1PPM and the 1PPH signals to be measured according to the reference signals of 1PPS, 1PPM and 1PPH under the working frequency of 100MHz. The method can realize the high-speed and high-efficient counting operation by adopting a field programmable logic sequence, realize the multi-path and multi-group pulse fast detection, and send the detection result to a user and is characterized by stable performances and convenient maintenance.

A frequency measurement device includes: a short gate time counter section that continuously measures a pulse stream signal supplied, and outputs a series of count values that behave like a pulse stream corresponding to a frequency of the pulse stream signal; and a low-pass filter that removes high frequency components from the series of count values to obtain a level signal corresponding to the frequency of the pulse stream signal supplied.

A ring oscillator clock frequency measuring circuit includes a reference clock count timer and a ring oscillator clock count timer. The reference clock count timer starts its counting of a reference clock signal in response to a start instruction fed from a CPU, and outputs an overflow signal when its counting reaches a preset value. The ring oscillator clock count timer starts its counting of pulses of a ring oscillator clock signal in response to the start instruction fed from the CPU, and continues its counting until the reference clock count timer generates the overflow signal. The frequency of the ring oscillator clock signal is obtained from the count value of the ring oscillator clock count timer. This makes it possible to measure the frequency of the ring oscillator clock signal at high accuracy, and to reduce the current consumption by operating the CPU based on the ring oscillator clock signal after the measurement.

In a semiconductor integrated circuit, a counter counts the number of high-speed clock signals that have been generated in a predetermined number of clock cycles of a low-speed clock signal. In synchronization with the low-speed clock signal, the semiconductor integrated circuit compares the counter value and a predetermined value, and judges whether the frequency of the high-speed clock signal has reaches a predetermined frequency. Since variations in the frequency become smaller as the oscillation of a high-speed oscillator stabilizes, the semiconductor integrated circuit detects that the oscillation is stable when the semiconductor integrated circuit has judged affirmatively a plurality of times.

A D/U ratio is measured for desired and undesired signals in a wireless video transmission system at a shared channel frequency based on a received signal at a geographic location in proximity to regions within respective service areas for the desired and undesired signals. A video tuner demodulates the received signal to generate a baseband video signal. A leveling circuit normalizes the baseband signal. A video processor identifies horizontal sync pulses within the baseband signal, generates a sampled signal comprising the horizontal sync pulses, and removes components of the desired signal from the sampled signal to generate an undesired signal component. A D/U analyzer determines a Fourier transform having a plurality of bins in response to the undesired signal component, identifies at least one of the bins having a spectral peak corresponding to an undesired signal, and calculates the D/U ratio in response to a magnitude of the identified peak.

An eye diagram analyzer equips each SUT data and clock signal input channel with individually variable delays in their respective paths. For a range of signal delay of n-many SUT clock cycles, the SUT clock signal delay might be set at about n/2. For each data channel there is specified a point in time relative to an instance of the delayed clock signal (data signal delay) and a voltage threshold. The specified combination (data signal delay, threshold and which channel) is a location on an eye diagram, although the trace may or may not ever go through that location. A counter counts the number of SUT clock cycles used as instances of the reference for the eye diagram, and another counter counts the number of times the specified combination of conditions was met (“hits”). After watching a specified combination for the requisite length of time or number of events, the number of SUT clock cycles involved and the associated number of hits are stored in memory using a data structure indexed by the components of the specified combination (data signal delay, threshold). Next, a new combination of data signal delay and threshold is specified and a measurement taken and recorded in the data structure. The process is repeated until all possible combinations within a stated range of data signal delay and threshold voltage (using specified resolution/step sizes for delay and voltage) have been investigated. As this process proceeds under the control of firmware within the logic analyzer, other firmware can be examining the data structure and generating a partial eye diagram visible on a display, and that will be complete soon after the measurement itself is finished.” has been changed to “An eye diagram analyzer equips each SUT data and clock signal input channel with individually variable delays in their respective paths. For a range of signal delay of n-many SUT clock cycles, the SUT clock signal delay might be set at about n/2. For each data channel there is specified a point in time relative to an instance of the delayed clock signal (data signal delay) and a voltage threshold. The specified combination (data signal delay, threshold and which channel) is a location on an eye diagram, although the trace may or may not ever go through that location.

The invention belongs to the technical field of frequency measurement and particularly relates to a large dynamic high-precision synchronization continuous frequency measurement method. The method disclosed by the invention comprises the following steps: S1, counting synchronized sampling time gate signals by adopting a measured signal; S2, counting by adopting a high-frequency impulse; S3, counting by adopting delay cell interpolation; S4, performing error correction to determine the frequency of the measured signal. According to the method disclosed by the invention, quantization errors which cannot be recognized by a high-frequency clock in a multi-period synchronizing method are subdivided, and therefore, the resolution ratio of the errors is improved, and large dynamic multichannel signal short time synchronization continuous high-precision measurement is realized.