4581 results about "Gate control" patented technology

The invention provides an organic light emitting diode active driving system with current feedback, thereby a driving current for organic light emitting diode is not affected by variation of characteristic parameters of thin film transistor under an active driving mode. The active driving system in accordance with the invention includes a transistor and a current comparator for driving an organic light emitting diode. The transistor has two current carrying electrodes respectively connected to a cathode of the organic light emitting diode and ground, and a gate controlled by a data signal. The current comparator has two input terminals respectively receive a reference current with predetermined value and a driving current flowing through the organic light emitting diode. The current comparator compares the reference current and the driving current, and then outputs a voltage to the gate of the transistor in response to the comparison result so as to make the value of the driving current equal to that of the reference current. Therefore, the active driving system for organic light emitting diode array or flat panel display in accordance with the invention can achieve a desirable light emission uniformity.

The present invention contemplates a choke control system that provides for local and off-site monitoring and control of the annulus flow pressure of a well. The choke control system includes a choke manifold connected to at least one choke and its associated actuator; a variety of instrumental drilling sensors, pump stroke counter switches, and choke position indicators; a local choke and hydraulic pressure control console; and a programmable controller in communication with the local choke and hydraulic pressure control console. The programmable controller handles the logical operations of the choke control system, including processing instrument measurements and operator input data to produce control signals for operating the choke, the choke actuator and the various valves associated with the choke manifold. The programmable controller is typically either an electronic digital computer and / or a programmable logic controller (PLC). The present invention further contemplates the two-way communication between the choke control system and the Internet via a satellite linkage.

A solid-state imaging device includes a substrate having a first surface and a second surface, light being incident on the second surface side; a wiring layer disposed on the first surface side; a photodetector formed in the substrate and including a first region of a first conductivity type; a transfer gate disposed on the first surface of the substrate and adjacent to the photodetector, the transfer gate transferring a signal charge accumulated in the photodetector; and at least one control gate disposed on the first surface of the substrate and superposed on the photodetector, the control gate controlling the potential of the photodetector in the vicinity of the first surface.

One aspect of this disclosure relates to a memory cell. In various embodiments, the memory cell includes an access transistor having a floating node, and a diode connected between the floating node and a diode reference potential line. The diode includes an anode, a cathode, and an intrinsic region between the anode and the cathode. A charge representative of a memory state of the memory cell is held across the intrinsic region of the diode. In various embodiments, the memory cell is implemented in bulk semiconductor technology. In various embodiments, the memory cell is implemented in semiconductor-on-insulator technology. In various embodiments, the diode is gate-controlled. In various embodiments, the diode is charge enhanced by an intentionally generated charge in a floating body of an SOI access transistor. Various embodiments include laterally-oriented diodes (stacked and planar configurations), and various embodiments include vertically-oriented diodes. Other aspects and embodiments are provided herein.

A non-synchronous boost converter includes a switched Schottky diode to rectify the switched output voltage of the boost converter where the switched Schottky diode has forward conduction blocking capability. The switched Schottky diode has an anode terminal coupled to receive the switched output voltage, a cathode terminal providing the output DC voltage, and a gate terminal coupled to receive a control signal. The control signal has a first state for turning the switched Schottky diode on where the switched Schottky diode conducts current when forward biased and a second state for turning the switched Schottky diode off where forward conduction of the switched Schottky diode is blocked even when the diode is forward biased. The switched Schottky diode can be a JFET controlled or an LDMOS gate controlled Schottky diode. Furthermore, the switched Schottky diode can be formed on-chip or off-chip of the controller circuit of the boost converter.

A method for fabricating a multiple-gate device including the steps of providing a substrate of a semi-conducting layer on an insulator stack which includes an insulator layer overlying an etch-stop layer; patterning a semi-conducting layer forming a semiconductor fin; etching the insulator layer at the base of the fin forming an undercut; depositing a gate dielectric layer overlying the fin; depositing an electrically conductive layer over the gate dielectric layer; etching the electrically conductive layer forming a gate straddling across the two sidewall surfaces and the top surface of the fin; and forming a source region and a drain region in the fin.

Various embodiments of a biological interface system and related methods are disclosed. The biological interface system may comprise a sensor comprising a plurality of electrodes for detecting multicellular signals emanating from one or more living cells of a patient, a processing unit configured to receive the multicellular signals from the sensor and process the multicellular signals to produce a processed signal, and a signal gate configured to receive the processed signal from the processing unit and an alternative signal generated by the system, the signal gate being configured to transmit a control signal to a controlled device based on either the processed signal or the alternative signal. A monitoring unit may receive system data and process the system data to produce a system status signal. The system status signal may be used to determine which of the processed signal and the alternative signal is to be used as the control signal.

A graphene device includes a graphene layer and a back gate electrode connected to apply a global electrical bias to the graphene from a first surface of the graphene. At least two graphene device electrodes are each connected to a corresponding and distinct region of the graphene at a second graphene surface. A dielectric layer blanket-coats the second graphene surface and the device electrodes. At least one top gate electrode is disposed on the dielectric layer and extends over a distinct one of the device electrodes and at least a portion of a corresponding graphene region. Each top gate electrode is connected to apply an electrical charge carrier bias to the graphene region over which that top gate electrode extends to produce a selected charge carrier type in that graphene region. Such a carbon structure can be exposed to a beam of electrons to compensate for extrinsic doping of the carbon.

A modulated transformer-coupled gate control signaling method and apparatus provides reduction of circuit complexity and robust design characteristics in switching power circuits having a transformer-coupled gate drive. A modulated control signal at a rate substantially higher than the switching circuit gate control rate is provided from the controller circuit to a demodulator via transformer coupling. Power for the demodulator can be obtained by rectifying the modulated control signal at the demodulator, or from another transformer winding. The modulation scheme is chosen to have a DC average value of zero, eliminating any magnetization current management requirements. The modulated control signal may carry redundant control information and / or may encode additional information to provide a more sophisticated gate drive control, such as oversampled gate control information.

A pixel cell comprises a photo-conversion device for generating charge and a gate controlled charge storage region for storing photo-generated charge under control of a control gate. The charge storage region can be a single CCD stage having a buried channel to obtain efficient charge transfer and low charge loss. The charge storage region is adjacent to a gate of a transistor. The transistor gate is adjacent to the photo-conversion device and, in conjunction with the control gate, transfers photo-generated charge from the photo-conversion device to the charge storage region.

Field effect devices having a gate controlled via a nanotube switching element. Under one embodiment, a non-volatile transistor device includes a source region and a drain region of a first semiconductor type of material and each in electrical communication with a respective terminal. A channel region of a second semiconductor type of material is disposed between the source and drain region. A gate structure is disposed over an insulator over the channel region and has a corresponding terminal. A nanotube switching element is responsive to a first control terminal and a second control terminal and is electrically positioned in series between the gate structure and the terminal corresponding to the gate structure. The nanotube switching element is electromechanically operable to one of an open and closed state to thereby open or close an electrical communication path between the gate structure and its corresponding terminal. When the nanotube switching element is in the closed state, the channel conductivity and operation of the device is responsive to electrical stimulus at the terminals corresponding to the source and drain regions and the gate structure.

A charge pump generates gate control voltage in a DC / DC converter. The input voltage to the charge pump may vary. To reduce noise at higher input voltages, a variable resistance is included in the charge pump and that resistance is controlled to vary with the input voltage.

An orthogonal gate extended drain MOSFET (EDMOS) structure provides a low gate-to-drain capacitance (CGD) and exhibits increased reliability. It has a gate electrode that is folded into the shallow trench isolation (STI) oxide region. Horizontal and vertical gate electrode segments provide gate control. It accommodates both high voltage devices and standard CMOS components on the same substrate. Reduced surface field (RESURF) technology is employed to optimize tradeoffs between high breakdown voltage and specific on-resistance. Device fabrication steps are compatible with standard CMOS flow and process modules can be added or removed from baseline CMOS technology.

A gate controlled fin resistance element for use as an electrostatic discharge (ESD) protection element in an electrical circuit has a fin structure having a first connection region, a second connection region and a channel region formed between the first and second connection regions. Furthermore, the fin resistance element has a gate region formed at least over a part of the surface of the channel region. The gate region is electrically coupled to a gate control device, which gate control device controls an electrical potential applied to the gate region in such a way that the gate controlled fin resistance element has a high electrical resistance during a first operating state of the electrical circuit and a lower electrical resistance during a second operating state, which is characterized by the occurrence of an ESD event.

Four switching circuit sections consisting of four FETs connected in series are provided between a plurality of input / output terminals which output and input a high frequency signal. Gate control voltages are individually applied to gate terminals of four FETs, respectively, so that an on-state and an off-state are achieved. Further drain control voltages are individually applied to drain terminals or source terminals of the FET in each switching circuit section, and a voltage according to an electric power value of the high frequency signal supplied to each of switching circuit sections is supplied as the gate control voltage and the drain control voltage.

Various embodiments of a biological interface system and related methods are disclosed. The biological interface system may comprise a sensor comprising a plurality of electrodes for detecting multicellular signals emanating from one or more living cells of a patient, a processing unit configured to receive the multicellular signals from the sensor and process the multicellular signals to produce a processed signal, and a signal gate configured to receive the processed signal from the processing unit and an alternative signal generated by the system, the signal gate being configured to transmit a control signal to a controlled device based on either the processed signal or the alternative signal. A monitoring unit may receive system data and process the system data to produce a system status signal. The system status signal may be used to determine which of the processed signal and the alternative signal is to be used as the control signal.

A semiconductor device includes a plurality of nonvolatile memory cells (1). Each of the nonvolatile memory cells comprises a MOS type first transistor section (3) used for information storage, and a MOS type second transistor section (4) which selects the first transistor section. The second transistor section has a bit line electrode (16) connected to a bit line, and a control gate electrode (18) connected to a control gate control line. The first transistor section has a source line electrode (10) connected to a source line, a memory gate electrode (14) connected to a memory gate control line, and a charge storage region (11) disposed directly below the memory gate electrode. A gate withstand voltage of the second transistor section is lower than that of the first transistor section. Assuming that the thickness of a gate insulating film of the second transistor section is defined as tc and the thickness of a gate insulating film of the first transistor section is defined as tm, they have a relationship of tc<tm.

An apparatus for converting direct voltage into alternating voltage and conversely comprises a VSC-converter (8) having a direct voltage intermediate link (9) and at least one phase leg (12, 13). Each current valve (14-17) of the phase legs has at least one semiconductor device of turn-off type and a rectifying member connected in anti-parallel therewith. A transformer (19) has two opposite ends of a first winding (20) thereof connected to an output (21, 22) each of the VSC-converter and a second winding (23) connected to a direct converter having at least one phase leg. Each of the current valves of the direct converter being able to conduct current and block voltage in both directions and to turn on by gate control. A midpoint (27) of the phase leg of the direct converter is provided with a phase output for forming a terminal for the alternating phase voltage between this output and a further phase output (28).

The invention discloses a triple-authentication gate control system and a control method. The triple-authentication gate control system comprises an image collection module, a card reader module, a local controller module, a gate control output module, a mobile phone, a system management module and a database module. Through verifying whether an identity card is legal or not, the local controller module is triggered to be connected to Internet through 3G / GPRS, the system management module receives the login request of the local controller to generate random two-dimensional codes and time stamps which are sent into the mobile phone and the local controller module through multimedia messages and network, then, the local controller obtains two-dimensional codes through the card reader module, and compares the obtained two-dimensional codes to the two-dimensional codes downloaded from the system management module through 3G / GPRS network, next, the time stamp comparison is carried out, finally, whether all the authentication is legal or not is judged, and the gate is opened and images are collected if all the authentication is legal. The invention ensures high safety of the gate control system, has the advantages of short authentication time, high authentication accurate rate and low cost, and is favorable for large-range application and popularization.

The invention discloses an integrated gating active quenching / restoring circuit. The integrated gating active quenching / restoring circuit comprises a quick detection circuit, a pulse generation circuit, a pixel control circuit, a quenching circuit and a restoring circuit, wherein the quick detection circuit is used for processing a detected anode current signal of an SPAD (Single Photon Avalanche Diode) into a pulse signal, the pulse signal can be output through the pulse generation circuit, the pixel control circuit is controlled by an output signal and a gating signal of the pulse generation circuit, the restoring circuit and the quenching circuit are respectively controlled by outputs of the pixel generation circuit, outputs of the restoring circuit and the quenching circuit can be fed back to an anode of the SPAD, and the restoring and the quenching of the SPAD can be controlled. According to the integrated gating active quenching / restoring circuit disclosed by the invention, by adopting a gating control method, the dark counting rate of the SPAD can be effectively reduced, the quenching time can be controlled by the pulse generation circuit, and the integrated gating active quenching / restoring circuit has the advantages of compact area and low power consumption.

A converter, and in particular a current source converter, including a bridge having an AC terminal for each of one or more AC lines, and first and second DC terminals. A converter arm is connected between each respective AC terminal and the first DC terminal, and between each respective AC terminal and the second DC terminal. Each converter arm includes a first power semiconductor switching device capable of being turned ‘on’ and ‘off’ by gate control and having a recovery time. The converter is adapted to be operated in one or more inverting modes.

The present invention discloses a gate control device which controls the passage (e.g., entry, exit, etc.) through a passageway of both authorized persons and unauthorized companions of authorized persons into a protected room. The device may be configured such that the unauthorized companions may be permitted or denied passage if the unauthorized companions are with an authorized person. For example, the device may be configured to allow an entire group of persons to enter a room if only one authorized person is present. In another example, the device may deny passage to the entire group if it contains even one unauthorized person.

A hybrid packaged gate controlled semiconductor switching device (HPSD) has an insulated-gate transistor (IGT) made of a first semiconductor die and a rectifying-gate transistor (RGT) made of a second semiconductor die. The RGT gate and source are electrically connected to the IGT source and drain respectively. The HPSD includes a package base with package terminals for interconnecting the HPSD to external environment. The IGT is die bonded atop the package base. The second semiconductor die is formed upon a composite semiconductor epi layer overlaying an electrically insulating substrate (EIS) thus creating a RGT die. The RGT die is stacked and bonded atop the IGT die via the EIS. The IGT, RGT die and package terminals are interconnected with bonding wires. Thus, the HPSD is a stacked package of IGT die and RGT die with reduced package footprint while allowing flexible placements of device terminal electrodes on the IGT.

A display apparatus includes a gate driver which sequentially outputs a gate signal at a high state in response to a gate control signal and a data driver which converts image data into a data signal in response to a data control signal. The display apparatus further includes a display panel which includes a plurality of gate lines which sequentially receive the gate signal, a plurality of data lines which receive the data signal and a plurality of pixels connected to the gate and data lines and which receive the data signal in response to the gate signal to display an image. The polarity of the data signal is inverted after the gate signal transitions to a low state.

A light-load power transistor and a heavy-load power transistor are connected in parallel between an input voltage and an output voltage. The light-load power transistor has a smaller current driving capability, i.e. a smaller dimension of a current path. During a light-load mode, only is the light-load power transistor activated to reduce the current consumption caused by an error amplifier, thereby enhancing the efficiency. When a detection current signal is higher than a threshold current signal, the heavy-load power transistor is additionally activated through a gate control circuit by a mode selection circuit, thereby achieving a sufficient current driving capability.

Circuit and method for controlling a synchronous rectifier. A circuit for monitoring the drain to source voltage of an SR transistor in a secondary side circuit of a voltage converter is disclosed, having a circuit for generating a gate control circuit for the SR MOSFET; the circuit preventing subsequent gate control signals until a primary turn on detection signal is received. In another embodiment a circuit for generating the primary turn on detection signal is provided. A method for controlling an SR transistor is disclosed comprising monitoring the drain to source voltage of the SR MOSFET, generating a gate control output, and preventing subsequent gate control output signals until a primary turn on detection signal is received. In another method embodiment a method for generating the primary turn on detection signal is disclosed. An SR embodiment incorporating the control circuit embodiments is disclosed.

A transistor being one of an IGBT and a MOSFET and arranged near a gate control circuit applies a gate control signal from the gate control circuit to the gate of a transistor arranged far from the gate control circuit. A gate control signal is applied via a resistive element to the transistor arranged near the gate control circuit.

Among first IGBTs and first MOSFETs, a transistor arranged near a first gate control circuit gives, through a gate thereof, a gate control signal supplied from the first gate control circuit to a gate of a transistor arranged at a position farther from the first gate control circuit. Among second IGBTs and second MOSFETs, a transistor arranged near a second gate control circuit gives, through a gate thereof, a gate control signal supplied from the second gate control circuit to a gate of a transistor arranged at a position farther from the second gate control circuit.

The invention provides an electric vehicle inverter protective device. A gate control signal is output to the gate of an IGBT through a driving circuit and a buffer circuit. An auxiliary power supply converts the power of an inverter controller into voltage controlling the on-off state of the IGBT and supplying power to the driving circuit. A bus voltage detection circuit determines whether bus voltage is higher than a bus high-voltage threshold value and outputs a voltage comparison signal to the inverter controller. An emergency circuit is powered by the bus voltage and outputs a gate signal to control the conduction of IGBTs at a three-phase lower half-bridge in order that the inverter is in an active short-circuit mode. Further, the inverter controller may output a reset signal to reset the driving circuit. The invention further provides an electric vehicle inverter protective method. The electric vehicle inverter protective device provides an active safe mode for the trailed condition of an electric vehicle, may detect the operating parameter of the inverter in real time, may isolate the high-voltage power from the low-voltage power of the inverter, and performs active protection on an electric vehicle inverter.