2524 results about "Die bonding" patented technology

Disclosed herein is an LED package for a backlight unit. The LED package includes a plurality of LEDs, a die bonding part, a wire bonding part and a body. The die bonding part, on which the plurality of LEDs is arranged, allows the first electrodes of the LEDs to be electrically connected to an external circuit. The wire bonding part is spaced apart from the die bonding part by a predetermined distance to be insulated from the die bonding part and allows the second electrodes of the LEDs to be electrically connected to the external circuit so that the LEDs are operated. The body has a molding cup which is used to fill a space above the LEDs with transparent resin and a base on which the die bonding part and the wire bonding part are arranged.

An LED comprises: a chip substrate formed with a die bond pattern and electrode terminals; an LED chip mounted on the chip substrate; a reflective frame arranged on the chip substrate to enclose a circumference of the LED chip and having an opening at a part of its side walls and on an upper surface; reflecting surfaces formed on inner circumferential surfaces of the side walls of the reflective frame; a light transmissive resin body formed in the reflective frame and using the opening in the side wall as a light emission face; and a reflecting film covering an upper surface of the light transmissive resin body exposed on an upper surface side of the reflective frame; wherein light produced by the LED chip is reflected by a reflecting surface of the refractive frame and by the reflecting film and is emitted outward from the light emission face. The side emission type LED of this construction can be reduced in thickness for surface mounting and can illuminate a small-width side surface of a liquid crystal panel with high efficiency.

Expanded bond pads are formed over a passivation layer on a semiconductor wafer before the wafer is diced into individual circuit chips. After dicing, the individual chips are packaged by fixing each chip within a package core and building up one or more metallization layers on the resulting assembly. In at least one embodiment, a high melting temperature (lead free) alternative bump metallurgy (ABM) form of controlled collapse chip connect (C4) processing is used to form relatively wide conducting platforms over the bond pads on the wafer.

An FPGA is readily connectable to a high-speed fiber optic link by snap fitting an external fiber optic cable into an accommodating duplex fiber optic connector of a low-profile packaged FPGA integrated circuit. The low-profile packaged FPGA integrated circuit includes a die-bonded assembly disposed within a co-fired multilayer ceramic integrated circuit package. The die-bonded assembly includes the optoelectronic die, the bottom surface of which is die-bonded and electrically interconnected by micropads to the upper surface of the core of an FPGA integrated circuit die. A first optical fiber communicates light from the connector, through the package, and to a photodetector on the optoelectronic die. A second optical fiber communicates light from a laser diode on the optoelectronic die, through the package, and to the connector. In some embodiments, a micromirror device is disposed within the package to redirect light between the optoelectronic die and the optical fibers.

A semiconductor device includes an insulating substrate 2 having an obverse surface formed with a die pad 3, a rectangular semiconductor chip 7 such as an LED chip bonded to the die pad with a die bonding material 10, and a molded portion 9 made of a synthetic resin for packaging the semiconductor chip. The die pad 3 may be rectangular with dimensions close to those of the semiconductor chip or circular with a diameter close to the diagonal dimension of the semiconductor chip, whereby the positioning and orienting of the semiconductor chip can be accurately performed in bonding the semiconductor chip.

A vertical stack type multi-chip package is provided having improved reliability by increasing the grounding performance and preventing the decrease in reliability of the multi-chip package from moisture penetration into a lower semiconductor chip. The vertical stack type multi-chip package comprises an organic substrate having a printed circuit pattern on which a semiconductor chip is mounted. A first semiconductor chip is mounted on a die bonding region of the organic substrate and is electrically connected to the organic substrate through a first wire. A metal stiffener is formed on the first semiconductor chip and connected to the organic substrate by a first ground unit around the first semiconductor chip. An encapsulant is used to seal the first semiconductor chip below the metal stiffener. A second semiconductor chip, which is larger in size than that the first semiconductor chip, is mounted on the metal stiffener and connected by a second ground unit. The second semiconductor chip is connected to the organic substrate by a second wire. A mold resin seals the second semiconductor chip and a solder ball is bonded to a solder ball pad below the organic substrate.

A dicing and die bonding pressure-sensitive adhesive sheet having a pressure-sensitive adhesive layer that exhibits excellent embedding properties in die bonding to thereby prevent formation of voids between die pads and the pressure-sensitive adhesive layer even when chips are mounted on die pads exhibiting great differences in height. The dicing and die bonding pressure-sensitive adhesive sheet comprises a base material and a pressure-sensitive adhesive layer disposed thereon, the pressure-sensitive adhesive layer having a ratio (M₁₀₀/M₇₀) of a modulus of elasticity at 100° C. (M₁₀₀) to a modulus of elasticity at 70° C. (M₇₀) of 0.5 or less.

An embodiment of the present invention relates to an expansion method comprising: a step (I) of preparing a laminate having a semiconductor wafer in which modified sections have been formed along intended cutting lines, a die bonding film and a dicing tape, a step (IIA) of expanding the dicing tape with the laminate in a cooled state, a step (IIB) of loosening the expanded dicing tape, and a step (IIC) of expanding the dicing tape with the laminate in a cooled state, dividing the semiconductor wafer and the die bonding film into chips along the intended cutting lines, and widening the spaces between the chips.

The LED comprises: a base having high thermal conductivity and having a mounting surface for die bonding; a printed circuit board mounted on the base and having a hole to expose a part of the mounting surface of the base and having a protruding portion projecting horizontally outward on the outer periphery of the base; an LED element mounted on the mounting surface of the base exposed in the hole of the printed circuit board; and a resin material sealing the LED element from above; wherein through-holes electrically connected to the LED element are formed at the outer periphery of the protruding portion and an external connection electrode is provided to the upper and lower surfaces of the through-holes. This LED enhances the heat dissipating effect to enable generation of high-luminance light and can also be mounted on either the upper or lower surface of a motherboard.

A method for creating electrical interconnects between a semiconductor die and package. In the preferred embodiment, an insulating material is applied over the die and extends to the substrate contact pads, leaving a portion of each contact pad exposed. Holes are then trimmed through the insulating material, exposing at least a portion of each die bond pad. A conductive material is then applied over the die, flowing into the holes, contacting the die bond pads, and extending out to contact at least a portion of each substrate contact pad. In another preferred embodiment, an electrically conductive bump may be formed on each die bond pad, protruding through said non-conductive material and at least partially through said conductive material. The conductive layer is then laser trimmed, forming conductive patches that serve as electrical interconnects between the die and package substrate.

A thermal mechanical process for bonding a flip chip die to a substrate. The flip chip die includes a plurality of copper pillar bumps, each copper pillar bump of the plurality of copper pillar bumps having a copper portion attached to the die and a bonding cap attached to the copper portion. The process includes positioning the die on the substrate such that the bonding cap of each copper pillar bump of the plurality of copper pillar bumps contacts a corresponding respective one of a plurality of bonding pads on the substrate, and thermosonically bonding the die to the substrate.

A dicing/die-bonding film including a pressure-sensitive adhesive layer (2) on a supporting base material (1) and a die-bonding adhesive layer (3) on the pressure-sensitive adhesive layer (2), wherein a releasability in an interface between the pressure-sensitive adhesive layer (2) and the die-bonding adhesive layer (3) is different between an interface (A) corresponding to a work-attaching region (3a) in the die-bonding adhesive layer (3) and an interface (B) corresponding to a part or a whole of the other region (3b), and the releasability of the interface (A) is higher than the releasability of the interface (B). The dicing/die-bonding film is excellent in balance between retention in dicing a work and releasability in releasing its diced chipped work together with the die-bonding adhesive layer.

A lead frame (2a) has a die bonding pad portion (3) and an inner lead portion (4). A power element (1) is mounted on the die bonding pad portion (3) of the lead frame (2a) and is bonded to the die bonding pad portion (3) with solder (9). The power element (1) has electrodes connected through an aluminum wire (8) to the inner lead portion (4) of another lead frame (2b). A metal block (5) has a surface formed with a protrusion bonded to the lead frame (2a) in opposed relation to the power element (1). A resin package (6) has an insulation layer (7) formed on the opposite surface of the metal block (5) from the lead frame (2a), and seals the power element (1), the lead frames (2a, 2b) and the metal block (5). An external heat dissipator (11) is mounted on a surface of the insulation layer (7) opposite from the metal block (5). A semiconductor device and a method of manufacturing the same improve a heat dissipation characteristic and maintain a dielectric breakdown voltage.