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5869 results about "Melting temperature" patented technology

Surgical device with tack-free gel and method of manufacture

A process of making a tack-free gel is disclosed comprising the steps of providing a mold defining a mold cavity, the mold cavity comprising a plastic material; pouring or injecting a molten gel having a high molding temperature into the mold cavity; and forming the tack-free gel as a thin layer of plastic of the mold cavity is melted over the gel. The forming step further comprises cooling the gel from the molten state to a solidified state. The melting temperature of the plastic material is lower than the molding temperature of the gel; and the higher the temperature differential, the greater the melting of the plastic material and the thicker the layer of the plastic material on the surface of the gel. The mold may be formed of low-density polyethylene (LDPE). With the process of the invention, the heat of the molten gel at its molding temperature is transferred to the surface of the LDPE mold so as to melt a thin layer of the LDPE. The mold may comprise a mold base having a plurality of mold holes forming a plurality of mold cavities, each of the mold holes comprising an axial pin to mold an axial hole through a center of the gel, an LDPE cylinder providing a predetermined inside diameter for the mold, and an LDPE disc mounted on the axial pin and disposed at the bottom of each mold cavity in the mold base. The process may further comprise the step of dabbing the gel in a low-friction powder such as polytetrafluoroethylene (PTFE) and a lubricant. The mold may further comprise a mold top disposed axially of the mold base and comprises a plurality of holes forming a plurality of cavities, each of the mold top holes is adapted to receive the LDPE cylinder, and a second LDPE disc disposed at the top of each mold cavity of the mold top.
Owner:APPL MEDICAL RESOURCES CORP

Metal attachment method and structure for attaching substrates at low temperatures

A high density integrated circuit structure and method of making the same includes providing a first silicon substrate structure having semiconductor device formations in accordance with a first circuit implementation and metal interlevel lines disposed on a top surface thereof and a second silicon substrate structure having a second circuit implementation and metal interlevel lines disposed on a top surface thereof. The first substrate structure includes a planarized low-K dielectric disposed between the metal interlevel lines and a protective coating separating the metal interlevel lines from is the low-K dielectric, the metal interlevel lines of the first silicon substrate structure have a melting temperature on the order of less than 500 DEG C. and the low-K dielectric having a dielectric K-value in the range of 2.0-3.8. The second substrate structure also includes a planarized low-K dielectric disposed between the metal interlevel lines and a protective coating separating the metal interlevel lines from the low-K dielectric, the metal interlevel lines having a melting temperature on the order of less than 500 DEG C. and the low-K dielectric having a dielectric K-value in the range of 2.0-3.8. Lastly, the first substrate structure is low temperature bonded to the second substrate structure at respective metal interlevel lines of the first and second substrate structures.
Owner:ADVANCED MICRO DEVICES INC

Z-axis compressible polymer with fine metal matrix suspension

A compressible interposer comprising an interposer sheet having a plurality of apertures filled with a dielectric material having a substantially uniform suspension of conductive particles therein forming a plurality of conductive sites. Preferably, the number of conductive sites on the interposer are greater in number than the number of contact pads on the electronic components such that precise alignment of the interposer between the electronic components is not required. The apertures of the interposer sheet confine the conductive particles within the dielectric material such that during compression of the interposer between the electronic components, z-axis conductive pathways are formed without shorting in the x and y directions. Preferably, the interposer sheet comprises polyimide. Preferably, the dielectric material comprises polyimide-siloxane. Preferably, the conductive particles have a diameter of about 2 to about 20 mum and comprise of a material selected from the group consisting of copper, gold, silver, nickel, palladium, platinum, and alloys thereof. The particles may also be coated with an additional conductive material such as solder having a lower melting temperature. Most preferably, the conductive particles comprise solder coated copper particles. The conductive particles are present in an amount of about 30 to about 90 wt. % of the total weight of the conductive particles and the dielectric material.
Owner:IBM CORP

Method of multiple pulse laser annealing to activate ultra-shallow junctions

A method for forming a highly activated ultra shallow ion implanted semiconductive elements for use in sub-tenth micron MOSFET technology is described. A key feature of the method is the ability to activate the implanted impurity to a highly active state without permitting the dopant to diffuse further to deepen the junction. A selected single crystalline silicon active region is first amorphized by implanting a heavy ion such as silicon or germanium. A semiconductive impurity for example boron is then implanted and activated by pulsed laser annealing whereby the pulse fluence, frequency, and duration are chosen to maintain the amorphized region just below it's melting temperature. It is found that just below the melting temperature there is sufficient local ion mobility to secure the dopant into active positions within the silicon matrix to achieve a high degree of activation with essentially no change in concentration profile. The selection of the proper laser annealing parameters is optimized by observation of the reduction of sheet resistance and concentration profile as measured on a test site. Application of the method is applied to forming a MOS FET and a CMOS device. The additional processing steps required by the invention are applied simultaneously to both n-channel and p-channel devices of the CMOS device pair.
Owner:CHARTERED SEMICONDUCTOR MANUFACTURING
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