115093 results about "Impurity" patented technology

In a thin film transistor (1), a gate insulating layer (4) is formed on a gate electrode (3) formed on an insulating substrate (2). Formed on the gate insulating layer (4) is a semiconductor layer (5). Formed on the semiconductor layer (5) are a source electrode (6) and a drain electrode (7). A protective layer (8) covers them, so that the semiconductor layer (5) is blocked from an atmosphere. The semiconductor layer (5) (active layer) is made of, e.g., a semiconductor containing polycrystalline ZnO to which, e.g., a group V element is added. The protective layer (8) thus formed causes decrease of a surface level of the semiconductor layer (5). This eliminates a depletion layer spreading therewithin. Accordingly, the ZnO becomes an n-type semiconductor indicating an intrinsic resistance, with the result that too many free electrons are generated. However, the added element works on the ZnO as an accepter impurity, so that the free electrons are reduced. This decreases a gate voltage required for removal of the free electrons, so that the threshold voltage of the thin film transistor (1) becomes on the order of 0V. This allows practical use of a semiconductor device which has an active layer made of zinc oxide and which includes an protective layer for blocking the active layer from an atmosphere.

To provide a semiconductor device in which a defect or fault is not generated and a manufacturing method thereof even if a ZnO semiconductor film is used and a ZnO film to which an n-type or p-type impurity is added is used for a source electrode and a drain electrode. The semiconductor device includes a gate insulating film formed by using a silicon oxide film or a silicon oxynitride film over a gate electrode, an Al film or an Al alloy film over the gate insulating film, a ZnO film to which an n-type or p-type impurity is added over the Al film or the Al alloy film, and a ZnO semiconductor film over the ZnO film to which an n-type or p-type impurity is added and the gate insulating film.

A thin film transistor (TFT), a method of manufacturing the TFT, and a flat panel display comprising the TFT are provided. The TFT includes a gate, a gate insulating layer that contacts the gate, a channel layer that contacts the gate insulating layer and faces the gate with the gate insulating layer therebetween, a source that contacts an end of the channel layer; and a drain that contacts an other end of the channel layer, wherein the channel layer is an amorphous oxide semiconductor layer, and each of the source and the drain is a conductive oxide layer comprising an oxide semiconductor layer having a conductive impurity in the oxide semiconductor layer. A low resistance metal layer can further be included on the source and drain. A driving circuit of a unit pixel of a flat panel display includes the TFT.

Disclosed is a thin film transistor including a P-type semiconductor layer, and an organic light-emitting display device having the thin film transistor. The present invention provides a thin film transistor including a substrate, a semiconductor layer, and a gate electrode and a source/drain electrode formed on the substrate, wherein the semiconductor layer is composed of P-type ZnO:N layers through a reaction of a mono-nitrogen gas with a zinc precursor, and the ZnO:N layer includes an un-reacted impurity element at a content of 3 at % or less.

Thin films are formed by formed by atomic layer deposition, whereby the composition of the film can be varied from monolayer to monolayer during cycles including alternating pulses of self-limiting chemistries. In the illustrated embodiments, varying amounts of impurity sources are introduced during the cyclical process. A graded gate dielectric is thereby provided, even for extremely thin layers. The gate dielectric as thin as 2 nm can be varied from pure silicon oxide to oxynitride to silicon nitride. Similarly, the gate dielectric can be varied from aluminum oxide to mixtures of aluminum oxide and a higher dielectric material (e.g., ZrO₂) to pure high k material and back to aluminum oxide. In another embodiment, metal nitride (e.g., WN) is first formed as a barrier for lining dual damascene trenches and vias. During the alternating deposition process, copper can be introduced, e.g., in separate pulses, and the copper source pulses can gradually increase in frequency, forming a transition region, until pure copper is formed at the upper surface. Advantageously, graded compositions in these and a variety of other contexts help to avoid such problems as etch rate control, electromigration and non-ohmic electrical contact that can occur at sharp material interfaces. In some embodiments additional seed layers or additional transition layers are provided.

In a method of forming a layer using an atomic layer deposition process, after a substrate is loaded into a chamber, a first reactant is provided onto the substrate. The first reactant is partially chemisorbed on the substrate. A second reactant is introduced into the chamber to form a preliminary layer on the substrate by chemically reacting the second reactant with the chemisorbed first reactant. Impurities in the preliminary layer and unreacted reactants are simultaneously removed using a plasma for removing impurities to thereby form the layer on the substrate. The impurities in the layer may be effectively removed so that the layer may have reduced leakage current.

A high k dielectric film and methods for forming the same are disclosed. The high k material includes two peaks of impurity concentration, particularly nitrogen, such as at a lower interface and upper interface, making the layer particularly suitable for transistor gate dielectric applications. The methods of formation include low temperature processes, particularly CVD using a remote plasma generator and atomic layer deposition using selective incorporation of nitrogen in the cyclic process. Advantageously, nitrogen levels are tailored during the deposition process and temperatures are low enough to avoid interdiffusion and allow maintenance of the desired impurity profile.

A chamber material made of Al alloy excellent in thermal cracking resistance and chemical and/or physical corrosion resistance and capable of reducing contamination excellently and further having excellent and wide applicable brazing property in a high temperature corrosive circumstance, in which the substrate aluminum material for the chamber material made of Al alloy having an anodized film comprises 0.1 to 2.0% Si, 0.1 to 3.5% Mg, 0.02 to 4.0% Cu on the mass % basis and the balance of Al and impurity element with Cr in the impurity elements being less than 0.04%. Preferably, Fe is 0.1% or less and Mn is 0.04% or less in the impurity element and, further, the total sum of impurity elements other than Cr and Mn being restricted to 0.1$ or less. This invention can be utilized suitably to various materials used in high temperature corrosive circumstance, particularly, in high temperature corrosive gas or plasma atmosphere.

Provided are a semiconductor layer manufacturing method and a semiconductor manufacturing apparatus capable of forming a high quality semiconductor layer even by a single chamber system, with a shortened process time required for reducing a concentration of impurities that exist in a reaction chamber before forming the semiconductor layer. A semiconductor device manufactured using such a method and apparatus is also provided. The present invention relates to a semiconductor layer manufacturing method of forming a semiconductor layer inside a reaction chamber (101) capable of being hermetically sealed, including an impurities removing step of removing impurities inside the reaction chamber (101) using a replacement gas, and a semiconductor layer forming step of forming the semiconductor layer, the impurities removing step being a step in which a cycle composed of a replacement gas introducing step of introducing the replacement gas into the reaction chamber (101) and an exhausting step of exhausting the replacement gas is repeated a plurality of times, the impurities removing step being performed at least before the semiconductor layer forming step.

There is disclosed a silicon focus ring consisting of silicon single crystal used as a silicon focus ring in a plasma apparatus, wherein concentration of interstitial oxygen contained in the silicon focus ring is not less than 5x10<17 >atoms/cm<3 >and not more than 1.5x10<18 >atoms/cm<3>, and a producing method for a silicon focus ring used for a plasma apparatus, wherein a single crystal silicon wherein concentration of interstitial oxygen contained in the silicon focus ring is not less than 5x10<17 >atoms/cm<3 >and not more than 1.5x10<18 >atoms/cm<3 >is grown by a Czochralski method, the single crystal silicon is processed in a circle, and a silicon focus ring is produced. There can be provided a silicon focus ring, which can prevent disadvantage due to impurities such as heavy metal.

An impurity-doped silicon nitride or oxynitride film is formed on a target substrate by CVD, in a process field to be selectively supplied with a first process gas containing a silane family gas, a second process gas containing a nitriding or oxynitriding gas, and a third process gas containing a doping gas. This method alternately includes first to fourth steps. The first step performs supply of the first and third process gases to the field. The second step stops supply of the first to third process gases to the field. The third step performs supply of the second process gas to the field while stopping supply of the first and third process gases to the field, and includes an excitation period of exciting the second process gas by an exciting mechanism. The fourth step stops supply of the first to third process gases to the field.

A method of manufacturing a semiconductor device includes: the first step of forming a gate electrode over a silicon substrate, with a gate insulating film; and the second step of digging down a surface layer of the silicon substrate by etching conducted with the gate electrode as a mask. The method of manufacturing the semiconductor device further includes the third step of epitaxially growing, on the surface of the dug-down portion of the silicon substrate, a mixed crystal layer including silicon and atoms different in lattice constant from silicon so that the mixed crystal layer contains an impurity with such a concentration gradient that the impurity concentration increases along the direction from the silicon substrate side toward the surface of the mixed crystal layer.

A method of fabricating a landing plug in a semiconductor memory device, which in one embodiment includes forming a landing plug contact hole on a semiconductor substrate having an impurity region to expose the impurity region; forming a landing plug by filling the landing plug contact hole with a polysilicon layer, wherein the landing plug is divided into a first region, a second region, a third region, and a fourth region from a lower portion of the landing plug, and the first region is doped with a first doping concentration that is relatively lowest, the second region is doped with a second doping concentration that is higher than the first doping concentration, the third region is doped with a third doping concentration that is higher than the second doping concentration and the fourth region is not doped; and annealing the resulting product formed with the landing plug.

A continuous renal replacement therapy device adapted to be worn on a portion of the body of a patient, including: a plurality of contoured dialyzers, which are connected in series and utilize dialysate to remove impurities from the blood of the patient; and a plurality of contoured sorbent device, which are connected in series and are for regenerating the spent dialysate.

Disclosed is a semiconductor light-emitting element, comprising an n-type-cladding layer; a light guide layer positioned on the n-type cladding layer; a multiple quantum well structure active layer positioned on the light guide layer; a p-type carrier overflow prevention layer positioned on the active layer and having an impurity concentration of 5×10¹⁸ cm⁻³ to not more than 3×10¹⁹ cm⁻³; a p-type light guide layer positioned on the p-type carrier overflow prevention layer and-having an impurity concentration of 1×10¹⁸ cm⁻³ or more and less-than that of the p-type carrier overflow prevention layer; and a p-type cladding layer positioned on the p-type light guide layer and having a band gap narrower than the p-type carrier overflow prevention layer, and a method of manufacturing the same.

The present invention provides an apparatus for manufacturing a semiconductor thin film that is capable of manufacturing an even thin film with substantially no adhesion of impurities, and is capable of improving in-plane evenness of a grown thin film. The invention is an apparatus for manufacturing a semiconductor thin film includes a reaction tube 12, a susceptor 20 disposed in the reaction tube 12, and a negative pressure generator, the negative pressure generator applying a negative pressure to a substrate 22A placed on the susceptor 20 to hold the substrate, and the substrate 22A is placed so that an angle of a normal line to a crystal growth face of the substrate 22A to a vertical downward direction is less than 180°.