4134 results about "Second source" patented technology

Embodiments of the invention include a method for fabricating a semiconductor device and the resulting structure. A plurality of nanosheet recesses are formed within a substrate. A placeholder structure is formed on a bottom surface within each nanosheet recess. A first source / drain region is formed within a first nanosheet recess. A second source / drain region is formed within the second nanosheet recess. The semiconductor structure is flipped. The substrate is removed respective to a sidewall spacer of the placeholder structure and a first etch stop layer of the placeholder structure. Backside interlayer dielectric is formed. A backside contact trench to the second source drain region is formed by removing a portion of the backside interlayer dielectric over the second source / drain region and removing exposed portions of the first etch stop layer, the sidewall spacer, and a silicon buffer layer of the placeholder structure. A backside contact is formed within the trench.

The invention provides a preparation method of a stacked transistor, the stacked transistor and a semiconductor device. The method comprises the steps of performing primary etching on a semiconductor substrate to form a stack structure, wherein the stack structure comprises an active structure and a first sacrificial layer; forming a pseudo gate structure covering the stacked structure in the gate region; etching the stack structure which is not covered by the pseudo gate structure to form a first deep groove; epitaxially growing a first source drain structure in the first deep groove based on the first active structure in the gate region; removing the pseudo gate structure and the first sacrificial layer to expose the active structure in the gate region; depositing a gate dielectric material on the exposed active structure to form a gate dielectric layer; depositing a metal material on the first gate dielectric layer to form a first gate electrode layer; reversing and removing the semiconductor substrate; epitaxially growing a second source drain structure in the first deep groove based on a second active structure in the gate region; and depositing a metal material on the second gate dielectric layer to form a second gate electrode layer.

A method includes forming a fin structure including first and second sacrificial layers and first and second channel layers over a substrate; forming a dummy gate structure across the fin structure; forming gate spacers on opposite sides of the dummy gate structure; forming first source / drain epitaxial layers on opposite sides of the first channel layer; forming second source / drain epitaxial layers on opposite sides of the second channel layer; removing the dummy gate structure and the first and second sacrificial layers to form a gate trench defined by the gate spacers; forming an oxynitride layer in the gate trench to surround the first channel layer; forming a dipole layer to surround the oxynitride layer; performing an anneal process to drive dipole dopants into the oxynitride layer; and depositing a high-k gate dielectric layer and a work function metal layer in the gate trench to form a gate structure.

A semiconductor structure including a dielectric bar arranged between and physically separating a first source drain region from a second source drain region, a first silicide liner directly beneath the first source drain region, and second silicide liner directly beneath the second source drain region, where the first silicide liner is a different material than the second silicide liner.

Integrated circuit devices and methods of forming the same are provided. The integrated circuit devices may include a transistor including first and second source / drain regions spaced apart from each other in a horizontal direction, a backside power distribution network structure (BSPDNS), a substrate between the first and second source / drain regions and the BSPDNS, a backside contact that is in the substrate and is overlapped by the first source / drain region, a placeholder that is in the substrate and is overlapped by the second source / drain region, and a cavity in the substrate between the backside contact and the placeholder.

A semiconductor structure includes a stacked device structure having a first field-effect transistor having a first source / drain region, and a second field-effect transistor vertically stacked above the first field-effect transistor, the second field-effect transistor having a second source / drain region and a gate region having first sidewall spacers. The stacked device structure further includes a frontside source / drain contact disposed on a first portion of a sidewall and a top surface of the second source / drain region, a first metal via connected to the frontside source / drain contact and to a first backside power line, and second sidewall spacers disposed on a first portion of the first metal via. The first sidewall spacers comprise a first dielectric material and the second sidewall spacers comprise a second dielectric material different than the first dielectric material.

The present application relates to the technical field of display, and discloses a display panel and a manufacturing method therefor, and a display device. The display panel comprises: a base substrate; a backboard wiring layer which comprises a first source-drain electrode layer, a first planarization layer, a second source-drain electrode layer, a second planarization layer, and a third source-drain electrode layer which are stacked; an encapsulation layer; a touch electrode layer; and a touch wire which is electrically connected to a touch electrode, wherein the touch wire is arranged in a non-display area and extends to a binding area through a bending area, the touch wire comprises a first wiring portion and a second wiring portion which are electrically connected, the first wiring portion crosses the bending area, the second wiring portion does not overlap with the bending area, the first wiring portion is located on the third source-drain electrode layer, and the second wiring portion is located on the touch electrode layer. The second source-drain electrode layer is replaced with the third source-drain electrode layer to transmit a touch signal in the bending area, so that the punching of the middle film layer of the third source-drain electrode layer and the second source-drain electrode layer is omitted, thereby reducing the thickness of the film layer needing to be punched.

An integrated circuit semiconductor device includes a base layer including a first surface and a second surface, a gate structure on the first surface of the base layer, a first source and drain region on a side of the gate structure, a second source and drain region on another side of the gate structure, a first placeholder in the base layer in a lower portion of the first source and drain region and electrically connected to the first source and drain region, a second placeholder in the base layer in a lower portion of the second source and drain region, and a metal power rail on the first placeholder and the second placeholder on the second surface of the base layer and electrically connected to the first placeholder.

The invention provides a preparation method of an inverted stacked transistor, a transistor, a device and equipment, and the method comprises the steps: forming an active structure on a substrate, the active structure is provided with a first part and a second part, and the first part is closer to the substrate than the second part; the active structure in the source-drain region is etched, the first source-drain region is filled with an insulating material to form a filling structure, the source-drain region comprises a first source-drain region and a second source-drain region, the first source-drain region corresponds to the first part, and the second source-drain region corresponds to the second part; forming a first source-drain structure and first source-drain metal of the first transistor based on the second source-drain region; reversing the first transistor and removing the substrate; selectively etching the filling structure through the material so as to expose the first source-drain region; and forming a second source-drain structure and second source-drain metal of the second transistor based on the first source-drain region. Complete self-alignment of the front and back transistors can be realized.

A semiconductor device includes a substrate that includes a first surface and a second surface, a first source / drain pattern disposed on the first surface of the substrate, a second source / drain pattern disposed on the first surface of the, a first source / drain contact disposed on the first source / drain pattern and connected to the first source / drain pattern, a second source / drain contact disposed on the second source / drain pattern and connected to the second source / drain pattern, a rear wiring line disposed on the second surface of the substrate, a first contact connection via that connects the rear wiring line with the first source / drain contact, a second contact connection via that connects the rear wiring line with the second source / drain contact and is spaced apart from the first contact connection via, and an air gap structure disposed between the first contact connection via and the second contact connection via.

The invention provides a low-resistance separation trench gate silicon carbide VDMOS and a preparation method thereof, and the method comprises the steps: depositing metal on the lower side surface of a silicon carbide substrate, and forming a drain metal layer; epitaxially growing on the upper side surface of the silicon carbide substrate to form a drift layer; forming a barrier layer, etching, performing ion implantation, and forming a P-type source region, a low-resistance region, a P-type well region and an N-type source region; a barrier layer is formed again, and a first insulating medium layer and a second insulating medium layer are formed through etching and deposition; re-forming a barrier layer, etching and depositing metal, and respectively forming a first gate metal layer and a second gate metal layer; forming a barrier layer again, etching and depositing metal, and forming a first source metal layer; and forming a barrier layer again, etching, depositing metal, forming a second source metal layer, and removing the barrier layer to complete preparation. And the driving loss and the body diode loss of the device are reduced.

The invention provides a left-right shielding trench gate silicon carbide VDMOS and a preparation method thereof, and the method comprises the steps: depositing metal on the lower side surface of a silicon carbide substrate, and forming a drain metal layer; epitaxially growing on the upper side surface of the silicon carbide substrate to form a drift layer; forming a barrier layer above the drift layer, and performing etching and ion implantation to form a P-type source region, a low-resistance region, a P-type well region and an N-type source region; forming a barrier layer again, etching to form a first groove, and depositing to form an insulating dielectric layer; forming a barrier layer again, etching and depositing metal, and forming a first gate metal layer and a second gate metal layer; forming a barrier layer again, etching and depositing metal, and forming a first source metal layer; and a barrier layer is formed again, the barrier layer is etched to form a through hole, the low-resistance region, the P-type source region and the N-type source region are etched, metal is deposited, a second source electrode metal layer is formed, the barrier layer is removed, and preparation is completed.

The invention discloses a common-gate pixel driving circuit which comprises a pre-storage module and a driving module, the pre-storage module comprises a first transistor and a second transistor, a first source drain electrode of the first transistor is coupled to a data signal line, a second source drain electrode of the first transistor is coupled to a pre-storage capacitor and the second transistor, and a second source drain electrode of the second transistor is coupled to a data signal line. The grid electrode is coupled to a control signal line; a gate of the second transistor is coupled to a transfer signal line; the driving module comprises a third transistor and a fourth transistor, a first source drain electrode of the third transistor is coupled to a first global signal, and a second source drain electrode of the third transistor is coupled to a pixel capacitor; a first source drain electrode of the fourth transistor is coupled to a second global signal, and a second source drain electrode of the fourth transistor is coupled to the pixel capacitor; grid electrodes of the third transistor and the fourth transistor are coupled to a second source drain electrode of the second transistor.

A semiconductor device includes a first transistor adjacent to a second transistor and an etch stop layer within an interlayer dialectic (ILD) to separate a lateral contact and a plurality of backside source / drain region-gate cut dielectric layers. The lateral contact connects a via over a first source / drain region of the first transistor to a second source / drain region of the second transistor.

The invention discloses a grid control field sequence circuit and method, and the circuit comprises M rows of sub-circuits, each sub-circuit comprises a compensation unit, and each compensation unit comprises a first transistor, a second transistor, a third transistor, a fourth transistor, and a pre-storage capacitor. A first source-drain electrode of the first transistor is coupled to a positive power line, and a second source-drain electrode of the first transistor is coupled to a second source-drain electrode of the second transistor and a first source-drain electrode of the third transistor; a first source drain electrode of the second transistor is coupled to a grid electrode of the third transistor and one end of the pre-storage capacitor; the second source electrode of the third transistor of the sub-circuit of the Nth row is coupled to the first source drain electrode of a fourth transistor, and the second source drain electrode of the fourth transistor is coupled to a data signal line. The beneficial effects of the invention are that the threshold voltage is written in advance by using the conduction characteristic of the transistor, thereby avoiding the image abnormity phenomenon caused by the drift of the threshold voltage.

Provided is a semiconductor device including a two-dimensional semiconductor material. The semiconductor device includes a first channel including a first two-dimensional material layer, a second channel being apart from the first channel and including a second two-dimensional material layer, a common gate electrode between the first channel and the second channel, a first source electrode and a first drain electrode in contact with the first channel, and a second source electrode and a second drain electrode in contact with the second channel, wherein one of the first channel and the second channel is an N-type channel, and the other is a P-type channel, and the first channel and the second channel are U-shaped.

A method includes forming a first device die and a second device die. The first device die includes a first integrated circuit, and a first bond pad at a first surface of the first device die. The first integrated circuit is electrically connected to the first bond pad. The second device die includes a power switch that includes a first source / drain region, a second source / drain region, a second bond pad electrically connecting to the first source / drain region, and a third bond pad electrically connecting to the second source / drain region. The method further includes bonding the first device die with the second device die to form a package, with the first bond pad bonding to the third bond pad, and bonding the package to a package component.

The invention belongs to the technical field of semiconductors, and provides a storage device, which comprises a substrate; the at least one memory device layer is arranged on the substrate, and the memory device layer at least comprises a memory unit, a write-in word line, a write-in bit line, a read word line and a read bit line; the storage unit comprises a write-in transistor and a read transistor; the write transistor comprises a first gate electrode, a first active layer, a first gate insulating layer and a first source electrode, and the first gate electrode is vertically arranged on the substrate; the reading transistor comprises a second gate electrode, a second active layer, a second gate insulating layer, a second source electrode and a second drain electrode, and the second active layer is vertically arranged on the substrate; the second gate electrode further comprises a horizontal extension part connected with the drain end of the first active layer; in the vertical direction, the write word line is located on the side, away from the horizontal extension part, of the first source electrode. The invention further provides a preparation method of the storage device. The space in the vertical direction and the space in the horizontal direction are effectively utilized, and the storage density can be improved.

Method for forming semiconductor device structure includes forming a sacrificial layer between first and second stacks of layers, the first stack of layers comprises first and second semiconductor layers alternatingly stacked, and the second stack of layers comprises third and fourth semiconductor layers alternatingly stacked, wherein the sacrificial layer comprises a semiconductor metal oxide, forming a sacrificial gate structure over portion of the second stack of layers, removing portions of the first and second stack of layers not covered by the sacrificial gate structure, removing the sacrificial layer to form cavity, filling the cavity with a dielectric to form an isolation layer, and forming first and second source / drain features on opposing sides of sacrificial gate structure, wherein the first source / drain feature is disposed below the second source / drain feature, and the first and second source / drain features are in contact with the isolation layer, first semiconductor layers, and third semiconductor layers.

The invention provides a semi-super junction side isolation planar gate silicon carbide VDMOS and a preparation method thereof, and the method comprises the steps: depositing metal on the lower side surface of a silicon carbide substrate, and forming a drain metal layer; performing epitaxial growth to obtain a first drift region; performing ion implantation to form a first source region; depositing to form a first insulating dielectric layer; epitaxially forming a second drift region, wherein the drift layer comprises a first drift region and a second drift region; performing ion implantation to form a second source region, wherein the P-type source region comprises a first source region and a second source region; depositing to form a second insulating medium layer, wherein the insulating medium region comprises the first insulating medium layer and the second insulating medium layer; forming a barrier layer again, and performing etching and ion implantation to form a column region, a P-type well region, a lug boss and an N-type source region; a barrier layer is formed again, and a gate dielectric layer is formed through etching and deposition; forming a barrier layer again, etching and depositing metal, and forming a gate metal layer and a source metal layer; the voltage endurance capability of the device is effectively improved, and the on-resistance of the device is reduced.

The invention belongs to the technical field of semiconductor devices, and discloses a diamond-based CMOS (complementary metal oxide semiconductor) inverter and a preparation method thereof. The diamond-based CMOS inverter comprises a diamond substrate, a monocrystalline diamond film, a hydrogen terminal region, a mesa isolation region, an n-type oxide semiconductor layer, a first source electrode, a first drain electrode, a second source electrode, a second drain electrode, a first gate dielectric layer, a first gate electrode, a second gate dielectric layer and a second gate electrode. The first drain electrode and the second drain electrode are in metal interconnection; the first gate electrode and the second gate electrode are metal-interconnected. The diamond-based CMOS phase inverter is prepared by combining the p-type hydrogen terminal diamond and the n-type oxide semiconductor, so that the technical problem that an n-type MOS device is difficult to realize by the diamond at present is effectively avoided, respective advantages of the diamond and the n-type oxide semiconductor are fully exerted, and the high-performance diamond-based monolithic integrated CMOS phase inverter is realized.

An SRAM cell includes a first inverter cross-coupled to a second inverter. The first inverter includes a first pull-up transistor and a first pull-down transistor, having coupled drains that define a first storage node. The SRAM cell further includes a first N-type pass-gate transistor having a first drain coupled to a write bit line, a first source coupled to the first storage node, and a first gate coupled to a first write word line. The SRAM cell further includes a first P-type pass-gate transistor having a second drain coupled to the write bit line and a second source coupled to the first storage node. The SRAM cell further includes a P-type transistor having a third drain, coupled to a second gate of the first P-type pass-gate transistor, a third source coupled to a second write word line, and a third gate coupled to an enable signal.

A method and device for a target end UE are disclosed. In one embodiment, the target end UE establishes a PC5 connection with the relay UE for supporting UE-to-UE relay communication between a first source end UE and the target end UE via the relay UE. The target end UE also receives a request message from the relay UE for request of establishing another PC5 connection with the relay UE for supporting UE-to-UE relay communication with a second source end UE via the relay UE. Furthermore, the target end UE, in response to reception of the request message, sends a reject message to the relay UE if the PC5 connection exists.

An electronic component. The electronic component includes a base; a first semiconductor device attached to the base and having: a first Gallium nitride (GaN)-based switch having a first gate, a first source and a first drain, the first gate arranged to control a current flow between the first source and the first drain; a second GaN-based switch having a second source, a second gate and a second drain, the second gate coupled to the first gate, and the second drain coupled to the first drain. In one aspect, the electronic component also includes a second semiconductor device attached to the base and having: a logic circuit coupled to the second source and arranged to detect a magnitude of the current flow; and a driver circuit coupled to the first and second gates, the driver circuit arranged to control on and off states of the first and second GaN-based switches.

Embodiments of the disclosure provide a semiconductor package including a first integrated circuit die having a first side and a second side opposite the first side, a first source / drain, a first interconnect structure disposed on the first side, a second interconnect structure disposed on the second side, and a first power rail extending between the first source / drain and the second interconnect structure. The package includes a second integrated circuit die disposed adjacent the first integrated circuit die, the second integrated circuit die having a first side and a second side, a second source / drain, a third interconnect structure disposed on the first side of the second integrated circuit die, a fourth interconnect structure disposed on the second side of the second integrated circuit die, and a second power rail extending between the second source / drain and the fourth interconnect structure, and an edge interconnect feature having a first end contacting the first interconnect structure and a second end contacting the third interconnect structure.

An integrated circuit device includes a first semiconductor layer, a second semiconductor layer, a first source / drain epitaxial structure, a second source / drain epitaxial structure, and a first contact plug. The second semiconductor layer is above the first semiconductor layer. The first and second semiconductor layers are vertically spaced apart from each other. The first source / drain epitaxial structure is on a side of the first semiconductor layer. The second source / drain epitaxial structure is on a side of the second semiconductor layer and above the first source / drain epitaxial structure. The first source / drain epitaxial structure has a portion extending beyond a sidewall of the second source / drain epitaxial structure from a top view. The first contact plug is over a frontside of the first source / drain epitaxial structure. The first contact plug overlaps the portion of the first source / drain epitaxial structure from the top view.

A semiconductor structure includes a stacked device structure having a first field-effect transistor having a first source / drain region, and a second field-effect transistor vertically stacked above the first field-effect transistor, the second field-effect transistor having a second source / drain region and a gate region having first sidewall spacers. The stacked device structure further includes a frontside source / drain contact disposed on a first portion of a sidewall and a top surface of the second source / drain region, a first metal via connected to the frontside source / drain contact and to a first backside power line, and second sidewall spacers disposed on a first portion of the first metal via. The first sidewall spacers comprise a first dielectric material and the second sidewall spacers comprise a second dielectric material different than the first dielectric material.

The utility model relates to the technical field of gallium nitride power devices, in particular to a double-channel enhanced GaN power device, which comprises a substrate, a nucleating layer, a buffer layer, a lower channel layer, a first barrier layer, an upper channel layer, a second barrier layer and an insulating medium layer which are sequentially arranged from bottom to top. The device further comprises a first source-drain electrode group, a second source-drain electrode group, a first grid electrode and a second grid electrode. The structure is provided with two channels, two source electrodes, two grid electrodes and two drain electrodes, the on-resistance of the channels is reduced by adding one conducting channel, and the ohmic contact resistance of the source electrodes is reduced by forming ohmic contact between the two source electrodes and the two channels respectively. The ohmic contact resistance of the drain electrodes is reduced by forming ohmic contact between the two drain electrodes and the two channels respectively, so that the on resistance of the whole device is reduced under the condition that the chip area is not increased, and finally the chip size and the chip cost are reduced. In addition, the design of the two grid electrodes can ensure the control capability of the grid electrodes on the two channels.

A semiconductor structure includes a device layer, which in turn includes a plurality of field effect transistors, each of which has a first source-drain region, a second source-drain region, at least one channel region coupling the first and second source-drain regions; and a gate surrounding the at least one channel region. The semiconductor structure further includes a front side wiring layer with wiring coupled to the plurality of field effect transistors at a front side of the device layer; a back side power rail at a back side of the device layer; and a back side gate via interconnecting the back side power rail to the gate of at least one of the plurality of field effect transistors.

The first source-drain region is adjacent to the first transistor, the second source-drain region is adjacent to the second transistor, the upper source-drain contact is arranged above the first source-drain region, the bottom source-drain contact is arranged below the second source-drain region, and the bottom source-drain contact and the upper source-drain contact are arranged on two opposite sides. A horizontal surface of the bottom source drain contact is adjacent to a horizontal surface of the dielectric side spacer surrounding the second source drain region. In an embodiment, a bottom source-drain contact surrounds a vertical side of a source-drain region. A method includes forming first and second nanosheet stacks, forming a top source-drain contact of a first source-drain region adjacent to the first nanosheet stack, and forming a bottom source-drain contact of a lower horizontal surface of a second source-drain region adjacent to the second nanosheet stack.