286 results about "Second source" patented technology

A display device can include a substrate, a first light shielding layer disposed on the substrate, a second light shielding layer disposed on the first light shielding layer, an active layer disposed on the second light shielding layer and including a semiconductor region of a first transistor, a gate layer including a gate electrode of the first transistor disposed on the active layer, a first source metal layer including a first hold line disposed on the gate layer and configured to supply a hold signal, a second source metal layer including a second hold line disposed on the first source metal layer and connected to the first hold line, and a light emitting element including a pixel electrode disposed on the second source metal layer.

A semiconductor device includes a bit line extending in a vertical direction, and a 2-transistor (2T) memory cell including a first transistor and a second transistor on the first transistor. The first transistor includes an active pattern contacting the bit line, the active pattern including a first and second source / drain region, and a channel region, and a first gate structure including a first gate electrode layer overlapping the channel region. The second transistor includes a second gate structure including a second gate electrode layer, a channel structure contacting the bit line, the channel structure including a first horizontal portion extending in a first horizontal direction away from the bit line, and a vertical portion extending vertically from one end of the first horizontal portion, and a storage node between the first gate electrode layer and the second gate electrode layer, and the storage node connected to the channel structure.

An object of the present disclosure is to suppress reduction of noise resistance and parasitic oscillation in a semiconductor device. A semiconductor device includes: a plurality of semiconductor chips parallelly connected to each other; a source electrode; a first source pattern connected to the source electrode; a source sensing terminal; and a second source pattern connected to the source sensing terminal, wherein a surface of each of the semiconductor chips is connected to the first source pattern, a surface of a reference chip is connected to the second source pattern, a surface of at least one non-reference chip as the semiconductor chip other than the reference chip is not connected to the second source pattern, and a resistance value of a gate resistance of the reference chip is larger than a resistance value of a gate resistance of the non-reference chip.

Techniques are presented for fabricating an integrated circuit with conductive backside contacts beneath source or drain regions. Backside cavities beneath the source or drain regions are formed using backside lithography and anisotropic etching. Subsequently, the backside cavities are filled with a conductive material to form the backside contacts. A semiconductor device includes a gate structure around or otherwise on a semiconductor region extending from a first source or drain region to a second source or drain region. The substrate beneath the semiconductor device is removed from the backside to expose a sub-fin region, which is also removed using backside etching and replaced with a dielectric material.Suitable lithographic operations can be performed on the dielectric backing material along with anisotropic etching to create any number of cavities through the dielectric material. The conductive backing contacts are then formed within these cavities.

This invention provides a common-source common-gate field-effect transistor (CFET) and a semiconductor chip with a shielded gate, comprising multiple parallel-connected transistor structure groups, each including a first transistor structure and a second transistor structure. A first stacked structure is connected to the upper end of a first drain, and both a first oxide layer and a second stacked structure are connected to the upper end of the first stacked structure. A first shielded gate is connected inside the first oxide layer and is connected to the first source. A first gate is connected to the upper end of the first oxide layer, and the first source is connected to the first oxide layer and the second stacked structure. A third stacked structure is connected to the upper end of a second drain, and the second oxide layer and a fourth stacked structure are connected to the upper end of the third stacked structure. A second shielded gate is connected to the interior of the second oxide layer and is connected to the second gate. The second gate is connected to the upper end of the second oxide layer, and the second source is connected to the second oxide layer and the fourth stacked structure.

An integrated circuit device is disclosed which has a substrate layer with input and output terminals and an array of FET elements formed over a top surface of the substrate layer, where each FET element includes an elongated source contact with opposed sides extending longitudinally between a first source end that is proximate to the output terminal layer and a second source end that is proximate to the input terminal; a U-shaped drain contact positioned to enclose the first source end and located to define a U-shaped channel region between the elongated source contact and the U-shaped drain contact; and a U-shaped gate contact positioned over the U-shaped channel region and between the U-shaped drain contact and the elongated source contact, where the U-shaped gate contact and U-shaped drain contact each have a closed end located in the peripheral ancillary region between the first source end and the output terminal.

Techniques for fully homomorphic encryption are described. In some examples, a fully homomorphic encryption includes a butterfly compute circuitry to support a polynomial integer multiplication in response to an instance of a single instruction of a first type, wherein the instance of the single instruction is at least to include one or more fields for a register file address for a first source operand of the integer multiplication, one or more fields for a register file address for a second source operand of the integer multiplication, and one more fields for a register file address for a result of the integer multiplication, wherein the butterfly compute circuitry is to additionally support modular arithmetic operations.

A transistor includes: a substrate; a first fin and a second fin protruding upwardly from a top surface of the substrate, wherein the first fin and the second fin are concentric, and each of the first fin and the second fin comprises a first straight section, a second straight section in parallel with the first straight section, a first curved section, and a second curved section; a first drain and a second drain; a first source and a second source; a first curved channel and a second curved channel located at the first curved section of the first fin and the first curved section of the second fin, respectively; and a third curved channel and a fourth curved channel located at the second curved section of the first fin and the second curved section of the second fin, respectively.

Example embodiments provide a vertical transistor, an inverter including the same, and a vertical semiconductor device including the same. The vertical transistor includes: a substrate; a first source / drain electrode layer provided on the substrate; a second source / drain electrode layer provided above the first source / drain electrode layer; a first gate electrode layer provided between the first and second source / drain electrode layers; a first gate insulating film passing through the first gate electrode layer; a hole passing through the second source / drain electrode layer, the first gate insulating film, and the first source / drain electrode layer; and a first channel layer provided on the side of the hole, wherein the first channel layer may include a 2D semiconductor.

A circuit is disclosed. The circuit includes a transformer having a primary winding extending between a first terminal and a second terminal, and further including a secondary winding extending between a third terminal and a first output terminal; a first switch having a first gate terminal, a first source terminal and a first drain terminal, the first drain terminal coupled to the second terminal and the first source terminal coupled to a power source; a second switch having a second gate terminal, a second source terminal and a second drain terminal, the second source terminal coupled to the second terminal, and the second drain terminal coupled to the power source; and a third switch having a third gate terminal, a third source terminal and a third drain terminal, the third source terminal coupled to the third terminal and the third drain terminal coupled to a second output terminal.

A method for forming a semiconductor structure is provided. The method includes forming a first transistor and a second transistor on a substrate, respectively. The first transistor includes a first source / drain feature adjoining first channel layers and a first gate stack surrounding the first channel layers. The second transistor includes a second source / drain feature adjoining second channel layers, and a second gate stack surrounding the second channel layers. The method further includes forming a first contact plug that partially passes through the first source / drain feature from the backside surface of the first source / drain feature, and forming a second contact plug that partially passes through the second source / drain feature from the backside surface of the second source / drain feature. The first contact plug is shallower than the second contact plug.

The application relates to a bidirectional power device module integrated with a driving circuit and an active substrate clamping circuit, which comprises a common-drain bidirectional power device, a driving circuit used for providing a driving signal to the common-drain bidirectional power device to turn on and turn off the device, and a substrate clamping circuit comprising a first switch tube and a second switch tube, wherein the first switch tube and the second switch tube are commonly connected to the substrate of the common-drain bidirectional power device, the drain of the first switch tube is connected to the first source of the common-drain bidirectional power device, and the gate is connected to the output end of a third driving unit; the drain of the second switch tube is connected to the second source of the common-drain bidirectional power device, and the gate is connected to the output end of a fourth driving unit; the input end of the third driving unit inputs a first PWM input signal which is subjected to logic processing; and the input end of the fourth driving unit inputs a second PWM input signal which is subjected to logic processing. The application can improve the substrate clamping speed and reduce the substrate potential.

A semiconductor device includes first and second active fins on first and second regions of a substrate, an isolation pattern on a boundary between the first and second regions and portions of the first and second regions adjacent thereto and separating the first and second active fins, a first gate structure on the first active fin and the isolation pattern on the first region, a second gate structure on the second active fin and the isolation pattern on the second region, a first source / drain layer on the first active fin adjacent to the first gate structure, and a second source / drain layer on the second active fin adjacent to the second gate structure. A width of a portion of the first gate structure overlapping the first active fin is greater than that of a portion of the second gate structure overlapping the second active fin.

A display panel and a display device are provided. The display panel includes a base substrate, a first source-drain layer, a second source-drain layer, an electrode layer, and a pixel definition layer. The first source-drain layer is provided on the base substrate and includes a data line, the second source-drain layer is provided on the first source-drain layer and includes a power line, the electrode layer is provided on the second source-drain layer and includes electrode parts, and the pixel definition layer is provided on the electrode layer and has pixel openings. The pixel opening is provided in correspondence with the electrode part. An orthographic projection of the pixel opening on the base substrate coincides with that of the electrode part. The orthographic projections of at least some of the electrode parts on the base substrate are at least partially overlapped with that of the data line.

Structures including an access transistor and a resistive memory element, and methods of forming such structures. The structure comprises an access transistor including a semiconductor layer, a first source / drain region, a second source / drain region, a gate dielectric layer on the semiconductor layer, and a gate electrode overlapped with the gate dielectric layer. The gate dielectric layer has a first portion with a first thickness adjacent to the first source / drain region and a second portion with a second thickness adjacent to the second source / drain region, and the first thickness is greater than the second thickness. The structure further comprises a resistive memory element that is coupled to the first source / drain region of the access transistor.

A semiconductor device includes a substrate having a frontside, a backside, and a transistor that includes a gate region, a first source / drain region of a first depth into the substrate, and a second source / drain region of a second depth into the substrate. The semiconductor device further includes a backside contact (BC) region extending from the backside into the substrate and electrically connected to the first source / drain region. The semiconductor device further includes a backside partial diffusion break (BPDB) region that includes a non-conducting material, extending from the backside into the substrate and distinct from the first source / drain region.

A semiconductor device includes: a bit line extending in a vertical direction; and a 2-transistor (2T) memory cell including a first transistor and a second transistor on the first transistor. The first transistor includes: an active pattern contacting the bit line, the active pattern including: a first source / drain region and a second source / drain region and a channel region; and a first gate structure including a first gate electrode layer overlapping the channel region. The second transistor includes: a second gate structure including a second gate electrode layer; a channel structure contacting the bit line, the channel structure including: a first horizontal portion extending away from the bit line in a first horizontal direction, and a vertical portion extending vertically from one end of the first horizontal portion; and a memory node between the first gate electrode layer and the second gate electrode layer, and the memory node being connected to the channel structure.

Semiconductor unit with a semiconductor region (40) having a first principal surface and a second principal surface opposite the first principal surface, wherein the semiconductor region has the following: - alternating first support layers (13) with a first conductivity type and second support layers (14) with a second conductivity type along the first main surface; - a first trough layer (21) with the second conductivity type, located within each of the first support layers (13) on an upper surface of the first support layer (13); - a first source layer (22) with the first conductivity type, which is located within the first trough layer (21) on an upper surface of the first trough layer (21); - a first dielectric layer (35) on a lateral surface, which is located on a lateral surface in a first trench (74) which is located at boundaries between the first support layers (13) and the second support layers (14), wherein the first dielectric layer on the lateral surface is in contact with the first trough layer (21) and the first source layer (22); - a first dielectric layer (36) on a soil surface located on a soil surface in the first trench, wherein the first dielectric layer (36) on the soil surface is at least partially in contact with one of the second support layers (14); and - a first gate electrode (71) located in the first trench, opposite the first trough layer (21) and the first source layer (22) by the first dielectric layer (35) on the lateral surface and opposite the second support layer (14) by the first dielectric layer (36) on the bottom surface, - wherein each of the second support layers (14) has a second source layer (27) of the first conductivity type located within the second support layer on an upper surface of the second support layer, - wherein the first dielectric layer (35) is located on opposite lateral surfaces in the first trench and is in contact with an area (26) with the second conductivity type within the second support layer (14) and the second source layer (27), - wherein the first dielectric layer on the bottom surface is in contact with the area with the second conductivity type within the second support layer (14) and - wherein a lower surface of the second source layer (27) is located closer to the second main surface than a lower surface of the first source layer (22) is located.

The present invention provides a semiconductor device that improves current spread by reducing saturated drain current, lowering the degree of current concentration at the active source contact, and improving voltage overshooting or non-uniformity of source current at different cell region locations. [Solution] The semiconductor device includes a substrate including a cell region and a peripheral region PERI located outside the cell region, a first conductivity type semiconductor layer located on the upper surface of the substrate, a second conductivity type doping wall region located within the first conductivity type semiconductor layer, a gate electrode located on the first conductivity type semiconductor layer, a gate insulating layer located between the first conductivity type semiconductor layer and the gate electrode, a source electrode 170 located on the second conductivity type doping wall region, and a drain electrode located below the lower surface of the substrate. The source electrode includes a first source electrode 171 located on the gate electrode and a second source electrode 172 located on the first source electrode and having a greater electrical resistance than the first source electrode.

The specification provides a processing method and a routing device for controlling a session, the method comprising: an NPU receiving a first control packet, converting a first source address in the first control packet into a second source address according to a network address translation (NAT) rule, the NPU uploading the first control packet and the second source address to a CPU kernel state, the NPU receiving a second control packet sent by the CPU kernel state, converting a first destination address in the second control packet into a second destination address according to the NAT rule, the NPU uploading the second control packet and the second destination address to the CPU kernel state, and the NPU receiving a takeover notification sent by the CPU kernel state and a control packet converted by a user state to process a session. By the method, the technical problem that the processing logic is limited by the NPU hardware and that the IP can be converted only once in each flow processing and the twice NAT conversion in the NAT hairpin scene cannot be implemented is avoided.

A display substrate and a display device are provided. The display substrate includes: a base substrate, and a low temperature poly-silicon thin film transistor and a metal oxide thin film transistor on the base substrate; the low temperature poly-silicon thin film transistor includes: a low temperature poly-silicon semiconductor layer, a first gate insulating layer, a first gate electrode, a first interlayer insulating layer, a first source electrode, and a first drain electrode; the metal oxide thin film transistor includes: a metal oxide semiconductor layer, a second gate insulating layer, a second gate electrode, a second interlayer insulating layer, a passivation layer, a second source electrode, and a second drain electrode; and the second drain electrode is on a side of the metal oxide semiconductor layer away from the base substrate.

A complementary field-effect transistor (CFET) circuit with a direct vertical connector and a method for manufacturing the same are disclosed. In one aspect, a semiconductor structure includes: a first field-effect transistor (FET) of a first charge carrier type, the first field-effect transistor (FET) including a first source / drain (S / D) region (412b) and a second source / drain (S / D) region (412a) and one or more channels (408b), the one or more channels being electrically connected to the first S / D region and the second S / D region through a first gate structure; a second FET of a second charge carrier type, the second FET being disposed above the first FET in the Z direction and including a third S / D region (414b) and a fourth S / D region (414a) and one or more channels (408a), the one or more channels being electrically connected to the third S / D region and the fourth S / D region through a second gate structure; and a vertical connector (420) extending in the Z direction from the top surface of the first S / D region (412b) to the bottom surface of the third S / D region (414b) and electrically coupling the first S / D region to the third S / D region.

The application provides a CMOS device and a preparation method thereof, the CMOS device comprising a GaN HEMT device and a diamond PMOS device arranged in a vertical direction, and an isolation layer arranged between the GaN HEMT device and the diamond PMOS device; the GaN HEMT device comprising a GaN layer, an AlGaN layer, a first source, a first gate and a first drain, the diamond PMOS device comprising a hydrogen-terminated diamond layer, a second source, a second drain and a second gate; the first gate and the second gate are arranged in correspondence in the vertical direction and are electrically connected through a first metal filling hole extending in the vertical direction; the first drain and the second drain are arranged in correspondence in the vertical direction and are electrically connected through a second metal filling hole extending in the vertical direction. The COMS device provided by the application has high carrier mobility, low power consumption and high heat dissipation performance, and can reduce parasitic resistance, parasitic capacitance and parasitic inductance, and improve integration density.

This disclosure provides a controller, address management method, and system for a phase-change memory (PCM). The method includes: determining the address mapping mode of the PCM; if it is a static mapping mode, mapping a first source address to a first destination address based on a preset mapping table; if it is a dynamic mapping mode, matching a corresponding address mapping rule according to a dynamic scenario, and mapping a second source address to a second destination address based on the address mapping rule; if it is a hybrid mapping mode, mapping a third source address to a third destination address based on a preset mapping table, controlling the PCM to perform read operations based on the third destination address; and matching a corresponding address mapping rule according to a dynamic scenario, mapping a fourth source address to a fourth destination address based on the address mapping rule, and controlling the PCM to perform write operations based on the fourth destination address. This application can reduce the read latency of the PCM, improve the write performance and media lifetime of the PCM, and achieve a balance between read and write performance.

A semiconductor device includes a first source region, a first sidewall body region, a gate region, a second source region and a link region formed in a substrate of a first conductivity type. The first source region and the second source region may be of the first conductivity type while the first sidewall body region and the link region may be of a second conductivity type opposite to the first conductivity type. The link region and the gate region are respectively disposed at a first side and a second side of the first source region. The first sidewall body region may be disposed below or underneath the first source region.

A nitride semiconductor device including: a substrate; a channel layer provided above the substrate; a vertical transistor provided in a first region, the vertical transistor being a normally-on transistor; and a lateral transistor provided in a second region, the lateral transistor being a normally-off transistor, in which the vertical transistor includes: a first portion that is a portion of the channel layer and overlaps the first region in a plan view of the substrate; a first gate electrode; and a first drain electrode, the lateral transistor includes: a second portion that is a portion of the channel layer and overlaps the second region in the plan view; a second gate electrode; and a second source electrode, the first gate electrode and the second source electrode are electrically connected to each other, and a source potential of the vertical transistor and a drain potential of the lateral transistor are equal.

Assembly for determining a characteristic of a structure on a substrate, comprising a radiation illumination dipole having first and second sources that are angularly offset to a transverse direction in an illumination pupil plane. The first and second sources irradiate a structure having a periodically repeating pattern along a transverse. A multi-part wedge is located in an exit pupil of the assembly, configured to receive from the structure: a lower radiation order and a higher radiation order of diffracted radiation of the first source on a first part of the multi-part wedge, and a lower radiation order and a higher radiation order of diffracted radiation of the second source on a second part of the multi-part wedge. A detector receives a first and second spatially separated images formed from first and second source radiation incident on the first and second parts of the wedge, respectively.

This application discloses a semiconductor structure and its fabrication method, relating to the field of semiconductor technology. The fabrication method includes: providing a substrate, the substrate including a first device region and a second device region spaced apart; forming an initial stacked structure on each device region, the initial stacked structure including an initial gate structure and a first dielectric layer, the first dielectric layer being located on the side of the initial gate structure away from the substrate; using the first dielectric layer of the first device region as a mask, forming a device filling trench in the first device region; forming a first source / drain electrode in the device filling trench, and removing the first dielectric layer of each device region; forming a second source / drain electrode in the second device region. This stabilizes the gate thickness corresponding to the initial gate structure, improving the performance of the semiconductor structure.

Embodiments of the disclosure include integrated circuit structures having source or drain dopant diffusion blocking layers. In an example, an integrated circuit structure includes a fin including silicon. A gate structure is over a channel region of the fin, the gate structure having a first side opposite a second side. A first source or drain structure is at the first side of the gate structure. A second source or drain structure is at the second side of the gate structure. The first and second source or drain structures include a first semiconductor layer and a second semiconductor layer. The first semiconductor layer is in contact with the channel region of the fin, and the second semiconductor layer is on the first semiconductor layer. The first semiconductor layer has a greater concentration of germanium than the second semiconductor layer, and the second semiconductor layer includes boron dopant impurity atoms.