2377 results about "Second source" patented technology

A semiconductor device includes a first transistor adjacent to a second transistor and an etch stop layer within an interlayer dialectic (ILD) to separate a lateral contact and a plurality of backside source / drain region-gate cut dielectric layers. The lateral contact connects a via over a first source / drain region of the first transistor to a second source / drain region of the second transistor.

An SRAM cell includes a first inverter cross-coupled to a second inverter. The first inverter includes a first pull-up transistor and a first pull-down transistor, having coupled drains that define a first storage node. The SRAM cell further includes a first N-type pass-gate transistor having a first drain coupled to a write bit line, a first source coupled to the first storage node, and a first gate coupled to a first write word line. The SRAM cell further includes a first P-type pass-gate transistor having a second drain coupled to the write bit line and a second source coupled to the first storage node. The SRAM cell further includes a P-type transistor having a third drain, coupled to a second gate of the first P-type pass-gate transistor, a third source coupled to a second write word line, and a third gate coupled to an enable signal.

An electronic component. The electronic component includes a base; a first semiconductor device attached to the base and having: a first Gallium nitride (GaN)-based switch having a first gate, a first source and a first drain, the first gate arranged to control a current flow between the first source and the first drain; a second GaN-based switch having a second source, a second gate and a second drain, the second gate coupled to the first gate, and the second drain coupled to the first drain. In one aspect, the electronic component also includes a second semiconductor device attached to the base and having: a logic circuit coupled to the second source and arranged to detect a magnitude of the current flow; and a driver circuit coupled to the first and second gates, the driver circuit arranged to control on and off states of the first and second GaN-based switches.

Embodiments of the disclosure provide a semiconductor package including a first integrated circuit die having a first side and a second side opposite the first side, a first source / drain, a first interconnect structure disposed on the first side, a second interconnect structure disposed on the second side, and a first power rail extending between the first source / drain and the second interconnect structure. The package includes a second integrated circuit die disposed adjacent the first integrated circuit die, the second integrated circuit die having a first side and a second side, a second source / drain, a third interconnect structure disposed on the first side of the second integrated circuit die, a fourth interconnect structure disposed on the second side of the second integrated circuit die, and a second power rail extending between the second source / drain and the fourth interconnect structure, and an edge interconnect feature having a first end contacting the first interconnect structure and a second end contacting the third interconnect structure.

A semiconductor structure includes a device layer, which in turn includes a plurality of field effect transistors, each of which has a first source-drain region, a second source-drain region, at least one channel region coupling the first and second source-drain regions; and a gate surrounding the at least one channel region. The semiconductor structure further includes a front side wiring layer with wiring coupled to the plurality of field effect transistors at a front side of the device layer; a back side power rail at a back side of the device layer; and a back side gate via interconnecting the back side power rail to the gate of at least one of the plurality of field effect transistors.

An integrated circuit includes a first nanostructure transistor including a plurality of first semiconductor nanostructures over a substrate and a source / drain region in contact with each of the first semiconductor nanostructures. The integrated circuit includes a second nanostructure transistor including a plurality of second semiconductor nanostructures and a second source / drain region in contact with one or more of the second semiconductor nanostructures but not in contact with one or more other second semiconductor nanostructures.

The present disclosure relates to a method. The method includes forming a plurality of first source / drain contacts and a second source / drain contact over a substrate. The second source / drain contact wraps around the plurality of first source / drain contacts. A plurality of gate structures are over the substrate. The plurality of gate structures are laterally between the plurality of first source / drain contacts and the second source / drain contact. An isolation region is formed within the substrate. The isolation region has one or more curved edges that face a curved outermost sidewall of the second source / drain contact. The one or more curved edges are separated from the curved outermost sidewall by a non-zero distance.

A mixer includes a mixing stage, and a first transistor and a second transistor coupled to the mixing stage. A gate of the first transistor is coupled to a first input of the mixer, and a gate of the second transistor is coupled to a second input of the mixer. The mixer also includes a first source resistor coupled to a source of the first transistor, and a second source resistor coupled to a source of the second transistor. The mixer further includes an amplifier having a first input coupled to the source of the first transistor, and a second input coupled to the source of the second transistor. The amplifier is configured to adjust at least one bias voltage of at least one of the first transistor and the second transistor based on a differential voltage between the first and second inputs of the amplifier.

Methods and apparatus for filtering a signal using a current mode filter circuit that enables source degradation. An example filter circuit generally includes an input node; an output node; a power supply node; a first transistor including a drain coupled with the input node; a second transistor including a drain coupled with the output node and including a gate coupled with a gate of the first transistor; a capacitive element coupled between a drain of the first transistor and the power supply node; a first resistive element coupled between the drain electrode and the gate electrode of the first transistor; a first source degeneration element coupled between a source of the first transistor and the power supply node; and a second source degeneration element coupled between a source of the second transistor and the power supply node.

A semiconductor structure is provided. The semiconductor structure includes a first plurality of nanostructures between a first source / drain feature and a second source / drain feature, a first gate segment surrounding the first plurality of nanostructures, and a wall structure abutting the first gate segment. A first nanostructure in the first plurality of nanostructures includes a bulk portion and a protrusion, and the protrusion protrudes from a first sidewall of the bulk portion toward the wall structure.

Current collapse of a normally-on type dual-gate bidirectional switch is suppressed. Dual-gate bidirectional switch includes first gate, first source, second gate, and second source. Control system includes first gate drive circuit, second gate drive circuit, and controller. Controller controls first gate drive circuit and second gate drive circuit. At the time of turning on dual-gate bidirectional switch and when the potential of first source is lower than the potential of second source, controller applies a first positive voltage for a first period between first gate and first source from first gate drive circuit, and applies a voltage smaller than the first positive voltage after the first period has elapsed.

A self-calibrating hybrid spectrophotometer comprises a receptacle for receiving the cuvette, first and second optodes that are configured to permit light to enter the cuvette, third and fourth optodes that are configured to permit light to leave the cuvette, and a controller that is configured to control delivery of light to one of the first and second optodes. Light entering one of the first and second optodes is received at the third and fourth optodes after having interacted with the turbid sample along different paths having different lengths. Measurements made at the third and fourth optodes in response to having illuminated both the first and second source optodes provide two slopes of optical transmittance as a function of path length. The spectrophotometer uses these slopes to identify a slope that is indicative of the absorption coefficient and the reduced scattering coefficient of the sample.

Integrated circuit devices and methods of forming the same are provided. An integrated circuit device may include a substrate and a transistor stack on the substrate, the transistor stack including a first transistor and a second transistor on the first transistor. The first transistor may be between the substrate and the second transistor and the first transistor may include first and second source / drain regions, a first channel region between the first and second source / drain regions, and a first gate structure on the first channel region. A lower surface of the first source / drain region may be higher than a lower surface of the first gate structure relative to the substrate.

A semiconductor device structure, along with methods of forming such, are described. The structure includes a stack of semiconductor layers spaced apart from and aligned with each other, a first source / drain epitaxial feature in contact with a first one or more semiconductor layers of the stack of semiconductor layers, and a second source / drain epitaxial feature disposed over the first source / drain epitaxial feature. The second source / drain epitaxial feature is in contact with a second one or more semiconductor layers of the stack of semiconductor layers. The structure further includes a first dielectric material disposed between the first source / drain epitaxial feature and the second source / drain epitaxial feature and a first liner disposed between the first source / drain epitaxial feature and the second source / drain epitaxial feature. The first liner is in contact with the first source / drain epitaxial feature and the first dielectric material.

The present disclosure provides a semiconductor device and a method of forming the same. The semiconductor device includes first nanostructures suspended above a first region of a substrate, first inner spacers interleaving the first nanostructures, a first gate structure wrapping around at least one of the first nanostructures, a first source / drain feature abutting the first nanostructures, second nanostructures suspended above a second region of the substrate, second inner spacers interleaving the second nanostructures, a second gate structure wrapping around at least one of the second nanostructures, and a second source / drain feature abutting the second nanostructures. The first and second regions of the substrate include different conductivity types. A thickness of the first inner spacers is smaller than a thickness of the second inner spacers.

The invention provides a vector instruction processing method, electronic equipment, a readable medium and a program product. The vector instruction processing method comprises the steps of obtaining a vector length of a vector instruction; when the vector length of the vector instruction is the first value and the effective indication of the second source operand is the first value, cancelling the transmission of the vector instruction, and setting the effective indication of the second source operand as a second value; a first value of the second source operation valid indication indicates that the old value of the destination register is not required as a valid indication of the second source operand, and a second value of the second source operation valid indication indicates that the old value of the destination register is required as a valid indication of the second source operand; under the condition that the destination register is ready, retransmitting the vector instruction; a first source operand and a second source operand are obtained based on the vector instruction, and the vector instruction is executed based on the first source operand and the second source operand, the second source operand being an old value of the destination register.

An integrated circuit structure includes a device layer including a plurality of devices. The plurality of devices includes (i) a plurality of source and drain regions, (ii) a plurality of gate stacks, and (iii) a plurality of gate spacers, each gate spacer separating a corresponding source or drain region from a corresponding gate stack, the gate spacers comprising a first dielectric material. A first source or drain contact is coupled to a frontside of a first source or drain region of the plurality of source or drain regions. A second dielectric material is coupled to a backside of the first source or drain region. A second source or drain contact is coupled to a backside of a second source or drain region of the plurality of source or drain regions. In an example, the first dielectric material and the second dielectric material comprise the same elemental constituents.

There are provided a semiconductor memory device and a manufacturing method of the same. The semiconductor memory device includes: a peripheral circuit structure with a page buffer group; a net-shaped first source pattern disposed on the peripheral circuit structure, the net-shaped first source pattern with a plurality of openings; a memory cell array disposed on the net-shaped first source pattern; a second source pattern disposed between the net-shaped first source pattern and the memory cell array; and a cell-array-side pad pattern, disposed between the net-shaped first source pattern and the second source pattern, extending toward the net-shaped first source pattern from the second source pattern, the cell-array-side pad pattern being bonded directly to the net-shaped first source pattern.

An integrated circuit (IC) device including fin-type active regions parallel to each other on a substrate, the fin-type active regions extending in a first lateral direction, a first nanosheet stack apart from a fin top surface of a first fin-type active region selected from the fin-type active regions, the first nanosheet stack including at least one nanosheet facing the fin top surface of the first fin-type active region, a gate structure surrounding the first nanosheet stack, the gate structure extending in a second lateral direction, a first source / drain region in contact with one sidewall of the first nanosheet stack, and a second source / drain region in contact with another sidewall of the first nanosheet stack, wherein a greatest width of the first source / drain region is less than a greatest width of the second source / drain region in the second lateral direction may be provided.

A superjunction trench MOSFET structure and its manufacturing method belong to the technical field of superjunction MOSFETs. A superjunction trench MOSFET structure includes an N+ substrate, a first cell structure, and a second cell structure. Among them, both the first cell structure and the second cell structure are regular hexagons. The first cell structure includes a first N pillar region and a first P pillar region surrounding the first N pillar region, and a first source trench is provided on the first N pillar region. The second cell structure includes a second N pillar region and a second P pillar region surrounding the second N pillar region, and a second source trench is provided on the second N pillar region. A number of second cell structures surround the first cell structure. The second cell structure further includes a gate trench, a first channel is formed between the gate trench and the first source trench, a second channel is formed between the gate trench and the second source trench, and the lengths of the first channel and the second channel are different. By setting a regularly tiled cell structure in the shape of a regular hexagon and having an asymmetric double channel, the present application not only improves the channel density but also provides a good gate oxide protection effect.

The invention relates to an integrated GaN power device including PFC and QR flyback controllers. An electronic component. The electronic component includes: a base; a first semiconductor device attached to the base and having: a first gallium nitride (GaN)-based switch having a first gate, a first source, and a first drain, the first gate being arranged to control a current flow between the first source and the first drain; and a second GaN-based switch having a second source, a second gate, and a second drain, the second gate coupled to the first gate, and the second drain coupled to the first drain. In one aspect, the electronic assembly also includes a second semiconductor device attached to the base and having: a logic circuit coupled to the second source and arranged to detect an amplitude of the current flow; and a drive circuit coupled to the first gate and the second gate, the drive circuit arranged to control on and off states of the first GaN-based switch and the second GaN-based switch.

The invention relates to a circuit and a method for generating a bias voltage in a substrate clamp circuit. An electronic device includes: a gallium nitride (GaN) substrate having a GaN-based top layer attached to a silicon-based bottom layer; a bidirectional switch formed on the GaN-based top layer and including a first source node, a second source node, and a common drain node; a first bias generator circuit arranged to couple the first source node to the silicon substrate layer; and a second bias generator circuit arranged to couple the second source node to the silicon substrate layer. In one aspect, when a voltage of the first source node is higher than a voltage of the second source node, the first bias generator circuit approaches a voltage at the silicon substrate layer to the voltage at the second source node.

A semiconductor device according to the present disclosure includes a first transistor and a second transistor sharing a first source / drain feature, a third transistor and a fourth transistor sharing a second source / drain feature, a first source / drain contact disposed over the first source / drain feature, a second source / drain contact disposed over the second source / drain feature, a first backside via disposed below the first source / drain feature, and a second backside via disposed below the second source / drain feature. A gate structure of the first transistor is coupled to the second source / drain contact and a gate structure of the fourth transistor is coupled to the first source / drain contact.

The present disclosure provides a three-dimensional DRAM array structure including L layers, M rows, and N columns of DRAM cell structures, each DRAM cell structure including first and second gate transistors having a tubular channel, disposed in a vertical direction and electrically connected in parallel, and a storage capacitor of a tubular structure disposed between the first and second gate transistors in the vertical direction, an inner electrode of the second transistor is connected to the first source / drain of the first and second gate-all-around transistors, and an outer electrode is connected to a source line; the M * N bit lines respectively extend in a tubular structure jointly formed by the first and second gate-all-around transistors and the storage capacitor in the M-row and N-column DRAM unit structure along the vertical direction, and are respectively connected to second source / drain electrodes of the first and second gate-all-around transistors; the L * M first word lines and the L * M second word lines extend in the first horizontal direction and are connected to grid electrodes of the first fence transistors and the second fence transistors in the L layers of DRAM unit structures respectively, and the M rows of DRAM unit structures are divided into M / s row groups.

A semiconductor structure includes an upper device stacked over a lower device. In an example, the upper device includes (i) a first source region, (ii) a first drain region, (iii) a body of semiconductor material extending laterally from the first source region to the first drain region, and (iv) a first gate structure at least in part wrapped around the body. In an example, the lower device includes (i) a second source region, (ii) a second drain region, and (iii) a second gate structure at least in part laterally between the second source region and the second drain region. In an example, the lower device lacks a body of semiconductor material extending laterally from the second source region to the second drain region. In another example, the upper device lacks a body of semiconductor material extending laterally from the first source region to the first drain region.

Techniques are provided herein to form an integrated circuit having a backside interconnect structure coupled between different transistor elements, such as between source or drain regions and / or gate structures. The backside interconnect structure may be used to replace frontside local interconnect structures, thus freeing up more space in the frontside interconnect region. In one such example, a first semiconductor device includes a first semiconductor region extending from a first source or drain region and a first gate structure extending over the first semiconductor region, and a second semiconductor device includes a second semiconductor region extending from a second source or drain region and a second gate structure extending over the second semiconductor region. A conductive structure is coupled between a bottom surface of each of the first source or drain region, the second source or drain region, and a portion of the first gate structure.

A semiconductor device includes a substrate insulating layer, a gate structure extending in a first direction on the substrate insulating layer, a plurality of channel layers spaced apart from each other in a second direction, the second direction perpendicular to an upper surface of the substrate insulating layer, the plurality of channel layers on the substrate insulating layer and surrounded by the gate structure, a first source / drain region and a second source / drain region, on both sides of the gate structure and connecting to the plurality of channel layers, a first spacer layer below the first source / drain region, and a second spacer layer below the second source / drain region, and a backside contact plug partially recessing a lower surface of the first source / drain region through the substrate insulating layer and the first spacer layer.

A fabricating method of an SOT MRAM structure includes forming an SOT MRAM. The SOT MRAM includes a word line. A second source / drain doping region and a fourth source / drain doping region are disposed at the same side of the word line. A first conductive line contacts the second source / drain doping region. A second conductive line contacts the fourth source / drain doping region. The second conductive line includes a third metal pad. A memory element contacts an end of the first conductive line. A second SOT element covers and contacts a top surface of the memory element. The third metal pad covers and contacts part of the top surface of the second SOT element.

An integrated circuit includes a complimentary field effect transistor (CFET). The CFET includes a first transistor and a second transistor stacked vertically. A conductive via extends vertically from a first source / drain region of the first transistor past the second transistor. The second transistor includes an asymmetric second source / drain region. The asymmetry of the second source / drain region helps ensure that the second source / drain region does not contact the conductive via.

A semiconductor device includes a first transistor cell. The first transistor cell generates a first current signal and a second current signal indicating a bit of a physical unclonable function. The first transistor cell includes a first transistor, a second transistor and a third transistor. The first transistor outputs the first current signal. The second transistor generates the first current signal from a first source / drain structure of the second transistor, and generates the second current signal from a second source / drain structure of the second transistor. The third transistor outputs the second current signal. The first transistor, the second transistor and the third transistor are stacked in order along a first direction. The first source / drain structure of the second transistor and the second source / drain structure of the second transistor are arranged along a second direction different from the first direction.