2930 results about "Second source" patented technology

The present application relates to the technical field of display, and discloses a display panel and a manufacturing method therefor, and a display device. The display panel comprises: a base substrate; a backboard wiring layer which comprises a first source-drain electrode layer, a first planarization layer, a second source-drain electrode layer, a second planarization layer, and a third source-drain electrode layer which are stacked; an encapsulation layer; a touch electrode layer; and a touch wire which is electrically connected to a touch electrode, wherein the touch wire is arranged in a non-display area and extends to a binding area through a bending area, the touch wire comprises a first wiring portion and a second wiring portion which are electrically connected, the first wiring portion crosses the bending area, the second wiring portion does not overlap with the bending area, the first wiring portion is located on the third source-drain electrode layer, and the second wiring portion is located on the touch electrode layer. The second source-drain electrode layer is replaced with the third source-drain electrode layer to transmit a touch signal in the bending area, so that the punching of the middle film layer of the third source-drain electrode layer and the second source-drain electrode layer is omitted, thereby reducing the thickness of the film layer needing to be punched.

A semiconductor device includes a substrate that includes a first surface and a second surface, a first source / drain pattern disposed on the first surface of the substrate, a second source / drain pattern disposed on the first surface of the, a first source / drain contact disposed on the first source / drain pattern and connected to the first source / drain pattern, a second source / drain contact disposed on the second source / drain pattern and connected to the second source / drain pattern, a rear wiring line disposed on the second surface of the substrate, a first contact connection via that connects the rear wiring line with the first source / drain contact, a second contact connection via that connects the rear wiring line with the second source / drain contact and is spaced apart from the first contact connection via, and an air gap structure disposed between the first contact connection via and the second contact connection via.

The invention provides a low-resistance separation trench gate silicon carbide VDMOS and a preparation method thereof, and the method comprises the steps: depositing metal on the lower side surface of a silicon carbide substrate, and forming a drain metal layer; epitaxially growing on the upper side surface of the silicon carbide substrate to form a drift layer; forming a barrier layer, etching, performing ion implantation, and forming a P-type source region, a low-resistance region, a P-type well region and an N-type source region; a barrier layer is formed again, and a first insulating medium layer and a second insulating medium layer are formed through etching and deposition; re-forming a barrier layer, etching and depositing metal, and respectively forming a first gate metal layer and a second gate metal layer; forming a barrier layer again, etching and depositing metal, and forming a first source metal layer; and forming a barrier layer again, etching, depositing metal, forming a second source metal layer, and removing the barrier layer to complete preparation. And the driving loss and the body diode loss of the device are reduced.

The invention provides a left-right shielding trench gate silicon carbide VDMOS and a preparation method thereof, and the method comprises the steps: depositing metal on the lower side surface of a silicon carbide substrate, and forming a drain metal layer; epitaxially growing on the upper side surface of the silicon carbide substrate to form a drift layer; forming a barrier layer above the drift layer, and performing etching and ion implantation to form a P-type source region, a low-resistance region, a P-type well region and an N-type source region; forming a barrier layer again, etching to form a first groove, and depositing to form an insulating dielectric layer; forming a barrier layer again, etching and depositing metal, and forming a first gate metal layer and a second gate metal layer; forming a barrier layer again, etching and depositing metal, and forming a first source metal layer; and a barrier layer is formed again, the barrier layer is etched to form a through hole, the low-resistance region, the P-type source region and the N-type source region are etched, metal is deposited, a second source electrode metal layer is formed, the barrier layer is removed, and preparation is completed.

A semiconductor device includes a first transistor adjacent to a second transistor and an etch stop layer within an interlayer dialectic (ILD) to separate a lateral contact and a plurality of backside source / drain region-gate cut dielectric layers. The lateral contact connects a via over a first source / drain region of the first transistor to a second source / drain region of the second transistor.

Provided is a semiconductor device including a two-dimensional semiconductor material. The semiconductor device includes a first channel including a first two-dimensional material layer, a second channel being apart from the first channel and including a second two-dimensional material layer, a common gate electrode between the first channel and the second channel, a first source electrode and a first drain electrode in contact with the first channel, and a second source electrode and a second drain electrode in contact with the second channel, wherein one of the first channel and the second channel is an N-type channel, and the other is a P-type channel, and the first channel and the second channel are U-shaped.

The invention belongs to the technical field of semiconductors, and provides a storage device, which comprises a substrate; the at least one memory device layer is arranged on the substrate, and the memory device layer at least comprises a memory unit, a write-in word line, a write-in bit line, a read word line and a read bit line; the storage unit comprises a write-in transistor and a read transistor; the write transistor comprises a first gate electrode, a first active layer, a first gate insulating layer and a first source electrode, and the first gate electrode is vertically arranged on the substrate; the reading transistor comprises a second gate electrode, a second active layer, a second gate insulating layer, a second source electrode and a second drain electrode, and the second active layer is vertically arranged on the substrate; the second gate electrode further comprises a horizontal extension part connected with the drain end of the first active layer; in the vertical direction, the write word line is located on the side, away from the horizontal extension part, of the first source electrode. The invention further provides a preparation method of the storage device. The space in the vertical direction and the space in the horizontal direction are effectively utilized, and the storage density can be improved.

Method for forming semiconductor device structure includes forming a sacrificial layer between first and second stacks of layers, the first stack of layers comprises first and second semiconductor layers alternatingly stacked, and the second stack of layers comprises third and fourth semiconductor layers alternatingly stacked, wherein the sacrificial layer comprises a semiconductor metal oxide, forming a sacrificial gate structure over portion of the second stack of layers, removing portions of the first and second stack of layers not covered by the sacrificial gate structure, removing the sacrificial layer to form cavity, filling the cavity with a dielectric to form an isolation layer, and forming first and second source / drain features on opposing sides of sacrificial gate structure, wherein the first source / drain feature is disposed below the second source / drain feature, and the first and second source / drain features are in contact with the isolation layer, first semiconductor layers, and third semiconductor layers.

The invention provides a semi-super junction side isolation planar gate silicon carbide VDMOS and a preparation method thereof, and the method comprises the steps: depositing metal on the lower side surface of a silicon carbide substrate, and forming a drain metal layer; performing epitaxial growth to obtain a first drift region; performing ion implantation to form a first source region; depositing to form a first insulating dielectric layer; epitaxially forming a second drift region, wherein the drift layer comprises a first drift region and a second drift region; performing ion implantation to form a second source region, wherein the P-type source region comprises a first source region and a second source region; depositing to form a second insulating medium layer, wherein the insulating medium region comprises the first insulating medium layer and the second insulating medium layer; forming a barrier layer again, and performing etching and ion implantation to form a column region, a P-type well region, a lug boss and an N-type source region; a barrier layer is formed again, and a gate dielectric layer is formed through etching and deposition; forming a barrier layer again, etching and depositing metal, and forming a gate metal layer and a source metal layer; the voltage endurance capability of the device is effectively improved, and the on-resistance of the device is reduced.

An SRAM cell includes a first inverter cross-coupled to a second inverter. The first inverter includes a first pull-up transistor and a first pull-down transistor, having coupled drains that define a first storage node. The SRAM cell further includes a first N-type pass-gate transistor having a first drain coupled to a write bit line, a first source coupled to the first storage node, and a first gate coupled to a first write word line. The SRAM cell further includes a first P-type pass-gate transistor having a second drain coupled to the write bit line and a second source coupled to the first storage node. The SRAM cell further includes a P-type transistor having a third drain, coupled to a second gate of the first P-type pass-gate transistor, a third source coupled to a second write word line, and a third gate coupled to an enable signal.

An electronic component. The electronic component includes a base; a first semiconductor device attached to the base and having: a first Gallium nitride (GaN)-based switch having a first gate, a first source and a first drain, the first gate arranged to control a current flow between the first source and the first drain; a second GaN-based switch having a second source, a second gate and a second drain, the second gate coupled to the first gate, and the second drain coupled to the first drain. In one aspect, the electronic component also includes a second semiconductor device attached to the base and having: a logic circuit coupled to the second source and arranged to detect a magnitude of the current flow; and a driver circuit coupled to the first and second gates, the driver circuit arranged to control on and off states of the first and second GaN-based switches.

Embodiments of the disclosure provide a semiconductor package including a first integrated circuit die having a first side and a second side opposite the first side, a first source / drain, a first interconnect structure disposed on the first side, a second interconnect structure disposed on the second side, and a first power rail extending between the first source / drain and the second interconnect structure. The package includes a second integrated circuit die disposed adjacent the first integrated circuit die, the second integrated circuit die having a first side and a second side, a second source / drain, a third interconnect structure disposed on the first side of the second integrated circuit die, a fourth interconnect structure disposed on the second side of the second integrated circuit die, and a second power rail extending between the second source / drain and the fourth interconnect structure, and an edge interconnect feature having a first end contacting the first interconnect structure and a second end contacting the third interconnect structure.

The utility model relates to the technical field of gallium nitride power devices, in particular to a double-channel enhanced GaN power device, which comprises a substrate, a nucleating layer, a buffer layer, a lower channel layer, a first barrier layer, an upper channel layer, a second barrier layer and an insulating medium layer which are sequentially arranged from bottom to top. The device further comprises a first source-drain electrode group, a second source-drain electrode group, a first grid electrode and a second grid electrode. The structure is provided with two channels, two source electrodes, two grid electrodes and two drain electrodes, the on-resistance of the channels is reduced by adding one conducting channel, and the ohmic contact resistance of the source electrodes is reduced by forming ohmic contact between the two source electrodes and the two channels respectively. The ohmic contact resistance of the drain electrodes is reduced by forming ohmic contact between the two drain electrodes and the two channels respectively, so that the on resistance of the whole device is reduced under the condition that the chip area is not increased, and finally the chip size and the chip cost are reduced. In addition, the design of the two grid electrodes can ensure the control capability of the grid electrodes on the two channels.

A semiconductor structure includes a device layer, which in turn includes a plurality of field effect transistors, each of which has a first source-drain region, a second source-drain region, at least one channel region coupling the first and second source-drain regions; and a gate surrounding the at least one channel region. The semiconductor structure further includes a front side wiring layer with wiring coupled to the plurality of field effect transistors at a front side of the device layer; a back side power rail at a back side of the device layer; and a back side gate via interconnecting the back side power rail to the gate of at least one of the plurality of field effect transistors.

The invention relates to a semiconductor structure and a manufacturing method thereof. The semiconductor structure comprises a substrate; the memory unit is arranged on the substrate, the memory unit comprises a transistor and a capacitor, the transistor comprises a first source / drain electrode, a grid electrode, a second source / drain electrode and a semiconductor layer surrounding the side wall of the grid electrode, the first source / drain electrode, the second source / drain electrode and the semiconductor layer are sequentially arranged in the first direction, and the first source / drain electrode and the second source / drain electrode are connected with the grid electrode through the semiconductor layer; the capacitor is arranged on one side of the second source / drain electrode and covers part of the side surface of the semiconductor layer; the bit line is arranged on one side of the first source / drain electrode and covers part of the side face of the semiconductor layer, the contact area of the bit line and the semiconductor layer is smaller than the contact area of the capacitor and the semiconductor layer, the contact area of the bit line and the transistor is reduced, and the opposite area of the bit line and the grid electrode of the transistor is reduced; therefore, the parasitic capacitance between the bit line and the grid electrode of the transistor is reduced, and the reading capability of the transistor is improved.

A device includes a fin on a substrate; a first transistor, including: a drain region and a first source region in the fin; and a first gate structure on the fin between the first source region and the drain region; a second transistor, including: the drain region and a second source region in the fin; and a second gate structure on the fin between the second source region and the drain region; a first resistor, including: the first source region and a first resistor region in the fin; and a third gate structure on the fin between the first source region and the first resistor region; and a second resistor, including: the second source region and a second resistor region in the fin; and a fourth gate structure on the fin between the second source region and the second resistor region.

The invention discloses an asymmetric hybrid multi-gate semiconductor device, a manufacturing method thereof and a chip, and belongs to the technical field of semiconductors. The asymmetric hybrid multi-gate semiconductor device comprises a substrate which comprises a first high-voltage well region, a drain region, a first drift region and a second drift region which are sequentially connected in the target direction are arranged in the first high-voltage well region, and the doping concentration of the second drift region is larger than that of the first drift region; a first source region and a second source region which are spaced in the target direction are arranged in the well region in the second drift region, the well region, close to one side of the first drift region, of the first source region forms a first channel region, and the well region at the bottom of the second source region forms a second channel region; a first gate structure covering the first channel region; the second gate structure is located in the first high-voltage well region and covers the second channel region. According to the invention, the overcurrent capability of the device can be improved, a small device area is maintained, and the integration level of the device is ensured.

A semiconductor device includes a substrate having a main surface and a back surface opposite to the main surface, a first FET group provided at the main surface and including a plurality of first source electrodes, a plurality of first drain electrodes, and a plurality of first gate electrodes, the plurality of first source electrodes, the plurality of first drain electrodes, and the plurality of first gate electrodes being aligned in a first direction, a second FET group provided at the main surface and including a plurality of second source electrodes, a plurality of second drain electrodes, and a plurality of second gate electrodes, the second FET group overlapping the first FET group as viewed in a second direction intersecting the first direction.

An integrated circuit includes a first nanostructure transistor including a plurality of first semiconductor nanostructures over a substrate and a source / drain region in contact with each of the first semiconductor nanostructures. The integrated circuit includes a second nanostructure transistor including a plurality of second semiconductor nanostructures and a second source / drain region in contact with one or more of the second semiconductor nanostructures but not in contact with one or more other second semiconductor nanostructures.

A semiconductor device fabrication method is provided and includes executing front-end-of-line (FEOL) processing to form first and second source / drain (S / D) epitaxy, forming a middle-of-line (MOL) contact to the first S / D epitaxy, executing a self-aligned backside S / D cut to form an opening in which respective sides of each of the first and second S / D epitaxy are exposed, depositing metallic material along the respective sides of each of the first and second S / D epitaxy in the opening and forming silicide from the metallic material whereby the silicide at the first S / D epitaxy contacts the MOL contact and the sides of the first S / D epitaxy.

An organic light emitting display device may include a first thin film transistor including a first active layer formed of a first material and includes a first source region, a first channel region, and a first drain region, a first gate electrode and a first source electrode and a first drain electrode, a second thin film transistor including a second active layer formed of a second material and includes a second source region, a second channel region, and a second drain region, a second gate electrode, and a second source electrode and a second drain electrode, a light blocking layer overlapping a lower portion of the second active layer and formed on the same layer as the second capacitor electrode, and a first protrusion pattern and a second protrusion pattern disposed on the same layer as the first gate electrode and overlapping the light blocking layer.

The invention discloses an LCD (Liquid Crystal Display) pixel driving circuit for color sequence display, which comprises a first transistor, a pre-storage capacitor, a second transistor, a holding capacitor, a third transistor and a liquid crystal capacitor, and is characterized in that a first source drain electrode of the first transistor is coupled to a data signal line, and a grid electrode is coupled to a control signal line; the second source and drain electrode is coupled to the first source and drain electrode of the second transistor and one end of the pre-storage capacitor; the grid electrode of the second transistor is coupled to the transfer signal line, and the second source-drain electrode is coupled to the first source-drain electrode of the third transistor, one end of the holding capacitor and one end of the liquid crystal capacitor; one ends, far away from the transistor, of the pre-storage capacitor, the holding capacitor and the liquid crystal capacitor are coupled to the first common electrode wire or the second common electrode wire; the grid electrode of the third transistor is coupled to the first reset signal line or the second reset signal line, and the second source drain electrode is coupled to the first common electrode line or the second common electrode line.

The present disclosure relates to a method. The method includes forming a plurality of first source / drain contacts and a second source / drain contact over a substrate. The second source / drain contact wraps around the plurality of first source / drain contacts. A plurality of gate structures are over the substrate. The plurality of gate structures are laterally between the plurality of first source / drain contacts and the second source / drain contact. An isolation region is formed within the substrate. The isolation region has one or more curved edges that face a curved outermost sidewall of the second source / drain contact. The one or more curved edges are separated from the curved outermost sidewall by a non-zero distance.

A method includes forming a first source / drain region and a second source / drain region in a semiconductor fin; depositing a first dielectric layer over the first source / drain region and the second source / drain region; etching an opening through the first dielectric layer, wherein etching the opening comprises etching the first dielectric layer; forming first sidewall spacers on sidewalls of the opening; and forming a gate stack in the opening, wherein the gate stack is disposed between the first sidewall spacers.

A mixer includes a mixing stage, and a first transistor and a second transistor coupled to the mixing stage. A gate of the first transistor is coupled to a first input of the mixer, and a gate of the second transistor is coupled to a second input of the mixer. The mixer also includes a first source resistor coupled to a source of the first transistor, and a second source resistor coupled to a source of the second transistor. The mixer further includes an amplifier having a first input coupled to the source of the first transistor, and a second input coupled to the source of the second transistor. The amplifier is configured to adjust at least one bias voltage of at least one of the first transistor and the second transistor based on a differential voltage between the first and second inputs of the amplifier.

An integrated circuit includes a complementary transistor, a first source / drain contact, a second source / drain contact, and an interconnect structure. The complementary transistor includes a first transistor having a first source / drain region and a second transistor having a second source / drain region. The second transistor is over the first transistor in the vertical direction. The second transistor is offset from the first transistor in a first direction perpendicular to the vertical direction. The first source / drain contact is electrically coupled to the first source / drain region, and the second source / drain contact is electrically coupled to the second source / drain region. The interconnect structure is electrically coupled to the first source / drain contact and the second source / drain contact, the interconnect structure including an inclined portion extending from the first source / drain contact to the second source / drain contact at an offset angle from a vertical direction. Some embodiments of the present disclosure are used for simplifying the process flow and reducing the cost.

The embodiment of the invention provides a driver cross-platform transplantation method and device, a storage medium and electronic device.The method comprises the steps that a set of first source driving blocks and a set of second source driving blocks corresponding to source driver codes of a source platform are obtained; the source driving program code is divided into a plurality of source driving blocks, a group of first source driving blocks are code blocks which do not allow direct cross-platform transplantation, and a group of second source driving blocks are code blocks which allow direct cross-platform transplantation; obtaining a transplantation rule table of each first source driving block in the group of first source driving blocks, and modifying each first source driving block according to the transplantation rule table of each first source driving block to obtain a group of modified first source driving blocks; and based on the modified group of first source driving blocks and the modified group of second source driving blocks, generating a target driving program code, and through the method and the device, the problem of low development efficiency of a computer driving program caused by manual transplantation in related technologies is solved.

Methods and apparatus for filtering a signal using a current mode filter circuit that enables source degradation. An example filter circuit generally includes an input node; an output node; a power supply node; a first transistor including a drain coupled with the input node; a second transistor including a drain coupled with the output node and including a gate coupled with a gate of the first transistor; a capacitive element coupled between a drain of the first transistor and the power supply node; a first resistive element coupled between the drain electrode and the gate electrode of the first transistor; a first source degeneration element coupled between a source of the first transistor and the power supply node; and a second source degeneration element coupled between a source of the second transistor and the power supply node.

A semiconductor structure is provided. The semiconductor structure includes a first plurality of nanostructures between a first source / drain feature and a second source / drain feature, a first gate segment surrounding the first plurality of nanostructures, and a wall structure abutting the first gate segment. A first nanostructure in the first plurality of nanostructures includes a bulk portion and a protrusion, and the protrusion protrudes from a first sidewall of the bulk portion toward the wall structure.

A semiconductor memory device including a plurality of semiconductor patterns extending in a first horizontal direction on a substrate and having a first source / drain region, a channel region, and a second source / drain region, at least one interlayer separation insulating layer that separates the plurality of semiconductor patterns from each other in a vertical direction, a plurality of word lines each surrounding the channel region, a bit line connected to the first source / drain region and extending in the vertical direction, a plurality of first electrodes each on one side of the second source / drain region, a plurality of second electrodes each positioned inside respective ones of the plurality of first electrodes, a ferroelectric film positioned between the first electrode and the second electrode, a plate line that contacts the plurality of second electrodes, and a leaker configured to transfer charge between the first electrode and the second electrode.