1672 results about "Second source" patented technology

An SRAM cell includes a first inverter cross-coupled to a second inverter. The first inverter includes a first pull-up transistor and a first pull-down transistor, having coupled drains that define a first storage node. The SRAM cell further includes a first N-type pass-gate transistor having a first drain coupled to a write bit line, a first source coupled to the first storage node, and a first gate coupled to a first write word line. The SRAM cell further includes a first P-type pass-gate transistor having a second drain coupled to the write bit line and a second source coupled to the first storage node. The SRAM cell further includes a P-type transistor having a third drain, coupled to a second gate of the first P-type pass-gate transistor, a third source coupled to a second write word line, and a third gate coupled to an enable signal.

A semiconductor structure is provided. The semiconductor structure includes a first plurality of nanostructures between a first source / drain feature and a second source / drain feature, a first gate segment surrounding the first plurality of nanostructures, and a wall structure abutting the first gate segment. A first nanostructure in the first plurality of nanostructures includes a bulk portion and a protrusion, and the protrusion protrudes from a first sidewall of the bulk portion toward the wall structure.

Current collapse of a normally-on type dual-gate bidirectional switch is suppressed. Dual-gate bidirectional switch includes first gate, first source, second gate, and second source. Control system includes first gate drive circuit, second gate drive circuit, and controller. Controller controls first gate drive circuit and second gate drive circuit. At the time of turning on dual-gate bidirectional switch and when the potential of first source is lower than the potential of second source, controller applies a first positive voltage for a first period between first gate and first source from first gate drive circuit, and applies a voltage smaller than the first positive voltage after the first period has elapsed.

The present disclosure provides a semiconductor device and a method of forming the same. The semiconductor device includes first nanostructures suspended above a first region of a substrate, first inner spacers interleaving the first nanostructures, a first gate structure wrapping around at least one of the first nanostructures, a first source / drain feature abutting the first nanostructures, second nanostructures suspended above a second region of the substrate, second inner spacers interleaving the second nanostructures, a second gate structure wrapping around at least one of the second nanostructures, and a second source / drain feature abutting the second nanostructures. The first and second regions of the substrate include different conductivity types. A thickness of the first inner spacers is smaller than a thickness of the second inner spacers.

The invention provides a vector instruction processing method, electronic equipment, a readable medium and a program product. The vector instruction processing method comprises the steps of obtaining a vector length of a vector instruction; when the vector length of the vector instruction is the first value and the effective indication of the second source operand is the first value, cancelling the transmission of the vector instruction, and setting the effective indication of the second source operand as a second value; a first value of the second source operation valid indication indicates that the old value of the destination register is not required as a valid indication of the second source operand, and a second value of the second source operation valid indication indicates that the old value of the destination register is required as a valid indication of the second source operand; under the condition that the destination register is ready, retransmitting the vector instruction; a first source operand and a second source operand are obtained based on the vector instruction, and the vector instruction is executed based on the first source operand and the second source operand, the second source operand being an old value of the destination register.

There are provided a semiconductor memory device and a manufacturing method of the same. The semiconductor memory device includes: a peripheral circuit structure with a page buffer group; a net-shaped first source pattern disposed on the peripheral circuit structure, the net-shaped first source pattern with a plurality of openings; a memory cell array disposed on the net-shaped first source pattern; a second source pattern disposed between the net-shaped first source pattern and the memory cell array; and a cell-array-side pad pattern, disposed between the net-shaped first source pattern and the second source pattern, extending toward the net-shaped first source pattern from the second source pattern, the cell-array-side pad pattern being bonded directly to the net-shaped first source pattern.

An integrated circuit (IC) device including fin-type active regions parallel to each other on a substrate, the fin-type active regions extending in a first lateral direction, a first nanosheet stack apart from a fin top surface of a first fin-type active region selected from the fin-type active regions, the first nanosheet stack including at least one nanosheet facing the fin top surface of the first fin-type active region, a gate structure surrounding the first nanosheet stack, the gate structure extending in a second lateral direction, a first source / drain region in contact with one sidewall of the first nanosheet stack, and a second source / drain region in contact with another sidewall of the first nanosheet stack, wherein a greatest width of the first source / drain region is less than a greatest width of the second source / drain region in the second lateral direction may be provided.

The present disclosure provides a three-dimensional DRAM array structure including L layers, M rows, and N columns of DRAM cell structures, each DRAM cell structure including first and second gate transistors having a tubular channel, disposed in a vertical direction and electrically connected in parallel, and a storage capacitor of a tubular structure disposed between the first and second gate transistors in the vertical direction, an inner electrode of the second transistor is connected to the first source / drain of the first and second gate-all-around transistors, and an outer electrode is connected to a source line; the M * N bit lines respectively extend in a tubular structure jointly formed by the first and second gate-all-around transistors and the storage capacitor in the M-row and N-column DRAM unit structure along the vertical direction, and are respectively connected to second source / drain electrodes of the first and second gate-all-around transistors; the L * M first word lines and the L * M second word lines extend in the first horizontal direction and are connected to grid electrodes of the first fence transistors and the second fence transistors in the L layers of DRAM unit structures respectively, and the M rows of DRAM unit structures are divided into M / s row groups.

A semiconductor structure includes an upper device stacked over a lower device. In an example, the upper device includes (i) a first source region, (ii) a first drain region, (iii) a body of semiconductor material extending laterally from the first source region to the first drain region, and (iv) a first gate structure at least in part wrapped around the body. In an example, the lower device includes (i) a second source region, (ii) a second drain region, and (iii) a second gate structure at least in part laterally between the second source region and the second drain region. In an example, the lower device lacks a body of semiconductor material extending laterally from the second source region to the second drain region. In another example, the upper device lacks a body of semiconductor material extending laterally from the first source region to the first drain region.

A semiconductor device includes a substrate insulating layer, a gate structure extending in a first direction on the substrate insulating layer, a plurality of channel layers spaced apart from each other in a second direction, the second direction perpendicular to an upper surface of the substrate insulating layer, the plurality of channel layers on the substrate insulating layer and surrounded by the gate structure, a first source / drain region and a second source / drain region, on both sides of the gate structure and connecting to the plurality of channel layers, a first spacer layer below the first source / drain region, and a second spacer layer below the second source / drain region, and a backside contact plug partially recessing a lower surface of the first source / drain region through the substrate insulating layer and the first spacer layer.

An integrated circuit includes a complimentary field effect transistor (CFET). The CFET includes a first transistor and a second transistor stacked vertically. A conductive via extends vertically from a first source / drain region of the first transistor past the second transistor. The second transistor includes an asymmetric second source / drain region. The asymmetry of the second source / drain region helps ensure that the second source / drain region does not contact the conductive via.

A semiconductor device includes a first transistor cell. The first transistor cell generates a first current signal and a second current signal indicating a bit of a physical unclonable function. The first transistor cell includes a first transistor, a second transistor and a third transistor. The first transistor outputs the first current signal. The second transistor generates the first current signal from a first source / drain structure of the second transistor, and generates the second current signal from a second source / drain structure of the second transistor. The third transistor outputs the second current signal. The first transistor, the second transistor and the third transistor are stacked in order along a first direction. The first source / drain structure of the second transistor and the second source / drain structure of the second transistor are arranged along a second direction different from the first direction.

Some embodiments include an integrated assembly having first and second pillars of semiconductor material. The first pillar includes a first source / drain region, and the second pillar includes a second source / drain region. First and second bottom electrodes are coupled with the first and second source / drain regions, respectively. The first and second source / drain regions are spaced from one another by an intervening region. First and second leaker-device-structures extend into the intervening region from the first and second bottom electrodes, respectively. Top-electrode-material extends into the intervening region and contacts the first and second leaker-device-structures. Ferroelectric-insulative-material is between the top-electrode-material and the bottom electrodes. Some embodiments include methods of forming integrated assemblies.

A method for manufacturing a semiconductor structure and a semiconductor structure are provided. The manufacturing method includes the following operations. A substrate is provided, and a first groove and a second groove are formed in the substrate, each of the first groove and the second groove having a depth in a first direction. The first groove includes multiple first sub-grooves arranged in the first direction, the second groove includes multiple second sub-grooves arranged in the first direction, and sidewalls of the first sub-grooves and sidewalls of the second sub-grooves are convex outwards. Word lines protruding away from the first groove each are formed at an interface of adjacent first sub-grooves. First source-drain layers formed on the sidewalls of the first sub-grooves, and second source-drain layers protruding away from the second groove each are formed at an interface of adjacent second sub-grooves.

A semiconductor structure is provided that includes a first FET device region including a plurality of first FETs, each first FET of the plurality of first FETs includes a first source / drain region located on each side of a functional gate structure. A second FET device region is stacked above the first FET device region and includes a plurality of second FETs, each second FET of the plurality of second FETs includes a second source / drain region located on each side of a functional gate structure. The structure further includes at least one first front side contact placeholder structure located adjacent to one of the first source / drain regions of at least one the first FETs, and at least one second front side contact placeholder structure located adjacent to at least one of the second source / drain regions of at one of the second FETs.

A semiconductor device may include a first memory cell array including a first source line, a first bit line, a first memory string, and first word lines; a second memory cell array including a second source line, a second bit line, a second memory string, and second word lines; a first interconnection structure including a first through via passing through the first memory cell array and commonly connected to the first bit line and the second bit line; a second interconnection structure including a second through via passing through the first memory cell array and commonly connected to the first word line and the second word line; a page buffer selectively accessing the first memory string or the second memory string through the first interconnection structure; and a row decoder commonly controlling the first word line and the second word line through the second interconnection structure.

A semiconductor structure according to the present disclosure includes a backside metal line, a backside dielectric layer over the backside metal line, a first source / drain feature and a second source / drain feature over the backside dielectric layer, a first backside contact extending through the backside dielectric layer to couple to a bottom surface of the first source / drain feature, a second backside contact extending through the backside dielectric layer to couple to a bottom surface of the second source / drain feature, a dielectric layer disposed over the backside dielectric layer, the first source / drain feature and the second source / drain feature, a common contact extending through the dielectric layer to electrically couple to the first source / drain feature and the second source / drain feature, an etch stop layer disposed over and interfacing the dielectric layer and the common contact. The common contact is not electrically coupled to any conductive feature that extends through the etch stop layer.

Provided are semiconductor devices and methods of fabricating the semiconductor device. The semiconductor device includes a channel, a first source / drain and a second source / drain being apart from each other in a first direction with the channel therebetween, a gate electrode surrounding the channel, an alternating-current wiring line configured to provide alternating current to the channel, and a first conductive contact connecting the alternating-current wiring line and the first source / drain to each other. A height difference from a first surface of the gate electrode facing the alternating-current wiring line to a first surface of the first source / drain in contact with the first conductive contact is less a height difference from a second surface of the gate electrode opposing the first surface of the gate electrode to a second surface of the first source / drain opposing the first surface of the first source / drain.

A semiconductor structure according to the present disclosure includes a backside metal line and a backside contact structure that includes a bar portion disposed on the backside metal line, a first via extending from the bar portion, a second via extending from the bar portion, and a protrusion disposed between the first via and the second via. The semiconductor structure also includes a first source / drain feature over the first via, a second source / drain feature over the second via, and a gate isolation feature disposed between the first via and the second via. The protrusion extends into the gate isolation feature.

A method and device according to the present disclosure includes a substrate that has a first transistor terminal such as a source feature and a second transistor terminal such as another source feature. Contact structures are formed on each source / drain feature. After forming the contact structures, a via opening is formed in dielectric materials above the contact structures, which is filled to form a non-linear via that extends from the contact on the first source feature to the contact on the second source feature. The non-linear via may include an outline in a top view of an undulating-shape having convex and / or concave portions.

A transistor comprising a first drain region split into first and second drain sub-regions aligned lengthwise and separated by a first low conductivity region, a first source region disposed on a first side of the first drain region split into first and second source sub-regions aligned lengthwise and separated by a second low conductivity region, a second source region disposed on a second side of the first drain region opposite the first side, the second source region split into third and fourth source sub-regions aligned lengthwise and separated by a third low conductivity region, a first gate electrode finger disposed over first and second active regions between the first drain region and first source region, and a second gate electrode finger disposed over third and fourth active regions between the first drain region and second source region.

The invention discloses a high-gain diamond logic phase inverter and a preparation method thereof, and aims to solve the problem that the voltage gain of an existing logic phase inverter is relatively small. According to the high-gain diamond logic inverter, a diamond substrate is subjected to hydrotreating through hydrogen plasma to form the diamond substrate with a hydrogen terminal, a conducting channel is formed after the surface of the hydrogen terminal is in contact with air, and a first source electrode, a first drain electrode, a second source electrode and a second drain electrode are arranged on the diamond substrate. A first ferroelectric medium layer and a second ferroelectric medium layer are deposited on a diamond substrate, a first grid electrode is arranged on the first ferroelectric medium layer, and a second grid electrode is arranged on the second ferroelectric medium layer. According to the invention, an electron beam evaporation process is adopted to form an orthorhombic phase on a ferroelectric material deposited at a low temperature, the ferroelectric material has convertible ferroelectric characteristics, and ultra-steep sub-threshold swing is realized; the surface conductivity can be regulated and controlled by treating the surface of the hydrogen terminal diamond through the oxygen plasma, current matching is achieved, and the logic inverter works in a deep subthreshold region.

A display device can include a display panel including first and second display areas, a plurality of substrates having different thickness, at least one metal layer on the plurality of substrates, a transistor over the metal layer, a passivation layer disposed on the transistor, a first planarization layer on the passivation layer, a second source-drain electrode pattern on the first planarization layer, a second planarization layer on the second source-drain electrode pattern, an anode electrode on the second planarization layer, a bank and a light emitting layer on the anode electrode, an encapsulation layer, and a touch sensor over the encapsulation layer. Also, a light receiving device is under the display panel and overlapped with the first display area, in which at least one of the passivation layer, the first planarization layer, and the second planarization layer in the second display area extends to the first display area.

In an embodiment, a semiconductor device may include a plurality of first nanostructures. The plurality of first nanostructures extend between first source / drain regions. The semiconductor device may also include a plurality of second nanostructures over the plurality of first nanostructures. The plurality of second nanostructures extend between second source / drain regions. The device may furthermore include a first gate stack around the plurality of first nanostructures. The device may in addition include a second gate stack over the first gate stack and disposed around the plurality of second nanostructures. The device may moreover include a vertical interconnect structure extending through the first and second gate stacks. The device may also include a frontside contact electrically coupled to a frontside of the vertical interconnect structure and a backside contact electrically coupled to a backside of the vertical interconnect structure.

A microelectronic device includes a first source and drain structure adjacent to a second source and drain structure. A first conductive contact is in contact with a top surface and side surface of the first source and drain structure. A second conductive contact is in contact with a top surface and side surface of the second source and drain structure. The second conductive contact includes a via extension to connect to a backside component. A separating layer is located between the first conductive contact and the second conductive contact. A first sidewall of the separating layer is flush with the first conductive contact. A second sidewall of the separating layer is flush with the second conductive contact.

A method for manufacturing a semiconductor structure includes forming first and second fins over a substrate. The fin includes first and second semiconductor layers alternating stacked. The method further includes forming a dummy gate structure over the first and second fins, forming first source / drain features on opposite sides of the dummy gate structures and over the first fin, forming second source / drain features on opposite sides of the dummy gate structures and over the second fin, forming a dielectric layer over and between the first and second source / drain features, replacing the dummy gate structure and the first semiconductor layers with a gate structure wrapping around the first semiconductor layers, forming first silicide features over the first source / drain features, and forming second silicide features over the second source / drain features.

Provided in the present disclosure are a preparation method for a semiconductor device, and a semiconductor device. The preparation method comprises: performing oxidization and deposition on a first surface of a first substrate to obtain a composite dielectric layer; performing metal thin film deposition on the composite dielectric layer to obtain a first metal layer; etching the first metal layer on a first top surface and the first metal layer on a second top surface, and exposing the composite dielectric layer, so as to obtain a first sidewall metal layer; performing metal thin film deposition on the first sidewall metal layer, the composite dielectric layer on the first top surface and the composite dielectric layer on the second top surface, so as to obtain a second metal layer; performing metal thin film deposition on the second metal layer to obtain a third metal layer; performing photolithography and etching on the third metal layer and the second metal layer to obtain a gate electrode; and performing doping on the first top surface adjacent to a second side surface of the gate electrode and the second top surface adjacent to a third side surface of the gate electrode, so as to respectively obtain a first source / drain region and a second source / drain region.

A MRAM circuit is provided in the present invention, wherein each memory cell includes a first transistor with a first gate, a first source and a first drain and the first gate is connected to a first word line, a second transistor with a second gate, a second source and a second drain and a second gate is connected to a second word line, and the second source and the second drain are connected respectively with the first source and the first drain, a first MTJ with one terminal connected to the first source and the second source and another terminal connected to a source line, and a second MTJ with one terminal connected to the first drain and the second drain and another terminal connected to a bit line.

A semiconductor device includes a nanosheet stack on a substrate. A first source / drain is on a first side of the nanosheet stack and a second source / drain is on an opposing side of the nanosheet stack. A backside contact includes a first contact end on a first end of the first source / drain and an opposing second contact end in electrical communication with a backside power distribution network. A frontside contact includes a first contact end on a first end of the second source / drain and an opposing second contact end in electrical communication with a backend of line (BEOL) interconnect. A placeholder extends from an opposing second end of the second source / drain.

A display device can include a substrate, a first light shielding layer disposed on the substrate, a second light shielding layer disposed on the first light shielding layer, an active layer disposed on the second light shielding layer and including a semiconductor region of a first transistor, a gate layer including a gate electrode of the first transistor disposed on the active layer, a first source metal layer including a first hold line disposed on the gate layer and configured to supply a hold signal, a second source metal layer including a second hold line disposed on the first source metal layer and connected to the first hold line, and a light emitting element including a pixel electrode disposed on the second source metal layer.