918 results about "Gate oxide" patented technology

The invention relates to the technical field of MOS (metal oxide semiconductor), and discloses a low-on-resistance SiC MOSFET (metal oxide semiconductor field effect transistor) terminal structure, which consists of a plurality of parallel MOS cells, and is characterized in that each MOS cell comprises a drain electrode, a semiconductor epitaxial layer, a source electrode, a grid electrode and a grid oxide layer, the semiconductor epitaxial layer sequentially comprises an N substrate layer, an N drift layer, a P well layer and an N well layer from bottom to top, P + layers are arranged on the two sides of the P well layer and the N well layer in a single MOS cell, a heavily doped N-layer is formed in the semiconductor epitaxial layer of the single MOS cell through ion implantation, and the heavily doped N-layer is located below the P well layer and is in contact with the P well layer. The heavily doped N-layer is additionally arranged below the P well layer to form a vertical low-resistance path, the uniformity of a grid electric field is destroyed in combination with the conduction P region, suppression of the grid on charge diffusion of a drain is weakened, the conduction resistance is greatly reduced compared with a traditional structure, and then the conduction current is greatly improved.

The invention provides a silicon carbide trench MOSFET device with a three-side trench structure and a preparation method thereof, and the method comprises the steps: growing a silicon carbide epitaxy on a silicon carbide substrate, and carrying out the injection to form a P-well region; forming a first barrier layer on the P-well region, and performing injection to form a P + region; removing the first barrier layer to form a second barrier layer, and performing injection to form an N + region; removing the second barrier layer, and simultaneously performing rapid thermal annealing on the P-well region, the P + region and the N + region; forming a third barrier layer, and etching to form a gate trench region; removing the third barrier layer, and performing dry-oxygen thermal oxidation to form a gate oxide layer; forming polycrystalline silicon by using chemical vapor deposition; after the polycrystalline silicon is doped, etching is carried out to form a grid electrode; and depositing metal to form a drain electrode and a source electrode, and performing rapid thermal annealing on the drain electrode and the source electrode to form ohmic contact. By arranging the three-side groove structure, the area of the channel is increased, and conduction resistance is reduced.

The invention relates to the technical field of MOS (metal oxide semiconductor), and discloses an MOSFET (metal oxide semiconductor field effect transistor) structure with a nanosheet full-surrounding grid electrode and a manufacturing process thereof, the MOSFET structure comprises a plurality of MOS cells which are arranged in parallel, each MOS cell comprises a drain electrode, a semiconductor epitaxial layer, a grid electrode, a grid oxide layer and a source electrode, the semiconductor epitaxial layer comprises an N substrate layer, an N drift layer, an N well layer, a P + layer and a P well layer, the grid electrode comprises a grid electrode covering layer and a grid electrode nanosheet; a plurality of grid nanosheets are arranged in a single MOS cell, are distributed in a horizontal matrix, extend to the inside of the grid covering layer and are in direct contact with the grid covering layer. Through the three-dimensional embedded contact between the nanosheet grids in horizontal matrix distribution and the high-conductivity covering layer, the static control capability of the channel is remarkably enhanced, the grid resistance is reduced, higher current driving density and better switching characteristics are realized, and the physical limitation of a traditional planar device is broken through.

The invention discloses a semiconductor device which comprises a cellular structure, and the cellular structure comprises an N + substrate, an N-drift layer and a functional area. The N-drift layer is located on the N + substrate; the functional region is embedded into one side, away from the N + substrate, of the N-drift layer, the functional region comprises two subunits and a second N + source region, and each subunit comprises a P + contact region, a P-type body region, a first N + source region and a first trench gate structure; the first N + source region is located on the P-type body region, the first groove is located between the P-type body region and the P + contact region, the first gate oxide layer covers the inner wall of the first groove, a first filling groove is formed in the inner wall of the first gate oxide layer, the first gate is filled in the first filling groove, and the P + shielding region of the P + contact region covers the bottom of the first gate oxide layer; and a second N + source region is arranged between the first trench gate structures of the two subunits. According to the device, the effective utilization rate of a channel can be improved, the specific on-resistance is further reduced, and the problem of long reverse recovery time is solved.

The invention provides a preparation method of a gate oxide layer and a gate, and the method comprises the steps: carrying out the rapid thermal annealing treatment of a silicon-based substrate in a nitrogen-containing gas atmosphere, which belongs to a non-destructive nitrogen doping mode, and carrying out the nitrogen pre-doping on the surface of the silicon-based substrate, so as to reduce the doping amount needed by the subsequent plasma nitrogen doping; therefore, the damage of the plasma nitrogen doping process to the SiON gate oxide layer is reduced, and the interface defect between the SiON gate oxide layer and the silicon-based substrate interface is reduced. Besides, after the nitrogen pre-doped layer is formed, the thermal oxidation process is carried out on the silicon-based substrate to form the silicon dioxide gate oxide layer, so that the damage to the SiON gate oxide layer film is reduced, and the interface defect between the SiON gate oxide layer and the silicon-based substrate interface is further reduced; moreover, the laser rapid annealing treatment can remove the intrinsic oxide layer on the surface of the SiON gate oxide layer, repair the damage to the crystal lattice of the SiON gate oxide layer caused by the plasma nitrogen doping treatment process, improve the film quality and repair the interface.

A LDMOS including a semiconductor substrate, a gate oxide, a gate, field plate oxide layers and field plate barrier layers is disclosed. A first field plate oxide layer and a second field plate oxide layer are positioned atop the gate oxide with a spacing between them. A first field plate barrier layer and a second field plate barrier layer are positioned atop the first and the second field plate oxide layers, respectively. A third field plate barrier layer is positioned atop the first and the second field plate barrier layers and the spacing. A third field plate oxide layer is positioned atop the third field plate barrier layer. The third field plate oxide layer includes a first portion positioned atop the first field plate oxide layer and a second portion positioned atop the spacing. A fourth field plate barrier layer is positioned atop the third field plate oxide layer.

The invention provides a manufacturing method of a sigma trench, which comprises the following steps: providing a substrate, forming a gate oxide layer and a gate structure on the substrate, the gate structure comprising a gate, a first mask layer and a second mask layer which are sequentially formed on the gate oxide layer; etching for the first time by taking the second mask layer as a mask until the second mask layer is removed, forming a first groove in the substrate on two sides of the gate structure, and gathering polymers generated by etching the second mask layer in the etching process on the gate oxide layer on the side wall of the first groove and a junction area of the gate oxide layer, the gate and the substrate as an etching protection layer; and performing second etching by taking the first mask layer as a mask, protecting the substrate covered by the etching protection layer from lateral etching by the etching protection layer, and forming a sigma-like groove in the first groove. According to the method, the etching protection layer is formed on the side wall of the first groove through the polymer generated by the second mask layer in the first etching process, the area is prevented from being excessively etched, serious lateral pushing of the area is avoided, and therefore the shape of the groove can be adjusted and controlled more easily.

The invention provides a power device and a preparation method thereof. The preparation method comprises the following steps: forming a P-type layer and an N-type layer on an N-type substrate; forming a groove; performing ion implantation to form an N-type source region; forming a gate oxide layer in the groove; forming a first polycrystalline silicon layer, a thick oxide layer and a second polycrystalline silicon layer in the groove; depositing a dielectric layer; forming a source contact region, wherein the source contact region exposes a part of the N-type source region and a part of the P-type layer; forming an insulating layer; forming a gate contact region, wherein the gate contact region extends into the first polycrystalline silicon layer; forming a drain contact region, wherein the N-type layer is exposed out of the drain contact region; and forming a source electrode, a grid electrode and a drain electrode, wherein the source electrode is simultaneously contacted with the N-type source region and the P-type epitaxial layer. According to the invention, the source electrode, the grid electrode and the drain electrode can be attached to the heat dissipation substrate at the same time, so that the heat dissipation path is greatly optimized, and the access inductance of the source electrode is reduced; the connection of the P-type layer and the N-type source region is formed in the device through the groove, so that the process can be effectively simplified, an additional lead-out process is avoided, and the manufacturing cost is effectively saved.

A method for forming a semiconductor structure and a semiconductor structure, the method comprising: providing a substrate including a high-voltage gate oxide region and high-voltage source and drain regions, the high-voltage source and drain regions being located at two sides of the high-voltage gate oxide region, and a shallow trench isolation structure between the high-voltage gate oxide region and the high-voltage source and drain regions; forming an isolating membrane on the surface of the preset region of the substrate, wherein the isolating membrane exposes the high-voltage gate oxide region; forming a first photoresist layer on the surface of the high-voltage gate oxide region, wherein the first photoresist layer exposes an edge region adjacent to the shallow trench isolation structure in the high-voltage gate oxide region; etching the exposed edge region in the high-voltage gate oxide region by taking the isolating film and the first photoresist layer as masks so as to reduce the height of the surface of the edge region of the high-voltage gate oxide region; and removing the first photoresist layer to expose the high-voltage gate oxide region, and forming a high-voltage device gate oxide layer on the high-voltage gate oxide region. The performance of the high-voltage device can be optimized, and the reliability of the high-voltage device is improved.

The invention relates to the technical field of MOS semiconductors, and discloses a SiC MOSFET structure with a second-order oxide layer and a preparation technology thereof.The SiC MOSFET structure comprises a plurality of MOS cells arranged in parallel, each MOS cell comprises a drain electrode, a semiconductor epitaxial layer, a grid electrode, a source electrode and a grid oxide layer, each semiconductor epitaxial layer comprises an N substrate layer, an N drift layer, a P + layer, a P well layer and an N well layer, an N-doped layer is formed in the N drift layer of the single MOS cell through ion implantation, and the N-doped layer is located under the grid electrode; and a plurality of N + doped isolation layers which are not in contact with each other are formed in the N-doped layer through ion implantation. By introducing the N-doped layer right below the grid electrode and the doped N + isolation layers arranged and distributed in the N-doped layer, the distribution of an electric field below the gate oxide is effectively modulated, and the peak of the electric field is inhibited, so that the breakdown voltage of the device is remarkably improved, the reliability of the gate oxide layer is enhanced, and meanwhile, relatively low specific on-resistance is kept.

The invention provides a preparation method of a semiconductor device, and the method comprises the steps: providing a substrate which comprises a high-voltage region, a source-drain region and an isolation region; forming a silicon nitride layer to cover the substrate, and etching to remove at least a part of thickness of the silicon nitride layer on the isolation region; etching to remove partial thickness of the silicon nitride layer on the high-voltage region, wherein the silicon nitride layer on the high-voltage region and the silicon nitride layer on the source-drain region have a height difference after etching; etching the substrate by taking the silicon nitride layer as a mask so as to form an isolation groove in the isolation region, synchronously etching and removing the silicon nitride layer on the high-voltage region, enabling the high-voltage region and the source-drain region to have a height difference after etching, and enabling the top edge of the high-voltage region to be arc-shaped; a first oxide layer is formed to fill the isolation groove and cover the high-voltage region, the surface of the first oxide layer is flat, and the first oxide layer on the high-voltage region serves as a gate oxide layer. The problem of foot warping at the edge of the high-voltage area can be solved, and the preparation cost is not additionally increased.

The invention provides a gate-source short-circuit SiC MOS device failure analysis method and related equipment, and the method comprises the steps: responding to the determination that the functional characteristics of a source and a drain have no abnormal conditions, carrying out the analysis of the cause of a short-circuit fault of a gate and the source based on the characteristics of a silicon carbide material and an MOS device failure mechanism, and carrying out the analysis of the short-circuit fault of the gate and the source. Comprising the following steps: judging whether gate source chemical lap joint caused by internal water vapor exists or not through a dry chip; unsealing the chip to expose the interior of the chip, testing the chip, and judging whether a metallization layer migration short circuit caused by high temperature occurs or not; analyzing whether breakdown caused by high electric field stress exists in the gate oxide layer; according to the failure analysis method provided by the invention, the reason of the failure of the SiC MOS device can be accurately analyzed, and the problem that the microdefect of the SiC MOS device cannot be positioned by a traditional means is solved.

The invention discloses a SiC MOSFET (Metal-Oxide-Semiconductor Field Effect Transistor) device structure for optimizing switching characteristics and a preparation method thereof, and provides a silicon carbide MOSFET device for reducing reverse output capacitance Crss, increasing input capacitance Ciss and increasing output capacitance Coss to improve Crosstalk voltage spike and a preparation method thereof. By introducing the composite gate oxide structure, the high-K material passivation layer and the P + structure at the bottom of the P-WELL into the planar silicon carbide MOSFET device, the reverse output capacitance Crss can be effectively reduced, the input capacitance Ciss can be increased, the output capacitance Coss can be increased, and finally, the Vgs voltage peak in the Crosstalk turn-off process can be effectively improved, and the performance of the device is improved. The breakdown and burnout of the device caused by overhigh voltage in the on-off process of the device are prevented, and the service life of the device is prolonged. Besides, the device structure and the preparation method are simple, and the effect is remarkable, so that high-performance and batch preparation and production can be realized, and the device has huge market potential and wide application prospects.

The invention discloses a structure for improving the gate oxide reliability of a silicon carbide MOSFET (Metal-Oxide-Semiconductor Field Effect Transistor) and a manufacturing method. The structure comprises an N-drift region, and an interconnection metal layer is deposited on the top surface of the N-drift region; performing ion implantation in the middle of the top end of the N-drift region to form a P well; an N + source region is formed in the P well in an injection mode, the two sides and the bottom face of the N + source region make contact with the P well, the N + source region comprises a heavily-doped region and a lightly-doped region, and the heavily-doped region is located in the middle close to the P well and makes contact with the interconnection metal layer; and depositing a gate oxide layer and an isolation oxide layer on two sides of the top surfaces of the N-drift region and the P well, wherein the bottom surface of the gate oxide layer is in contact with the top surface of the N-drift region. According to the invention, the step injection structure is introduced into the N + source region, and the N + source region is divided into the heavily doped region and the lightly doped region, so that the problem of overlapping of the N + source region and the grid electrode is fundamentally solved by reducing the contact resistance through the heavily doped region and relieving the electric field concentration through the lightly doped region, and high requirements for photoetching alignment are not required.

The invention provides a trench MOSFET and a manufacturing method thereof, and the method comprises the steps: forming a trench, a shield gate oxide layer, a control gate oxide layer, an isolation oxide layer, a shield gate, a control gate, a body region, a source region, and a dielectric layer; a first contact hole penetrating through the dielectric layer and the source region and extending into the body region and a second contact hole penetrating through the dielectric layer, the control gate and the isolation oxide layer and exposing the shield gate are formed, a subsequently formed source metal layer is electrically connected with the source region and the body region through the first contact hole, and a gate metal layer is electrically connected with the control gate and the shield gate through the second contact hole. When the trench MOSFET provided by the invention is in forward conduction, because the shield grid is connected to the control grid, an electron accumulation layer is formed on the side wall of the shield grid, so that the conduction resistance is reduced. Besides, in the manufacturing process of the trench MOSFET, the number of photomasks can be reduced, for example, only three photomasks corresponding to the trench, the contact hole and the metal layer respectively are needed, and the production cost can be reduced.

According to the preparation method of the semiconductor structure and the semiconductor structure provided by the invention, the longitudinal space of a chip is fully utilized, and a gate dielectric layer, an active layer and a first source-drain layer are sequentially formed on a shallow trench isolation structure in a substrate, so that a longitudinally arranged high-voltage gate oxide layer MOS (Metal Oxide Semiconductor) tube is formed; therefore, the transverse area of the high-voltage gate oxide layer MOS tube is reduced, and the integration level of a chip where the high-voltage gate oxide layer MOS tube is located is improved. As the high-voltage gate oxide MOS tube is positioned above the shallow trench isolation structure in the substrate and is positioned on a different horizontal plane from the first MOS tube positioned in the substrate in the chip, the interference of the high-voltage gate oxide MOS tube on the adjacent first MOS tube is reduced. Therefore, an isolation structure does not need to be arranged between the high-voltage gate oxide layer MOS tube and the adjacent first MOS tube, the horizontal distance between the high-voltage gate oxide layer MOS tube and the adjacent first MOS tube is reduced, the overall area of a chip is reduced, the integration degree of the chip is further improved, and the preparation cost of the chip is reduced.

The invention provides a semiconductor device and a manufacturing method thereof, and the method comprises the steps: providing a substrate, sequentially forming a gate oxide layer and a mask material layer on the substrate, etching the mask material layer to form a mask layer, and enabling the mask layer to be located in a region where a gate is preset to be formed; a furnace tube annealing process is carried out, so that the top angle of the edge of the gate oxide layer right below the mask layer upwards lifts the mask layer, and the bottom angle downwards consumes the substrate, and then the gate oxide layer right below the mask layer is in a shape with a thick edge and a thin middle part. Wherein the edge of the gate oxide layer is an area aligned with the edge of the mask layer; and removing the mask layer. The electric field intensity at the edge of the grid electrode is reduced by increasing the thickness of the edge of the grid oxide layer, so that the leakage current of the grid-induced drain electrode is reduced, the performance of the device is improved, and the thickness of the middle of the grid oxide layer can meet the requirement of the device so as to ensure the grid control capability.

The invention provides a silicon carbide MOSFET (Metal-Oxide-Semiconductor Field Effect Transistor) integrated with an SCR (Selective Catalytic Reduction) and a manufacturing method thereof, and relates to the technical field of power semiconductor devices, the device is integrated with a PNPN four-layer structure consisting of a P + region, an N-type epitaxial layer, a P-type body region and an N + source region between a grid electrode and a source electrode, and the P + region is in metal ohmic contact with the source electrode. Through collaborative design of the distance and the doping concentration of the P + region and the N + source region, the forward and reverse trigger voltage thresholds of the PNPN structure can be accurately matched with the asymmetric driving window of the electric control main drive. The structure is arranged on the outer edge of a cellular area or a terminal area, and is electrically isolated from an active area, a field plate is arranged to suppress false triggering, ohmic contact is optimized to accelerate turn-off, and it is ensured that holding current is higher than parasitic latch triggering current, so that rapid and reliable discharge and self-protection of bidirectional surge between a gate and a source are achieved on the premise that the performance of a main device is not affected, and the reliability of the device is improved. And the gate oxide reliability is obviously improved.

The embodiment of the invention provides a field effect transistor and a preparation method thereof. The field effect transistor comprises an epitaxial layer, wherein one side of the epitaxial layer is provided with a gate oxide lower region; the oxide layer is arranged on the gate oxide lower region; the polycrystalline silicon layer is arranged on one side, deviating from the epitaxial layer, of the oxide layer; the first source region and the second source region are respectively arranged on two sides of the gate oxide lower region along the first direction; the well region is arranged on the outer sides of the first source region and the second source region, and the upper surfaces, close to the oxide layer, of the first source region and the second source region are exposed out of the well region; the first buffer layer is arranged in the epitaxial layer, the first buffer layer is arranged on the side, away from the oxide layer, of the well region, and the first buffer layer extends in the first direction; wherein the doping type of the epitaxial layer, the first source region and the second source region is a first doping type, the doping type of the first buffer layer and the well region is a second doping type, and the doping concentration of the first buffer layer is different from the doping concentration of the well region.

An improved silicon carbide (SiC) planar MOSFET having at least one buried P-shield (BPS) region including one center portion and two side portions for the gate oxide electric field and saturation current reductions is disclosed. Two saturation current pitching (SCP) structures formed in two Junction Field Effect Transistor (JFET) regions sandwiched between the side portions and the center portion of the BPS region limit a saturation current of the device in a forward conduction stage for the short-circuit capability improvement. Moreover, a Junction barrier Schottky diode (JBSD) is integrated with the SiC MOSFET in a location between the two adjacent split gate electrodes for the reverse conduction switching loss reduction.

The invention discloses a semiconductor device and a preparation method thereof. The semiconductor device comprises a groove which extends into an epitaxial layer along a first surface, and the first surface is the surface of one side, away from a substrate, of the epitaxial layer; the source region is located in the epitaxial layer on the two sides of the groove, and the source region is a region formed by carrying out ion implantation on part of the first surface; the grid electrode is located in the groove, the grid electrode comprises a first part and a second part which are distributed in the first direction, in the second direction, the maximum width of the first part is smaller than that of the second part, the bottom of the grid electrode is an arc face protruding towards the substrate, the first direction is the direction, away from the substrate, of the groove, and the second direction is perpendicular to the extending direction of the groove. According to the invention, the problems of low reliability of the gate oxide layer and non-uniform electric field distribution caused by electric field concentration of the semiconductor device in the related technology are solved.

A method for fabricating a semiconductor device includes the steps of first providing a substrate comprising an one time programmable (OTP) device region, forming a shallow trench isolation (STI) in the substrate, removing part of the STI to form a first step on a corner of the substrate, forming a first gate oxide layer on the substrate, removing the first gate oxide layer to form a second step on the corner of the substrate, forming a second gate oxide layer on the substrate, and then forming a first gate structure on the substrate and the STI.

The application discloses an integrated super-junction power MOS device with corrugated gate oxide and a preparation method thereof, and belongs to the technical field of semiconductors. The device comprises a substrate, a buffer layer and an epitaxial layer which are sequentially stacked from bottom to top; wherein the epitaxial layer is provided with a plurality of vertically spaced super-junction columns, and the top of each super-junction column is provided with a body region; the surface layer of the body region is provided with a contact hole doped region and a source doped region which are in contact with each other; the upper surface of the epitaxial layer is further provided with a gate oxide layer; the gate oxide layer is in a corrugated structure, and the lower surface of the gate oxide layer is adapted to and contacts with a corrugated groove located on the upper surface of the epitaxial layer, the body region and part of the source doped region; the upper surface of the gate oxide layer and part of the source doped region is covered with a polysilicon layer, and the gate oxide layer and the polysilicon layer form a corrugated gate structure. The integrated super-junction power MOS device with corrugated gate oxide has good single-particle burnout resistance and single-particle gate penetration resistance.

This invention provides a radio frequency (RF) switch circuit and module. The RF switch circuit includes a first resistor and stacked switching units. Each stacked switching unit comprises multiple stages of stacked field-effect transistor (FET) circuits connected in series. Each stage of the stacked FET circuit includes a FET, a second resistor, and a bootstrap unit, which includes one or two bootstrap circuits. The bootstrap unit in each stage of the stacked FET circuit is used to raise the gate voltage of the corresponding FET during electrostatic discharge (ESD) to assist in turning on the FET and allowing the ESD current to be discharged through the path formed by the FET. This invention can prevent gate oxide breakdown or thermal damage caused by localized overheating of the FET acting as a switch during an ESD event in the RF switch circuit, thereby improving the stability of the RF switch circuit.

The invention discloses an IGBT device, a preparation method and a preparation system thereof, and a storage medium. The device comprises a substrate; the second groove region and the first groove region are formed in the substrate; the semi-insulating material layer is formed in the first groove region and the second groove region; a CS layer, a Pwell layer and an NSD layer; a contact hole penetrating from top to bottom; the contact hole is filled with a metal contact layer. According to the invention, the first groove region and the second groove region are formed on the side wall of the first HM layer, gate oxidation, polysilicon filling and the second HM layer are carried out in sequence, ion implantation and annealing are carried out, and the gate oxide layer between the grooves is used as a barrier mask to realize etching of the contact hole. The method is suitable for forming the contact hole under the condition that the cellular mesa is small, photoetching sleeve deviation between the contact hole and the groove can be effectively avoided, so that the in-chip consistency of saturation voltage drop is greatly improved, and meanwhile, a wider upper opening can be formed so as to be beneficial to further reducing the conduction voltage drop of a device.

The invention discloses a groove SiC MOSFET device and a preparation method thereof. The preparation method comprises the following steps: epitaxial growth; performing P-type ion implantation for the first time; performing first-stage groove etching; performing N-type ion implantation; implanting P-type ions for the second time; carrying out second-stage groove etching; growing gate oxide, polycrystalline silicon and an interlayer insulating layer; carrying out metal deposition; the beneficial effects of the invention are that the multi-stage trench structure is combined with the plane gate and the trench gate, so that the channel density is increased, the current capability is provided, and the conduction loss is reduced; the MPS diode structure is integrated, the forward voltage drop of the body diode is reduced, the discharge capacity is improved when inrush current occurs in the circuit, the reverse follow current capacity can be improved through the parallel Schottky diode structure, and electronic elements needed by a peripheral circuit are reduced; by integrating the built-in field plate structure, the electric field concentration effect at the bottom of the trench gate is effectively relieved.

The embodiment of the present disclosure relates to the semiconductor field, and provides a semiconductor structure and a manufacturing method thereof, which comprises: a substrate comprising an array region and a peripheral circuit active region, wherein the peripheral circuit active region comprises at least a first PMOS region and a second PMOS region, the gate oxide layer thickness of the PMOS tube formed in the first PMOS region is less than that of the PMOS tube formed in the second PMOS region; a first insulating layer covering the bottom and sidewall of the first PMOS region towards the substrate, and the top of the first insulating layer is flush with the top of the substrate; a dielectric layer covering the first insulating layer, and the top of the dielectric layer in the first PMOS region is lower than the top of the substrate; a second insulating layer covering the dielectric layer, and the top of the second insulating layer in the first PMOS region is flush with the top of the substrate; and a pad layer covering the top of the substrate in the first PMOS region, so as to improve the defect problem between the isolation structure of the first PMOS region in the peripheral circuit active region and the top of the substrate.

The invention provides a semiconductor device and a preparation method thereof, and the semiconductor device comprises a substrate which comprises a substrate and an epitaxial layer, and the epitaxial layer is located at one side of the substrate; the multiple source region structures are located in the epitaxial layer, and the surfaces of the sides, away from the substrate, of the source region structures are located in the surface of the side, away from the substrate, of the epitaxial layer; the gate structure is located in the epitaxial layer, the source region structures are located on the two sides of the gate structure in the first direction, the gate structure comprises a gate oxide layer and a gate, the gate oxide layer makes contact with the substrate, one part of the gate oxide layer is located between the gate and the epitaxial layer, and the other part of the gate oxide layer is located between the gate and the source region structures; the first length of the gate oxide layer located at the bottom of the gate is larger than or equal to the second length of the gate oxide layer located between the gate and the source region structure, the first length is the length of the gate oxide layer in the thickness direction of the substrate, the second length is the length of the gate oxide layer in the first direction, and the first direction is perpendicular to the thickness direction of the substrate; the problem of low reliability of a semiconductor device in the prior art is solved.

The present application relates to the technical field of MOS semiconductor, and discloses a MOSFET structure with gate nanosheet and a manufacturing process thereof, which comprises a plurality of mutually parallel MOS cells, a single MOS cell comprising a drain, a semiconductor epitaxial layer, a gate, a gate oxide layer and a source, the semiconductor epitaxial layer comprising an N substrate layer, an N drift layer, an N well layer, a P+ layer and a P well layer, and the gate comprising a gate cover layer and a gate nanosheet; the gate nanosheet in a single MOS cell has a plurality of gate nanosheets, and the plurality of gate nanosheets are horizontally matrix distributed, and the gate nanosheet extends to the inside of the gate cover layer and directly contacts with the gate cover layer. The present application realizes higher current driving density and better switching characteristics by the three-dimensional embedded contact of the horizontally matrix distributed nanosheet gate and the high-conductivity cover layer, significantly enhances the channel electrostatic control ability, and reduces the gate resistance, thereby breaking through the physical limitation of the traditional planar device.

The invention provides a groove type silicon carbide MOSFET device structure. The device structure comprises a silicon carbide substrate of a first doping type; a first doping type silicon carbide epitaxial layer on the upper surface of the silicon carbide substrate; the groove protection regions of the second doping type are arranged in the silicon carbide epitaxial layer in an array mode in the first direction, the tops of the groove protection regions are discontinuous in the second direction, and the first direction is perpendicular to the second direction; the body regions are arranged in an array in the first direction, are arranged between two adjacent groove protection regions, and extend in the second direction; the source regions are arranged in an array in the first direction, are arranged in the body region, and are discontinuous in the second direction; the one or two gate trenches are arranged between two adjacent trench protection regions, the gate trenches penetrate through the body region, gate oxide layers and polycrystalline silicon are arranged in the gate trenches, and the upper surface of the polycrystalline silicon is lower than the upper surface of the silicon carbide substrate; the interlayer dielectric layer extends along a second direction; and a front metal layer.