474 results about "Gate oxide" patented technology

The invention discloses a semiconductor device which comprises a cellular structure, and the cellular structure comprises an N + substrate, an N-drift layer and a functional area. The N-drift layer is located on the N + substrate; the functional region is embedded into one side, away from the N + substrate, of the N-drift layer, the functional region comprises two subunits and a second N + source region, and each subunit comprises a P + contact region, a P-type body region, a first N + source region and a first trench gate structure; the first N + source region is located on the P-type body region, the first groove is located between the P-type body region and the P + contact region, the first gate oxide layer covers the inner wall of the first groove, a first filling groove is formed in the inner wall of the first gate oxide layer, the first gate is filled in the first filling groove, and the P + shielding region of the P + contact region covers the bottom of the first gate oxide layer; and a second N + source region is arranged between the first trench gate structures of the two subunits. According to the device, the effective utilization rate of a channel can be improved, the specific on-resistance is further reduced, and the problem of long reverse recovery time is solved.

The invention provides a preparation method of a gate oxide layer and a gate, and the method comprises the steps: carrying out the rapid thermal annealing treatment of a silicon-based substrate in a nitrogen-containing gas atmosphere, which belongs to a non-destructive nitrogen doping mode, and carrying out the nitrogen pre-doping on the surface of the silicon-based substrate, so as to reduce the doping amount needed by the subsequent plasma nitrogen doping; therefore, the damage of the plasma nitrogen doping process to the SiON gate oxide layer is reduced, and the interface defect between the SiON gate oxide layer and the silicon-based substrate interface is reduced. Besides, after the nitrogen pre-doped layer is formed, the thermal oxidation process is carried out on the silicon-based substrate to form the silicon dioxide gate oxide layer, so that the damage to the SiON gate oxide layer film is reduced, and the interface defect between the SiON gate oxide layer and the silicon-based substrate interface is further reduced; moreover, the laser rapid annealing treatment can remove the intrinsic oxide layer on the surface of the SiON gate oxide layer, repair the damage to the crystal lattice of the SiON gate oxide layer caused by the plasma nitrogen doping treatment process, improve the film quality and repair the interface.

The invention provides a manufacturing method of a sigma trench, which comprises the following steps: providing a substrate, forming a gate oxide layer and a gate structure on the substrate, the gate structure comprising a gate, a first mask layer and a second mask layer which are sequentially formed on the gate oxide layer; etching for the first time by taking the second mask layer as a mask until the second mask layer is removed, forming a first groove in the substrate on two sides of the gate structure, and gathering polymers generated by etching the second mask layer in the etching process on the gate oxide layer on the side wall of the first groove and a junction area of the gate oxide layer, the gate and the substrate as an etching protection layer; and performing second etching by taking the first mask layer as a mask, protecting the substrate covered by the etching protection layer from lateral etching by the etching protection layer, and forming a sigma-like groove in the first groove. According to the method, the etching protection layer is formed on the side wall of the first groove through the polymer generated by the second mask layer in the first etching process, the area is prevented from being excessively etched, serious lateral pushing of the area is avoided, and therefore the shape of the groove can be adjusted and controlled more easily.

The invention provides a semiconductor device and a manufacturing method thereof, and the method comprises the steps: providing a substrate, sequentially forming a gate oxide layer and a mask material layer on the substrate, etching the mask material layer to form a mask layer, and enabling the mask layer to be located in a region where a gate is preset to be formed; a furnace tube annealing process is carried out, so that the top angle of the edge of the gate oxide layer right below the mask layer upwards lifts the mask layer, and the bottom angle downwards consumes the substrate, and then the gate oxide layer right below the mask layer is in a shape with a thick edge and a thin middle part. Wherein the edge of the gate oxide layer is an area aligned with the edge of the mask layer; and removing the mask layer. The electric field intensity at the edge of the grid electrode is reduced by increasing the thickness of the edge of the grid oxide layer, so that the leakage current of the grid-induced drain electrode is reduced, the performance of the device is improved, and the thickness of the middle of the grid oxide layer can meet the requirement of the device so as to ensure the grid control capability.

The invention provides a silicon carbide MOSFET (Metal-Oxide-Semiconductor Field Effect Transistor) integrated with an SCR (Selective Catalytic Reduction) and a manufacturing method thereof, and relates to the technical field of power semiconductor devices, the device is integrated with a PNPN four-layer structure consisting of a P + region, an N-type epitaxial layer, a P-type body region and an N + source region between a grid electrode and a source electrode, and the P + region is in metal ohmic contact with the source electrode. Through collaborative design of the distance and the doping concentration of the P + region and the N + source region, the forward and reverse trigger voltage thresholds of the PNPN structure can be accurately matched with the asymmetric driving window of the electric control main drive. The structure is arranged on the outer edge of a cellular area or a terminal area, and is electrically isolated from an active area, a field plate is arranged to suppress false triggering, ohmic contact is optimized to accelerate turn-off, and it is ensured that holding current is higher than parasitic latch triggering current, so that rapid and reliable discharge and self-protection of bidirectional surge between a gate and a source are achieved on the premise that the performance of a main device is not affected, and the reliability of the device is improved. And the gate oxide reliability is obviously improved.

The invention discloses a semiconductor device and a preparation method thereof. The semiconductor device comprises a groove which extends into an epitaxial layer along a first surface, and the first surface is the surface of one side, away from a substrate, of the epitaxial layer; the source region is located in the epitaxial layer on the two sides of the groove, and the source region is a region formed by carrying out ion implantation on part of the first surface; the grid electrode is located in the groove, the grid electrode comprises a first part and a second part which are distributed in the first direction, in the second direction, the maximum width of the first part is smaller than that of the second part, the bottom of the grid electrode is an arc face protruding towards the substrate, the first direction is the direction, away from the substrate, of the groove, and the second direction is perpendicular to the extending direction of the groove. According to the invention, the problems of low reliability of the gate oxide layer and non-uniform electric field distribution caused by electric field concentration of the semiconductor device in the related technology are solved.

A method for fabricating a semiconductor device includes the steps of first providing a substrate comprising an one time programmable (OTP) device region, forming a shallow trench isolation (STI) in the substrate, removing part of the STI to form a first step on a corner of the substrate, forming a first gate oxide layer on the substrate, removing the first gate oxide layer to form a second step on the corner of the substrate, forming a second gate oxide layer on the substrate, and then forming a first gate structure on the substrate and the STI.

This invention provides a radio frequency (RF) switch circuit and module. The RF switch circuit includes a first resistor and stacked switching units. Each stacked switching unit comprises multiple stages of stacked field-effect transistor (FET) circuits connected in series. Each stage of the stacked FET circuit includes a FET, a second resistor, and a bootstrap unit, which includes one or two bootstrap circuits. The bootstrap unit in each stage of the stacked FET circuit is used to raise the gate voltage of the corresponding FET during electrostatic discharge (ESD) to assist in turning on the FET and allowing the ESD current to be discharged through the path formed by the FET. This invention can prevent gate oxide breakdown or thermal damage caused by localized overheating of the FET acting as a switch during an ESD event in the RF switch circuit, thereby improving the stability of the RF switch circuit.

The embodiment of the present disclosure relates to the semiconductor field, and provides a semiconductor structure and a manufacturing method thereof, which comprises: a substrate comprising an array region and a peripheral circuit active region, wherein the peripheral circuit active region comprises at least a first PMOS region and a second PMOS region, the gate oxide layer thickness of the PMOS tube formed in the first PMOS region is less than that of the PMOS tube formed in the second PMOS region; a first insulating layer covering the bottom and sidewall of the first PMOS region towards the substrate, and the top of the first insulating layer is flush with the top of the substrate; a dielectric layer covering the first insulating layer, and the top of the dielectric layer in the first PMOS region is lower than the top of the substrate; a second insulating layer covering the dielectric layer, and the top of the second insulating layer in the first PMOS region is flush with the top of the substrate; and a pad layer covering the top of the substrate in the first PMOS region, so as to improve the defect problem between the isolation structure of the first PMOS region in the peripheral circuit active region and the top of the substrate.

The invention provides a semiconductor device and a preparation method thereof, and the semiconductor device comprises a substrate which comprises a substrate and an epitaxial layer, and the epitaxial layer is located at one side of the substrate; the multiple source region structures are located in the epitaxial layer, and the surfaces of the sides, away from the substrate, of the source region structures are located in the surface of the side, away from the substrate, of the epitaxial layer; the gate structure is located in the epitaxial layer, the source region structures are located on the two sides of the gate structure in the first direction, the gate structure comprises a gate oxide layer and a gate, the gate oxide layer makes contact with the substrate, one part of the gate oxide layer is located between the gate and the epitaxial layer, and the other part of the gate oxide layer is located between the gate and the source region structures; the first length of the gate oxide layer located at the bottom of the gate is larger than or equal to the second length of the gate oxide layer located between the gate and the source region structure, the first length is the length of the gate oxide layer in the thickness direction of the substrate, the second length is the length of the gate oxide layer in the first direction, and the first direction is perpendicular to the thickness direction of the substrate; the problem of low reliability of a semiconductor device in the prior art is solved.

The present application relates to the technical field of MOS semiconductor, and discloses a MOSFET structure with gate nanosheet and a manufacturing process thereof, which comprises a plurality of mutually parallel MOS cells, a single MOS cell comprising a drain, a semiconductor epitaxial layer, a gate, a gate oxide layer and a source, the semiconductor epitaxial layer comprising an N substrate layer, an N drift layer, an N well layer, a P+ layer and a P well layer, and the gate comprising a gate cover layer and a gate nanosheet; the gate nanosheet in a single MOS cell has a plurality of gate nanosheets, and the plurality of gate nanosheets are horizontally matrix distributed, and the gate nanosheet extends to the inside of the gate cover layer and directly contacts with the gate cover layer. The present application realizes higher current driving density and better switching characteristics by the three-dimensional embedded contact of the horizontally matrix distributed nanosheet gate and the high-conductivity cover layer, significantly enhances the channel electrostatic control ability, and reduces the gate resistance, thereby breaking through the physical limitation of the traditional planar device.

The invention provides a groove type silicon carbide MOSFET device structure. The device structure comprises a silicon carbide substrate of a first doping type; a first doping type silicon carbide epitaxial layer on the upper surface of the silicon carbide substrate; the groove protection regions of the second doping type are arranged in the silicon carbide epitaxial layer in an array mode in the first direction, the tops of the groove protection regions are discontinuous in the second direction, and the first direction is perpendicular to the second direction; the body regions are arranged in an array in the first direction, are arranged between two adjacent groove protection regions, and extend in the second direction; the source regions are arranged in an array in the first direction, are arranged in the body region, and are discontinuous in the second direction; the one or two gate trenches are arranged between two adjacent trench protection regions, the gate trenches penetrate through the body region, gate oxide layers and polycrystalline silicon are arranged in the gate trenches, and the upper surface of the polycrystalline silicon is lower than the upper surface of the silicon carbide substrate; the interlayer dielectric layer extends along a second direction; and a front metal layer.

This invention provides a method for fabricating a dummy gate process in a semiconductor chip, comprising: providing a substrate in which a plurality of shallow trench isolation structures are formed; forming an ONO layer on the surface of the substrate with the shallow trench isolation structures; forming photoresist at the position of the dummy gate pattern corresponding to the shallow trench isolation structure; wet etching to remove the top silicon oxide layer in the ONO layer not covering the photoresist; after removing the photoresist, wet etching to remove the silicon nitride layer and silicon oxide layer in the ONO layer; forming a gate oxide layer; forming a dummy gate pattern on the surface of the substrate with the gate oxide layer; forming a sidewall layer on the surface of the dummy gate pattern; etching the substrate on both sides of the dummy gate pattern and forming source / drain regions using epitaxy; filling the source / drain regions with an intermediate dielectric layer, and then removing the dummy gate pattern. This invention avoids device failure caused by device short circuits, thereby improving device reliability.

The present disclosure provides a trench gate semiconductor device and a manufacturing method therefor. Compared with the related art in which a gate oxide layer is formed by oxidizing a first epitaxial layer, in the embodiments of the present disclosure, the gate oxide layer is formed by oxidizing a prefabricated epitaxial layer, so as to address the problem of high roughness of trench sidewalls caused by the etching process during the forming the trench by means of etching on the first epitaxial layer, thereby reducing the influence of surface roughness scattering of the trench on channel mobility. Further, a shielding layer is arranged between the gate oxide layer on the outer bottom wall of the trench and the first epitaxial layer, so as to reduce the peak electric field at the bottom corners of the trench, thereby improving the breakdown voltage.

The invention relates to a silicon carbide multi-channel longitudinal groove type MOSFET (Metal-Oxide-Semiconductor Field Effect Transistor) and a manufacturing method thereof, and belongs to the technical field of silicon carbide semiconductors. The device comprises a substrate, a drift region arranged on the substrate and a plurality of grooves arranged in the drift region, wherein the plurality of grooves are periodically arranged along the transverse direction; the groove extends along a direction vertical to the surface of the substrate; gate oxide layers and gates located on the gate oxide layers are arranged on the two sides in the trenches respectively, channel regions are formed between the adjacent trenches and at the bottoms of the trenches in the drift region, source regions and body contact regions are formed in the channel regions, intermetallic dielectric layers are formed between the surfaces of the gates and the source regions, top-layer source metal is formed on the source regions, and bottom-layer source metal is formed on the body contact regions. And an ohmic contact layer is formed between the source electrode region and the top layer source electrode metal. According to the device disclosed by the invention, the inverted conduction channels are simultaneously formed in the side walls and the bottoms of the grooves, so that conduction current flows in parallel in the longitudinal and transverse directions, and the number of the effective conduction channels is remarkably increased.

The invention relates to a defect detection method and device, defect detection equipment, a storage medium and a product. The method comprises the steps of obtaining a first threshold voltage of a to-be-detected MOSFET, obtaining a second threshold voltage of the to-be-detected MOSFET under the condition that the duration of applying a target gate-source voltage to a gate-source electrode of the to-be-detected MOSFET is a first preset duration, and determining a defect detection result of a gate oxide layer of the to-be-detected MOSFET based on a difference value between the first threshold voltage and the second threshold voltage, the target gate source voltage is used for exciting defects of a gate oxide layer of the MOSFET to be detected. And more comprehensive and accurate defect detection on macroscopic defects and microscopic defects is realized.

The invention provides a field stop layer preparation method, a process monitoring method and a semiconductor device preparation method, and belongs to the technical field of semiconductor power devices. Comprising a gate oxide layer located on the upper surface of the epitaxial layer, a polycrystalline silicon layer located on the upper surface of the gate oxide layer, a body region located in the epitaxial layer and a first injection region located in the body region; gluing the front surface of the wafer prefabricated member, turning over the wafer prefabricated member with the front surface protection glue, and thinning the back surface of the wafer prefabricated member; performing ion implantation on the back surface of the wafer prefabricated member by adopting a front surface implantation machine to form a field stop layer; and turning over again, and removing the front protection glue. The method has the beneficial effects that the field stop layer is formed by utilizing a front injection machine in the front-section process, so that production line pollution is avoided, and the manufacturing process of the field stop layer is more favorably realized; the problem that the back injection machine table of a wafer factory is limited is solved, no extra machine table needs to be purchased, the utilization rate of the machine table is improved, and cost is reduced.

The invention provides a manufacturing method of a field effect transistor, the field effect transistor and a layout structure, and the transistor enables a shielding grid and a grid electrode to be separately placed, enables the shielding grid to be in uniform contact with source electrode metal, facilitates the timely response to state conversion, and avoids the local breakdown of a device. And the oxide layer is thinned at the top end of the shield gate, and injection of reverse recovery charges is reduced during reverse recovery. By adjusting the position of the shield gate and reducing the thickness of the shield gate oxide layer, the Eas capability of the device is effectively improved, the reverse recovery time of the transistor is shortened, the reverse recovery capability of the transistor is improved, and the reliability is improved.

The present disclosure provides a trench gate semiconductor device and a preparation method thereof. The trench gate semiconductor device comprises a substrate, a drift region and a body region. The drift region is arranged on the surface of the substrate and has a first conductivity type. The body region is epitaxially formed on the surface of the drift region away from the substrate and is an in-situ doped region with a second conductivity type. In the embodiment of the present disclosure, the body region is directly epitaxially formed, which can reduce the lattice damage in the body region, thereby reducing the interface defects between the body region and the gate oxide layer, and further improving the channel mobility. In addition, the tailing effect of the channel caused by ion implantation can be avoided, thereby improving the threshold voltage stability.

The application provides a simple gate oxide integrity testing device, which comprises a test sample and a test structure; the test sample comprises a substrate, a dielectric layer (gate oxide layer) on the substrate, a gate replacement layer used for replacing a gate layer or being located above the gate layer, so that the test sample forms a three-layer structure comprising the substrate-dielectric layer-gate replacement layer, and the gate oxide integrity of the dielectric layer is tested by combining a thermal desorption technology; the test structure is used for accommodating the test sample, providing a test temperature, and recording released elements; the application also provides a simple gate oxide integrity testing method, which has the technical effects of low cost, simple operation, and rapid feedback of test results, and does not need to prepare a transistor device, adopts the gate replacement layer arranged on the substrate-dielectric layer (gate oxide layer) to combine the thermal desorption technology, and directly tests the stacked layer material contained in a MOS stacked layer structure.

The application provides a semiconductor structure and a preparation method thereof. The preparation method of the semiconductor structure comprises the following steps: providing a substrate, a surface of the substrate is formed with an epitaxial layer, and a groove is formed on a side of the epitaxial layer away from the substrate; a first gate oxide layer is formed through a thermal oxidation process, the first gate oxide layer covers at least a sidewall of the groove; a second gate oxide layer is formed through a chemical vapor deposition process, the second gate oxide layer fills a bottom of the groove and covers a surface of the first gate oxide layer away from the epitaxial layer, the first gate oxide layer and the second gate oxide layer jointly form a gate oxide structure, and a thickness of the gate oxide structure at the bottom of the groove is greater than or equal to a thickness of the gate oxide structure on the sidewall of the groove. The preparation method of the semiconductor structure is beneficial to improving the breakdown voltage and the gate oxide reliability of a semiconductor device.

The invention discloses a silicon carbide metal oxide semiconductor field effect transistor and a manufacturing method thereof. The silicon carbide metal oxide semiconductor field effect transistor comprises a silicon carbide substrate, a grid electrode oxidation layer located on the silicon carbide substrate, an isolation oxidation layer located on the grid electrode oxidation layer, two grid electrodes located on the grid electrode oxidation layer on the two sides of the isolation oxidation layer respectively, wherein the two grid electrodes are respectively provided with an extending part which extends inwards to the isolation oxidation layer, two source electrodes are respectively arranged in the silicon carbide substrate at two sides of the grid electrode oxidation layer, and a drain electrode contact metal is arranged on the other surface of the silicon carbide substrate relative to the grid electrode oxidation layer.

The present application belongs to the technical field of semiconductor, and particularly relates to a trench gate SiC MOSFET and a preparation method thereof. The preparation method of the trench gate SiC MOSFET forms a relatively thick N-type doping layer below the groove bottom of the gate groove. In the subsequent gate oxide process, the relatively thick N-type doping layer generates more electrons, which accelerates the oxidation of SiC. After the gate oxide process, the thickness of the gate oxide formed at the bottom of the gate groove is obviously thicker than that at the channel sidewall position. The relatively thick gate oxide enhances the tolerance of the device to high voltage, and reduces Qgd (the charge amount of the gate-drain), thereby improving the switching speed of the device.

The application provides a neuron-like transistor device, which comprises a substrate, a buried oxygen layer and a channel layer which are sequentially stacked on the substrate, a gate oxide layer and a gate electrode on the channel layer, and a source electrode and a drain electrode which are respectively located on both sides of the channel layer. The gate electrode is used for applying a front gate voltage as an input signal, the drain electrode is used for applying a constant input current, the voltage of the drain electrode is used as an output signal, and the input signal is changed in a step-by-step manner from small to large. The neuron nonlinear activation of a single device is realized, and it is possible to build a complete and programmable artificial neuron by using a single or few transistors. The neuron-like transistor device has a simple structure, and a manufacturing process which is suitable for a CMOS manufacturing process. The measurement method of the neuron-like transistor device is simple, and an electrode does not need to be additionally introduced, so that the simulation of the neuron characteristics can be realized without additional device design, the integration density of the transistors in a chip is improved, and the neuron-like transistor device is suitable for the integration of a large-scale circuit.

MOS junction barrier Schottky diode relates to the technical field of power semiconductor device. N-type substrate, N-type epitaxial layer, deep P region, slot gate, slot gate oxide layer, conductive enhancement region and isolation oxide layer are arranged between cathode metal and anode metal, the lower surface of the N-type substrate is in contact with the cathode metal, the upper surface is in contact with the lower surface of the N-type epitaxial layer, the upper surface of the N-type epitaxial layer is in contact with the P region, the conductive enhancement region is arranged on the outer surface of the slot gate oxide layer and is in contact with the N-type epitaxial layer, part of the slot gate oxide layer, the conductive enhancement region, the isolation oxide layer and part of the deep P region are respectively in contact with part of the anode metal. The MOS junction barrier Schottky diode structure of the application improves the carrier density at the channel, reduces the channel resistance, and further improves the reverse leakage current characteristics and the forward voltage drop by inserting a slot gate MOS structure in the adjacent P region of the traditional junction barrier Schottky (JBS) diode.

The invention provides a semiconductor device and a manufacturing method thereof, and the method comprises the steps: providing a substrate, and sequentially forming a gate oxide material layer, a gate material layer and a patterned hard mask layer; performing first dry etching by taking the patterned hard mask layer as a mask, and forming a footing at the bottom of the gate material layer; performing wet cleaning for the first time; performing second dry etching to form a grid electrode and a grid oxide layer; and carrying out second-time wet cleaning. According to the invention, the footing is formed at the bottom of the gate material layer during the first dry etching, the gate oxide material layer below is protected, the cross section width of the gate oxide material layer is greater than the preset cross section width of the gate, and then the gate oxide material layer is laterally excavated during the first wet cleaning. The section width of the gate oxide material layer after side digging is still greater than the preset grid section width, and the second wet cleaning is subsequently carried out, so that the side digging problem of the gate oxide layer can be improved, the influence on the subsequent process is avoided, and the performance of the semiconductor device is improved.

The invention relates to a complementary metal oxide semiconductor device and a repair circuit. The CMOS device comprises a substrate and a heating electrode arranged on a first surface of the substrate, wherein the heating electrode is used for heating the CMOS device under the condition that a heating power supply is connected; the insulating layer is formed on the second surface of the substrate; the self-repairing function layer is formed on the insulating layer; the self-repairing function layer is used for carrying out damage self-repairing under the condition that the CMOS device is heated; the gate oxide layer is formed on the self-repairing functional layer; the metal electrode layer is formed on the gate oxide layer; and a source electrode and a drain electrode in the metal electrode layer are respectively connected to the self-repairing functional layer in a mode of penetrating through the gate oxide layer. When the CMOS device is heated, the self-repairing functional layer can perform self-repairing on the damage of the microstructure, so that the damage of the microstructure in the self-repairing functional layer is greatly reduced, the CMOS device is recovered to an available state, the service life of the CMOS device is prolonged, and the cost of a circuit applying the CMOS device is reduced.

The invention discloses a preparation method of a silicon carbide trench gate type MOSFET (Metal-Oxide-Semiconductor Field Effect Transistor) power device. The preparation method comprises six steps of substrate buffer layer deposition, gate oxide layer preparation, trench etching, gate metal layer deposition, source and drain region ion implantation and source and drain metal layer deposition and annealing. In the preparation process, a multi-physics field coupling dynamic thermal resistance model, a multi-working-condition thermal reliability boundary algorithm, a full-working-area variable temperature parameter fitting model and a power device multi-parameter calibration platform are integrated, technological parameters of all steps are set through model calculation and algorithm analysis, and key performance parameters of the device are detected in real time and dynamically adjusted by means of the calibration platform. According to the method, the problems of non-uniform heat distribution, stress concentration, insufficient parameter fitting and calibration deficiency in traditional preparation are solved, the interface bonding quality of the buffer layer and the metal layer and the electrical property consistency of the device are improved, the thermal reliability and the working efficiency of the device are enhanced, and the application requirement of a high-voltage high-power power electronic system for a core device is met.

The invention provides an SONOS (Silicon Oxide Nitride Oxide Semiconductor) memory and an array memory unit, which comprise a selection tube gate oxide positioned on the surface of a well region, selection gate polycrystalline silicon positioned on the surface of the selection tube gate oxide, memory tube polycrystalline silicon positioned on two sides of the selection gate polycrystalline silicon, a side wall covering part of the memory tube polycrystalline silicon, and a gate electrode positioned on the surface of the selection gate polycrystalline silicon, wherein the memory tube polycrystalline silicon and the selection gate polycrystalline silicon are separated by an ONO (Oxide-Nitride-Oxide) layer; the side wall is located on the side, opposite to the selection gate polycrystalline silicon, of the storage tube polycrystalline silicon, the side wall covers the surface of the well region, an LDD region is formed in the well region below the side wall, a first source-drain injection region and a second source-drain injection region are formed in the well region, the first source-drain injection region is adjacent to the LDD region on one side of the selection gate polycrystalline silicon, and the second source-drain injection region is adjacent to the LDD region on one side of the selection gate polycrystalline silicon. The second source-drain injection region is adjacent to the LDD region on the other side of the selection gate polycrystalline silicon, the first source-drain injection region and the second source-drain injection region are both located on the side, opposite to the storage tube polycrystalline silicon, of the side wall, and the storage tube polycrystalline silicon on the two sides of the selection gate polycrystalline silicon are electrically communicated.

Provided is an electrochemical memory device including a channel layer extending in a vertical direction, the channel layer including a semiconductor oxide, a gate electrode surrounding at least a portion of a side surface of the channel layer, a reservoir layer between the channel layer and the gate electrode, and a gate oxide layer between the gate electrode and the reservoir layer, and wherein the channel layer includes a first channel layer and a second channel layer, the second channel layer spaced farther apart from the gate electrode than the first channel layer, and an oxygen dissociation energy of the first channel layer may be lower than an oxygen dissociation energy of the second channel layer.