1274 results about "Gate oxide" patented technology

The invention discloses a SiC MOSFET (Metal-Oxide-Semiconductor Field Effect Transistor) device with a high-mobility gate oxide layer and a preparation process of the SiC MOSFET device, and belongs to the technical field of semiconductors. Comprising a drain electrode, a semiconductor epitaxial layer, a source electrode and a grid electrode; the semiconductor epitaxial layer comprises an N substrate layer, an N drift layer, a P + layer, an N well layer and a P well layer, and a lightly doped N layer is arranged in the middle of the N drift layer of each MOS cell; by optimizing the gate oxide layer preparation process and combining the design of the T-shaped P-layer, the semi-elliptical lightly doped N-type half layer and the like in the device, the interface quality of the gate oxide layer and a semiconductor material is effectively improved, the scattering of a carrier by an interface state is reduced, and meanwhile, due to the synergistic effect of the structures such as the quarter-circle-shaped side symmetric P-layer and the square heavily doped N layer, the performance of the device is improved. The internal electric field distribution and the carrier transmission path of the device are optimized, and the channel carrier mobility is remarkably improved.

The disclosure relates to a π type trench gate silicon carbide MOSFET device and a fabrication method thereof. To protect a trench gate oxide layer without increasing a channel resistance and process complexity, a second conductivity type of heavily doped deep well inserted with double gate trenches along the sidewalls of deep well is designed. The deep well is connected to the source metal directly. The electric potential is clamped to the source during the voltage blocking and turn-off state, which reduces the electric field in the gate oxide and reduces the miller capacitance. An interlayer dielectric layer is deposited above the conductive dielectric polysilicon layers and extends outward separately to cover a part of the source region. A smaller cell pitch can be achieved by controlling the spacing between the first and the second trench gate, thereby increasing the channel density and reducing the channel resistance.

The invention relates to the technical field of MOS (Metal Oxide Semiconductor) semiconductors, and discloses a double-gate structure for a high-performance MOSFET (Metal Oxide Semiconductor Field Effect Transistor) and an optimization method, the double-gate structure comprises a plurality of MOS cells, and each MOS cell comprises a drain electrode, a source electrode, a gate electrode, a gate oxide layer and a semiconductor epitaxial layer; the semiconductor epitaxial layer comprises an N substrate layer, an N diffusion layer, a P-layer, a P well layer and an N well layer, two grid electrodes are arranged in a single MOS cell and are respectively positioned on the left side and the right side in a grid oxide layer, and the section outline of the grid oxide layer is semicircular; polycrystalline silicon is arranged in the gate oxide layer and located between the two grid electrodes, and the polycrystalline silicon is in ohmic contact with the source electrode. Through the double-gate structure, geometric shape optimization, doping layer design and process innovation, the switching speed, the voltage endurance capability, the thermal stability and the integration degree of the MOSFET are remarkably improved, meanwhile, the leakage current and the on-resistance are reduced, and the MOSFET is suitable for high-performance power devices and high-frequency application scenes.

The invention relates to the technical field of MOS (metal oxide semiconductor), and discloses a VDMOSFET (vertical double-diffused metal oxide semiconductor field effect transistor) device with low threshold voltage, which comprises a drain electrode, a semiconductor epitaxial layer, a source electrode, a grid electrode and a grid oxide layer covering the surface of the grid electrode, and is characterized in that an N substrate layer, an N drift layer, an N well layer, a P well layer and a heavily doped P layer are formed in the semiconductor epitaxial layer through ion implantation, the grid electrode comprises a triangular grid electrode and a rectangular grid electrode, the grid oxide layer covering the surface of the triangular grid electrode is in contact with the N substrate layer, and the N drift layer is divided into a left part and a right part by the grid oxide layer. According to the invention, the grid electrode is designed to further comprise the triangular grid electrode, the electric field effect of the grid electrode between the tip part of the triangular grid electrode and the drain electrode is better, but the grid oxide layer wrapped by the triangular grid electrode at the tip part is thicker, so that charges flowing out of the drain electrode gather towards the inside of the heavily doped N layer more quickly along the grid oxide layer; at the moment, more charge flow can be provided in a smaller grid voltage environment.

The invention relates to the technical field of MOS semiconductors, and discloses a vertical D-MOSFET with trench isolation and an improved channel structure and a preparation method, the vertical D-MOSFET comprises a plurality of MOS cells which are parallel to one another, each MOS cell comprises a drain electrode, a source electrode, a grid electrode, a grid oxide layer and a semiconductor epitaxial layer, the semiconductor epitaxial layer comprises an N substrate layer, an N diffusion layer, a P + layer, a P well layer and an N well layer, the profile of the cross section of the grid electrode is triangular, and a polycrystalline silicon covering layer is deposited at the junction of the grid electrode and the gate oxide layer; the profile of the cross section of the gate oxide layer is in a semi-elliptical shape, and the profile of the cross section of the polycrystalline silicon covering layer is in a triangular shape. The section profile of the grid electrode is designed to be triangular, the grid oxide layer is controlled to be in a semi-oval shape, electric field distribution and a carrier migration path are optimized, the triangular grid electrode can reduce electric field concentration at the edge of the grid electrode, and the breakdown risk is reduced.

The invention relates to the technical field of MOS (metal oxide semiconductor), and discloses a low-on-resistance SiC MOSFET (metal oxide semiconductor field effect transistor) terminal structure, which consists of a plurality of parallel MOS cells, and is characterized in that each MOS cell comprises a drain electrode, a semiconductor epitaxial layer, a source electrode, a grid electrode and a grid oxide layer, the semiconductor epitaxial layer sequentially comprises an N substrate layer, an N drift layer, a P well layer and an N well layer from bottom to top, P + layers are arranged on the two sides of the P well layer and the N well layer in a single MOS cell, a heavily doped N-layer is formed in the semiconductor epitaxial layer of the single MOS cell through ion implantation, and the heavily doped N-layer is located below the P well layer and is in contact with the P well layer. The heavily doped N-layer is additionally arranged below the P well layer to form a vertical low-resistance path, the uniformity of a grid electric field is destroyed in combination with the conduction P region, suppression of the grid on charge diffusion of a drain is weakened, the conduction resistance is greatly reduced compared with a traditional structure, and then the conduction current is greatly improved.

An improved silicon carbide (SiC) super junction (SJ) MOSFET having at least two buried P-shield (BPS) regions facing each other for gate oxide electric-field and saturation current reductions is disclosed. The two BPS regions are spaced apart from a body region and formed either adjoining sidewalls or below a bottom of a P column region. Moreover, a saturation current pitching (SCP) structure formed in a Junction Field Effect Transistor (JFET) region sandwiched between the two BPS regions limits saturation current of the device in a forward conduction stage for the short-circuit capability improvement.

The invention relates to a silicon carbide super-junction transverse MOS device and a manufacturing method thereof, and belongs to the technical field of semiconductor devices. The device sequentially comprises a substrate and an epitaxial layer from bottom to top, a p column region is arranged on the outer side of the epitaxial layer, a drain region is arranged on the outer side of the p column region, a p well region is arranged on the inner side of the epitaxial layer, a source region is arranged on the inner side of the p well region, a p + region is arranged on the outer side of the p well region, a groove is formed in the middle of the epitaxial layer, and a gate oxide layer is arranged in the groove. A gate polycrystalline silicon is arranged in the gate oxide layer, source electrode metal is arranged on the upper sides of the source electrode region and the p + region, drain electrode metal is arranged on the upper side of the drain electrode region, a dielectric layer is arranged between the source electrode metal and the drain electrode metal, and top layer metal is arranged at the tops of the source electrode metal and the drain electrode metal. According to the invention, the doping concentration of the drift region can be improved while the withstand voltage of the device is ensured, and higher withstand voltage and lower on resistance of the device are realized.

The invention relates to the technical field of MOS (Metal Oxide Semiconductor) semiconductors, and discloses a SiC VDMOSFET (Vertical Double-diffused Metal Oxide Semiconductor Field Effect Transistor) structure with high heat dissipation performance, which comprises a plurality of MOS cells arranged in parallel, and is characterized in that each MOS cell comprises a metal drain electrode, a semiconductor epitaxial layer, a metal source electrode and a gate oxide layer covering the surface of the metal source electrode, performing ion implantation in the semiconductor epitaxial layer to form an N substrate layer, an N drift layer, an N well layer, a heavily doped P layer and a P well layer; source electrode doping layers are arranged on the two sides of a single MOS cell, the source electrode doping layers are in ohmic contact with the metal source electrodes, and the source electrode doping layers are made of gallium arsenide or gallium nitride or nichrome. According to the invention, the source electrode doping layer with the sinking design is arranged above the MOS cell, so that the N well layer can be in direct contact with the metal source electrode, and the N well layer can be in indirect contact with the metal source electrode through the source electrode doping layer, thereby reducing the ohmic resistance of the N well layer and the metal source electrode, and reducing the heating at the contact position.

The invention belongs to the technical field of power semiconductor device life prediction, and particularly relates to a SiC MOSFET life prediction method based on gate oxide layer aging. The method comprises the following steps: firstly, acquiring a real threshold voltage sequence under different working conditions through a SiC MOSFET accelerated aging test, and preprocessing the real threshold voltage sequence; then, a life prediction model is constructed based on the conditional generative adversarial network, and the life prediction model comprises a generator, a common discriminator, a conditional discriminator, a coding network and a reverse recovery network; enabling the working condition as a condition label and the preprocessed real threshold voltage sequence to sequentially pass through a coding network and a reverse recovery network to obtain a real threshold voltage sequence embedded with the working condition; using the working condition as a condition label and a randomly generated Gaussian noise sequence to pass through a generator to obtain an analog threshold voltage sequence embedded with the working condition; inputting the real threshold voltage sequence and the simulation threshold voltage sequence with the embedded working conditions into a common discriminator and a condition discriminator at the same time for discrimination; and finally, training the life prediction model, and generating a threshold voltage sequence under an expected working condition by using a trained generator. According to the method, the service life of the SiC MOSFET under different working conditions can be predicted offline, and the method is more applicable.

A SiC trench MOSFET with an embedded junction Schottky barrier diode (JBSD) having P-shield (PS) regions surrounding bottoms of source-body-Schottky contact (SBSC) trenches for gate oxide electric-field and switching loss reductions is disclosed. A source metal connects with the PS regions and the JBSD directly. Sidewall P (SP) regions are formed along a portion of sidewalls of the SBSC trenches to improve a tradeoff between a drain-source leakage current of the SiC trench MOSFET and a forward voltage of the JBSD. The device further comprises an N-type shield region formed below each of gate trenches for gate oxide electric field strength and specific on-resistance reductions.

The invention provides a silicon carbide trench MOSFET device with a three-side trench structure and a preparation method thereof, and the method comprises the steps: growing a silicon carbide epitaxy on a silicon carbide substrate, and carrying out the injection to form a P-well region; forming a first barrier layer on the P-well region, and performing injection to form a P + region; removing the first barrier layer to form a second barrier layer, and performing injection to form an N + region; removing the second barrier layer, and simultaneously performing rapid thermal annealing on the P-well region, the P + region and the N + region; forming a third barrier layer, and etching to form a gate trench region; removing the third barrier layer, and performing dry-oxygen thermal oxidation to form a gate oxide layer; forming polycrystalline silicon by using chemical vapor deposition; after the polycrystalline silicon is doped, etching is carried out to form a grid electrode; and depositing metal to form a drain electrode and a source electrode, and performing rapid thermal annealing on the drain electrode and the source electrode to form ohmic contact. By arranging the three-side groove structure, the area of the channel is increased, and conduction resistance is reduced.

The utility model discloses a drain-shared double-SGT MOSFET device, and relates to the technical field of semiconductors, the drain-shared double-SGT MOSFET device comprises a substrate and an epitaxial layer, the top surface of the epitaxial layer is provided with a plurality of grooves side by side, the bottom side walls and the inner bottoms of the grooves are provided with shield gate oxide layers, and the shield gate oxide layers on the bottom side walls of the grooves are filled with first polycrystalline silicon; a trench middle shielding oxide layer is deposited at the top end of the first polycrystalline silicon, a gate oxide layer is arranged at the top end of the trench middle shielding oxide layer and located on the side wall of the trench, and the gate oxide layer is filled with second polycrystalline silicon; a source region and a base region are formed between every two adjacent grooves from top to bottom, communicated first top layer contact holes are formed in the source regions and the base regions, the first top layer contact holes are filled with conductive materials to form MOS structures, and connecting layers are formed on the surfaces of the MOS structures; and a groove middle insulating column is vertically arranged in the middle in the groove. According to the utility model, the on-resistance is greatly reduced.

The invention discloses a trench-type power semiconductor device with a gate protrusion structure and a preparation method thereof. The preparation method comprises the following steps: depositing an epitaxial layer on a silicon substrate; sequentially preparing a silicon dioxide cushion layer, a first mask layer and a second mask layer on the epitaxial layer; etching to form a gate trench; forming a gate oxide layer; depositing grid polycrystalline silicon; removing the grid polycrystalline silicon on the surface of the first mask layer through chemical mechanical grinding; etching to remove the first mask layer, and adjusting the morphology of the grid polycrystalline silicon on the silicon platform region; forming a body region and a source region through ion implantation; and preparing a source region contact hole and a tungsten bolt. According to the invention, the grid protrusion structure is formed in the preparation process of the groove type power semiconductor device, the problem that the channel electric leakage is increased after the polycrystalline silicon is etched is solved, the grid resistance is reduced by increasing the cross sectional area of the grid polycrystalline silicon, the switching speed and the linear region capability are improved, and the device performance is optimized.

The invention relates to the technical field of MOS (metal oxide semiconductor), and discloses an MOSFET (metal oxide semiconductor field effect transistor) structure with a nanosheet full-surrounding grid electrode and a manufacturing process thereof, the MOSFET structure comprises a plurality of MOS cells which are arranged in parallel, each MOS cell comprises a drain electrode, a semiconductor epitaxial layer, a grid electrode, a grid oxide layer and a source electrode, the semiconductor epitaxial layer comprises an N substrate layer, an N drift layer, an N well layer, a P + layer and a P well layer, the grid electrode comprises a grid electrode covering layer and a grid electrode nanosheet; a plurality of grid nanosheets are arranged in a single MOS cell, are distributed in a horizontal matrix, extend to the inside of the grid covering layer and are in direct contact with the grid covering layer. Through the three-dimensional embedded contact between the nanosheet grids in horizontal matrix distribution and the high-conductivity covering layer, the static control capability of the channel is remarkably enhanced, the grid resistance is reduced, higher current driving density and better switching characteristics are realized, and the physical limitation of a traditional planar device is broken through.

The invention discloses a semiconductor device which comprises a cellular structure, and the cellular structure comprises an N + substrate, an N-drift layer and a functional area. The N-drift layer is located on the N + substrate; the functional region is embedded into one side, away from the N + substrate, of the N-drift layer, the functional region comprises two subunits and a second N + source region, and each subunit comprises a P + contact region, a P-type body region, a first N + source region and a first trench gate structure; the first N + source region is located on the P-type body region, the first groove is located between the P-type body region and the P + contact region, the first gate oxide layer covers the inner wall of the first groove, a first filling groove is formed in the inner wall of the first gate oxide layer, the first gate is filled in the first filling groove, and the P + shielding region of the P + contact region covers the bottom of the first gate oxide layer; and a second N + source region is arranged between the first trench gate structures of the two subunits. According to the device, the effective utilization rate of a channel can be improved, the specific on-resistance is further reduced, and the problem of long reverse recovery time is solved.

The invention provides a preparation method of a gate oxide layer and a gate, and the method comprises the steps: carrying out the rapid thermal annealing treatment of a silicon-based substrate in a nitrogen-containing gas atmosphere, which belongs to a non-destructive nitrogen doping mode, and carrying out the nitrogen pre-doping on the surface of the silicon-based substrate, so as to reduce the doping amount needed by the subsequent plasma nitrogen doping; therefore, the damage of the plasma nitrogen doping process to the SiON gate oxide layer is reduced, and the interface defect between the SiON gate oxide layer and the silicon-based substrate interface is reduced. Besides, after the nitrogen pre-doped layer is formed, the thermal oxidation process is carried out on the silicon-based substrate to form the silicon dioxide gate oxide layer, so that the damage to the SiON gate oxide layer film is reduced, and the interface defect between the SiON gate oxide layer and the silicon-based substrate interface is further reduced; moreover, the laser rapid annealing treatment can remove the intrinsic oxide layer on the surface of the SiON gate oxide layer, repair the damage to the crystal lattice of the SiON gate oxide layer caused by the plasma nitrogen doping treatment process, improve the film quality and repair the interface.

A LDMOS including a semiconductor substrate, a gate oxide, a gate, field plate oxide layers and field plate barrier layers is disclosed. A first field plate oxide layer and a second field plate oxide layer are positioned atop the gate oxide with a spacing between them. A first field plate barrier layer and a second field plate barrier layer are positioned atop the first and the second field plate oxide layers, respectively. A third field plate barrier layer is positioned atop the first and the second field plate barrier layers and the spacing. A third field plate oxide layer is positioned atop the third field plate barrier layer. The third field plate oxide layer includes a first portion positioned atop the first field plate oxide layer and a second portion positioned atop the spacing. A fourth field plate barrier layer is positioned atop the third field plate oxide layer.

The invention relates to the technical field of MOS (Metal Oxide Semiconductor) semiconductors, and discloses a silicon carbide MOSFET (Metal Oxide Semiconductor Field Effect Transistor) structure with a nail-shaped electrode on the back surface and a preparation process of the silicon carbide MOSFET structure. The silicon carbide MOSFET structure comprises a plurality of MOS cells which are arranged in parallel, and each MOS cell comprises a source electrode, a grid electrode, a grid oxide layer, a semiconductor epitaxial layer and a drain electrode, wherein an N substrate layer, an N drift layer, a P + layer, a P well layer and an N well layer are formed in the semiconductor epitaxial layer through ion implantation, and a discharge tip is further arranged in the middle area of the drain electrode in the single MOS cell; wherein the section shape of the N substrate layer is matched with the shape of the discharge tip. According to the invention, current can be guided to flow through the channel more uniformly through the discharge tip, the problem of over-high local current density is reduced, heat can be managed better through the discharge tip, formation of local hot spots is reduced, the risk of thermal runaway is reduced, and the long-term stability of the device is improved.

The invention provides an optimal selection method and a measurement method of electrical parameters and an estimation method of the degradation condition of a gate oxide layer of a SiC MOSFET, and the optimal selection method comprises the following steps: determining a relation model between a plurality of electrical parameters and the degradation degree of the gate oxide layer in a turn-off process in combination with a gate oxide layer degradation model of the SiC MOSFET and the I-V characteristics of the turn-off process; determining a plurality of alternative electrical parameters in combination with the relation model and the actual working characteristics of the SiC inverter; on the basis of the equivalent circuit model of each alternative electrical parameter, evaluating the online measurement difficulty of each alternative electrical parameter and the coupling degree between the alternative electrical parameter and the SiC MOSFET temperature, and determining a preferred electrical parameter according to an evaluation result; and determining a mapping electrical parameter for joint measurement with the preferred electrical parameter. By deeply exploring the relationship between the aging of the gate oxide layer and each electrical parameter, the electrical parameter suitable for online monitoring of the degradation degree of the gate oxide layer of the SiC MOSFET can be preferably selected.

The present disclosure provides a manufacturing method of a semiconductor structure and a semiconductor structure. The manufacturing method of a semiconductor structure includes: providing a substrate; forming a plurality of silicon pillars arranged in an array on the substrate; pre-processing the silicon pillar, to form an active pillar, where along a first direction, the active pillar includes a first segment, a second segment, and a third segment that are connected sequentially; forming a gate oxide layer on sidewalls of each of the second segment and the third segment; and forming a gate dielectric layer on the gate oxide layer, where along the first direction, the gate dielectric layer is shorter than the gate oxide layer, and a top surface of the gate dielectric layer is flush with that of the third segment.

The invention provides a manufacturing method of a sigma trench, which comprises the following steps: providing a substrate, forming a gate oxide layer and a gate structure on the substrate, the gate structure comprising a gate, a first mask layer and a second mask layer which are sequentially formed on the gate oxide layer; etching for the first time by taking the second mask layer as a mask until the second mask layer is removed, forming a first groove in the substrate on two sides of the gate structure, and gathering polymers generated by etching the second mask layer in the etching process on the gate oxide layer on the side wall of the first groove and a junction area of the gate oxide layer, the gate and the substrate as an etching protection layer; and performing second etching by taking the first mask layer as a mask, protecting the substrate covered by the etching protection layer from lateral etching by the etching protection layer, and forming a sigma-like groove in the first groove. According to the method, the etching protection layer is formed on the side wall of the first groove through the polymer generated by the second mask layer in the first etching process, the area is prevented from being excessively etched, serious lateral pushing of the area is avoided, and therefore the shape of the groove can be adjusted and controlled more easily.

The invention provides a power device and a preparation method thereof. The preparation method comprises the following steps: forming a P-type layer and an N-type layer on an N-type substrate; forming a groove; performing ion implantation to form an N-type source region; forming a gate oxide layer in the groove; forming a first polycrystalline silicon layer, a thick oxide layer and a second polycrystalline silicon layer in the groove; depositing a dielectric layer; forming a source contact region, wherein the source contact region exposes a part of the N-type source region and a part of the P-type layer; forming an insulating layer; forming a gate contact region, wherein the gate contact region extends into the first polycrystalline silicon layer; forming a drain contact region, wherein the N-type layer is exposed out of the drain contact region; and forming a source electrode, a grid electrode and a drain electrode, wherein the source electrode is simultaneously contacted with the N-type source region and the P-type epitaxial layer. According to the invention, the source electrode, the grid electrode and the drain electrode can be attached to the heat dissipation substrate at the same time, so that the heat dissipation path is greatly optimized, and the access inductance of the source electrode is reduced; the connection of the P-type layer and the N-type source region is formed in the device through the groove, so that the process can be effectively simplified, an additional lead-out process is avoided, and the manufacturing cost is effectively saved.

A superjunction trench MOSFET structure and its manufacturing method belong to the technical field of superjunction MOSFETs. A superjunction trench MOSFET structure includes an N+ substrate, a first cell structure, and a second cell structure. Among them, both the first cell structure and the second cell structure are regular hexagons. The first cell structure includes a first N pillar region and a first P pillar region surrounding the first N pillar region, and a first source trench is provided on the first N pillar region. The second cell structure includes a second N pillar region and a second P pillar region surrounding the second N pillar region, and a second source trench is provided on the second N pillar region. A number of second cell structures surround the first cell structure. The second cell structure further includes a gate trench, a first channel is formed between the gate trench and the first source trench, a second channel is formed between the gate trench and the second source trench, and the lengths of the first channel and the second channel are different. By setting a regularly tiled cell structure in the shape of a regular hexagon and having an asymmetric double channel, the present application not only improves the channel density but also provides a good gate oxide protection effect.

A method for forming a semiconductor structure and a semiconductor structure, the method comprising: providing a substrate including a high-voltage gate oxide region and high-voltage source and drain regions, the high-voltage source and drain regions being located at two sides of the high-voltage gate oxide region, and a shallow trench isolation structure between the high-voltage gate oxide region and the high-voltage source and drain regions; forming an isolating membrane on the surface of the preset region of the substrate, wherein the isolating membrane exposes the high-voltage gate oxide region; forming a first photoresist layer on the surface of the high-voltage gate oxide region, wherein the first photoresist layer exposes an edge region adjacent to the shallow trench isolation structure in the high-voltage gate oxide region; etching the exposed edge region in the high-voltage gate oxide region by taking the isolating film and the first photoresist layer as masks so as to reduce the height of the surface of the edge region of the high-voltage gate oxide region; and removing the first photoresist layer to expose the high-voltage gate oxide region, and forming a high-voltage device gate oxide layer on the high-voltage gate oxide region. The performance of the high-voltage device can be optimized, and the reliability of the high-voltage device is improved.

The utility model discloses a SiC MOS with a better gate protection structure, and relates to the technical field of semiconductors. Comprising a SiC Sub layer and a SiC Epi layer which are arranged from bottom to top; the SiC Epi layer is provided with: a P-body region, which extends downwards from the top surface of the SiC Epi layer; the NP region extends downwards from the top surface of the P-body region; the PP region extends downwards from the top surface of the P-body region and is connected with the NP region; the P-shield region extends downwards from the top surface of the P-body region, and a distance is formed between the P-shield region and the P-body region; the N + region extends downwards from the top surface of the P-shield region; the grid ohmic contact alloy layer is formed on the top surface of the P-shield region, and the bottom surface of the grid ohmic contact alloy layer is respectively connected with the P-shield region and the N + region; the gate oxide layer is connected with the gate ohmic contact alloy layer, and the bottom of the gate oxide layer is connected with the NP region, the P-body region and the SiC Epi layer; the top surface of the gate oxide layer is lower than the bottom surface of the gate ohmic contact alloy layer; according to the utility model, a good protection effect on the gate oxide layer of the SiC MOSFET device is realized, and the reliability of the gate oxide layer of the device is improved.

The invention belongs to the technical field of power semiconductors, and relates to a 1200V SiC trench-type MOSFET (Metal-Oxide-Semiconductor Field Effect Transistor) integrated with a super junction and shield gate technology, which comprises an N + substrate layer, a drift region positioned above the N + substrate layer, and a trench gate structure and a source structure positioned above the drift region, compared with a conventional SiC trench type MOSFET with a P-type shielding layer, the SiC trench type MOSFET with the P-type shielding layer has the advantages that the peak electric field of the gate oxide layer is reduced, and the reliability of the device is ensured; the drift region adopts a super-junction structure, so that the electric field distribution is optimized, the blocking capability of the device is improved, the high doping concentration of the drift region can be adopted while the high breakdown voltage is maintained, the specific on-resistance of the device is remarkably reduced, and the conduction loss of the device is reduced; a shield gate structure is adopted, and the overlapping area of the gate and the drain is reduced, so that the gate-drain capacitance and the gate-drain charge are reduced, the switching speed of the device is improved, and the dynamic loss of the device is reduced. The performance is excellent in the high-voltage and high-frequency field.

The invention relates to the technical field of MOS semiconductors, and discloses a SiC MOSFET structure with a second-order oxide layer and a preparation technology thereof.The SiC MOSFET structure comprises a plurality of MOS cells arranged in parallel, each MOS cell comprises a drain electrode, a semiconductor epitaxial layer, a grid electrode, a source electrode and a grid oxide layer, each semiconductor epitaxial layer comprises an N substrate layer, an N drift layer, a P + layer, a P well layer and an N well layer, an N-doped layer is formed in the N drift layer of the single MOS cell through ion implantation, and the N-doped layer is located under the grid electrode; and a plurality of N + doped isolation layers which are not in contact with each other are formed in the N-doped layer through ion implantation. By introducing the N-doped layer right below the grid electrode and the doped N + isolation layers arranged and distributed in the N-doped layer, the distribution of an electric field below the gate oxide is effectively modulated, and the peak of the electric field is inhibited, so that the breakdown voltage of the device is remarkably improved, the reliability of the gate oxide layer is enhanced, and meanwhile, relatively low specific on-resistance is kept.

The invention provides a preparation method of a semiconductor device, and the method comprises the steps: providing a substrate which comprises a high-voltage region, a source-drain region and an isolation region; forming a silicon nitride layer to cover the substrate, and etching to remove at least a part of thickness of the silicon nitride layer on the isolation region; etching to remove partial thickness of the silicon nitride layer on the high-voltage region, wherein the silicon nitride layer on the high-voltage region and the silicon nitride layer on the source-drain region have a height difference after etching; etching the substrate by taking the silicon nitride layer as a mask so as to form an isolation groove in the isolation region, synchronously etching and removing the silicon nitride layer on the high-voltage region, enabling the high-voltage region and the source-drain region to have a height difference after etching, and enabling the top edge of the high-voltage region to be arc-shaped; a first oxide layer is formed to fill the isolation groove and cover the high-voltage region, the surface of the first oxide layer is flat, and the first oxide layer on the high-voltage region serves as a gate oxide layer. The problem of foot warping at the edge of the high-voltage area can be solved, and the preparation cost is not additionally increased.

The invention provides a manufacturing method of a semiconductor device, which comprises the following steps of: performing pre-amorphization injection on an active region to damage surface crystal lattices of the active region and enhance a subsequent surface treatment effect, and performing etching removal on a vertex angle of a device isolation structure at the boundary of the active region to expose a boundary vertex angle surface (including a top surface and a side wall of the vertex angle) of the active region, and then, carrying out surface treatment on the active region in an oxygen-containing atmosphere of which the temperature is lower than 100 DEG C, thereby eliminating threshold voltage regulation ions on the top surface of the active region and the surface of the side wall of the boundary vertex angle, further improving the density of a gate oxide layer on the surface of the active region when the gate oxide layer is grown on the active region in situ, and improving the yield of the gate oxide layer. And the problem that the gate oxide is subjected to pressure stress during growth is reduced, the thickness uniformity of the gate oxide grown at different positions of the same active region is finally improved, and the reliability of the device and the yield of the product are improved.