1800 results about "Gate oxide" patented technology

The invention discloses a SiC MOSFET gate oxide layer degradation monitoring method based on turn-off oscillation, and the method comprises the steps: measuring the drain-source current change rate diDS / dt when a SiC MOSFET is turned off through the source stray inductance voltage vcir, and carrying out the measurement of the gate oxide layer degradation of the SiC MOSFET based on the offset of the negative temperature sensitivity of the threshold voltage VTH in the diDS / dt and the positive temperature sensitivity of the electron mobility mu. Zero temperature sensitivity of a source stray inductance voltage negative peak value vcircmin is realized by adjusting a driving resistor RG and a negative voltage VEE during turn-off, and the gate oxide layer degradation degree of the SiC MOSFET is monitored under a selected monitoring driving resistor RGM and a turn-off gate voltage VEEM. The monitoring method is high in universality and has a good monitoring effect on degradation of gate oxide layers of SiC MOSFETs of different models; the temperature influence is extremely small, so that the device can work in an environment with large temperature fluctuation; a pin of a monitored device does not need to be used as a measurement interface, so that the system invasiveness is small; the parameter measurement methods are many and mature; and the method has great online application potential.

The invention discloses a SiC MOSFET (Metal-Oxide-Semiconductor Field Effect Transistor) device with a high-mobility gate oxide layer and a preparation process of the SiC MOSFET device, and belongs to the technical field of semiconductors. Comprising a drain electrode, a semiconductor epitaxial layer, a source electrode and a grid electrode; the semiconductor epitaxial layer comprises an N substrate layer, an N drift layer, a P + layer, an N well layer and a P well layer, and a lightly doped N layer is arranged in the middle of the N drift layer of each MOS cell; by optimizing the gate oxide layer preparation process and combining the design of the T-shaped P-layer, the semi-elliptical lightly doped N-type half layer and the like in the device, the interface quality of the gate oxide layer and a semiconductor material is effectively improved, the scattering of a carrier by an interface state is reduced, and meanwhile, due to the synergistic effect of the structures such as the quarter-circle-shaped side symmetric P-layer and the square heavily doped N layer, the performance of the device is improved. The internal electric field distribution and the carrier transmission path of the device are optimized, and the channel carrier mobility is remarkably improved.

The disclosure relates to a π type trench gate silicon carbide MOSFET device and a fabrication method thereof. To protect a trench gate oxide layer without increasing a channel resistance and process complexity, a second conductivity type of heavily doped deep well inserted with double gate trenches along the sidewalls of deep well is designed. The deep well is connected to the source metal directly. The electric potential is clamped to the source during the voltage blocking and turn-off state, which reduces the electric field in the gate oxide and reduces the miller capacitance. An interlayer dielectric layer is deposited above the conductive dielectric polysilicon layers and extends outward separately to cover a part of the source region. A smaller cell pitch can be achieved by controlling the spacing between the first and the second trench gate, thereby increasing the channel density and reducing the channel resistance.

The invention relates to the technical field of MOS (Metal Oxide Semiconductor) semiconductors, and discloses a double-gate structure for a high-performance MOSFET (Metal Oxide Semiconductor Field Effect Transistor) and an optimization method, the double-gate structure comprises a plurality of MOS cells, and each MOS cell comprises a drain electrode, a source electrode, a gate electrode, a gate oxide layer and a semiconductor epitaxial layer; the semiconductor epitaxial layer comprises an N substrate layer, an N diffusion layer, a P-layer, a P well layer and an N well layer, two grid electrodes are arranged in a single MOS cell and are respectively positioned on the left side and the right side in a grid oxide layer, and the section outline of the grid oxide layer is semicircular; polycrystalline silicon is arranged in the gate oxide layer and located between the two grid electrodes, and the polycrystalline silicon is in ohmic contact with the source electrode. Through the double-gate structure, geometric shape optimization, doping layer design and process innovation, the switching speed, the voltage endurance capability, the thermal stability and the integration degree of the MOSFET are remarkably improved, meanwhile, the leakage current and the on-resistance are reduced, and the MOSFET is suitable for high-performance power devices and high-frequency application scenes.

The invention relates to the technical field of MOS semiconductors, and discloses a low-groove high-power MOS device which comprises a plurality of MOS cells which are arranged in parallel, and each MOS cell comprises a metal source electrode, a grid electrode, a semiconductor epitaxial layer and a drain electrode; wherein the semiconductor epitaxial layer comprises a substrate layer, a diffusion layer, a P well layer and an N well layer; the N-well layer comprises a heavily doped N-well layer I and a lightly doped N-well layer II; the P well layer comprises a heavily doped P well layer I, a heavily doped P well layer II, a heavily doped P well layer III, a lightly doped P well layer I and a lightly doped P well layer II. According to the invention, the lightly-doped P-well layers are arranged at the left and right lower corners of the gate, so that the phenomenon that the lightly-doped P-well layers and the gate oxide layer are punctured together in the background is avoided, and the stable use of the MOS device in high-power equipment is realized.

The invention relates to the technical field of MOS (metal oxide semiconductor), and discloses a VDMOSFET (vertical double-diffused metal oxide semiconductor field effect transistor) device with low threshold voltage, which comprises a drain electrode, a semiconductor epitaxial layer, a source electrode, a grid electrode and a grid oxide layer covering the surface of the grid electrode, and is characterized in that an N substrate layer, an N drift layer, an N well layer, a P well layer and a heavily doped P layer are formed in the semiconductor epitaxial layer through ion implantation, the grid electrode comprises a triangular grid electrode and a rectangular grid electrode, the grid oxide layer covering the surface of the triangular grid electrode is in contact with the N substrate layer, and the N drift layer is divided into a left part and a right part by the grid oxide layer. According to the invention, the grid electrode is designed to further comprise the triangular grid electrode, the electric field effect of the grid electrode between the tip part of the triangular grid electrode and the drain electrode is better, but the grid oxide layer wrapped by the triangular grid electrode at the tip part is thicker, so that charges flowing out of the drain electrode gather towards the inside of the heavily doped N layer more quickly along the grid oxide layer; at the moment, more charge flow can be provided in a smaller grid voltage environment.

The invention discloses a high-voltage SiC MOSFET cellular structure. The high-voltage SiC MOSFET cellular structure comprises an N + type silicon carbide power substrate, an N type drift region and a current expansion layer which are stacked in sequence, the electric field modulation regions are arranged on the left side and the right side of the current expansion layer, the P-body region is arranged above the current expansion layer, and the N + type source region and the P + type source region are arranged above the P-body region; the gate trench is arranged in the middle of the current expansion layer, a P + type shielding region is arranged at the bottom of the gate trench, a gate is arranged in the gate trench, and the gate is located above the P + type shielding region; and the gate oxide layer covers the upper surfaces of the gate, the N + type source region and the P + type source region. According to the structure, the electric field modulation areas are arranged on the two sides of the current expansion layer, the peak electric field intensity of the bottom of the groove of the UMOSFET device is reduced, the reverse breakdown voltage of the device is greatly improved, and meanwhile, the N-type areas in the electric field modulation areas also effectively reduce the characteristic on-resistance when the power device is conducted.

The invention relates to the technical field of MOS (metal oxide semiconductor), and discloses a shallow-channel super-junction MOS device and a preparation process thereof, the shallow-channel super-junction MOS device comprises a drain electrode, a source electrode, a semiconductor epitaxial layer, a grid electrode and a grid oxide layer covering the surface of the grid electrode, and the semiconductor epitaxial layer comprises an N substrate layer and a drift layer; a P well layer, a P-layer II and an N well layer are formed in the drift layer through ion implantation; the cross section of the grid electrode is T-shaped; a first P-layer is formed in the N well layer through ion implantation, and a narrow heavily doped N layer is formed in the drift layer and located between two adjacent second P-layers through ion implantation. After the gate voltage is accessed, a charge channel is formed in the P-layer 2, so that the N-well layer and the drift layer can form a path, and the existence of the P-layer 1 can inhibit the collection of charges flowing in the N-well layer to the gate region, so that the number of parasitic charges can be greatly reduced, and the response speed of the MOS semiconductor device is improved.

According to the MTP device and the preparation method thereof, an MOS capacitor composed of a substrate, a gate oxide layer and a floating gate in a traditional MTP device is replaced with a capacitor located on the substrate and composed of the floating gate, an insulating layer and a conductive plug, so that the potential of the floating gate is controlled through capacitive coupling between the floating gate and the conductive plug; according to the MTP device disclosed by the invention, the capacitor is completely isolated from the substrate, so that the MTP device is not influenced by the potential of the substrate during programming and erasing operation, the operation range of the MTP device is further effectively expanded, namely the programming efficiency and the erasing efficiency of the MTP device are improved, and the reliability of the MTP device is improved. And meanwhile, higher capacitance coupling efficiency is realized in a smaller area, and the reduction of the chip area is facilitated.

The invention relates to the technical field of MOS semiconductors, and discloses a vertical D-MOSFET with trench isolation and an improved channel structure and a preparation method, the vertical D-MOSFET comprises a plurality of MOS cells which are parallel to one another, each MOS cell comprises a drain electrode, a source electrode, a grid electrode, a grid oxide layer and a semiconductor epitaxial layer, the semiconductor epitaxial layer comprises an N substrate layer, an N diffusion layer, a P + layer, a P well layer and an N well layer, the profile of the cross section of the grid electrode is triangular, and a polycrystalline silicon covering layer is deposited at the junction of the grid electrode and the gate oxide layer; the profile of the cross section of the gate oxide layer is in a semi-elliptical shape, and the profile of the cross section of the polycrystalline silicon covering layer is in a triangular shape. The section profile of the grid electrode is designed to be triangular, the grid oxide layer is controlled to be in a semi-oval shape, electric field distribution and a carrier migration path are optimized, the triangular grid electrode can reduce electric field concentration at the edge of the grid electrode, and the breakdown risk is reduced.

The invention relates to the technical field of MOS (metal oxide semiconductor), and discloses a low-on-resistance SiC MOSFET (metal oxide semiconductor field effect transistor) terminal structure, which consists of a plurality of parallel MOS cells, and is characterized in that each MOS cell comprises a drain electrode, a semiconductor epitaxial layer, a source electrode, a grid electrode and a grid oxide layer, the semiconductor epitaxial layer sequentially comprises an N substrate layer, an N drift layer, a P well layer and an N well layer from bottom to top, P + layers are arranged on the two sides of the P well layer and the N well layer in a single MOS cell, a heavily doped N-layer is formed in the semiconductor epitaxial layer of the single MOS cell through ion implantation, and the heavily doped N-layer is located below the P well layer and is in contact with the P well layer. The heavily doped N-layer is additionally arranged below the P well layer to form a vertical low-resistance path, the uniformity of a grid electric field is destroyed in combination with the conduction P region, suppression of the grid on charge diffusion of a drain is weakened, the conduction resistance is greatly reduced compared with a traditional structure, and then the conduction current is greatly improved.

The invention discloses a double-groove super junction structure and a manufacturing method thereof, the double-groove super junction structure comprises a plurality of MOS cells which are connected in parallel, and each MOS cell comprises a drain electrode, an upper metal source electrode, a grid electrode, a semiconductor epitaxial layer, a substrate layer, a P well layer and an N well layer; a groove is formed between adjacent MOS cells and in the middle of the heavily doped P well layer I through etching, an oxide layer is deposited at the bottom of the groove, a side metal source electrode is arranged on the surface of the oxide layer, and the top of the side metal source electrode is in contact with the upper metal source electrode; the side surface of the side metal source is in ohmic contact with the N well layer, the lightly doped P well layer I and the heavily doped P well layer I; the grid electrode is a longitudinal groove type grid electrode and is arranged between the two N well layers of the single MOS cell, and the grid electrode is connected with the N well layers, the first lightly-doped P well layer and the diffusion layer in an isolated mode through a grid oxide layer. According to the invention, the injection depth of the heavily doped P well layer I is increased through the groove, and the (11-20) surface channel is adopted, so that the interface state density is greatly reduced, and the overall size of the device is reduced.

An improved silicon carbide (SiC) super junction (SJ) MOSFET having at least two buried P-shield (BPS) regions facing each other for gate oxide electric-field and saturation current reductions is disclosed. The two BPS regions are spaced apart from a body region and formed either adjoining sidewalls or below a bottom of a P column region. Moreover, a saturation current pitching (SCP) structure formed in a Junction Field Effect Transistor (JFET) region sandwiched between the two BPS regions limits saturation current of the device in a forward conduction stage for the short-circuit capability improvement.

The invention relates to a silicon carbide super-junction transverse MOS device and a manufacturing method thereof, and belongs to the technical field of semiconductor devices. The device sequentially comprises a substrate and an epitaxial layer from bottom to top, a p column region is arranged on the outer side of the epitaxial layer, a drain region is arranged on the outer side of the p column region, a p well region is arranged on the inner side of the epitaxial layer, a source region is arranged on the inner side of the p well region, a p + region is arranged on the outer side of the p well region, a groove is formed in the middle of the epitaxial layer, and a gate oxide layer is arranged in the groove. A gate polycrystalline silicon is arranged in the gate oxide layer, source electrode metal is arranged on the upper sides of the source electrode region and the p + region, drain electrode metal is arranged on the upper side of the drain electrode region, a dielectric layer is arranged between the source electrode metal and the drain electrode metal, and top layer metal is arranged at the tops of the source electrode metal and the drain electrode metal. According to the invention, the doping concentration of the drift region can be improved while the withstand voltage of the device is ensured, and higher withstand voltage and lower on resistance of the device are realized.

The invention relates to the technical field of MOS (Metal Oxide Semiconductor) semiconductors, and discloses a SiC VDMOSFET (Vertical Double-diffused Metal Oxide Semiconductor Field Effect Transistor) structure with high heat dissipation performance, which comprises a plurality of MOS cells arranged in parallel, and is characterized in that each MOS cell comprises a metal drain electrode, a semiconductor epitaxial layer, a metal source electrode and a gate oxide layer covering the surface of the metal source electrode, performing ion implantation in the semiconductor epitaxial layer to form an N substrate layer, an N drift layer, an N well layer, a heavily doped P layer and a P well layer; source electrode doping layers are arranged on the two sides of a single MOS cell, the source electrode doping layers are in ohmic contact with the metal source electrodes, and the source electrode doping layers are made of gallium arsenide or gallium nitride or nichrome. According to the invention, the source electrode doping layer with the sinking design is arranged above the MOS cell, so that the N well layer can be in direct contact with the metal source electrode, and the N well layer can be in indirect contact with the metal source electrode through the source electrode doping layer, thereby reducing the ohmic resistance of the N well layer and the metal source electrode, and reducing the heating at the contact position.

The invention belongs to the technical field of power semiconductor device life prediction, and particularly relates to a SiC MOSFET life prediction method based on gate oxide layer aging. The method comprises the following steps: firstly, acquiring a real threshold voltage sequence under different working conditions through a SiC MOSFET accelerated aging test, and preprocessing the real threshold voltage sequence; then, a life prediction model is constructed based on the conditional generative adversarial network, and the life prediction model comprises a generator, a common discriminator, a conditional discriminator, a coding network and a reverse recovery network; enabling the working condition as a condition label and the preprocessed real threshold voltage sequence to sequentially pass through a coding network and a reverse recovery network to obtain a real threshold voltage sequence embedded with the working condition; using the working condition as a condition label and a randomly generated Gaussian noise sequence to pass through a generator to obtain an analog threshold voltage sequence embedded with the working condition; inputting the real threshold voltage sequence and the simulation threshold voltage sequence with the embedded working conditions into a common discriminator and a condition discriminator at the same time for discrimination; and finally, training the life prediction model, and generating a threshold voltage sequence under an expected working condition by using a trained generator. According to the method, the service life of the SiC MOSFET under different working conditions can be predicted offline, and the method is more applicable.

A SiC trench MOSFET with an embedded junction Schottky barrier diode (JBSD) having P-shield (PS) regions surrounding bottoms of source-body-Schottky contact (SBSC) trenches for gate oxide electric-field and switching loss reductions is disclosed. A source metal connects with the PS regions and the JBSD directly. Sidewall P (SP) regions are formed along a portion of sidewalls of the SBSC trenches to improve a tradeoff between a drain-source leakage current of the SiC trench MOSFET and a forward voltage of the JBSD. The device further comprises an N-type shield region formed below each of gate trenches for gate oxide electric field strength and specific on-resistance reductions.

The invention provides a silicon carbide trench MOSFET device with a three-side trench structure and a preparation method thereof, and the method comprises the steps: growing a silicon carbide epitaxy on a silicon carbide substrate, and carrying out the injection to form a P-well region; forming a first barrier layer on the P-well region, and performing injection to form a P + region; removing the first barrier layer to form a second barrier layer, and performing injection to form an N + region; removing the second barrier layer, and simultaneously performing rapid thermal annealing on the P-well region, the P + region and the N + region; forming a third barrier layer, and etching to form a gate trench region; removing the third barrier layer, and performing dry-oxygen thermal oxidation to form a gate oxide layer; forming polycrystalline silicon by using chemical vapor deposition; after the polycrystalline silicon is doped, etching is carried out to form a grid electrode; and depositing metal to form a drain electrode and a source electrode, and performing rapid thermal annealing on the drain electrode and the source electrode to form ohmic contact. By arranging the three-side groove structure, the area of the channel is increased, and conduction resistance is reduced.

The embodiment of the invention provides a field effect transistor, electronic equipment and a preparation method of the field effect transistor, and relates to the technical field of semiconductors. Wherein the field effect transistor comprises a second substrate, an oxide layer and a grid electrode, and the material of the second substrate comprises silicon carbide; the second substrate comprises a source region and a channel region, and the doping concentration of the source region is larger than that of the channel region. The oxide layer is bonded with the second substrate; the oxide layer covers at least part of the channel region; the oxide layer is formed by oxidizing a silicon material. The grid electrode is arranged on the side, away from the second substrate, of the oxide layer. According to the field effect transistor provided by the embodiment of the invention, the oxidation degree of the gate oxide layer is relatively high, and the interface state density between the silicon carbide substrate and the gate oxide layer is relatively small, so that the channel mobility of the silicon carbide field effect transistor is effectively improved, and the electrical performance and reliability of the field effect transistor are optimized.

The utility model discloses a drain-shared double-SGT MOSFET device, and relates to the technical field of semiconductors, the drain-shared double-SGT MOSFET device comprises a substrate and an epitaxial layer, the top surface of the epitaxial layer is provided with a plurality of grooves side by side, the bottom side walls and the inner bottoms of the grooves are provided with shield gate oxide layers, and the shield gate oxide layers on the bottom side walls of the grooves are filled with first polycrystalline silicon; a trench middle shielding oxide layer is deposited at the top end of the first polycrystalline silicon, a gate oxide layer is arranged at the top end of the trench middle shielding oxide layer and located on the side wall of the trench, and the gate oxide layer is filled with second polycrystalline silicon; a source region and a base region are formed between every two adjacent grooves from top to bottom, communicated first top layer contact holes are formed in the source regions and the base regions, the first top layer contact holes are filled with conductive materials to form MOS structures, and connecting layers are formed on the surfaces of the MOS structures; and a groove middle insulating column is vertically arranged in the middle in the groove. According to the utility model, the on-resistance is greatly reduced.

The invention discloses a super-junction trench MOSFET structure and a manufacturing method thereof, and belongs to the technical field of super-junction MOSFETs, and the super-junction trench MOSFET structure comprises an N + substrate, a first cellular structure and a second cellular structure. Wherein the first cellular structure and the second cellular structure are both in a regular hexagon shape; the first cell structure comprises a first N column region and a first P column region surrounding the first N column region, and a first source groove is formed in the first N column region; the second cellular structure comprises a second N column region and a second P column region surrounding the second N column region, and a second source groove is formed in the second N column region; the plurality of second cellular structures surround the first cellular structures; the second cellular structure further comprises a gate groove, a first channel is formed between the gate groove and the first source groove, a second channel is formed between the gate groove and the second source groove, and the length of the first channel is different from that of the second channel. According to the invention, by arranging the regularly hexagonal densely laid cellular structure and having the asymmetric double channels, the channel density is improved, and a good gate oxide protection effect is also provided.

The invention discloses a trench-type power semiconductor device with a gate protrusion structure and a preparation method thereof. The preparation method comprises the following steps: depositing an epitaxial layer on a silicon substrate; sequentially preparing a silicon dioxide cushion layer, a first mask layer and a second mask layer on the epitaxial layer; etching to form a gate trench; forming a gate oxide layer; depositing grid polycrystalline silicon; removing the grid polycrystalline silicon on the surface of the first mask layer through chemical mechanical grinding; etching to remove the first mask layer, and adjusting the morphology of the grid polycrystalline silicon on the silicon platform region; forming a body region and a source region through ion implantation; and preparing a source region contact hole and a tungsten bolt. According to the invention, the grid protrusion structure is formed in the preparation process of the groove type power semiconductor device, the problem that the channel electric leakage is increased after the polycrystalline silicon is etched is solved, the grid resistance is reduced by increasing the cross sectional area of the grid polycrystalline silicon, the switching speed and the linear region capability are improved, and the device performance is optimized.

The invention relates to the technical field of MOS (Metal Oxide Semiconductor) semiconductors, and discloses an anti-radiation SiC MOSFET (Metal Oxide Semiconductor Field Effect Transistor) structure which comprises a drain electrode, a semiconductor epitaxial layer, a source electrode, a grid electrode and a grid oxide layer positioned on the surface of the grid electrode, a P well layer, a heavily-doped P well I and a heavily-doped N well layer are formed in the N diffusion layer of each MOS cell through ion implantation, the heavily-doped P well I further comprises a heavily-doped P well II, and the height of the cross section of the heavily-doped P well II is the same as that of the cross section of the heavily-doped N well layer; the N diffusion layer further comprises a carrier storage layer. According to the method, the trench is introduced into the device JFET, P-type impurities are injected into the side wall and the bottom of the trench to form the P-type doped region, the trench is filled with dielectric materials such as SiO2 and the like, and the trench structure transfers a strong electric field at a gate oxide interface to the bottom of the JFET region, so that the electric field intensity in thin gate oxide is greatly reduced, and the single-particle gate penetration resistance of the SiC MOSFET device is improved.

The invention relates to the technical field of MOS (metal oxide semiconductor), and discloses an MOSFET (metal oxide semiconductor field effect transistor) structure with a nanosheet full-surrounding grid electrode and a manufacturing process thereof, the MOSFET structure comprises a plurality of MOS cells which are arranged in parallel, each MOS cell comprises a drain electrode, a semiconductor epitaxial layer, a grid electrode, a grid oxide layer and a source electrode, the semiconductor epitaxial layer comprises an N substrate layer, an N drift layer, an N well layer, a P + layer and a P well layer, the grid electrode comprises a grid electrode covering layer and a grid electrode nanosheet; a plurality of grid nanosheets are arranged in a single MOS cell, are distributed in a horizontal matrix, extend to the inside of the grid covering layer and are in direct contact with the grid covering layer. Through the three-dimensional embedded contact between the nanosheet grids in horizontal matrix distribution and the high-conductivity covering layer, the static control capability of the channel is remarkably enhanced, the grid resistance is reduced, higher current driving density and better switching characteristics are realized, and the physical limitation of a traditional planar device is broken through.

The invention provides a method for forming a semiconductor device, which comprises the following steps of: removing a pad oxide layer of a medium-voltage region and pad oxide layers of a source region and a drain region of a high-voltage region at the same time instead of removing pad oxide layer residues caused by the pad oxide layers when a second gate oxide layer is etched, so that the pad oxide layer with beak defects is removed; in other words, no pad oxide layer remains in the source region and the drain region of the high-voltage region in the subsequent etching for forming the gate structure, so that the metal silicide layer formed on the semiconductor substrate of the source region and the drain region of the high-voltage region in the subsequent process is not influenced; and the contact between a plug formed on the source region and the drain region of the high-voltage region and the substrate is not influenced, so that the electrical property and the reliability of the high-voltage device are not influenced.

The invention discloses a self-aligned double-epitaxial super-junction MOSFET and a manufacturing method, the self-aligned double-epitaxial super-junction MOSFET comprises a semiconductor layer arranged on a substrate, a plurality of body regions distributed along the surface of the semiconductor layer are arranged in the semiconductor layer, and a source region located below the surface of the semiconductor layer is arranged in each body region; the pair of first side walls are arranged on the surface of the semiconductor layer above each source region in a self-aligned manner; the super junction groove is arranged in the semiconductor layer in a penetrating manner between each pair of first side walls; the first epitaxial layer of the first conductive type and the second epitaxial layer of the second conductive type are arranged in the super junction groove and are connected with the body region; and the gate oxide layer and the gate electrode are arranged on the surface of the semiconductor layer between two adjacent pairs of first side walls. According to the invention, the range of ion implantation can be accurately adjusted while the number of photomasks is reduced and self-alignment is realized, and the drift region can be directly changed into the intrinsic semiconductor layer, so that the on-resistance can be reduced while the withstand voltage is improved.

The invention discloses a semiconductor device which comprises a cellular structure, and the cellular structure comprises an N + substrate, an N-drift layer and a functional area. The N-drift layer is located on the N + substrate; the functional region is embedded into one side, away from the N + substrate, of the N-drift layer, the functional region comprises two subunits and a second N + source region, and each subunit comprises a P + contact region, a P-type body region, a first N + source region and a first trench gate structure; the first N + source region is located on the P-type body region, the first groove is located between the P-type body region and the P + contact region, the first gate oxide layer covers the inner wall of the first groove, a first filling groove is formed in the inner wall of the first gate oxide layer, the first gate is filled in the first filling groove, and the P + shielding region of the P + contact region covers the bottom of the first gate oxide layer; and a second N + source region is arranged between the first trench gate structures of the two subunits. According to the device, the effective utilization rate of a channel can be improved, the specific on-resistance is further reduced, and the problem of long reverse recovery time is solved.

The invention provides a preparation method of a gate oxide layer and a gate, and the method comprises the steps: carrying out the rapid thermal annealing treatment of a silicon-based substrate in a nitrogen-containing gas atmosphere, which belongs to a non-destructive nitrogen doping mode, and carrying out the nitrogen pre-doping on the surface of the silicon-based substrate, so as to reduce the doping amount needed by the subsequent plasma nitrogen doping; therefore, the damage of the plasma nitrogen doping process to the SiON gate oxide layer is reduced, and the interface defect between the SiON gate oxide layer and the silicon-based substrate interface is reduced. Besides, after the nitrogen pre-doped layer is formed, the thermal oxidation process is carried out on the silicon-based substrate to form the silicon dioxide gate oxide layer, so that the damage to the SiON gate oxide layer film is reduced, and the interface defect between the SiON gate oxide layer and the silicon-based substrate interface is further reduced; moreover, the laser rapid annealing treatment can remove the intrinsic oxide layer on the surface of the SiON gate oxide layer, repair the damage to the crystal lattice of the SiON gate oxide layer caused by the plasma nitrogen doping treatment process, improve the film quality and repair the interface.

The invention discloses a planar gate dual-control electrode 4H-SiC composite transistor structure which comprises a plurality of cell structures connected in parallel, each cell structure comprises an n buffer layer on a 4H-SiC n + substrate, an n-drift region, an n carrier expansion layer and p body regions in the two sides of the n carrier expansion layer, each p body region is of a mesa structure, an n + source region and a p + region are arranged in the upper part and the lower part, and a gap is formed between the n + source region and the p + region; gate oxide layers and polycrystalline silicon layers are arranged on the surfaces of the n carrier expansion layer, the p body regions on the two sides and part of the n + source region; a plane grid G is arranged on the surface of the polycrystalline silicon layer; a source S is arranged on the surface of the n + source region; a base B is arranged on the surface of the p + region; a drain electrode D is arranged on the back surface of the 4H-SiC n + substrate; the cellular structure is in bilateral symmetry with the planar grid G as the axis, equivalently, the VDMOS and the BJT are connected in parallel, the VDMOS is located in the center, and the BJT is located on the outer side. According to the invention, the conduction loss of the device can be reduced, the anti-short-circuit capability is improved, and the influence of a body diode is eliminated.

An integrated circuit (IC) including Flash memory and CMOS logic circuitry and a method of fabrication thereof is disclosed. The IC comprises a substrate including a first region and a second region, where a Flash memory cell gate stack is formed in the first region, a first transistor is formed in the first region and operable at a first voltage level, the first transistor including a gate formed over a first gate oxide layer exclusive of nitridation, and one or more sets of second transistors are formed in the second region, each set operable at a corresponding second voltage level different than the first voltage level and including a corresponding second gate oxide layer having nitridation.