432 results about "Body region" patented technology

The invention discloses a semiconductor device which comprises a cellular structure, and the cellular structure comprises an N + substrate, an N-drift layer and a functional area. The N-drift layer is located on the N + substrate; the functional region is embedded into one side, away from the N + substrate, of the N-drift layer, the functional region comprises two subunits and a second N + source region, and each subunit comprises a P + contact region, a P-type body region, a first N + source region and a first trench gate structure; the first N + source region is located on the P-type body region, the first groove is located between the P-type body region and the P + contact region, the first gate oxide layer covers the inner wall of the first groove, a first filling groove is formed in the inner wall of the first gate oxide layer, the first gate is filled in the first filling groove, and the P + shielding region of the P + contact region covers the bottom of the first gate oxide layer; and a second N + source region is arranged between the first trench gate structures of the two subunits. According to the device, the effective utilization rate of a channel can be improved, the specific on-resistance is further reduced, and the problem of long reverse recovery time is solved.

The utility model provides a power semiconductor device, comprising a substrate which comprises a body region and a drift region which are arranged at an interval; the first well region is formed in the body region; the substrate leading-out region is formed in the body region, the first well region and the substrate leading-out region are arranged at intervals, the substrate leading-out region comprises a polycrystalline silicon body, the polycrystalline silicon body extends into the body region from the surface of the body region, and the vertical size of the polycrystalline silicon body is larger than the junction depth of the first well region; the first dielectric layer is arranged on the outer side of the polycrystalline silicon body, and the first well region and the polycrystalline silicon body are separated by the first dielectric layer; the second well region is formed in the drift region; the gate dielectric layer is arranged on the surface of the drift region, the gate dielectric layer is located between the body region and the second well region, and the gate dielectric layer is separated from the second well region; and the polysilicon gate layer is arranged on the surfaces of the gate dielectric layer, the drift region, the substrate and the body region. Without increasing the lateral dimension of the semiconductor device, the withstand voltage between the source electrode and the substrate can be improved.

The disclosure relates to a semiconductor die with a semiconductor body. The semiconductor die includes: a vertical transistor device with a first load region and a second load region at opposite sides of the semiconductor body; an additional transistor device with a source region at a first side of the semiconductor body, a gate trench, a body region aside the gate trench, and a drain region below the body region; an electrical isolation in the semiconductor body; and a vertical contact element extending from the first side into the semiconductor body. The electrical isolation is arranged laterally between the vertical transistor device and the additional transistor device. The vertical contact element makes electrical contact to the drain region of the additional transistor device and connects the drain region to the first side of the semiconductor body.

In an embodiment, a vertical transistor device includes a semiconductor substrate having a first major surface and a second major surface opposing the first major surface. At least one transistor cell formed in the semiconductor substrate includes a fin having an upper surface and side walls. The fin includes a source region, a body region and a drift zone that are located along a length of the fin. The body region extends between the source region and the drift zone. The transistor cell further includes a gate arranged on the upper surface and the side walls of the fin. A source pad is located on the first major surface and a drain pad is located on the second major surface of the semiconductor substrate.

A semiconductor device including a semiconductor substrate having upper and lower areas, the lower area including a lower layer having a first conductivity type; a first deep well region having the first conductivity type and being on the upper area; a connection layer having the first conductivity type and being on the first deep well region; a body region having the first conductivity type and a first drift region having a second conductivity type, the body region and the first drift region being side-by-side in a first direction on the connection layer; a first source region having the second conductivity type and being on the body region; a drain region having the second conductivity type and being on the upper area and spaced apart from the first drift region in the first direction; and a gate structure on the first drift region and being adjacent to the first source region.

The invention provides a groove type silicon carbide MOSFET device structure. The device structure comprises a silicon carbide substrate of a first doping type; a first doping type silicon carbide epitaxial layer on the upper surface of the silicon carbide substrate; the groove protection regions of the second doping type are arranged in the silicon carbide epitaxial layer in an array mode in the first direction, the tops of the groove protection regions are discontinuous in the second direction, and the first direction is perpendicular to the second direction; the body regions are arranged in an array in the first direction, are arranged between two adjacent groove protection regions, and extend in the second direction; the source regions are arranged in an array in the first direction, are arranged in the body region, and are discontinuous in the second direction; the one or two gate trenches are arranged between two adjacent trench protection regions, the gate trenches penetrate through the body region, gate oxide layers and polycrystalline silicon are arranged in the gate trenches, and the upper surface of the polycrystalline silicon is lower than the upper surface of the silicon carbide substrate; the interlayer dielectric layer extends along a second direction; and a front metal layer.

A process of forming an electronic device can form an accumulation channel or an integrated diode by selective doping parts of a workpiece. In an embodiment, a doped region can be formed by implanting a sidewall of a body region. In another embodiment, a doped region can correspond to a remaining portion of a semiconductor layer after forming another doped region by implanting into a contact opening. The accumulation channel or the integrated diode can lower the barrier for a body diode turn-on. Reduced stored charge and QRR may be achieved, leading to lower switching losses.

The present application provides a kind of transistor element and its manufacturing method, the manufacturing method of transistor element includes the following steps: first, provide first conductive type epitaxial layer, set on substrate.Second, first conductive type epitaxial layer is implanted with second conductive type ion using first mask, to form second conductive type body region.Then, second conductive type body region is implanted with first conductive type ion using second mask, to form first conductive type heavily doped region in second conductive type body region.Finally, the second conductive type body region of two side edges of first conductive type heavily doped region is implanted with second conductive type oblique angle ion using second mask, to form two in-situ self-aligned second conductive type doped channel in the second conductive type body region of two side edges of first conductive type heavily doped region.

The invention provides an LDMOS device and a manufacturing method thereof, and relates to the technical field of semiconductors. The LDMOS device may include: a semiconductor substrate; the drift region is located on the semiconductor substrate and is provided with a first conduction type; the body region is located at one end of the drift region and has a second conductive type; the gate structure is positioned on the surface of the body region and partially extends to the drift region; the source region is located in the body region and is adjacent to one side of the gate structure, and the body contact region is adjacent to the source region and is of a second conduction type; the drain region is located at one end, away from the body region, of the drift region; and the plurality of strip-shaped current modulation units are arranged in the drift region in an interdigital alternate arrangement mode, and extend and are arranged in the direction from the body region to the drain region. The chip has the advantages of being low in cost, small in overall chip area and easier to manufacture.

RC-IGBT (1), comprising: - an active region (1-2) with an IGBT region (1-21) and a diode region (1-22); - a semiconductor body (10) having a first side (110) and a second side (120); - a first load terminal (11) on the first side (110) and a second load terminal (12) on the second side (120); - multiple control trenches (14) and multiple source trenches (16), wherein the multiple trenches (14, 16) are arranged parallel to each other along a first lateral direction (X) and extending along a vertical direction (Z) into the semiconductor body (10), wherein the multiple source trenches (16) extend into both the IGBT region (1-21) and the diode region (1-22);- several IGBT measures (17) and several diode measures (18) in the semiconductor body (10), wherein the measures (17, 18) are laterally delimited along the first lateral direction (X) by two of the several trenches (14, 16), wherein: ◯ the IGBT measures (17) each comprise: ▪ a source region (101) of a first conductivity type electrically connected to the first load terminal (11), and ▪ a body region (102) of a second conductivity type electrically connected to the first load terminal (11) and isolating the source region (101) from another region (100) of the first conductivity type of the RC-IGBT (1); ◯ wherein the diode measures (18) each comprise: ▪ a first anode region (1061) of the second conductivity type electrically connected to the first load terminal (11). Conductivity type;- in the semiconductor body (10) and on the second side (120), both◯ a diode emitter region (104) of the first conductivity type, which forms part of the diode region (1-22) and has a lateral extent in the first lateral direction (X) that is at least 50% of the drift region thickness or at least 50% of the semiconductor body thickness (d); and◯ an IGBT emitter region (103) of the second conductivity type, which forms part of the IGBT region (1-21) and has a lateral extent in the first lateral direction (X) that is at least 70% of the drift region thickness or at least 70% of the semiconductor body thickness (d); and- in the diode region (1-22), a second anode region (1062) of the second conductivity type electrically connected to the first load terminal (11), wherein the second anode region (1062)◯ extends deeper along the vertical direction (Z) compared with the trenches (14, 16) in the diode region (1-22);and◯ overlaps with the diode emitter region (104) for at least 5% of the horizontal area of ​​the diode emitter region (104).

The invention provides a field stop layer preparation method, a process monitoring method and a semiconductor device preparation method, and belongs to the technical field of semiconductor power devices. Comprising a gate oxide layer located on the upper surface of the epitaxial layer, a polycrystalline silicon layer located on the upper surface of the gate oxide layer, a body region located in the epitaxial layer and a first injection region located in the body region; gluing the front surface of the wafer prefabricated member, turning over the wafer prefabricated member with the front surface protection glue, and thinning the back surface of the wafer prefabricated member; performing ion implantation on the back surface of the wafer prefabricated member by adopting a front surface implantation machine to form a field stop layer; and turning over again, and removing the front protection glue. The method has the beneficial effects that the field stop layer is formed by utilizing a front injection machine in the front-section process, so that production line pollution is avoided, and the manufacturing process of the field stop layer is more favorably realized; the problem that the back injection machine table of a wafer factory is limited is solved, no extra machine table needs to be purchased, the utilization rate of the machine table is improved, and cost is reduced.

The invention relates to an LDMOS with a bias circuit for biasing a field plate. A semiconductor device (100) includes: a drain extension transistor (101) having: a semiconductor layer (104) including oppositely doped body and drain drift regions (104, 120); a gate dielectric layer (134) over the body region (104) and extending over a junction between the body region (104) and the drain drift region (120); a gate electrode (140) over the gate dielectric layer (134); a drain region (160) in the drain drift region (120) and having a dopant density greater than a dopant density of the drain drift region (120); and a field plate (142) between the gate electrode (140) and the drain region (160); and a bias circuit (190) including an output coupled to the field plate (142) and a bias input coupled to a gate drive circuit (192).

The present disclosure provides a trench gate semiconductor device and a preparation method thereof. The trench gate semiconductor device comprises a substrate, a drift region and a body region. The drift region is arranged on the surface of the substrate and has a first conductivity type. The body region is epitaxially formed on the surface of the drift region away from the substrate and is an in-situ doped region with a second conductivity type. In the embodiment of the present disclosure, the body region is directly epitaxially formed, which can reduce the lattice damage in the body region, thereby reducing the interface defects between the body region and the gate oxide layer, and further improving the channel mobility. In addition, the tailing effect of the channel caused by ion implantation can be avoided, thereby improving the threshold voltage stability.

A silicon carbide semiconductor device includes a silicon carbide substrate having a first main surface and a second main surface opposite to the first main surface. The silicon carbide substrate includes a drift region being a first-conductivity type, a body region being a second-conductivity type and provided on the drift region, a source region being the first-conductivity type and provided on the body region such that the source region is separated from the drift region, a contact region being the second-conductivity type and provided on the body region. Gate trenches are provided in the first main surface, and extend in a first direction parallel to the first main surface. The contact region is in contact with a first gate trench from both sides in a second direction orthogonal to the first direction and spaced apart from a second gate trench adjacent to the first gate trench in the second direction.

The embodiment of the invention provides a SiC LDMOS device, a manufacturing method and a chip. The SiC LDMOS device comprises a P-type substrate; the N-type buried layer is located in the P-type substrate; the N-type epitaxial layer is located on the surface of the P-type substrate and the surface of the N-type buried layer; the P-type injection layer is located in the N-type epitaxial layer, and the bottom of the P-type injection layer is connected with part of the surface of the N-type buried layer; the P-type body region is located in the N-type epitaxial layer and extends into the P-type substrate; and the N-type buffer layer is located in the P-type injection layer and extends into the N-type buried layer. When the device is in a reverse withstand voltage state, the drift region is depleted, ionization donors in the P-type injection layer and the P-type substrate emit power lines and point to ionization acceptors of the N-type buried layer and the N-type epitaxial layer, the N-type epitaxial layer and the N-type buried layer are mutually overlapped, electric field distribution in the drift region of the device can be effectively adjusted, an electric field peak is introduced to the surface of the drift region of the device, and the device is prevented from being damaged. And the overall electric field of the drift region is lifted, so that the voltage resistance of the device is improved.

An electronic device may include a buried shield (426) and a gap region (452). The electronic device may include a body contact region (1826), a deep body region (1046), or both. The deep body region may be separated from the gap interval and does not cause RSP reduction. The combination of the body contact region and the deep body region may form a stepped conductive structure to couple the buried shield and the source terminal to each other. In one implementation, a body contact region, a deep body region, or another p-type doped region may be spaced from a gate member (2930) by at least a minimum distance to improve long term reliability of a gate dielectric layer (2814). When designing an electronic device, the minimum distance may be applied as a design rule.

A method of an electronic device is provided. The method includes obtaining, from a memory of the electronic device, information indicating a usage relationship between distinct states of a user of the electronic device and at least one body part, identifying a first state of the user corresponding to a first function among a plurality of functions executable by the electronic device, identifying an event for executing a second function different from the first function, comparing, in response to identifying the event, a first body part used by the user associated with the first state and a second body part used by the user associated with a second state corresponding to the second function, based on the obtained information, and executing, in response to the identified event, a third function indicated in the information as being associated with the second function, based on a result of the comparing.

Flexible acoustic sensor systems using an acoustic lens are disclosed. In some embodiments, an apparatus may include: a platen having an imaging portion associated with a surface of the platen; a flexible substrate including an acoustic sensing element; and an acoustic lens disposed between the platen and the flexible substrate, the acoustic lens having a curvature configured to expand a propagation angle range of one or more acoustic signals emitted from the acoustic sensing element such that an area associated with the imaging portion is larger than an area associated with the acoustic sensing element; wherein the flexible substrate is constructed to conform to the curvature of the acoustic lens. In some implementations, the platen may include a curved platen having a curved surface configured to contact the body part of the user; and the flexible substrate may be constructed to conform to a curvature of the curved platen.

A hybrid trench Schottky trench-type superbarrier diode and its fabrication method are disclosed. This relates to the field of semiconductor technology. From bottom to top, the diode comprises: a cathode electrode layer, an N+ substrate layer, an N- epitaxial layer, wherein the N- epitaxial layer has a plurality of spaced-apart P-type implantation regions; each P-type implantation region includes conductive channels and P-body regions spaced-apart from top to bottom; a dielectric layer, a silicon dioxide layer, wherein the silicon dioxide layer has a plurality of trenches extending downward from its top to the P-body regions; and an anode electrode layer, the bottom of which extends to the P-body regions through trenches. This invention improves the on-resistance characteristics of the device during forward operation, thereby enhancing the device's performance and reliability.

The invention relates to a method for manufacturing a silicon carbide power electronic device with improved input capacitance definition of the silicon carbide power electronic device. A method of manufacturing a vertical conductive power device is provided. An example includes forming a body region of a second conductivity opposite to a first conductivity in a body including a semiconductor material and of the first conductivity; forming a source region of a first conductivity in the respective body region; forming gate structures, each including an insulated gate region, a conductive gate region on the insulated gate region, and a passivated gate region on the conductive gate region, where the conductive gate region partially overlaps the source region of a corresponding adjacent body region; and forming source metallization regions on the body and the gate structures including contact portions between adjacent gate structures with respective source regions. Forming the contact portion includes: forming a spacer dielectric layer on the gate structure and the body; and anisotropically etching the spacer dielectric layer up to the source region.

A field-effect transistor (FET) and a radio-frequency module are provided comprising an active region comprising a source region, a drain region, a body region disposed between the source region and the drain region, a first body extension portion in contact with the body region, a second body extension portion in contact with the body region, and a body contact region in contact with the first extension portion and the second extension portion; and a gate disposed on a top surface of the body region. A die is also provided comprising two or more such FETs.

An electronic apparatus may include: a sensor; a communicator configured to receive an Ultra Wide-Band (UWB) signal; memory storing at least one instruction; and at least one processor operatively connected to the sensor, the communicator, and the memory, wherein the at least one instruction, when executed by the at least one processor individually or collectively, causes the electronic apparatus to: obtain a first candidate location corresponding to a location of an external device, based on the UWB signal received by the communicator; based on a first image obtained through the sensor, obtain a second candidate location corresponding to at least one body part in the first image; obtain location information of a user body part of a user corresponding to the external device based on the first candidate location and the second candidate location; and generate a second image based on the location information.

Wave gear (1) with a ring-shaped, fixed, internally toothed gear (2), a flexible, externally toothed gear (3) arranged inside the internally toothed gear (2), and a wave generator (4) which is inserted into the externally toothed gear (3), wherein the flexible, externally toothed gear (3) has a flexible, cylindrical body region (301) and an annular membrane (302) extending radially from a rear end (301a) of the cylindrical body region (301), and wherein a toothed region formed in a region of the cylindrical body region (301) near an open region at the front end (301b) is deformed into an elliptical shape by the wave generator (4) over a region extending from a rear end region near the diaphragm (302) to a front end region near the opening, such that the deformation is substantially proportional to the distance from the diaphragm (302), wherein the wave gear (1) has a compound tooth profile which is engaged during positive deformation, wherein: the fixed, internally toothed gear (2) is designed as a spur gear with a module (m); the flexible, externally toothed gear (3) is designed as a spur gear with a module (m); a number of teeth of the flexible, externally toothed gear (3) is smaller by the size 2n, where n is a positive integer, than the number of teeth of the fixed, internally toothed gear (2); the deformation of a principal axis of an elliptical boundary neutral line of the flexible, externally toothed gear (3) in a cross-section which is perpendicular to an axis and is hereinafter referred to as the principal cross-sectional area, and which is selected at a predetermined position of the toothing of the flexible, externally toothed gear (3) in a tooth path direction, is set to 2κmn (κ>1); the engagement of the teeth of the fixed, internally toothed gear (2) and the flexible, externally toothed gear (3) in the main cross-sectional area is approximated by rack engagement in order to calculate a motion position curve (M) of the teeth of the flexible, externally toothed gear (3) in relation to the teeth of the fixed, internally toothed gear (2) in connection with a rotation of the shaft generator (4); characterized by the fact that a curve region (AB) is obtained from a region of the motion position curve (M) extending from the main axis of the deepest engagement position of the two gears (2, 3) to a side where the engagement of the teeth is disengaged, such that the curve region (AB) begins at position (A) of the deepest engagement of the two gears (2, 3), which is the position where the inclination angle is 90°, and reaches a position (B) where the inclination angle of the motion position curve (M) relative to a radial line of the fixed, internally toothed gear (2) is α° (0°<α°<30°); and a main area of ​​the tooth profile (30) of the flexible, externally toothed gear (3) is defined by a first similarity transformation curve (AC) in which the curve area (AB) is enlarged by a multiple of λ, and by a straight line (33) smoothly connected to an endpoint of the first similarity transformation curve (AC); a main region of a tooth profile (20) of the fixed, internally toothed gear (2) by a second similarity transformation curve (AD) in which the curve region (AB) is enlarged by a multiple of (λ+1), and is defined by a straight line (24) smoothly connected to an endpoint of the second similarity transformation curve (AD); and a value of λ is less than a maximum value of λ, where the maximum value of λ is obtained when the curve region (AB) is subjected to a similarity transformation with the factor (λ+1), where the origin of the similarity transformation of the curve region (AB) is placed at the position of the deepest intervention (A), such that a remote end of the second similarity transformation curve (AD) is arranged on the motion position curve (M).

The application discloses a super-junction LDMOS device with high-resistance substrate TSV grounding and a manufacturing method thereof. The super-junction LDMOS device comprises a high-resistance substrate, a body region and a drift region formed in the high-resistance substrate, a body region contact region and a source region formed in the body region, a polysilicon gate formed on a substrate surface above the body region, and a drain region formed in the drift region. The drift region comprises a super-junction structure formed by a first column region and a second column region arranged at intervals in a gate width direction. A first buffer layer is arranged between the first column region and the drain region, a second buffer layer is arranged between the second column region and the drain region, and the first buffer layer and the second buffer layer are arranged to surround the drain region. The super-junction LDMOS device can effectively suppress substrate auxiliary effect, can realize optimal design of device breakdown voltage and on-resistance, and can reduce output capacitance of the device.

The invention discloses an IGBT (Insulated Gate Bipolar Translator) device with a reverse conducting characteristic and a manufacturing method thereof. The manufacturing method comprises the following steps: forming a terminal injection region on a silicon substrate through ion injection; defining an active region on the silicon substrate, and forming an active region trench in the active region; filling polycrystalline silicon in the active region trench, and forming a body region and a source region through ion implantation; forming a terminal area metal field plate, a grid electrode and an emitting electrode on the silicon substrate; forming a field stop layer and a collector layer on the back surface of the silicon substrate through ion implantation; and removing the collector layer in the predetermined region through a femtosecond laser trepanning process, and forming a back metal layer connecting the collector layer and the field stop layer through a back metal deposition process. According to the method, the wafer back photoetching technology is replaced by the femtosecond laser trepanning process, so that the equipment cost is reduced, and the fragment risk is greatly reduced.

Flexible attachment device for portable mobile devices on the body (4), characterized in that it comprises: - a flexible band (1) designed to enclose and be fixed to a part of a person's body (5); - at least one elastic element (2) designed to span at least one group of diagonally opposite corner regions of the mobile device (4) in the tensioned state and to fix the mobile device (4); - at least two guide elements (3) arranged on the flexible band (1), wherein the at least two guide elements (3) are arranged offset from each other in the width direction of the flexible band (1); wherein the at least two guide elements (3) are configured such that they impose a position limitation and path guidance on the tensioned elastic element (2), so that the stabilization and alignment of the mobile device (4) is primarily achieved by the force path guidance of the guide elements (3) and without the need for a rigid support plate; and wherein the guide elements (3) ensure that the direction of the principal clamping force generated by the elastic element (2) substantially coincides with the diagonal direction of the mobile device (4) in its predetermined orientation position in order to suppress any positional deviation of the mobile device (4).

A semiconductor device includes a first source region, a first sidewall body region, a gate region, a second source region and a link region formed in a substrate of a first conductivity type. The first source region and the second source region may be of the first conductivity type while the first sidewall body region and the link region may be of a second conductivity type opposite to the first conductivity type. The link region and the gate region are respectively disposed at a first side and a second side of the first source region. The first sidewall body region may be disposed below or underneath the first source region.

The invention relates to the technical field of battery manufacturing, and particularly discloses a gluing quality detection method and system. The gluing quality detection method comprises the following steps: driving a camera to return along the original path of a gluing track by using a robot which finishes gluing to carry out segmented shooting on the gluing track of a workpiece, so as to obtain a plurality of glue line images; performing parallel processing on the plurality of glue line images to obtain a plurality of colloid regions and obtain colloid boundary contours in the colloid regions; calculating a glue width mean value, a glue width standard deviation or a glue spacing mean value of the gluing track according to the glue boundary contours in the plurality of glue areas; and according to the glue width mean value, the glue width standard deviation or the glue spacing mean value, the gluing track quality is judged. The gluing robot is used for driving the camera to return along the gluing track along the original path for shooting, the camera moves along the whole gluing path and collects images through the track synchronous flying shooting technology, and the problem of detection blind areas caused by view limitation of large-size workpieces is fundamentally solved.

An immersive scene description is defined by a data structure containing information representing triggers and haptic effects. When a trigger occurs while the user is interacting with the immersive scene, parameters for the haptic effect are retrieved from the data structure and provided to the haptic actuator for rendering the haptic effect. These parameters determine at least the modality and perception of the haptic effect, and can determine at least some of the body parts to which the haptic effect should be applied. The modality relates to the type of haptic effect, such as temperature, vibration, pressure, or acceleration. Perception determines the haptic signal to be applied to the corresponding haptic actuator. This signal is generated or retrieved from a file or other device.