1456 results about "Body region" patented technology

The invention provides a high-reliability planar gate silicon carbide VDMOS and a preparation method thereof, and the method comprises the steps: depositing metal on the lower side surface of a silicon carbide substrate, and forming a drain metal layer; epitaxially growing on the upper side surface of the silicon carbide substrate to form a drift layer; a barrier layer is formed, etching and ion implantation are carried out, and a current sharing layer, a body region, a P-type well region and an N-type source region are formed; forming a barrier layer again, etching and depositing to form an insulating medium layer; a barrier layer is formed again, and etching and deposition are carried out to form a gate dielectric layer; the preparation method comprises the following steps: forming a barrier layer again, etching, depositing metal, forming a gate metal layer and a source metal layer, removing the barrier layer, and completing the preparation. The gate reliability of the device can be effectively improved, and the follow current loss and reverse recovery speed of a body diode can be effectively improved.

The invention provides a quasi-super junction planar gate silicon carbide VDMOS and a preparation method thereof, and the method comprises the steps: depositing metal on the lower side surface of a silicon carbide substrate, and forming a drain metal layer; performing epitaxial growth on the upper side surface of the silicon carbide substrate to form a drift layer; forming a barrier layer, etching, performing ion implantation, forming a plurality of N-type body regions and a plurality of diffusion regions, and forming a P-type well region, an N-type source region and a current sharing layer; re-forming a barrier layer, etching the barrier layer to form a through hole, and depositing to form a gate dielectric layer; a barrier layer is formed again, the barrier layer is etched to form a through hole, metal is deposited, and a gate metal layer is formed; the preparation method comprises the following steps of: re-forming a barrier layer, etching the barrier layer to form a through hole, depositing metal, forming a source metal layer, removing the barrier layer, and completing preparation, so that a quasi-super junction structure and a current sharing layer are constructed in the device, and the voltage endurance capability, the gate reliability and the conduction capability of the device can be effectively improved.

The invention discloses a cellular structure of a shield gate trench MOSFET and a manufacturing method thereof, the cellular structure of the shield gate trench MOSFET comprises a substrate, a drift region and an interlayer dielectric layer, the drift region is provided with a deep trench, and the deep trench is internally provided with a shield gate, an intermediate oxide layer and a control gate; a body region and a source region are formed at the upper part of the drift region through injection, the interlayer dielectric is provided with a source electrode contact hole which penetrates through the source region and extends into the body region, and highly doped contact regions are formed on the side wall and the bottom of the source electrode contact hole through injection; and a charge balance region is formed below the source electrode contact hole through high-energy ion implantation. According to the invention, by arranging the charge balance region, the lateral depletion of the shield gate to the adjacent drift region can be enhanced when the shield gate trench MOSFET device is in a reverse bias state, the specific on-resistance of the device is reduced, the depletion of the drift region of the epitaxial layer is accelerated, and the reliability and radiation resistance of the device are improved.

The invention discloses an SJ-MOSFET device. The SJ-MOSFET device comprises a first conductive type substrate; a first conductive type epitaxial layer; a source region; a body region; a second conductive type doped column; the trench gate is arranged on the side surface of the second conductive type doped column and penetrates through the source region and the body region; and the trench pseudo gate is arranged on the side surface of the second conductive type doped column and penetrates through the source region and the body region. On the other hand, the invention discloses a manufacturing method. According to the invention, the grid electrode and the grid electrode groove are arranged on the side surface of the doped column, and a part of the grid electrode groove is arranged in the doped column, so that the area of the grid electrode groove occupying the MESA is small, and the grid electrode groove is arranged towards the interior of the doped column, so that the cell size and the pitch between two source electrode contact holes can be reduced to the greatest extent, and the performance of the MESA is improved. And meanwhile, no JFET resistor exists, so that the optimization of the on-resistance is realized.

The invention relates to a super junction power device and a preparation method thereof. The preparation method comprises the following steps: providing a silicon carbide substrate; a silicon carbide epitaxial layer is formed on the top surface of the silicon carbide substrate, the silicon carbide epitaxial layer has first type impurity ions, a plurality of doped columns are formed in the silicon carbide epitaxial layer, the doped columns have second type impurity ions, and the doped columns are formed through an etching process and an epitaxial process or through a multi-step epitaxial process and a multi-step ion implantation process; forming a body region in the surface, far away from the silicon carbide substrate, of the silicon carbide epitaxial layer, wherein the body region has second type impurity ions; forming a source region between the doped columns, wherein the source region is provided with a first type of foreign ions; forming a first groove penetrating through the source region and the body region between the adjacent doped columns, and forming a second groove penetrating through the body region above the doped columns; forming a gate structure in the first groove; and forming a source trench structure in the second trench. The on resistance of the super junction power device is reduced, and the voltage withstanding characteristic of the super junction power device is improved.

The utility model discloses a semiconductor device, which belongs to the field of semiconductors, and at least comprises a substrate; the well region is arranged in the substrate; the two drift regions are arranged in the well region at intervals, and shallow trench isolation structures are arranged in the drift regions; the body region is arranged in the well region between the two drift regions; the vertical grid electrode is located in the body region, and the vertical grid electrode extends into the well region from the surface of the substrate; the source doped regions are respectively arranged in the body regions on the two sides of the vertical grid electrode; the drain doping region is arranged in the drift region; and the planar grid electrode is arranged around the vertical grid electrode and the source doping region and covers part of the body region, part of the well region and part of the shallow trench isolation structure. According to the semiconductor device provided by the utility model, the characteristic on-resistance can be reduced and the performance of the semiconductor device can be improved under the condition that the breakdown voltage is not changed.

A target material removal (TMR) element is provided and includes a body region (112); thermal elements (120) within the body region (112); and vibration elements (130) within the body region (112). The TMR element is controlled to perform TMR operations that include one or more of the thermal elements (120) generating heat that is transmitted through the body region (112) to a target material in a manner that defines one or more zones of the target material. The TMR operations further include, subsequent to the one or more of the thermal elements (120) beginning generating the heat that is transmitted through the body region (112) to the target material, the one or more of the vibration elements (130) generating vibrations that are transmitted through the body region (112) to the one or more zones of the target material.

The present invention provides a metal molded article, a manufacturing method therefor, and an inspection device having same. The metal molded article has an overall length dimension in a longitudinal direction, an overall thickness dimension in a thickness direction perpendicular to the longitudinal direction, and an overall width dimension in a width direction perpendicular to the longitudinal direction. The metal molded article is divided into a first body region and a second body region in the thickness direction. The lateral surfaces of the first body region are provided with multiple micro-trenches that are grooves formed to be elongated in the thickness direction and arranged side by side all over the entire lateral surfaces of the first body region. The lateral surfaces of the second body region are not provided with these micro-trenches.

The invention relates to the technical field of power semiconductor devices, in particular to a power semiconductor device with a shield gate trench structure and a manufacturing method thereof, and the power semiconductor device comprises a drain electrode located at the bottom, an N + substrate located on the upper end face of the drain electrode, an N-drift region located on the upper end face of the N + substrate, a P-type body region located on the upper end face of the N-drift region, and a source electrode located at the top. By introducing the nano-composite super-junction shielding structure, optimizing the shape and the size of the groove and integrating the micro-nano fin structure and the reconfigurable self-adaptive shielding grid structure, the electric field distribution in the device can be remarkably improved, and the nano-particles in the nano-composite super-junction shielding structure, the P columns and the N columns have a synergistic effect; the reconfigurable self-adaptive shield grid structure adjusts the electric field in real time according to the working state, and the measures effectively relieve the groove electric field aggregation effect, so that the electric field distribution is more uniform, and the breakdown voltage and reliability of the device are improved.

The invention provides a semiconductor device and a manufacturing method thereof, the semiconductor device comprises a semiconductor layer and a trench gate, the trench gate is located in a trench of a first surface of the semiconductor layer, and the semiconductor layer comprises a body region, a source region and a drift region; the first buried layer is located at the bottom of the trench gate and connected with the trench gate, the third buried layer is connected with a part of the first buried layer in the width direction of the trench gate, and the third buried layer is further connected with a part of the body region. The first buried layer is arranged at the bottom of the trench gate, the voltage endurance capability is improved, and the first buried layer is electrically connected with the source region through the third buried layer, the body region and the source region in sequence, so that the electric field shielding function of the first buried layer to the bottom of the trench gate is more stable.

The invention relates to the technical field of semiconductors, in particular to a source heterojunction contact semiconductor structure and device and a manufacturing method, the semiconductor structure comprises a gate structure, a body region structure, a source structure and a drain structure, and the source structure comprises a polycrystalline silicon source contact layer; the semiconductor structure comprises a body region structure and a polycrystalline silicon source contact layer, the body region structure is surrounded by the gate structure, a source contact region is arranged in the body region structure, the polycrystalline silicon source contact layer is in contact with the source structure through the source contact region so as to form a heterojunction diode with the source structure, and the heterojunction diode is a freewheeling diode of the semiconductor structure. The drain electrode structure is located on one side, back to the gate electrode structure, of the body region structure; the semiconductor structure can be a SiC MOSFET structure, reverse conduction voltage drop during follow current of the SiC MOSFET can be greatly reduced, and conduction loss and loss caused during switching are reduced.

The invention relates to a super-junction vertical double-diffused metal oxide semiconductor device and a preparation method thereof. The super-junction vertical double-diffused metal oxide semiconductor device comprises a substrate structure; the super junction structure is arranged in the substrate structure; the super junction structure comprises first doped regions and second doped regions which are sequentially and alternately arranged along a first direction; the second doped region comprises a first sub-region and two second sub-regions which are arranged along the first direction, and the first sub-region is located between the two second sub-regions; the body region is arranged in the substrate structure; the body region is located on the side, close to the front face of the substrate structure, of the first doping region and connected with the first doping region. The source region is arranged in the body region; the grid electrode is arranged on the substrate structure; wherein the substrate structure, the first sub-region, the second sub-region and the source region are of a first conductive type, the doping concentration of the first sub-region is greater than that of the second sub-region, and the first doped region and the body region are of a second conductive type. The performance of the device can be improved.

The invention discloses a self-aligned double-epitaxial super-junction MOSFET and a manufacturing method, the self-aligned double-epitaxial super-junction MOSFET comprises a semiconductor layer arranged on a substrate, a plurality of body regions distributed along the surface of the semiconductor layer are arranged in the semiconductor layer, and a source region located below the surface of the semiconductor layer is arranged in each body region; the pair of first side walls are arranged on the surface of the semiconductor layer above each source region in a self-aligned manner; the super junction groove is arranged in the semiconductor layer in a penetrating manner between each pair of first side walls; the first epitaxial layer of the first conductive type and the second epitaxial layer of the second conductive type are arranged in the super junction groove and are connected with the body region; and the gate oxide layer and the gate electrode are arranged on the surface of the semiconductor layer between two adjacent pairs of first side walls. According to the invention, the range of ion implantation can be accurately adjusted while the number of photomasks is reduced and self-alignment is realized, and the drift region can be directly changed into the intrinsic semiconductor layer, so that the on-resistance can be reduced while the withstand voltage is improved.

The invention discloses a semiconductor device which comprises a cellular structure, and the cellular structure comprises an N + substrate, an N-drift layer and a functional area. The N-drift layer is located on the N + substrate; the functional region is embedded into one side, away from the N + substrate, of the N-drift layer, the functional region comprises two subunits and a second N + source region, and each subunit comprises a P + contact region, a P-type body region, a first N + source region and a first trench gate structure; the first N + source region is located on the P-type body region, the first groove is located between the P-type body region and the P + contact region, the first gate oxide layer covers the inner wall of the first groove, a first filling groove is formed in the inner wall of the first gate oxide layer, the first gate is filled in the first filling groove, and the P + shielding region of the P + contact region covers the bottom of the first gate oxide layer; and a second N + source region is arranged between the first trench gate structures of the two subunits. According to the device, the effective utilization rate of a channel can be improved, the specific on-resistance is further reduced, and the problem of long reverse recovery time is solved.

The invention provides a super-junction MOSFET structure and a preparation method thereof, and relates to the technical field of semiconductor devices. Comprising a first conductive type epitaxial layer formed on a first conductive type substrate layer; the second conduction type doped columns are formed in the middle area of the first conduction type epitaxial layer, the second conduction type doped columns comprise second preset conduction type doped columns and a plurality of second target conduction type doped columns located on the two sides of the lower surfaces of the second preset conduction type doped columns, and the second target conduction type doped columns are arranged at intervals; the second conduction type body region is formed on the second preset conduction type doped column; the plurality of first conductive type source regions are formed in the second conductive type body region and are arranged at intervals; gate oxide layers are formed in edge regions on two sides of the first conductive type epitaxial layer; the polycrystalline silicon layer is formed on the gate oxide layer; and sequentially forming a plurality of interlayer dielectric layers and metal layers on the polycrystalline silicon layer. And the failure risk caused by starting of an in-vivo parasitic NPN triode is reduced.

A transistor device includes: a semiconductor body having opposing first and second surfaces; an edge termination region laterally surrounding an active area; a drain region of a first conductivity type at the second surface; and a drift region of the first conductivity type on the drain region. In the active area, a body region of a second conductivity type is on the drift region, a source region of the first conductivity type is on the body region, and at least one gate electrode is positioned in a gate trench that extends into the semiconductor body from the first surface. A superjunction structure includes columns of the second conductivity type extending into the semiconductor body substantially perpendicular to the first surface in the active area and edge termination region. A first contact extends through the body region for each second conductivity type column in the active region and is electrically conductive.

The invention discloses a split gate IGBT (Insulated Gate Bipolar Translator) structure, and belongs to the field of semiconductor devices. Comprising collector metal, a P-type collector region, an N-type field stop layer and an N-type drift region which are sequentially arranged from bottom to top, an N-type storage layer, a P-type body region and emitter metal are sequentially arranged above the N-type drift region, an N + contact region is arranged in the P-type body region, a first oxide layer medium is arranged in the middle of the bottom of the emitter metal, a cross-shaped groove is formed in the N-type drift region, and a second oxide layer medium is arranged in the cross-shaped groove. The cross-shaped groove divides the N-type drift region, the N-type storage layer, the P-type body region and the N + contact region into a left part and a right part. The top of the cross-shaped groove is provided with a gate oxide layer, the bottom of the cross-shaped groove is provided with a second oxide layer medium, the top of the cross-shaped groove is provided with gate polycrystalline silicon which divides the gate oxide layer into a left part and a right part, and the left wide part and the right wide part of the cross-shaped groove are both internally provided with separation gate polycrystalline silicon. According to the split gate IGBT structure provided by the invention, the Miller capacitance and the conduction voltage drop can be effectively reduced.

The invention provides a preparation method of a piezoelectric resonator, and the method comprises the steps: providing a first wafer which is provided with an anchoring region used for cooperating to form an anchoring part and a release region used for providing a vibration space for a resonance main body, and the release region is formed around the anchoring region; patterning the first wafer to form a plurality of grooves in the release area; providing a second wafer, wherein the second wafer comprises a third insulating layer and a second silicon layer which are stacked; the second wafer and the first wafer are bonded, a second silicon layer covers the groove to form a cavity, and the second silicon layer is provided with a main body area right opposite to the cavity and an anchor point area right opposite to the anchoring area; carrying out thinning processing on the second wafer; forming a driving function layer on the second silicon layer; the second silicon layer is selectively removed to form a resonant body in the body region, and an anchor is formed in the anchor point region in cooperation with the anchor region. Therefore, the anchor point can be arranged in the middle of the resonance main body, so that the reliability of the device is improved.

The invention provides a semiconductor device and a manufacturing method thereof. The semiconductor device comprises a substrate; the two body regions are formed in the substrate, and a groove is formed in the substrate between the two body regions; the second epitaxial layer is formed on the substrate, and the second epitaxial layer extends to the side wall of the groove from a part of the body region; the source electrode region is formed in the body region, the source electrode region extends to the position below the second epitaxial layer from the side, away from the groove, of the second epitaxial layer, and the doping type of the substrate, the doping type of the second epitaxial layer and the doping type of the source electrode region are opposite to the doping type of the body region; the gate oxide layer is formed on the surface of the second epitaxial layer and the bottom wall of the groove; and the gate layer is formed on the gate oxide layer, and the gate layer extends from the gate oxide layer above the second epitaxial layer to the gate oxide layer on the side wall of the groove. According to the technical scheme, the performance of the device can be improved.

The invention discloses an MOSFET (Metal-Oxide-Semiconductor Field Effect Transistor) device and a preparation method thereof, and the MOSFET device comprises a substrate, an epitaxial layer located above the substrate, a drain electrode located below the substrate, a current expansion region located in the epitaxial layer, a well region located above the current expansion region, a source region located in the well region, and a body region located in the source region, the grooves are formed in the two ends of the epitaxial layer, the gate groove is formed in the center of the epitaxial layer, the gate dielectric layer is located in the grooves and the gate groove, the polycrystalline silicon is located on the surface of the gate dielectric layer, and the passivation layer is located on the upper surface of the epitaxial layer. The trench gate injection region is introduced into the MOSFET device and can be used for modulating an internal electric field of the device, so that gate-oxide breakdown is protected, meanwhile, the effective conduction area of the device can be increased, and the conduction capability of the device is improved. The device structure and the preparation method are simple, the effect is remarkable, high-performance and batch preparation and production of the groove type SiC MOSFET device can be achieved, and the device has huge market potential and wide application prospects.

The utility model provides a power semiconductor device, comprising a substrate which comprises a body region and a drift region which are arranged at an interval; the first well region is formed in the body region; the substrate leading-out region is formed in the body region, the first well region and the substrate leading-out region are arranged at intervals, the substrate leading-out region comprises a polycrystalline silicon body, the polycrystalline silicon body extends into the body region from the surface of the body region, and the vertical size of the polycrystalline silicon body is larger than the junction depth of the first well region; the first dielectric layer is arranged on the outer side of the polycrystalline silicon body, and the first well region and the polycrystalline silicon body are separated by the first dielectric layer; the second well region is formed in the drift region; the gate dielectric layer is arranged on the surface of the drift region, the gate dielectric layer is located between the body region and the second well region, and the gate dielectric layer is separated from the second well region; and the polysilicon gate layer is arranged on the surfaces of the gate dielectric layer, the drift region, the substrate and the body region. Without increasing the lateral dimension of the semiconductor device, the withstand voltage between the source electrode and the substrate can be improved.

The invention relates to a semiconductor device with a temperature sensor and a preparation method thereof, and the key points of the technical scheme are that the method comprises the steps: constructing a super-junction charge balance region on the surface of a substrate, and forming a body region at the top of the super-junction charge balance region; generating a first shallow trench and a second shallow trench on the body region; sequentially depositing an oxidation dielectric layer and first polycrystalline silicon in each of the first shallow trench and the second shallow trench; etching the first polycrystalline silicon in the second shallow trench, and depositing second polycrystalline silicon above the first polycrystalline silicon in the second shallow trench; depositing a dielectric layer on the surface of the body region, and etching in the dielectric layer to form a contact hole; the contact hole is communicated with the first polycrystalline silicon and the second polycrystalline silicon; the temperature detection diode structure is integrated in the epitaxial material of the device, and the problem that the internal thermal characteristics of the device cannot be fed back in time is solved by improving the manufacturing process under the condition that the characteristics of the device are not influenced by utilizing the linear relation between the forward conduction voltage and the temperature of the diode.

The utility model discloses a SiC MOS with a better gate protection structure, and relates to the technical field of semiconductors. Comprising a SiC Sub layer and a SiC Epi layer which are arranged from bottom to top; the SiC Epi layer is provided with: a P-body region, which extends downwards from the top surface of the SiC Epi layer; the NP region extends downwards from the top surface of the P-body region; the PP region extends downwards from the top surface of the P-body region and is connected with the NP region; the P-shield region extends downwards from the top surface of the P-body region, and a distance is formed between the P-shield region and the P-body region; the N + region extends downwards from the top surface of the P-shield region; the grid ohmic contact alloy layer is formed on the top surface of the P-shield region, and the bottom surface of the grid ohmic contact alloy layer is respectively connected with the P-shield region and the N + region; the gate oxide layer is connected with the gate ohmic contact alloy layer, and the bottom of the gate oxide layer is connected with the NP region, the P-body region and the SiC Epi layer; the top surface of the gate oxide layer is lower than the bottom surface of the gate ohmic contact alloy layer; according to the utility model, a good protection effect on the gate oxide layer of the SiC MOSFET device is realized, and the reliability of the gate oxide layer of the device is improved.

The invention provides an LDMOS (Laterally Diffused Metal Oxide Semiconductor) device and a manufacturing method thereof. The method comprises the following steps: providing a semiconductor substrate; a photoresist layer with an opening is formed on the surface of the semiconductor substrate, the opening at least exposes the surface of a region, where a drain region is predetermined to be formed, of the semiconductor substrate, the photoresist layer covers part of the surface corresponding to the first region, and the body region is predetermined to be located on the side, away from the drain region, of the drift region; performing first-time first conduction type ion implantation on at least the first region exposed from the opening; performing a finishing process on the photoresist layer to enlarge the opening; taking the trimmed photoresist layer as a mask, and at least executing second-time first conductive type ion implantation on the first region exposed out of the opening; the trimming process and the first conduction type ion implantation step are repeatedly executed at least once, the drift region comprises a plurality of implantation regions with different doping concentrations, and the doping concentrations of the plurality of implantation regions are gradually reduced in the direction from the drain region to the body region, so that the breakdown voltage is improved, and the specific on-resistance is reduced.

A semiconductor device includes a current spreading layer, a gate trench, a gate electrode, a first body region, a first source region, a second body region and a second source region. The first body region is beneath and in contact with the gate trench. The first source region is formed in the first body region. The second body region extends from a first surface of the current spreading layer into the current spreading layer and adjoins a first sidewall of the gate trench. The second source region is formed in the second body region and adjoins the first sidewall of the gate trench.

The invention discloses a semiconductor structure and a forming method thereof, and the method comprises the steps: providing a substrate which comprises a first surface; forming an epitaxial layer on the first surface; forming a first photoresist layer on the epitaxial layer; etching the epitaxial layer by taking the first photoresist layer as a mask to form a groove located in the first region; forming a first doped column in the groove and a second doped column in the second region, wherein the first doped column and the second doped column are arranged along a second direction; forming a second photoresist layer with a body region pattern on the epitaxial layer; and injecting ions into the epitaxial layer by taking the second photoresist layer as a mask to form body regions, and arranging the body regions along the first direction. The body region, the first doped column and the second doped column are located in the different directions of the epitaxial layer respectively, the situation that the space size of the super-junction MOS tube device is limited by the existence of the first doped column and the second doped column is avoided, the channel length of the super-junction MOS tube device is not limited by the space size, and then the channel length is increased.

The invention provides an LDMOS (Laterally Diffused Metal Oxide Semiconductor) device and a preparation method thereof. The LDMOS device comprises a semiconductor substrate; the first well region and the second well region are arranged in the semiconductor substrate, and the first well region and the second well region are arranged adjacently; the body region is arranged in the second well region; the source region is arranged in the body region; the body extraction region and the Schottky region are arranged in the body region and are adjacent to the source region, a metal layer is formed on the Schottky region, and the Schottky region is in contact with the metal layer to form a Schottky diode; the drain region is arranged in the first well region; and the gate structure is formed on the surface of the semiconductor substrate. According to the invention, the device has a lower ESD trigger voltage in an ESD event, and the ESD protection capability of the device is greatly improved.

The invention relates to the technical field of silicon carbide semiconductor devices, in particular to an integrally-formed equal-depth double-groove SiC MOSFET structure and a preparation method thereof. According to the structure, an N + buffer layer and an N-drift layer are sequentially formed on an N-type SiC substrate, and a main groove and an auxiliary groove which are consistent in depth are formed in the surface of the N-type SiC substrate; a gate oxide layer and a polycrystalline silicon gate are sequentially formed in the main groove, and the auxiliary groove is filled with a SiC epitaxial material which is doped with the drift layer in the same type, so that a charge compensation and electric field regulation and control unit is formed; the P-type body region surrounds the trench structure and forms an N + source region, and the drain electrode is formed through a back metallization process. Through the collaborative design of the equal-depth double grooves, the uniformization of electric field distribution is realized, the on-resistance and the switching loss are effectively reduced, the thermal stability and the reliability of the device are improved, the integrated process is adopted for integration, the process is simplified, the production efficiency and the yield are improved, and the semiconductor device is suitable for high-frequency and high-voltage application scenes and has a wide industrialization prospect.

The invention discloses an IGBT structure and a manufacturing method thereof, and a semiconductor device, and the IGBT structure comprises a substrate, a drift region of a first conduction type, a field cut-off region of the first conduction type, a collector region of a second conduction type, a plurality of trench gates, a body region of the second conduction type, an emitter region of the first conduction type, and a protection ring of the first conduction type. The substrate comprises an active region and a terminal region located on the outer side of the active region, the field cut-off region is arranged on the side, facing the first surface, of the drift region, the collector region is arranged on the side, facing the first surface, of the field cut-off region, and the field cut-off region comprises a first field cut-off region located in the active region and a second field cut-off region located in the terminal region; and the doping concentration of at least partial region of the second field stop region is greater than that of the first field stop region. According to the IGBT structure, the manufacturing method thereof and the semiconductor device, the turn-off loss can be effectively reduced, and the conduction voltage drop cannot be influenced.

The present application provides a semiconductor device and a manufacturing method thereof, wherein the device comprises: a body region, adjacent to the sidewall of the trench gate; an epitaxial layer, at least a portion of the epitaxial layer is located between the body region and the second surface, and adjacent to the trench gate and the body region, wherein the trench comprises a first trench extending from the first surface of the semiconductor layer to the second surface and a second trench located at the bottom of the first trench and connected to the first trench, the cross-sectional shape of the second trench is circular or elliptical, and at least a portion of the sidewall of the second trench is adjacent to the body region. The semiconductor device and the manufacturing method thereof of the present application increase the length of the channel by forming a second trench with a circular or elliptical cross-sectional shape at the bottom of the first trench and making the second trench at least partially adjacent to the body region.