1110 results about "Body region" patented technology

The invention relates to a super junction power device and a preparation method thereof. The preparation method comprises the following steps: providing a silicon carbide substrate; a silicon carbide epitaxial layer is formed on the top surface of the silicon carbide substrate, the silicon carbide epitaxial layer has first type impurity ions, a plurality of doped columns are formed in the silicon carbide epitaxial layer, the doped columns have second type impurity ions, and the doped columns are formed through an etching process and an epitaxial process or through a multi-step epitaxial process and a multi-step ion implantation process; forming a body region in the surface, far away from the silicon carbide substrate, of the silicon carbide epitaxial layer, wherein the body region has second type impurity ions; forming a source region between the doped columns, wherein the source region is provided with a first type of foreign ions; forming a first groove penetrating through the source region and the body region between the adjacent doped columns, and forming a second groove penetrating through the body region above the doped columns; forming a gate structure in the first groove; and forming a source trench structure in the second trench. The on resistance of the super junction power device is reduced, and the voltage withstanding characteristic of the super junction power device is improved.

The utility model discloses a semiconductor device, which belongs to the field of semiconductors, and at least comprises a substrate; the well region is arranged in the substrate; the two drift regions are arranged in the well region at intervals, and shallow trench isolation structures are arranged in the drift regions; the body region is arranged in the well region between the two drift regions; the vertical grid electrode is located in the body region, and the vertical grid electrode extends into the well region from the surface of the substrate; the source doped regions are respectively arranged in the body regions on the two sides of the vertical grid electrode; the drain doping region is arranged in the drift region; and the planar grid electrode is arranged around the vertical grid electrode and the source doping region and covers part of the body region, part of the well region and part of the shallow trench isolation structure. According to the semiconductor device provided by the utility model, the characteristic on-resistance can be reduced and the performance of the semiconductor device can be improved under the condition that the breakdown voltage is not changed.

The present invention provides a metal molded article, a manufacturing method therefor, and an inspection device having same. The metal molded article has an overall length dimension in a longitudinal direction, an overall thickness dimension in a thickness direction perpendicular to the longitudinal direction, and an overall width dimension in a width direction perpendicular to the longitudinal direction. The metal molded article is divided into a first body region and a second body region in the thickness direction. The lateral surfaces of the first body region are provided with multiple micro-trenches that are grooves formed to be elongated in the thickness direction and arranged side by side all over the entire lateral surfaces of the first body region. The lateral surfaces of the second body region are not provided with these micro-trenches.

The invention relates to the technical field of power semiconductor devices, in particular to a power semiconductor device with a shield gate trench structure and a manufacturing method thereof, and the power semiconductor device comprises a drain electrode located at the bottom, an N + substrate located on the upper end face of the drain electrode, an N-drift region located on the upper end face of the N + substrate, a P-type body region located on the upper end face of the N-drift region, and a source electrode located at the top. By introducing the nano-composite super-junction shielding structure, optimizing the shape and the size of the groove and integrating the micro-nano fin structure and the reconfigurable self-adaptive shielding grid structure, the electric field distribution in the device can be remarkably improved, and the nano-particles in the nano-composite super-junction shielding structure, the P columns and the N columns have a synergistic effect; the reconfigurable self-adaptive shield grid structure adjusts the electric field in real time according to the working state, and the measures effectively relieve the groove electric field aggregation effect, so that the electric field distribution is more uniform, and the breakdown voltage and reliability of the device are improved.

The invention relates to the technical field of semiconductors, in particular to a source heterojunction contact semiconductor structure and device and a manufacturing method, the semiconductor structure comprises a gate structure, a body region structure, a source structure and a drain structure, and the source structure comprises a polycrystalline silicon source contact layer; the semiconductor structure comprises a body region structure and a polycrystalline silicon source contact layer, the body region structure is surrounded by the gate structure, a source contact region is arranged in the body region structure, the polycrystalline silicon source contact layer is in contact with the source structure through the source contact region so as to form a heterojunction diode with the source structure, and the heterojunction diode is a freewheeling diode of the semiconductor structure. The drain electrode structure is located on one side, back to the gate electrode structure, of the body region structure; the semiconductor structure can be a SiC MOSFET structure, reverse conduction voltage drop during follow current of the SiC MOSFET can be greatly reduced, and conduction loss and loss caused during switching are reduced.

The invention discloses a semiconductor device which comprises a cellular structure, and the cellular structure comprises an N + substrate, an N-drift layer and a functional area. The N-drift layer is located on the N + substrate; the functional region is embedded into one side, away from the N + substrate, of the N-drift layer, the functional region comprises two subunits and a second N + source region, and each subunit comprises a P + contact region, a P-type body region, a first N + source region and a first trench gate structure; the first N + source region is located on the P-type body region, the first groove is located between the P-type body region and the P + contact region, the first gate oxide layer covers the inner wall of the first groove, a first filling groove is formed in the inner wall of the first gate oxide layer, the first gate is filled in the first filling groove, and the P + shielding region of the P + contact region covers the bottom of the first gate oxide layer; and a second N + source region is arranged between the first trench gate structures of the two subunits. According to the device, the effective utilization rate of a channel can be improved, the specific on-resistance is further reduced, and the problem of long reverse recovery time is solved.

A transistor device includes: a semiconductor body having opposing first and second surfaces; an edge termination region laterally surrounding an active area; a drain region of a first conductivity type at the second surface; and a drift region of the first conductivity type on the drain region. In the active area, a body region of a second conductivity type is on the drift region, a source region of the first conductivity type is on the body region, and at least one gate electrode is positioned in a gate trench that extends into the semiconductor body from the first surface. A superjunction structure includes columns of the second conductivity type extending into the semiconductor body substantially perpendicular to the first surface in the active area and edge termination region. A first contact extends through the body region for each second conductivity type column in the active region and is electrically conductive.

The utility model provides a power semiconductor device, comprising a substrate which comprises a body region and a drift region which are arranged at an interval; the first well region is formed in the body region; the substrate leading-out region is formed in the body region, the first well region and the substrate leading-out region are arranged at intervals, the substrate leading-out region comprises a polycrystalline silicon body, the polycrystalline silicon body extends into the body region from the surface of the body region, and the vertical size of the polycrystalline silicon body is larger than the junction depth of the first well region; the first dielectric layer is arranged on the outer side of the polycrystalline silicon body, and the first well region and the polycrystalline silicon body are separated by the first dielectric layer; the second well region is formed in the drift region; the gate dielectric layer is arranged on the surface of the drift region, the gate dielectric layer is located between the body region and the second well region, and the gate dielectric layer is separated from the second well region; and the polysilicon gate layer is arranged on the surfaces of the gate dielectric layer, the drift region, the substrate and the body region. Without increasing the lateral dimension of the semiconductor device, the withstand voltage between the source electrode and the substrate can be improved.

The invention relates to a semiconductor device with a temperature sensor and a preparation method thereof, and the key points of the technical scheme are that the method comprises the steps: constructing a super-junction charge balance region on the surface of a substrate, and forming a body region at the top of the super-junction charge balance region; generating a first shallow trench and a second shallow trench on the body region; sequentially depositing an oxidation dielectric layer and first polycrystalline silicon in each of the first shallow trench and the second shallow trench; etching the first polycrystalline silicon in the second shallow trench, and depositing second polycrystalline silicon above the first polycrystalline silicon in the second shallow trench; depositing a dielectric layer on the surface of the body region, and etching in the dielectric layer to form a contact hole; the contact hole is communicated with the first polycrystalline silicon and the second polycrystalline silicon; the temperature detection diode structure is integrated in the epitaxial material of the device, and the problem that the internal thermal characteristics of the device cannot be fed back in time is solved by improving the manufacturing process under the condition that the characteristics of the device are not influenced by utilizing the linear relation between the forward conduction voltage and the temperature of the diode.

The utility model discloses a SiC MOS with a better gate protection structure, and relates to the technical field of semiconductors. Comprising a SiC Sub layer and a SiC Epi layer which are arranged from bottom to top; the SiC Epi layer is provided with: a P-body region, which extends downwards from the top surface of the SiC Epi layer; the NP region extends downwards from the top surface of the P-body region; the PP region extends downwards from the top surface of the P-body region and is connected with the NP region; the P-shield region extends downwards from the top surface of the P-body region, and a distance is formed between the P-shield region and the P-body region; the N + region extends downwards from the top surface of the P-shield region; the grid ohmic contact alloy layer is formed on the top surface of the P-shield region, and the bottom surface of the grid ohmic contact alloy layer is respectively connected with the P-shield region and the N + region; the gate oxide layer is connected with the gate ohmic contact alloy layer, and the bottom of the gate oxide layer is connected with the NP region, the P-body region and the SiC Epi layer; the top surface of the gate oxide layer is lower than the bottom surface of the gate ohmic contact alloy layer; according to the utility model, a good protection effect on the gate oxide layer of the SiC MOSFET device is realized, and the reliability of the gate oxide layer of the device is improved.

The invention relates to the technical field of silicon carbide semiconductor devices, in particular to an integrally-formed equal-depth double-groove SiC MOSFET structure and a preparation method thereof. According to the structure, an N + buffer layer and an N-drift layer are sequentially formed on an N-type SiC substrate, and a main groove and an auxiliary groove which are consistent in depth are formed in the surface of the N-type SiC substrate; a gate oxide layer and a polycrystalline silicon gate are sequentially formed in the main groove, and the auxiliary groove is filled with a SiC epitaxial material which is doped with the drift layer in the same type, so that a charge compensation and electric field regulation and control unit is formed; the P-type body region surrounds the trench structure and forms an N + source region, and the drain electrode is formed through a back metallization process. Through the collaborative design of the equal-depth double grooves, the uniformization of electric field distribution is realized, the on-resistance and the switching loss are effectively reduced, the thermal stability and the reliability of the device are improved, the integrated process is adopted for integration, the process is simplified, the production efficiency and the yield are improved, and the semiconductor device is suitable for high-frequency and high-voltage application scenes and has a wide industrialization prospect.

An electronic device may include a communication interface, a memory storing one or more instructions, and at least one processor configured to execute the one or more instructions, wherein the at least one processor may be configured to execute the one or more instructions to obtain sensing information for controlling an avatar from a plurality of external devices corresponding to body parts, through the communication interface, determine action information indicating an action that is implementable in relation to a corresponding body part, based on the sensing information, and control the avatar, based on the determined action information.

A trench gate power MOSFET, including: a substrate provided with a hexagonal wide bandgap semiconductor of a first conductivity type; an epitaxial layer grown on the substrate and of the first conductivity type; a body region formed on the epitaxial layer and of a second conductivity type; a trench formed in the body region by etching, where a length direction of the trench is parallel to a projection, on the surface of a wafer, of the C axis; a second conductivity-type pillar formed by implanting first ions into a bottom region of the trench along the C axis of the hexagonal wide bandgap semiconductor material, where the bottom region of the trench is located below the trench, and is connected to the bottom of the trench, and the longitudinal depth of the second conductivity-type pillar is at least not less than 50% of the thickness of the epitaxial layer located in the bottom region of the trench; and a trench gate formed by filling the trench with a filler.

The invention discloses a semiconductor structure and a forming method thereof. The semiconductor structure comprises a substrate; the drift region is located in the substrate, first type doping ions are arranged in the drift region, the drift region comprises a plurality of sub-drift regions with different doping ion concentrations, any sub-drift region close to one side of the top surface of the substrate is located in the other adjacent sub-drift region and points to the top surface of the substrate along the bottom surface of the substrate, and the doping ion concentrations of the sub-drift regions are gradually increased; the first body region is positioned in the substrate at the side part of the drift region, and the first body region is internally provided with second type doping ions; the gate structure is located on the substrate and covers part of the drift region and part of the first body region; and the drain doped region is positioned on one side of the gate structure and is positioned in the sub-drift region with the maximum doped ion concentration in the drift region. The doping ion concentration of each sub drift region is increased progressively, so that the average concentration of the doping ions of the drift region is increased, and the on-resistance of the semiconductor structure is reduced.

The disclosure relates to a semiconductor die with a semiconductor body. The semiconductor die includes: a vertical transistor device with a first load region and a second load region at opposite sides of the semiconductor body; an additional transistor device with a source region at a first side of the semiconductor body, a gate trench, a body region aside the gate trench, and a drain region below the body region; an electrical isolation in the semiconductor body; and a vertical contact element extending from the first side into the semiconductor body. The electrical isolation is arranged laterally between the vertical transistor device and the additional transistor device. The vertical contact element makes electrical contact to the drain region of the additional transistor device and connects the drain region to the first side of the semiconductor body.

A method of making a semiconductor device includes providing semiconductor region of a first conductivity type. A first region comprising the first conductivity type and a second dopant concentration greater than the first dopant concentration is provided within the region. The first region provides a JFET channel region for a JFET device. A second region comprising a second conductivity type is provided within the first region. The second region provides a body region for a MOSFET device and a gate region for the JFET device. The second region comprises a first portion and a second portion below the first portion. The second portion has a higher peak dopant concentration than the first portion. A third region comprising the first conductivity type is provided within and self-aligned to the second region. The third region provides a JFET source for the JFET device.

A semiconductor device is provided which is a trench MOSFET with a vertical channel fin structure, capable of improving short-circuit tolerance and reducing gate capacitance while maintaining high channel density.A semiconductor 1 is configured so that a channel current flows in the vertical direction, and comprises: a plurality of trenches having a longitudinal direction in a first direction and a lateral direction in a second direction in plan view, the plurality of trenches being arranged in the second direction; a first source region 3 of a first conductivity type; a second source region 4 of the first conductivity type and including a region having a fin structure at least partially partitioned by the plurality of trenches 2; a channel region 5 of a second conductivity type and having a fin structure partitioned by the plurality of trenches 2; a gate insulating film and gate electrodes disposed in the trenches 2; and a JFET region 8 of the first conductivity type and a body region 9 of the second conductivity type.The second source region 4 has a shallower depth from a surface than the first source region 3.

The embodiment of the invention discloses a semiconductor device and a manufacturing method thereof, the semiconductor device can comprise a silicon carbide body, a gate trench, a body region, a source region and a shielding region, and the gate trench is arranged on a first surface of the silicon carbide body; the body region forms part of the side wall of the gate trench; the source region forms part of the side wall of the gate trench, and the source region is located between the body region and the first surface; the shielding regions extend into the silicon carbide body from the first surface and are arranged on the two sides of the gate trenches, and each shielding region comprises a semi-surrounding shielding region located between any two adjacent gate trenches in the plurality of gate trenches; wherein the semi-surrounding shielding region forms the side wall and part of the bottom of one of the two gate trenches, and covers one side, far away from the body region, of the source region between the two gate trenches; and one side, far away from the semi-surrounding shielding region, in the source region between the two gate trenches is partially exposed to the other gate trench in the two gate trenches.

The invention provides a trench MOSFET and a manufacturing method thereof, and the method comprises the steps: forming a trench, a shield gate oxide layer, a control gate oxide layer, an isolation oxide layer, a shield gate, a control gate, a body region, a source region, and a dielectric layer; a first contact hole penetrating through the dielectric layer and the source region and extending into the body region and a second contact hole penetrating through the dielectric layer, the control gate and the isolation oxide layer and exposing the shield gate are formed, a subsequently formed source metal layer is electrically connected with the source region and the body region through the first contact hole, and a gate metal layer is electrically connected with the control gate and the shield gate through the second contact hole. When the trench MOSFET provided by the invention is in forward conduction, because the shield grid is connected to the control grid, an electron accumulation layer is formed on the side wall of the shield grid, so that the conduction resistance is reduced. Besides, in the manufacturing process of the trench MOSFET, the number of photomasks can be reduced, for example, only three photomasks corresponding to the trench, the contact hole and the metal layer respectively are needed, and the production cost can be reduced.

A switching element includes a semiconductor substrate having: an n-type drift region in contact with each of gate insulating films on a bottom surface and side surfaces of each of the trenches; a p-type body region in contact with the gate insulating films on the side surfaces of each of the trenches at a position above the n-type drift region; an n-type source region in contact with the gate insulating films on the side surfaces of each of the trenches at a position above the p-type body region, the n-type source region being separated away from the n-type drift region by the p-type body region; plurality of p-type bottom regions each of which is located under a corresponding one of the trenches and located away from a corresponding one of the gate insulating films; and a p-type connection region that connects the p-type bottom regions and the p-type body region.

The invention provides a silicon carbide MOSFET (Metal-Oxide-Semiconductor Field Effect Transistor) integrated with an SCR (Selective Catalytic Reduction) and a manufacturing method thereof, and relates to the technical field of power semiconductor devices, the device is integrated with a PNPN four-layer structure consisting of a P + region, an N-type epitaxial layer, a P-type body region and an N + source region between a grid electrode and a source electrode, and the P + region is in metal ohmic contact with the source electrode. Through collaborative design of the distance and the doping concentration of the P + region and the N + source region, the forward and reverse trigger voltage thresholds of the PNPN structure can be accurately matched with the asymmetric driving window of the electric control main drive. The structure is arranged on the outer edge of a cellular area or a terminal area, and is electrically isolated from an active area, a field plate is arranged to suppress false triggering, ohmic contact is optimized to accelerate turn-off, and it is ensured that holding current is higher than parasitic latch triggering current, so that rapid and reliable discharge and self-protection of bidirectional surge between a gate and a source are achieved on the premise that the performance of a main device is not affected, and the reliability of the device is improved. And the gate oxide reliability is obviously improved.

In an embodiment, a vertical transistor device includes a semiconductor substrate having a first major surface and a second major surface opposing the first major surface. At least one transistor cell formed in the semiconductor substrate includes a fin having an upper surface and side walls. The fin includes a source region, a body region and a drift zone that are located along a length of the fin. The body region extends between the source region and the drift zone. The transistor cell further includes a gate arranged on the upper surface and the side walls of the fin. A source pad is located on the first major surface and a drain pad is located on the second major surface of the semiconductor substrate.

The invention discloses a charge compensation MOSFET with a graded epitaxial distribution and a method of manufacturing the same. A vertical power semiconductor transistor device includes: a drain region of a first conductivity type; a body region of a second conductivity type; a drift region of the first conductivity type separating the body region from the drain region; a source region of the first conductivity type separated from the drift region by the body region; a gate trench extending through the source region and the body region and into the drift region, the gate trench including a gate electrode; and a field electrode in the gate trench or in the separate trench. The drift region has a generally linearly tapered first doping profile that increases from the body region toward a bottom of the trench including the field electrode, and a tapered second doping profile that increases from an end of the first doping profile toward the drain region at a greater ratio than the first doping profile.

The invention provides an LDMOS (Laterally Diffused Metal Oxide Semiconductor) device and a preparation method thereof. The LDMOS device comprises a substrate; the first conductive type drift region and the second conductive type body region adjacent to the first conductive type drift region are both located in the substrate; the grid electrode is located on the first conduction type drift region and extends to the second conduction type body region; the groove is positioned in the first conduction type drift region and is self-aligned with the edge of the grid electrode; the side walls are located on the side edges of the two sides of the grid electrode and extend to the side edges of the groove; and the barrier layer fills the groove and extends to a part of the upper surface of the grid electrode. According to the LDMOS device, breakdown voltage is maintained and even improved, on-resistance is reduced, the length of the drift region is reduced, and the size of the device is further reduced.

A semiconductor device including a semiconductor substrate having upper and lower areas, the lower area including a lower layer having a first conductivity type; a first deep well region having the first conductivity type and being on the upper area; a connection layer having the first conductivity type and being on the first deep well region; a body region having the first conductivity type and a first drift region having a second conductivity type, the body region and the first drift region being side-by-side in a first direction on the connection layer; a first source region having the second conductivity type and being on the body region; a drain region having the second conductivity type and being on the upper area and spaced apart from the first drift region in the first direction; and a gate structure on the first drift region and being adjacent to the first source region.

The application discloses an integrated super-junction power MOS device with corrugated gate oxide and a preparation method thereof, and belongs to the technical field of semiconductors. The device comprises a substrate, a buffer layer and an epitaxial layer which are sequentially stacked from bottom to top; wherein the epitaxial layer is provided with a plurality of vertically spaced super-junction columns, and the top of each super-junction column is provided with a body region; the surface layer of the body region is provided with a contact hole doped region and a source doped region which are in contact with each other; the upper surface of the epitaxial layer is further provided with a gate oxide layer; the gate oxide layer is in a corrugated structure, and the lower surface of the gate oxide layer is adapted to and contacts with a corrugated groove located on the upper surface of the epitaxial layer, the body region and part of the source doped region; the upper surface of the gate oxide layer and part of the source doped region is covered with a polysilicon layer, and the gate oxide layer and the polysilicon layer form a corrugated gate structure. The integrated super-junction power MOS device with corrugated gate oxide has good single-particle burnout resistance and single-particle gate penetration resistance.

A switching element having multiple trench-type gate electrodes. The semiconductor substrate comprises: an n-type drift region in contact with a gate insulating film at the bottom and side surfaces of each trench; a p-type body region in contact with the gate insulating film above the drift region; multiple p-type bottom regions arranged directly below the trenches and spaced apart from the gate insulating film; and a p-type connection region connecting each of the bottom regions to the body region. Half the depletion layer extension distance required to deplete the gap between adjacent bottom regions is longer than both the depletion layer extension distance required to deplete the gap between the body region and the lower end of the trench and the depletion layer extension distance required to deplete the gap between the bottom region and the lower end of the trench.

The invention provides a groove type silicon carbide MOSFET device structure. The device structure comprises a silicon carbide substrate of a first doping type; a first doping type silicon carbide epitaxial layer on the upper surface of the silicon carbide substrate; the groove protection regions of the second doping type are arranged in the silicon carbide epitaxial layer in an array mode in the first direction, the tops of the groove protection regions are discontinuous in the second direction, and the first direction is perpendicular to the second direction; the body regions are arranged in an array in the first direction, are arranged between two adjacent groove protection regions, and extend in the second direction; the source regions are arranged in an array in the first direction, are arranged in the body region, and are discontinuous in the second direction; the one or two gate trenches are arranged between two adjacent trench protection regions, the gate trenches penetrate through the body region, gate oxide layers and polycrystalline silicon are arranged in the gate trenches, and the upper surface of the polycrystalline silicon is lower than the upper surface of the silicon carbide substrate; the interlayer dielectric layer extends along a second direction; and a front metal layer.

The invention discloses a high-speed IGBT device and a manufacturing method thereof. The high-speed IGBT device comprises a P-type collector region, an N-type drift region, a P-type body region, an N-type emitter region, a groove, an insulating dielectric layer and emitter metal. The trench which is in short circuit with the gate metal and is connected with the N-type emitter region is a gate trench, the trench which is in short circuit with the emitter metal is an emitter trench, and the trench which is in short circuit with the gate metal and is not connected with the N-type emitter region is a pseudo gate trench. The bottoms of the dummy gate trench and the emitter trench are provided with doped regions which are connected with each other, so that the potential of the bottom of the emitter trench can be pulled up by the potential of the bottom of the dummy gate trench. During switching, extra charges are provided for the potential at the bottom of the emitter trench, the potential at the bottom of the gate trench is maintained at a high level, the switching-off time is shortened, and the Vce voltage trailing phenomenon is reduced.

A process of forming an electronic device can form an accumulation channel or an integrated diode by selective doping parts of a workpiece. In an embodiment, a doped region can be formed by implanting a sidewall of a body region. In another embodiment, a doped region can correspond to a remaining portion of a semiconductor layer after forming another doped region by implanting into a contact opening. The accumulation channel or the integrated diode can lower the barrier for a body diode turn-on. Reduced stored charge and QRR may be achieved, leading to lower switching losses.