785 results about "Body region" patented technology

The invention relates to a super junction power device and a preparation method thereof. The preparation method comprises the following steps: providing a silicon carbide substrate; a silicon carbide epitaxial layer is formed on the top surface of the silicon carbide substrate, the silicon carbide epitaxial layer has first type impurity ions, a plurality of doped columns are formed in the silicon carbide epitaxial layer, the doped columns have second type impurity ions, and the doped columns are formed through an etching process and an epitaxial process or through a multi-step epitaxial process and a multi-step ion implantation process; forming a body region in the surface, far away from the silicon carbide substrate, of the silicon carbide epitaxial layer, wherein the body region has second type impurity ions; forming a source region between the doped columns, wherein the source region is provided with a first type of foreign ions; forming a first groove penetrating through the source region and the body region between the adjacent doped columns, and forming a second groove penetrating through the body region above the doped columns; forming a gate structure in the first groove; and forming a source trench structure in the second trench. The on resistance of the super junction power device is reduced, and the voltage withstanding characteristic of the super junction power device is improved.

The utility model discloses a semiconductor device, which belongs to the field of semiconductors, and at least comprises a substrate; the well region is arranged in the substrate; the two drift regions are arranged in the well region at intervals, and shallow trench isolation structures are arranged in the drift regions; the body region is arranged in the well region between the two drift regions; the vertical grid electrode is located in the body region, and the vertical grid electrode extends into the well region from the surface of the substrate; the source doped regions are respectively arranged in the body regions on the two sides of the vertical grid electrode; the drain doping region is arranged in the drift region; and the planar grid electrode is arranged around the vertical grid electrode and the source doping region and covers part of the body region, part of the well region and part of the shallow trench isolation structure. According to the semiconductor device provided by the utility model, the characteristic on-resistance can be reduced and the performance of the semiconductor device can be improved under the condition that the breakdown voltage is not changed.

The invention relates to the technical field of semiconductors, in particular to a source heterojunction contact semiconductor structure and device and a manufacturing method, the semiconductor structure comprises a gate structure, a body region structure, a source structure and a drain structure, and the source structure comprises a polycrystalline silicon source contact layer; the semiconductor structure comprises a body region structure and a polycrystalline silicon source contact layer, the body region structure is surrounded by the gate structure, a source contact region is arranged in the body region structure, the polycrystalline silicon source contact layer is in contact with the source structure through the source contact region so as to form a heterojunction diode with the source structure, and the heterojunction diode is a freewheeling diode of the semiconductor structure. The drain electrode structure is located on one side, back to the gate electrode structure, of the body region structure; the semiconductor structure can be a SiC MOSFET structure, reverse conduction voltage drop during follow current of the SiC MOSFET can be greatly reduced, and conduction loss and loss caused during switching are reduced.

The invention discloses a semiconductor device which comprises a cellular structure, and the cellular structure comprises an N + substrate, an N-drift layer and a functional area. The N-drift layer is located on the N + substrate; the functional region is embedded into one side, away from the N + substrate, of the N-drift layer, the functional region comprises two subunits and a second N + source region, and each subunit comprises a P + contact region, a P-type body region, a first N + source region and a first trench gate structure; the first N + source region is located on the P-type body region, the first groove is located between the P-type body region and the P + contact region, the first gate oxide layer covers the inner wall of the first groove, a first filling groove is formed in the inner wall of the first gate oxide layer, the first gate is filled in the first filling groove, and the P + shielding region of the P + contact region covers the bottom of the first gate oxide layer; and a second N + source region is arranged between the first trench gate structures of the two subunits. According to the device, the effective utilization rate of a channel can be improved, the specific on-resistance is further reduced, and the problem of long reverse recovery time is solved.

A transistor device includes: a semiconductor body having opposing first and second surfaces; an edge termination region laterally surrounding an active area; a drain region of a first conductivity type at the second surface; and a drift region of the first conductivity type on the drain region. In the active area, a body region of a second conductivity type is on the drift region, a source region of the first conductivity type is on the body region, and at least one gate electrode is positioned in a gate trench that extends into the semiconductor body from the first surface. A superjunction structure includes columns of the second conductivity type extending into the semiconductor body substantially perpendicular to the first surface in the active area and edge termination region. A first contact extends through the body region for each second conductivity type column in the active region and is electrically conductive.

The utility model provides a power semiconductor device, comprising a substrate which comprises a body region and a drift region which are arranged at an interval; the first well region is formed in the body region; the substrate leading-out region is formed in the body region, the first well region and the substrate leading-out region are arranged at intervals, the substrate leading-out region comprises a polycrystalline silicon body, the polycrystalline silicon body extends into the body region from the surface of the body region, and the vertical size of the polycrystalline silicon body is larger than the junction depth of the first well region; the first dielectric layer is arranged on the outer side of the polycrystalline silicon body, and the first well region and the polycrystalline silicon body are separated by the first dielectric layer; the second well region is formed in the drift region; the gate dielectric layer is arranged on the surface of the drift region, the gate dielectric layer is located between the body region and the second well region, and the gate dielectric layer is separated from the second well region; and the polysilicon gate layer is arranged on the surfaces of the gate dielectric layer, the drift region, the substrate and the body region. Without increasing the lateral dimension of the semiconductor device, the withstand voltage between the source electrode and the substrate can be improved.

The invention relates to the technical field of silicon carbide semiconductor devices, in particular to an integrally-formed equal-depth double-groove SiC MOSFET structure and a preparation method thereof. According to the structure, an N + buffer layer and an N-drift layer are sequentially formed on an N-type SiC substrate, and a main groove and an auxiliary groove which are consistent in depth are formed in the surface of the N-type SiC substrate; a gate oxide layer and a polycrystalline silicon gate are sequentially formed in the main groove, and the auxiliary groove is filled with a SiC epitaxial material which is doped with the drift layer in the same type, so that a charge compensation and electric field regulation and control unit is formed; the P-type body region surrounds the trench structure and forms an N + source region, and the drain electrode is formed through a back metallization process. Through the collaborative design of the equal-depth double grooves, the uniformization of electric field distribution is realized, the on-resistance and the switching loss are effectively reduced, the thermal stability and the reliability of the device are improved, the integrated process is adopted for integration, the process is simplified, the production efficiency and the yield are improved, and the semiconductor device is suitable for high-frequency and high-voltage application scenes and has a wide industrialization prospect.

The invention discloses a semiconductor structure and a forming method thereof. The semiconductor structure comprises a substrate; the drift region is located in the substrate, first type doping ions are arranged in the drift region, the drift region comprises a plurality of sub-drift regions with different doping ion concentrations, any sub-drift region close to one side of the top surface of the substrate is located in the other adjacent sub-drift region and points to the top surface of the substrate along the bottom surface of the substrate, and the doping ion concentrations of the sub-drift regions are gradually increased; the first body region is positioned in the substrate at the side part of the drift region, and the first body region is internally provided with second type doping ions; the gate structure is located on the substrate and covers part of the drift region and part of the first body region; and the drain doped region is positioned on one side of the gate structure and is positioned in the sub-drift region with the maximum doped ion concentration in the drift region. The doping ion concentration of each sub drift region is increased progressively, so that the average concentration of the doping ions of the drift region is increased, and the on-resistance of the semiconductor structure is reduced.

The disclosure relates to a semiconductor die with a semiconductor body. The semiconductor die includes: a vertical transistor device with a first load region and a second load region at opposite sides of the semiconductor body; an additional transistor device with a source region at a first side of the semiconductor body, a gate trench, a body region aside the gate trench, and a drain region below the body region; an electrical isolation in the semiconductor body; and a vertical contact element extending from the first side into the semiconductor body. The electrical isolation is arranged laterally between the vertical transistor device and the additional transistor device. The vertical contact element makes electrical contact to the drain region of the additional transistor device and connects the drain region to the first side of the semiconductor body.

A method of making a semiconductor device includes providing semiconductor region of a first conductivity type. A first region comprising the first conductivity type and a second dopant concentration greater than the first dopant concentration is provided within the region. The first region provides a JFET channel region for a JFET device. A second region comprising a second conductivity type is provided within the first region. The second region provides a body region for a MOSFET device and a gate region for the JFET device. The second region comprises a first portion and a second portion below the first portion. The second portion has a higher peak dopant concentration than the first portion. A third region comprising the first conductivity type is provided within and self-aligned to the second region. The third region provides a JFET source for the JFET device.

The invention provides a trench MOSFET and a manufacturing method thereof, and the method comprises the steps: forming a trench, a shield gate oxide layer, a control gate oxide layer, an isolation oxide layer, a shield gate, a control gate, a body region, a source region, and a dielectric layer; a first contact hole penetrating through the dielectric layer and the source region and extending into the body region and a second contact hole penetrating through the dielectric layer, the control gate and the isolation oxide layer and exposing the shield gate are formed, a subsequently formed source metal layer is electrically connected with the source region and the body region through the first contact hole, and a gate metal layer is electrically connected with the control gate and the shield gate through the second contact hole. When the trench MOSFET provided by the invention is in forward conduction, because the shield grid is connected to the control grid, an electron accumulation layer is formed on the side wall of the shield grid, so that the conduction resistance is reduced. Besides, in the manufacturing process of the trench MOSFET, the number of photomasks can be reduced, for example, only three photomasks corresponding to the trench, the contact hole and the metal layer respectively are needed, and the production cost can be reduced.

The invention provides a silicon carbide MOSFET (Metal-Oxide-Semiconductor Field Effect Transistor) integrated with an SCR (Selective Catalytic Reduction) and a manufacturing method thereof, and relates to the technical field of power semiconductor devices, the device is integrated with a PNPN four-layer structure consisting of a P + region, an N-type epitaxial layer, a P-type body region and an N + source region between a grid electrode and a source electrode, and the P + region is in metal ohmic contact with the source electrode. Through collaborative design of the distance and the doping concentration of the P + region and the N + source region, the forward and reverse trigger voltage thresholds of the PNPN structure can be accurately matched with the asymmetric driving window of the electric control main drive. The structure is arranged on the outer edge of a cellular area or a terminal area, and is electrically isolated from an active area, a field plate is arranged to suppress false triggering, ohmic contact is optimized to accelerate turn-off, and it is ensured that holding current is higher than parasitic latch triggering current, so that rapid and reliable discharge and self-protection of bidirectional surge between a gate and a source are achieved on the premise that the performance of a main device is not affected, and the reliability of the device is improved. And the gate oxide reliability is obviously improved.

In an embodiment, a vertical transistor device includes a semiconductor substrate having a first major surface and a second major surface opposing the first major surface. At least one transistor cell formed in the semiconductor substrate includes a fin having an upper surface and side walls. The fin includes a source region, a body region and a drift zone that are located along a length of the fin. The body region extends between the source region and the drift zone. The transistor cell further includes a gate arranged on the upper surface and the side walls of the fin. A source pad is located on the first major surface and a drain pad is located on the second major surface of the semiconductor substrate.

The invention discloses a charge compensation MOSFET with a graded epitaxial distribution and a method of manufacturing the same. A vertical power semiconductor transistor device includes: a drain region of a first conductivity type; a body region of a second conductivity type; a drift region of the first conductivity type separating the body region from the drain region; a source region of the first conductivity type separated from the drift region by the body region; a gate trench extending through the source region and the body region and into the drift region, the gate trench including a gate electrode; and a field electrode in the gate trench or in the separate trench. The drift region has a generally linearly tapered first doping profile that increases from the body region toward a bottom of the trench including the field electrode, and a tapered second doping profile that increases from an end of the first doping profile toward the drain region at a greater ratio than the first doping profile.

The invention provides an LDMOS (Laterally Diffused Metal Oxide Semiconductor) device and a preparation method thereof. The LDMOS device comprises a substrate; the first conductive type drift region and the second conductive type body region adjacent to the first conductive type drift region are both located in the substrate; the grid electrode is located on the first conduction type drift region and extends to the second conduction type body region; the groove is positioned in the first conduction type drift region and is self-aligned with the edge of the grid electrode; the side walls are located on the side edges of the two sides of the grid electrode and extend to the side edges of the groove; and the barrier layer fills the groove and extends to a part of the upper surface of the grid electrode. According to the LDMOS device, breakdown voltage is maintained and even improved, on-resistance is reduced, the length of the drift region is reduced, and the size of the device is further reduced.

A semiconductor device including a semiconductor substrate having upper and lower areas, the lower area including a lower layer having a first conductivity type; a first deep well region having the first conductivity type and being on the upper area; a connection layer having the first conductivity type and being on the first deep well region; a body region having the first conductivity type and a first drift region having a second conductivity type, the body region and the first drift region being side-by-side in a first direction on the connection layer; a first source region having the second conductivity type and being on the body region; a drain region having the second conductivity type and being on the upper area and spaced apart from the first drift region in the first direction; and a gate structure on the first drift region and being adjacent to the first source region.

The application discloses an integrated super-junction power MOS device with corrugated gate oxide and a preparation method thereof, and belongs to the technical field of semiconductors. The device comprises a substrate, a buffer layer and an epitaxial layer which are sequentially stacked from bottom to top; wherein the epitaxial layer is provided with a plurality of vertically spaced super-junction columns, and the top of each super-junction column is provided with a body region; the surface layer of the body region is provided with a contact hole doped region and a source doped region which are in contact with each other; the upper surface of the epitaxial layer is further provided with a gate oxide layer; the gate oxide layer is in a corrugated structure, and the lower surface of the gate oxide layer is adapted to and contacts with a corrugated groove located on the upper surface of the epitaxial layer, the body region and part of the source doped region; the upper surface of the gate oxide layer and part of the source doped region is covered with a polysilicon layer, and the gate oxide layer and the polysilicon layer form a corrugated gate structure. The integrated super-junction power MOS device with corrugated gate oxide has good single-particle burnout resistance and single-particle gate penetration resistance.

The invention provides a groove type silicon carbide MOSFET device structure. The device structure comprises a silicon carbide substrate of a first doping type; a first doping type silicon carbide epitaxial layer on the upper surface of the silicon carbide substrate; the groove protection regions of the second doping type are arranged in the silicon carbide epitaxial layer in an array mode in the first direction, the tops of the groove protection regions are discontinuous in the second direction, and the first direction is perpendicular to the second direction; the body regions are arranged in an array in the first direction, are arranged between two adjacent groove protection regions, and extend in the second direction; the source regions are arranged in an array in the first direction, are arranged in the body region, and are discontinuous in the second direction; the one or two gate trenches are arranged between two adjacent trench protection regions, the gate trenches penetrate through the body region, gate oxide layers and polycrystalline silicon are arranged in the gate trenches, and the upper surface of the polycrystalline silicon is lower than the upper surface of the silicon carbide substrate; the interlayer dielectric layer extends along a second direction; and a front metal layer.

A process of forming an electronic device can form an accumulation channel or an integrated diode by selective doping parts of a workpiece. In an embodiment, a doped region can be formed by implanting a sidewall of a body region. In another embodiment, a doped region can correspond to a remaining portion of a semiconductor layer after forming another doped region by implanting into a contact opening. The accumulation channel or the integrated diode can lower the barrier for a body diode turn-on. Reduced stored charge and QRR may be achieved, leading to lower switching losses.

The present application provides a kind of transistor element and its manufacturing method, the manufacturing method of transistor element includes the following steps: first, provide first conductive type epitaxial layer, set on substrate.Second, first conductive type epitaxial layer is implanted with second conductive type ion using first mask, to form second conductive type body region.Then, second conductive type body region is implanted with first conductive type ion using second mask, to form first conductive type heavily doped region in second conductive type body region.Finally, the second conductive type body region of two side edges of first conductive type heavily doped region is implanted with second conductive type oblique angle ion using second mask, to form two in-situ self-aligned second conductive type doped channel in the second conductive type body region of two side edges of first conductive type heavily doped region.

The invention discloses an LDMOS (Laterally Diffused Metal Oxide Semiconductor) device and a preparation method thereof. The LDMOS device comprises a semiconductor layer of a first doping type; the body region and the drift region are located in the semiconductor layer, the body region is provided with a first doping type, the drift region is provided with a second doping type opposite to the first doping type, the drift region comprises a plurality of partitions arranged in the horizontal direction, and the partitions are separated from one another; the source region is positioned in the body region; the drain region is positioned in the drift region; the source region and the drain region have a second doping type; the gate conductor is positioned on the surface of the semiconductor layer between the source region and the drain region; the polycrystalline silicon field plates are positioned on the surface of the partition between the source region and the drain region; wherein the plurality of polycrystalline silicon field plates are electrically connected with one another and are externally connected with voltage.

The present application relates to the technical field of semiconductor, and especially relates to a planar gate IGBT device and a manufacturing method thereof, which comprises a substrate, a doped region and a gate region, and a P-type floating region corresponding to the doped region; the gate region is located on the substrate; the doped region is located on the substrate and below the gate region and at both ends of the gate region; the doped region comprises an N+ source region and a P-type body region, the N+ source region is located in the P-type body region, and the surface of the N+ source region, the surface of the P-type body region and the surface of the substrate are located on the same horizontal plane; the P-type floating region is located in the substrate, below the gate region, between the doped regions and in a specified area beside the corresponding P-type body region, and the P-type floating region is close to the P-type body region and not in contact with the P-type body region. Through the structural arrangement of the device, the on-state voltage drop of the planar gate IGBT device is reduced, and the reliability and practicability of the planar gate IGBT device are improved.

The invention provides an LDMOS device and a manufacturing method thereof, and relates to the technical field of semiconductors. The LDMOS device may include: a semiconductor substrate; the drift region is located on the semiconductor substrate and is provided with a first conduction type; the body region is located at one end of the drift region and has a second conductive type; the gate structure is positioned on the surface of the body region and partially extends to the drift region; the source region is located in the body region and is adjacent to one side of the gate structure, and the body contact region is adjacent to the source region and is of a second conduction type; the drain region is located at one end, away from the body region, of the drift region; and the plurality of strip-shaped current modulation units are arranged in the drift region in an interdigital alternate arrangement mode, and extend and are arranged in the direction from the body region to the drain region. The chip has the advantages of being low in cost, small in overall chip area and easier to manufacture.

This invention belongs to the field of power semiconductor technology, specifically relating to a silicon carbide power MOSFET and its fabrication method. The silicon carbide power MOSFET provided by this invention includes a substrate, a first epitaxial layer, a first CSL layer, a first P-body region, a second epitaxial layer, a second CSL layer, and a second P-body region. A trench region is provided between the two P-body regions, with P+ regions injected at the bottom of the trench and N+ regions distributed on the sidewalls. Specifically, the on-resistance is reduced by the double CSL layer and P-body structure, while the JFET region length is extended to limit short-circuit current, significantly improving short-circuit withstand time. This makes it suitable for high-power, high-reliability power electronic devices.

RC-IGBT (1), comprising: - an active region (1-2) with an IGBT region (1-21) and a diode region (1-22); - a semiconductor body (10) having a first side (110) and a second side (120); - a first load terminal (11) on the first side (110) and a second load terminal (12) on the second side (120); - multiple control trenches (14) and multiple source trenches (16), wherein the multiple trenches (14, 16) are arranged parallel to each other along a first lateral direction (X) and extending along a vertical direction (Z) into the semiconductor body (10), wherein the multiple source trenches (16) extend into both the IGBT region (1-21) and the diode region (1-22);- several IGBT measures (17) and several diode measures (18) in the semiconductor body (10), wherein the measures (17, 18) are laterally delimited along the first lateral direction (X) by two of the several trenches (14, 16), wherein: ◯ the IGBT measures (17) each comprise: ▪ a source region (101) of a first conductivity type electrically connected to the first load terminal (11), and ▪ a body region (102) of a second conductivity type electrically connected to the first load terminal (11) and isolating the source region (101) from another region (100) of the first conductivity type of the RC-IGBT (1); ◯ wherein the diode measures (18) each comprise: ▪ a first anode region (1061) of the second conductivity type electrically connected to the first load terminal (11). Conductivity type;- in the semiconductor body (10) and on the second side (120), both◯ a diode emitter region (104) of the first conductivity type, which forms part of the diode region (1-22) and has a lateral extent in the first lateral direction (X) that is at least 50% of the drift region thickness or at least 50% of the semiconductor body thickness (d); and◯ an IGBT emitter region (103) of the second conductivity type, which forms part of the IGBT region (1-21) and has a lateral extent in the first lateral direction (X) that is at least 70% of the drift region thickness or at least 70% of the semiconductor body thickness (d); and- in the diode region (1-22), a second anode region (1062) of the second conductivity type electrically connected to the first load terminal (11), wherein the second anode region (1062)◯ extends deeper along the vertical direction (Z) compared with the trenches (14, 16) in the diode region (1-22);and◯ overlaps with the diode emitter region (104) for at least 5% of the horizontal area of ​​the diode emitter region (104).

The invention provides an LDMOS process TVS (Transient Voltage Suppressor) device and a manufacturing method thereof, and belongs to the technical field of TVS semiconductor preparation. Comprising a P-type silicon substrate, the surface of the P-type silicon substrate is provided with a deep N well, the deep N well is used for providing isolation for a source / drain high-voltage N + region and preventing punch-through or premature breakdown between the deep N well and the P-type substrate, the deep N well is used as a collector region of a parasitic NPN BJT, and a P-type body region is arranged in the deep N well. According to the invention, the inherent high-voltage capability of an LDMOS and a parasitic BJT structure are utilized to realize rapid triggering and low clamping, the manufacturing process is highly compatible with a standard CMOS / BCD process, key parameters such as breakdown voltage, clamping voltage, capacitance, surge capability and the like can be optimized by accurately designing a drift region, a P body region, a deep N well and layout, various harsh circuit protection requirements are met, and the reliability of the device is improved. The method is particularly applied to applications requiring low capacitance, high integration level and high reliability.

The invention provides a field stop layer preparation method, a process monitoring method and a semiconductor device preparation method, and belongs to the technical field of semiconductor power devices. Comprising a gate oxide layer located on the upper surface of the epitaxial layer, a polycrystalline silicon layer located on the upper surface of the gate oxide layer, a body region located in the epitaxial layer and a first injection region located in the body region; gluing the front surface of the wafer prefabricated member, turning over the wafer prefabricated member with the front surface protection glue, and thinning the back surface of the wafer prefabricated member; performing ion implantation on the back surface of the wafer prefabricated member by adopting a front surface implantation machine to form a field stop layer; and turning over again, and removing the front protection glue. The method has the beneficial effects that the field stop layer is formed by utilizing a front injection machine in the front-section process, so that production line pollution is avoided, and the manufacturing process of the field stop layer is more favorably realized; the problem that the back injection machine table of a wafer factory is limited is solved, no extra machine table needs to be purchased, the utilization rate of the machine table is improved, and cost is reduced.

The invention relates to an LDMOS with a bias circuit for biasing a field plate. A semiconductor device (100) includes: a drain extension transistor (101) having: a semiconductor layer (104) including oppositely doped body and drain drift regions (104, 120); a gate dielectric layer (134) over the body region (104) and extending over a junction between the body region (104) and the drain drift region (120); a gate electrode (140) over the gate dielectric layer (134); a drain region (160) in the drain drift region (120) and having a dopant density greater than a dopant density of the drain drift region (120); and a field plate (142) between the gate electrode (140) and the drain region (160); and a bias circuit (190) including an output coupled to the field plate (142) and a bias input coupled to a gate drive circuit (192).

The present disclosure provides a trench gate semiconductor device and a preparation method thereof. The trench gate semiconductor device comprises a substrate, a drift region and a body region. The drift region is arranged on the surface of the substrate and has a first conductivity type. The body region is epitaxially formed on the surface of the drift region away from the substrate and is an in-situ doped region with a second conductivity type. In the embodiment of the present disclosure, the body region is directly epitaxially formed, which can reduce the lattice damage in the body region, thereby reducing the interface defects between the body region and the gate oxide layer, and further improving the channel mobility. In addition, the tailing effect of the channel caused by ion implantation can be avoided, thereby improving the threshold voltage stability.

A silicon carbide semiconductor device includes a silicon carbide substrate having a first main surface and a second main surface opposite to the first main surface. The silicon carbide substrate includes a drift region being a first-conductivity type, a body region being a second-conductivity type and provided on the drift region, a source region being the first-conductivity type and provided on the body region such that the source region is separated from the drift region, a contact region being the second-conductivity type and provided on the body region. Gate trenches are provided in the first main surface, and extend in a first direction parallel to the first main surface. The contact region is in contact with a first gate trench from both sides in a second direction orthogonal to the first direction and spaced apart from a second gate trench adjacent to the first gate trench in the second direction.