5890 results about "Field effect" patented technology

The disclosure relates to a CFET device (100) comprising: a bottom FET device (130) and a top FET device (140) stacked on top of the bottom FET device (130), the bottom FET device (130) comprising a bottom channel nanostructure (132) and a bottom gate electrode (134) comprising a side gate portion (134a) arranged along a first side surface (132a) of the bottom channel nano structure, and the top FET device (140) comprising a top channel nanosheet (142) and a top gate electrode (144) configured to define a tri-gate with respect to the top channel nanosheet and comprising a side gate portion (144b) arranged along a second side surface (142b) of the top channel nanosheet, wherein the side gate portion (134a) of the bottom gate electrode (134) defines a via contact portion protruding outside the top gate electrode (144) and the first side surface (142a) of the top channel nanosheet (142); and atop gate contact via (146) for coupling the top gate electrode (144) to a first conductive line (124) over the top FET device (140) and a bottom gate contact via (136) for coupling the via contact portion (134a) of the bottom gate electrode (134) to a second conductive line (128) over the top FET device (140).

A semiconductor structure includes a front-end-of-line level including a plurality of field effect transistors. Each field effect transistor includes source / drain regions located on opposite sides of the field effect transistors. A shallow trench isolation region located between adjacent field effect transistors electrically separates the plurality of field effect transistors from one another. The shallow trench isolation region has a tapered profile. A backside isolation region is embedded within the shallow trench isolation region and cuts through the source / drain regions. The backside isolation region has a reverse tapered profile.

The invention belongs to the technical field of field effect transistor performance prediction, and particularly relates to a reliability prediction method, device and system for a field effect transistor, and the method comprises the steps: determining the correlation between the time sequence data of environment parameters, electrical parameters and performance parameters in historical operation records and the change of the performance parameters through a correlation analysis method when the time sequence data changes; key performance parameters are screened out, then a virtual operation model of the field effect transistor is constructed before life prediction is conducted through the screened key performance parameters, and historical data are used for conducting validity verification on the virtual operation model; finally, dynamic changes of environment parameters and electrical parameters are simulated through historical data when the successfully verified virtual operation model is utilized, the degradation trend of key performance parameters is recorded, residual life prediction is carried out based on the degradation trend, prediction efficiency is improved, life prediction can more accurately reflect actual working conditions, and the service life prediction efficiency is improved. And the accuracy of residual life prediction is improved.

The disclosure relates to a π type trench gate silicon carbide MOSFET device and a fabrication method thereof. To protect a trench gate oxide layer without increasing a channel resistance and process complexity, a second conductivity type of heavily doped deep well inserted with double gate trenches along the sidewalls of deep well is designed. The deep well is connected to the source metal directly. The electric potential is clamped to the source during the voltage blocking and turn-off state, which reduces the electric field in the gate oxide and reduces the miller capacitance. An interlayer dielectric layer is deposited above the conductive dielectric polysilicon layers and extends outward separately to cover a part of the source region. A smaller cell pitch can be achieved by controlling the spacing between the first and the second trench gate, thereby increasing the channel density and reducing the channel resistance.

A semiconductor device is provided. The semiconductor device includes a back-end-of-line (BEOL) layer, a backside power distribution network (BSPDN), a stacked field effect transistor (stacked FET) and a backside contact. The stacked FET is vertically interposed between the BEOL layer and the BSPDN and includes a top FET with top source / drain (S / D) epitaxy and a bottom FET with bottom S / D epitaxy. The stacked FET is characterized as having at least partial vertical alignment of the top FET and the bottom FET. A backside contact electrically connects the BSPDN and the top S / D epitaxy and cuts through the bottom S / D epitaxy with isolation between the backside contact and the bottom S / D epitaxy.

An embodiment relates to a device comprising SiC, the device having a p-shield region that is outside a junction gate field-effect transistor region, wherein a doping concentration in a p-well region within a MOSFET channel is non-uniform. Another embodiment relates to a device comprising SiC, the device having a p-shield region, wherein a doping concentration in a p-well region within a MOSFET channel is non-uniform, wherein at least a portion of the p-shield region is located within the p-well region.

A method of fabricating a field effect transistor (FET) over a substrate that includes: growing a doped p-type semiconductor from a silicon nanosheet of the substrate, the substrate including a layer stack of alternating layers of the silicon nanosheet and a sacrificial layer, and a dummy gate formed over the layer stack, the layer stack including a trench exposing sidewalls of the layer stack, the doped p-type semiconductor and the sacrificial layer being separated by a dielectric inner spacer; removing the dummy gate; and etching the sacrificial layer selectively to the doped p-type semiconductor, the etching including exposing the substrate to a process gas including a fluorocarbon and a fluorine-containing etch gas in the absence of plasma.

Embodiments are disclosed for a semiconductor structure. The semiconductor structure includes a field effect transistor (FET). The FET includes a source / drain (S / D) epitaxy and a metal gate. Additionally, the semiconductor structure includes a backside epitaxy in electrical contact with the S / D epitaxy. Further, the backside epitaxy includes a highly doped epitaxy. Additionally, the semiconductor structure includes a backside contact in electrical contact with the backside epitaxy. Further, the semiconductor structure includes a backside power distribution network in electrical contact with the backside contact.

The invention discloses a manufacturing method of a two-dimensional semiconductor field effect transistor based on a high-k gate dielectric integration technology capable of eliminating a buffer layer. The manufacturing method comprises the following steps: depositing a back gate electrode and a back gate dielectric on a substrate in sequence; transferring the channel layer to the back gate medium; sequentially forming a buffer layer, a source electrode, a drain electrode, a top gate dielectric layer formed by a high-k dielectric material and a top gate electrode on the channel layer; and annealing treatment is carried out in a vacuum environment, and the buffer layer sublimates, so that Van der Waals interfaces are formed between the channel layer and the top gate dielectric layer and between the channel layer and the source electrode as well as between the channel layer and the drain electrode. According to the high-k gate dielectric integration technology based on the erasable buffer layer, the erasable buffer layer after vacuum annealing is utilized, damage to a two-dimensional material is avoided, a high-quality high-k gate dielectric is deposited, interface regulation and control between a channel layer and a top gate dielectric are achieved, and the equivalent oxide thickness is reduced; and good contact between the channel layer and source and drain metal is realized, the contact resistance of the transistor is reduced, and the electrical performance of the transistor is improved.

The invention provides a method for manufacturing a semiconductor device and a vertically stacked semiconductor device, which can be applied to the technical field of semiconductors. The manufacturing method includes: disposing a lower field effect transistor and an upper field effect transistor on a substrate, the lower field effect transistor and the upper field effect transistor being stacked in a vertical direction; the upper surface of the substrate is connected with the lower surface of the lowermost gate stack in the lower field effect transistor and the lower surface of the source / drain layer; forming a full silicide layer on the exposed lower surface of the gate stack in the lower field effect transistor and the exposed lower surface of the source / drain layer; patterning the full silicide layer to form an opening which exposes the lower surface of the lowermost gate stack in the lower field effect transistor, and forming silicide layer patterns which are arranged on the two sides of the opening in the first direction and are connected with the lower surface of a source / drain layer in the lower field effect transistor at the same time; filling a dielectric material in the opening so that the dielectric material filled in the opening is used as a lower isolation layer of the gate stack; a contact hole is provided in contact with the silicification layer pattern.

In a semiconductor storage device, a first ROM cell includes a first nanosheet FET having a first nanosheet as the channel region, provided between a first bit line and a first ground power supply line. A second ROM cell includes a second nanosheet FET having a second nanosheet as the channel region, provided between a second bit line and a second ground power supply line. The face of the first nanosheet closer to the second nanosheet in the X direction is exposed from a first gate interconnect, and the face of the second nanosheet closer to the first nanosheet in the X direction is exposed from a second gate interconnect.

A semiconductor device including a stacked structure including first vertically stacked channel regions positioned over second vertically stacked channel regions. The first and second vertically stacked channel regions have a mid dielectric layer positioned therebetween. A structure is present having a first portion in electrical communication with the first vertically stacked channel regions and a second portion in electrical communication with the second vertically stacked channel regions. The semiconductor device also includes at least one two-component gate cut structure present adjacent to the gate all around structure. A first component of the two-component gate cut structure in positioned on one side of the mid dielectric layer adjacent to the first portion of the gate structure, and a second component of the two-component gate cut structure is positioned on a second side of the mid dielectric layer adjacent to the second portion of the gate structure.

A semiconductor device includes a top transistor, a bottom transistor, an isolation box between the top transistor and the bottom transistor, a first gate dielectric, and a second gate dielectric. First portions of the first gate dielectric cover a top surface and top-half of sidewalls of the isolation box, and first portions of the second gate dielectric cover a bottom surface and bottom-half of the sidewalls of the isolation box.

The invention provides a grid-controlled junction field effect transistor, which comprises a substrate and an epitaxial layer formed on the substrate, the channel region of the second doping type is formed downwards from the top surface of the epitaxial layer; the second doping type source electrode contact region is formed downwards from the top surface of the epitaxial layer and is connected to the outer edge of the channel region; the grid electrode of the first doping type is formed on the channel region in the vertical direction, and the outer edge of the grid electrode is located in the outer edge of the channel region in the transverse direction, so that a preset distance is kept between the grid electrode and the source electrode contact region of the second doping type in the transverse direction; and the well region is positioned below the second doping type source contact region. According to the invention, the technical problem that the input capacitance and grid leakage of a traditional grid-controlled junction field effect transistor are relatively large is solved.

The invention belongs to but is not limited to the technical field of state monitoring, and particularly relates to a multi-feature fusion power field effect transistor online state monitoring and evaluation method and system, which are used for understanding the aging mechanism of a device by selecting a proper aging signal and calculating the features of the aging signal. Then, effective feature information strongly correlated with the life sequence is screened out by using a mutual information correlation coefficient algorithm; next, dimension reduction fusion is performed on the screened features by using a KPCA polynomial kernel function algorithm, so that a health index is constructed, and the degradation state of the device is reflected; and monitoring and evaluating the health state of the device by using CNN, XGBoost and RF classifiers according to the constructed health indexes so as to determine the health state of the device. In addition, the RF classification model with the best classification effect is deployed on the DSP development board, the performance of the prediction model is further optimized, and the prediction time of the model is shortened. According to the method, the health state of the power device is described by integrating the multi-feature information.

N-type gate-all-around (nanosheet, nanoribbon, nanowire) field-effect transistors (GAAFETs) vertically stacked on top of p-type GAAFETs in complementary FET (CFET) devices comprise non-crystalline silicon layers that form the n-type transistor source, drain, and channel regions. The non-crystalline silicon layers can be formed via deposition, which can provide for a simplified processing flow to form the middle dielectric layer between the n-type and p-type GAAFETs relative to processing flows where the silicon layers forming the n-type transistor source, drain, and channel regions are grown epitaxially.

The invention discloses a cascode cascade type switching device with a cascode current limiting structure. The cascode cascade type switching device comprises a grid end, a source end, a drain end, a low-voltage enhancement type field effect transistor, a high-voltage depletion type field effect transistor and the current limiting structure. The current limiting structure comprises a plurality of common-gate current limiting depletion type field effect transistors and a current limiting resistor. According to the current-limiting depletion type field-effect transistor, when a switching device is turned on, the grid current of the high-voltage depletion type field-effect transistor can be limited through the current-limiting resistor and the series internal resistors of the plurality of current-limiting depletion type field-effect transistors, so that the working reliability of the current-limiting depletion type field-effect transistor and the whole switching device is improved.

There is provided a high withstand voltage LDMOS field-effect transistor that enables the compatibility of an increase of its withstand voltage and a decrease of its ON resistance. The high withstand voltage LDMOS is characterizing in including: a first electroconductive type body region formed on a main surface of a semiconductor substrate; a second electroconductive type source region formed on a surface of the body region; a second electroconductive type drift region formed so as to have contact with the body region; a second electroconductive type drain region formed on the drift region; a first electroconductive type buried region having contact with the body region and formed below the drift region; a gate electrode formed above the body region between the source region and the drift region and above the drift region nearer to the source region via a gate insulating film; a first field plate that extends from the gate electrode toward the drain region and that is formed above the drift region via a first insulating film; and a second field plate that has contact with the source region or the gate electrode and that is formed above the first field plate via a second insulating film, in which a distance between the buried region and the drain region is smaller than a distance between the first field plate and the drain region and larger than a distance between the second field plate and the drain region.

An improved silicon carbide (SiC) super junction (SJ) MOSFET having at least two buried P-shield (BPS) regions facing each other for gate oxide electric-field and saturation current reductions is disclosed. The two BPS regions are spaced apart from a body region and formed either adjoining sidewalls or below a bottom of a P column region. Moreover, a saturation current pitching (SCP) structure formed in a Junction Field Effect Transistor (JFET) region sandwiched between the two BPS regions limits saturation current of the device in a forward conduction stage for the short-circuit capability improvement.

The present disclosure provides a device and system for detecting and / or measuring a constituent of an interstitial fluid from the skin of a subject. The device is a wearable extended gate field effect transistor (EGFET) device comprising a polymeric substrate for fixing to the skin of the subject: an extended gate electrode comprising a first microneedle configured for accessing the interstitial fluid and a first electric contact, wherein the first microneedle and the first electric contact are disposed on the polymeric substrate; and a field effect transistor (FET) associated with the first microneedle through the first electric contact. Further provided are a method for detecting and / or measuring a constituent of an interstitial fluid from the skin of a subject involving the use of the system and a method for fabricating the EGFET device.

A semiconductor device includes a stacked transistor structure having field effect transistors on two levels. The two levels include a top side and a bottom side. Active regions are disposed on the bottom side including a leveled surface facing the top side and a faceted backside surface opposite the leveled surface. The leveled surface includes two different semiconductor materials. A backside contact in contact with the faceted backside surface forms a wraparound contact to reduce contact resistance.

Embodiments are disclosed for a semiconductor structure. The semiconductor structure includes a protection diode. The protection diode includes a substrate, a gate, a first nanosheet layer, and a second nanosheet layer. The first nanosheet layer includes a heavily doped n-type epitaxial disposed over the substrate. Additionally, the first nanosheet layer is in contact with the gate. Further, the second nanosheet layer includes a heavily doped p-type epitaxial disposed over the substrate. Additionally, the second nanosheet layer is in contact with the gate. Further, the first nanosheet layer and the second nanosheet layer surround the gate.

A metal insulator metal capacitor (MIM capacitor) between adjacent stacked nanosheet FETs, each include a first nanosheet stack including alternating layers of a first work function metal and a semiconductor channel material vertically aligned and stacked one on top of another and a second nanosheet stack including alternating layers of a second work function metal and the semiconductor channel material vertically aligned and stacked one on top of another, the second nanosheet stack on the first nanosheet stack. Forming adjacent stacked nanosheet FETs, each include a first nanosheet stack and a second nanosheet stack, the second nanosheet stack on the first nanosheet stack, and forming a MIM capacitor between adjacent stacked nanosheet field effect transistors.

A semiconductor device includes a plurality of field effect transistors (FET) formed upon semiconductor fins. Each FET includes a gate disposed transversely upon a first portion of the fins of the FET, one or more source / drain regions disposed upon the fins and in contact with the gate, and an electrically isolating layer disposed adjacent to a second portion of the fins above the gate and the source / drain regions, the electrically isolating layer having an interface with the gate. The device further includes a buried power rail (BPR) disposed between otherwise adjacent FETs. The BPR includes a metal rail extending beyond the interface into the gate, and electrically isolating sidewalls separating the metal rail from the gate and the source / drain regions. The device also includes a via-buried power rail contact disposed adjacent to the electrically isolating sidewalls, in contact with the metal rail, and in contact with one source / drain region.

A semiconductor device includes a dielectric wall provided in a direction perpendicular to a substrate, a first metal oxide field effect transistor (MOSFET) provided on one side surface of the dielectric wall, a second MOSFET provided above the first MOSFET in a direction perpendicular to the substrate, and a third MOSFET provided in parallel with the first MOSFET on the other side surface of the dielectric wall.

The invention relates to the technical field of electronic circuits, in particular to a threshold voltage control system and control equipment of a field effect transistor. Comprising a main feedback loop used for obtaining an actual value of a threshold voltage of a field effect transistor, comparing the actual value of the threshold voltage with a set value to obtain a deviation signal, and sending the deviation signal to a control module; the auxiliary feedback loop is used for collecting the current change rate of the field effect transistor and sending the current change rate to the control module; the control module is used for generating a control signal according to the deviation signal and the current change rate and adjusting the grid voltage of the field effect transistor according to the control signal so as to control the threshold voltage of the field effect transistor. According to the invention, the main feedback loop and the auxiliary feedback loop cooperatively collect the voltage deviation signal and the current change rate of the field effect transistor so as to dynamically adjust the grid voltage of the field effect transistor, thereby improving the control precision.

A semiconductor structure includes a stacked device structure having a first field-effect transistor having a first source / drain region, and a second field-effect transistor vertically stacked above the first field-effect transistor, the second field-effect transistor having a second source / drain region and a gate region having first sidewall spacers. The stacked device structure further includes a frontside source / drain contact disposed on a first portion of a sidewall and a top surface of the second source / drain region, a first metal via connected to the frontside source / drain contact and to a first backside power line, and second sidewall spacers disposed on a first portion of the first metal via. The first sidewall spacers comprise a first dielectric material and the second sidewall spacers comprise a second dielectric material different than the first dielectric material.

A current may be passed through a channel of an anti-fuse field-effect transistor (FET) to increase a temperature of a gate dielectric of the anti-fuse FET and change a rupture voltage of the gate dielectric of the anti-fuse FET from a first rupture voltage to a second rupture voltage. The gate dielectric may be ruptured by applying a first voltage between the gate dielectric and the channel of the anti-fuse FET, where the first voltage is between the first rupture voltage and the second rupture voltage.

A semiconductor structure includes a device layer, which in turn includes a plurality of field effect transistors, each of which has a first source-drain region, a second source-drain region, at least one channel region coupling the first and second source-drain regions; and a gate surrounding the at least one channel region. The semiconductor structure further includes a front side wiring layer with wiring coupled to the plurality of field effect transistors at a front side of the device layer; a back side power rail at a back side of the device layer; and a back side gate via interconnecting the back side power rail to the gate of at least one of the plurality of field effect transistors.

The embodiment of the invention provides a field effect transistor, electronic equipment and a preparation method of the field effect transistor, and relates to the technical field of semiconductors. Wherein the field effect transistor comprises a second substrate, an oxide layer and a grid electrode, and the material of the second substrate comprises silicon carbide; the second substrate comprises a source region and a channel region, and the doping concentration of the source region is larger than that of the channel region. The oxide layer is bonded with the second substrate; the oxide layer covers at least part of the channel region; the oxide layer is formed by oxidizing a silicon material. The grid electrode is arranged on the side, away from the second substrate, of the oxide layer. According to the field effect transistor provided by the embodiment of the invention, the oxidation degree of the gate oxide layer is relatively high, and the interface state density between the silicon carbide substrate and the gate oxide layer is relatively small, so that the channel mobility of the silicon carbide field effect transistor is effectively improved, and the electrical performance and reliability of the field effect transistor are optimized.