3777 results about "Field effect" patented technology

A semiconductor device is provided. The semiconductor device includes a back-end-of-line (BEOL) layer, a backside power distribution network (BSPDN), a stacked field effect transistor (stacked FET) and a backside contact. The stacked FET is vertically interposed between the BEOL layer and the BSPDN and includes a top FET with top source / drain (S / D) epitaxy and a bottom FET with bottom S / D epitaxy. The stacked FET is characterized as having at least partial vertical alignment of the top FET and the bottom FET. A backside contact electrically connects the BSPDN and the top S / D epitaxy and cuts through the bottom S / D epitaxy with isolation between the backside contact and the bottom S / D epitaxy.

The invention belongs to but is not limited to the technical field of state monitoring, and particularly relates to a multi-feature fusion power field effect transistor online state monitoring and evaluation method and system, which are used for understanding the aging mechanism of a device by selecting a proper aging signal and calculating the features of the aging signal. Then, effective feature information strongly correlated with the life sequence is screened out by using a mutual information correlation coefficient algorithm; next, dimension reduction fusion is performed on the screened features by using a KPCA polynomial kernel function algorithm, so that a health index is constructed, and the degradation state of the device is reflected; and monitoring and evaluating the health state of the device by using CNN, XGBoost and RF classifiers according to the constructed health indexes so as to determine the health state of the device. In addition, the RF classification model with the best classification effect is deployed on the DSP development board, the performance of the prediction model is further optimized, and the prediction time of the model is shortened. According to the method, the health state of the power device is described by integrating the multi-feature information.

An improved silicon carbide (SiC) super junction (SJ) MOSFET having at least two buried P-shield (BPS) regions facing each other for gate oxide electric-field and saturation current reductions is disclosed. The two BPS regions are spaced apart from a body region and formed either adjoining sidewalls or below a bottom of a P column region. Moreover, a saturation current pitching (SCP) structure formed in a Junction Field Effect Transistor (JFET) region sandwiched between the two BPS regions limits saturation current of the device in a forward conduction stage for the short-circuit capability improvement.

The invention relates to the technical field of electronic circuits, in particular to a threshold voltage control system and control equipment of a field effect transistor. Comprising a main feedback loop used for obtaining an actual value of a threshold voltage of a field effect transistor, comparing the actual value of the threshold voltage with a set value to obtain a deviation signal, and sending the deviation signal to a control module; the auxiliary feedback loop is used for collecting the current change rate of the field effect transistor and sending the current change rate to the control module; the control module is used for generating a control signal according to the deviation signal and the current change rate and adjusting the grid voltage of the field effect transistor according to the control signal so as to control the threshold voltage of the field effect transistor. According to the invention, the main feedback loop and the auxiliary feedback loop cooperatively collect the voltage deviation signal and the current change rate of the field effect transistor so as to dynamically adjust the grid voltage of the field effect transistor, thereby improving the control precision.

A current may be passed through a channel of an anti-fuse field-effect transistor (FET) to increase a temperature of a gate dielectric of the anti-fuse FET and change a rupture voltage of the gate dielectric of the anti-fuse FET from a first rupture voltage to a second rupture voltage. The gate dielectric may be ruptured by applying a first voltage between the gate dielectric and the channel of the anti-fuse FET, where the first voltage is between the first rupture voltage and the second rupture voltage.

A semiconductor structure includes a device layer, which in turn includes a plurality of field effect transistors, each of which has a first source-drain region, a second source-drain region, at least one channel region coupling the first and second source-drain regions; and a gate surrounding the at least one channel region. The semiconductor structure further includes a front side wiring layer with wiring coupled to the plurality of field effect transistors at a front side of the device layer; a back side power rail at a back side of the device layer; and a back side gate via interconnecting the back side power rail to the gate of at least one of the plurality of field effect transistors.

The invention relates to a folded cascode low noise amplifier. The disclosed low noise amplifiers (LNAs) include a common emitter amplifier (CE-A), a common gate amplifier (CG-A), and various passive devices located in CE-A and CG-A. The CE-A includes an NPN type bipolar junction transistor (BJT) having emitter and collector (E / C) regions, and a base region located between the E / C regions and connected to an input node. The CG-A includes a P-channel field effect transistor (PFET) having source and drain (S / D) regions, a channel region between the S / D regions, and a gate adjacent to the channel region. A drain region of the PFET is connected to the output node. Further, the common inductor, the collector region of the BJT, and the source region of the PFET are connected at an intermediate node. The LNA is implemented on a three-dimensional integrated circuit (3DIC) in which the BJT and the FET are located on different chips and the passive device is located in a back-end-of-line region between the BJT and the FET.

A P-type Extended Drain MOS (PEDMOS) FETs capable of high speed operation and the capability to withstand relatively high drain voltages. The PEDMOS device includes an active layer (preferably <110> orientated Si) having a P+ SiGe source region, a first P− Si drift region, a second P− SiGe drift region, and a P+ SiGe drain region. The SiGe regions exert compression on the N-type Si channel, improving hole mobility within the PEDMOS device and resulting in low leakage currents at active layer edges, low channel resistance, and good HCI and GIDL characteristics. Forming the SiGe regions may include etching voids in the Si active layer and depositing SiGe within the voids; implanting Ge into defined regions of the Si active layer; or etching partial voids in the Si active layer, depositing SiGe within the partial voids in contact with Si, and diffusing the Ge into the Si.

The invention discloses a neuron circuit and brain-like computing system based on multi-neuromorphic behaviors, and the neuron circuit maps an appreciation-Ross model to the field of physical circuits through a capacitance dynamic response mechanism and the cross-interval nonlinear characteristics of a metal-oxide semiconductor field effect transistor. Then the expanded appreciation-Ross model is realized through the design of a metal-oxide semiconductor field effect transistor; the neuron circuit comprises a membrane voltage circuit, a slow variable circuit and a recovery variable circuit. The membrane voltage circuit is used for receiving an input signal and accumulating membrane voltage; the slow variable circuit is used for accumulating a slow variable according to the membrane voltage and enabling the neuron circuit to enter a hyperpolarization stage after the slow variable is greater than a preset threshold value; the recovery variable circuit is used for outputting a recovery variable according to the film voltage delay and resetting the film voltage to a resting potential through the recovery variable.

A semiconductor device includes a semiconductor substrate having a mesa structure, a dielectric layer surrounding the mesa structure, and a gate electrode over the dielectric layer. The semiconductor substrate includes a bottom source region, a contact source region, and a sidewall body region in the mesa structure. The semiconductor substrate includes a liner doped region adjoining a frontside surface of the semiconductor substrate and a drain region adjoining a backside surface of the semiconductor substrate. The bottom source region, the contact source region, and the drain region have a first conductivity type, and the sidewall body region and the liner doped region have a second conductivity type opposite to the first conductivity type. A bottom of the gate electrode is higher than a top end of a first portion of the liner doped region in the mesa structure.

The invention provides a preparation method of a planar gate accumulation layer channel field effect transistor embedded with a 3C / 4H-SiC heterogeneous junction. The preparation method comprises the following steps: growing an (n-) 4H-SiC drift region and an (n) 4H-SiC current expansion layer (CSL) on an (n +) 4H-SiC substrate by adopting a hot wall chemical vapor deposition (HWCVD) technology; forming a (p) 4H-SiC body region and an (n) 4H-SiC layer on the two sides of the CSL by using a mask, inductively coupled plasma (ICP) etching and ion implantation methods; growing a (p) 3C-SiC region on the upper part of the inner side of each (p) 4H-SiC body region by using a mask, ICP (Inductively Coupled Plasma) etching and HWCVD (High Weight Chemical Vapor Deposition); forming (n) 4H-SiC channels on the two sides of the middle part of the CSL by using a mask and HWCVD, and forming a (p) 3C / (n) 4H-SiC heterogeneous junction with a (p) 3C-SiC region at the bottom; respectively forming an (n +) 4H-SiC source region and a (p +) 4H-SiC source region on the outer side of each (n) 4H-SiC channel by utilizing ion implantation; forming an (n +) 3C-SiC region on the outer side of each (p +) 4H-SiC source region by adopting mask, ICP etching and HWCVD, and forming an (n +) 3C / (n) 4H-SiC heterogeneous junction with the (n) 4H-SiC layer below the (p +) 4H-SiC source region; performing high-temperature annealing to eliminate defects and activate impurities; forming an oxide layer and an (n +) poly-Si gate on the top; and respectively evaporating an alloy grid electrode, a source electrode and a drain electrode to prepare the planar gate accumulation layer channel field effect transistor embedded with the 3C / 4H-SiC heterogeneous junction. The leakage current of the transistor is small and is smaller than the on-resistance (Ron, sp), and the reverse recovery time is short.

A current control module is for controlling an in-rush current resulting from the initiation of an electrical connection of a battery to an electrical load, wherein a metal-oxide-semiconductor field-e

In a method of manufacturing a semiconductor device, a field effect transistor (FET) having a metal gate structure, a source and a drain over a substrate is formed. A first frontside contact disposed between dummy metal gate structures is formed over an isolation insulating layer. A frontside wiring layer is formed over the first frontside contact. A part of the substrate is removed from a backside of the substrate so that a bottom of the isolation insulating layer is exposed. A first opening is formed in the isolation insulating layer from the bottom of the isolation insulating layer to expose a bottom of the first frontside contact. A first backside contact is formed by filling the first opening with a conductive material to connect the first frontside contact.

The invention discloses a ferroelectric semiconductor junction field effect transistor, a preparation method and application. The transistor can simultaneously realize optical sensor, storage, synapse and logic in a single device by utilizing the physical characteristics of the transistor. The structure comprises a source electrode, a drain electrode, a control grid electrode, a channel layer, a ferroelectric grid layer, an oxide layer and a substrate from top to bottom. The channel layer is made of a two-dimensional transition metal sulfide semiconductor material, the ferroelectric gate layer is made of a two-dimensional ferroelectric semiconductor material, the source electrode and the drain electrode are located on two layers of the two-dimensional semiconductor channel respectively, and the control gate is located over the ferroelectric gate layer. According to the preparation method and application of the ferroelectric semiconductor junction field effect transistor, the logic functions of optical signal sensing, data storage, synaptic calculation and self-switching can be integrated in a single transistor, the function discrete limitation of a traditional device is broken through, a new path is provided for a high-density integrated reconfigurable electronic device, and the field effect transistor is suitable for large-scale popularization and application. And the structure complexity and the function density are effectively balanced.

The invention provides an MOSFET and a manufacturing method thereof. The MOSFET includes a substrate; the epitaxial layer is arranged on the substrate; the trench gate group comprises a first trench gate and a plurality of second trench gates, the first trench gate extends into the epitaxial layer from the surface of the side, away from the substrate, of the epitaxial layer, the first trench gate extends in the first direction on the plane where the epitaxial layer is located, and the second trench gates are arranged at intervals in the first direction; the orthographic projection of the second trench gate on the substrate is located in the orthographic projection range of the first trench gate on the substrate, the top of the second trench gate is in contact with the bottom of the first trench gate, and a gate layer in the second trench gate is connected with a gate layer in the first trench gate; each shielding region wraps the bottom and all the side walls of the second trench gate and extends towards the surface of the side, away from the substrate, of the epitaxial layer so as to cover the side wall of the first trench gate, and the multiple shielding regions are arranged at intervals. The shielding region has a three-dimensional structure, so that the stress of a trench gate oxide electric field can be reduced, the cell size of the MOSFET can be reduced, and the current density of the MOSFET can be improved.

A disclosed low noise amplifier (LNA) includes a common-emitter amplifier (CE-A), a common-gate amplifier (CG-A) and various passive devices in CE-A and CG-A. CE-A includes an NPN-type bipolar junction transistor (BJT) with emitter and collector (E / C) regions and a base region between the E / C regions and connected to an input node. CG-A includes P-channel field effect transistor (PFET) with source and drain (S / D) regions, a channel region between the S / D region, and a gate adjacent to the channel region. The drain region of the PFET is connected to an output node. Additionally, a common inductor, collector region of the BJT, and source region of the PFET are connected at an intermediate node. The LNA is implemented on a three-dimensional integrated circuit (3DIC) with the BJT and FET on different chips and with passive devices in back end of the line regions between the BJT and FET.

The invention provides a switching power supply device comprising a transformer which comprises a primary winding and a secondary winding and is used for converting an input voltage into an output voltage; the primary switching tube is connected with the primary winding and controls the on-off of the primary winding; the rectifying unit is connected with the secondary winding and rectifies the output of the secondary winding, and the rectifying unit comprises a semiconductor field effect transistor; the control unit is connected with the rectification unit and generates a control signal so as to control the switch of the semiconductor field effect transistor through the control signal; the current detection unit detects the output current and generates a current detection signal; the control unit receives the current detection signal and adjusts the control signal according to the current detection signal. According to the device, the COOLMOS with small internal resistance and high switching speed is adopted, the switching loss is reduced, the switching signal is dynamically adjusted by the control unit according to the real-time output current, the rectification conduction loss and the switching noise are reduced, the power supply conversion efficiency is improved, and the electromagnetic interference is reduced.

A Schottky barrier integrated field effect transistor and a manufacturing method therefor. The field effect transistor comprises: a first conductive type substrate (1); a first conductive type epitaxial layer (2), wherein the first conductive type epitaxial layer (2) comprises second conductive type doped regions (21), and a JFET region (23) is formed between adjacent second conductive type doped regions (21); gate-source isolation structures (3), wherein an accommodating region (4) is formed between adjacent gate-source isolation structures (3); a Schottky barrier layer (5), wherein the Schottky barrier layer (5) is located in the accommodating region (4) and in contact with the JFET region (23); and gates (6), separated from the Schottky barrier layer (5) by means of at least the gate-source isolation structures (3), wherein the thickness of the sides of the gate-source isolation structures (3) close to the Schottky barrier layer (5) is greater than the thickness of the sides of the gate-source isolation structures (3) distant from the Schottky barrier layer (5).

Techniques are provided to form an integrated circuit having different semiconductor devices with different backside contact structures. Field effect transistors (FETs) each includes semiconductor material extending in a first direction between source and drain regions, and gate structures extending in a second direction around the semiconductor material of each FET. Different contact structures are formed on the source or drain regions of the n-channel FETs compared to the p-channel FETs. A backside contact structure on an n-channel source or drain region includes a first layer of phosphorous-doped titanium, a second layer that includes scandium, and a third layer that includes a metal, such as molybdenum. A backside contact structure on a p-channel source or drain region may include only a layer of metal, such as molybdenum, or the layer of metal and a layer of boron-doped titanium. The contact structures may be used to provide enhanced ohmic contact.

The invention discloses a P-type tellurium oxide thin film field effect transistor and a preparation method thereof. The transistor is provided with a bottom gate top contact structure. The preparation method comprises the following steps: firstly, cleaning the silicon / silicon dioxide substrate, then depositing a tellurium oxide film as the semiconductor active layer by using a metal mask and an electron beam evaporation method, and finally preparing a layer of nickel with the thickness of about 50nm on the active layer by using the mask to serve as the source electrode and the drain electrode. Compared with a traditional tellurium oxide transistor, the tellurium oxide transistor prepared by the method has the advantages that the carrier mobility and the switching ratio are obviously improved, and the hysteresis effect can be ignored. The electrical performance of the tellurium oxide transistor with the bottom gate top contact structure is improved, and the tellurium oxide transistor has the advantages of being low in cost and simple in process step.

A semiconductor device is provided. The semiconductor device includes: an active pattern provided on a substrate having an upper surface; an insulation pattern provided above the substrate and contacting an upper surface of the active pattern; channels spaced apart from each other along a direction perpendicular to the upper surface of the substrate, each of the channels including a material provided in the active pattern; and a gate structure contacting an upper surface of the insulation pattern, an upper surface of the channels, a lower surface of the channels, and sidewalls of the channels opposite to each other. A first distance between an upper surface of the active pattern and a lowermost one of the channels is greater than a second distance between an upper surface of one of the channels and a lower surface of an adjacent channel.

A semiconductor structure including a substrate, a first stack of channel layers on the substrate and a second stack of channel layers vertically aligned above the first stack. The width of the first is greater than the second. Additionally, the first channel layers can be cladded with germanium while the second channel layers can have a dog-bone shape.

Integrated circuit devices and methods of forming the same are provided. An integrated circuit device may include a substrate and a transistor stack on the substrate, the transistor stack including a first transistor and a second transistor on the first transistor. The first transistor may be between the substrate and the second transistor and the first transistor may include first and second source / drain regions, a first channel region between the first and second source / drain regions, and a first gate structure on the first channel region. A lower surface of the first source / drain region may be higher than a lower surface of the first gate structure relative to the substrate.

The present invention relates to an open-gate AlGaN / GaN heterojunction field-effect transistor with an auxiliary gate structure and its application, belonging to the field of microelectronic research technology. Compared with conventional open-gate AlGaN / GaN heterojunction field-effect transistors, the present invention introduces a non-open auxiliary gate structure, effectively improving the saturation characteristics of open-gate devices. The auxiliary gate is located between the drain of the device and the open main gate. Its purpose is to fix the surface potential of the region in which it is located, so that the current saturation of the open-gate device is freed from dependence on the surface virtual gate, thereby improving the saturation characteristics of the device and making it more stable and controllable. By applying different potentials to the main gate and the auxiliary gate, different device operating modes can be obtained, which makes the application of the present invention in circuits more flexible and more suitable for the increasingly complex field of integrated circuits.

A semiconductor device includes: a substrate including active patterns; a device isolation layer disposed between the active patterns; a stacked pattern disposed on the substrate; a power transmission network layer disposed on a first surface of the substrate; a first through via penetrating the stacked pattern; and a second through via disposed between the power transmission network layer and the first through via, wherein the second through via penetrates the active patterns and the device isolation layer.

The invention provides a low-noise amplification circuit, a radio frequency front-end module and an electronic terminal.The low-noise amplification circuit comprises an input matching adjustment circuit, a common-source amplification circuit, a first inductor, an inter-stage feedback circuit, a common-gate amplification circuit, an input and output feedback circuit, an output matching adjustment circuit and an output attenuation circuit; the common-source amplification circuit comprises at least two first signal amplification units; each first signal amplification unit comprises a first field effect transistor; the common-gate amplification circuit comprises at least two second signal amplification units; and each second signal amplification unit comprises a second field effect transistor. According to the low-noise amplification circuit, transconductance nonlinearity of devices under different bias signals can be mutually counteracted, so that the linearity fluctuation of the low-noise amplification circuit at different temperatures is optimized, and the linearity of the low-noise amplification circuit is kept basically not to change along with the temperature change.

The invention belongs to the field of new energy and relates to a novel electric energy acquisition technology. The non-equilibrium conductors are substances with the same Fermi level, and the contact potential generated by the non-equilibrium field effect existing between the non-equilibrium conductors with different mass and form is converted into electric energy for utilization. A medium (hereinafter referred to as an electric conduction control medium) which has electric conduction performance and controls voltage and limits electric conductivity under a certain condition is placed between conductors, good close contact is achieved between the medium and the conductors, and the result is that under the effect of the electric conduction control medium, non-equilibrium field contact potential is converted into electric energy capable of being continuously output.

A semiconductor device is provided that includes a multilayered insulator region located between stacked FETs. The multilayered insulator region is referred to herein as a multi-dielectric material middle isolation structure. The multi-dielectric material middle isolation structure includes a middle dielectric isolation structure having a middle dielectric isolation spacer located at two opposing ends of, or surrounding, the middle dielectric isolation structure. The middle dielectric isolation spacer protects the middle dielectric isolation structure during processing of the stacked FETs such that no damage to the middle dielectric isolation structure and the semiconductor channel regions of the stacked FETs is observed.

Embodiments of the present disclosure provide a semiconductor device structure having vertically stacked complementary field effect transistors (CFETs). The CFETs are formed by bonding two substrates having semiconductor stacks formed thereon. A bonding structure is formed between the semiconductor stacks using wafer bonding technology. Embodiments of the resent disclosure enable the flexibility of choosing different N / P channel properties, provide a simple way to form the N / P channel isolation structure, and reduce potential leakage path and defects in stacked CFETs.

According to the junction field effect transistor device, the preparation method thereof and the electronic equipment provided by the invention, the threshold voltage of the device can be controlled through the low-voltage JFET channel region (namely the first horizontal part) formed by the first P-type ion implantation. Meanwhile, the size of the vertical channel (namely the first vertical part) is determined through first P-type ion implantation, groove etching is carried out in an implantation region, the size of the etched vertical channel and the size of the P-type gate (namely the second P-type region) are decoupled, and the influence of vertical channel etching on threshold voltage and drain breakdown voltage is avoided. Moreover, the gate ohmic contact layer is formed in the trench region (namely above the second horizontal part) to be connected to the gate of the device, so that the gate-drain capacitance CGD of the device can be reduced, the input capacitance and gate charge of the device are reduced, the switching speed of the device can be improved, the switching loss of the device is reduced, and the switching performance of the device is improved. The method is very suitable for the common direct drive type application of the high-voltage normally-open JFET.