Ultra-thin body super-steep retrograde well (SSRW) FET devices

Abstract

A method of manufacture of a Super Steep Retrograde Well Field Effect Transistor device starts with an SOI layer formed on a substrate, e.g. a buried oxide layer. Thin the SOI layer to form an ultra-thin SOI layer. Form an isolation trench separating the SOI layer into N and P ground plane regions. Dope the N and P ground plane regions formed from the SOI layer with high levels of N-type and P-type dopant. Form semiconductor channel regions above the N and P ground plane regions. Form FET source and drain regions and gate electrode stacks above the channel regions. Optionally form a diffusion retarding layer between the SOI ground plane regions and the channel regions.

Description

BACKGROUND OF INVENTION

[0001] This invention relates to and methods of manufacture of ultra-thin body Field Effect Transistor (FET) devices as well as the ultra-thin body FET devices produced thereby.

[0002] In semiconductor devices Field Effect Transistors (FETs) such as Complementary Metal Oxide Semiconductor (MOS) FETs or Metal Insulator Semiconductor (MIS) FETs, the trend continues to be a steady reduction in the minimum feature size of the devices. The reduction of the minimum transistor gate length, realizable on a chip, has helped the microelectronic industry to produce products with a resultant spectacular increase in computational capability and integration density.

[0003] FIG. 1 shows a conventional prior art MOSFET device 10 formed on a p-type doped silicon substrate 11. A gate dielectric layer 12 (e.g. gate oxide) and a gate electrode 14 (e.g. doped polysilicon) are formed as a gate electrode stack on the top surface of the substrate with an n+ doped source region 15 and...

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