Ultra-thin body super-steep retrograde well (SSRW) FET devices

Active Publication Date: 2006-02-02
GLOBALFOUNDRIES US INC
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Benefits of technology

[0028] 4. The partially depleted body and undoped surface layer can greatly minimize the space-charge related fluctuation of threshold voltage (Vth), which is a very important issue for manufacturability.
[0029] In accordance with one aspect of this invention, a method of manufacture of a Super Steep Retrograde Well (SSRW) FET (Field Effect Transistor) device is provided including the following steps. Form an SOI layer on a substrate. Thin the SOI layer to form an ultra-thin SOI layer. Form an isolation trench separating the SOI layer into N and P ground plane regions. Dope the N and P ground plane regions formed from the SOI layer with N-type and P-type dopant respectively. Form semiconductor channel regions above the N and P ground plane regions. Form gate electrode stacks above the channel regions and FET source and drain regions. Preferably, the SOI layer is thinned by successive oxidation and stripping steps forming a thinned SOI layer. Preferably a pad oxide and a pad nitride layer are formed over the thinned SOI layer. Preferably an isolation trench is formed in the device separating the thinned SOI layer into first and second regions. Preferably an isolation dielectric is formed filling the isolation trench. Preferably, the first and second re

Problems solved by technology

However, there is the problem that such devices have been rejected for smaller dimensions, because the process is limited by the diffusion of dopant atoms during subsequent th

Method used

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  • Ultra-thin body super-steep retrograde well (SSRW) FET devices
  • Ultra-thin body super-steep retrograde well (SSRW) FET devices
  • Ultra-thin body super-steep retrograde well (SSRW) FET devices

Examples

Experimental program
Comparison scheme
Effect test

example i

[0056] In this example, two Silicon-On-Insulator (SOI) substrates, each having an SOI layer that has a thickness of about 55 nm were employed. Each of the SOI substrates, in particular each SOI layer, was doped with boron (B) by ion implantation using an ion dose of 2E13 B atoms / cm implanted at an energy of 10 keV in an ion implanter tool. The samples were then annealed at about 1000° C. for less than 10 seconds. Each SOI substrate was then subjected to a step in which the SOI layer was hydrogen terminated. The hydrogen termination was provided by applying dilute hydrofluoric acid to each of the SOI substrates at room temperature. After hydrogen termination, one of the SOI substrates was soaked at room temperature in a solution of 5×10−4 M iodine in methanol to provide a methoxy termination comprising carbon and oxygen bonded to the SOI layer as a monolayer of Si—O—CH 3. The iodine / methanol soak occurred at room temperature for about 20 minutes. The soaked SOI substrate was then rin...

example ii

[0057] Another SOI substrate was processed using the iodine / methanol treatment method of the present invention described above and thereafter the sample was annealed in vacuum at 850° C. and then an epitaxial Si overlayer having a thickness of about 30 nm was deposited at 850° C. A high-resolution (3 nm scale) TEM image and low resolution (50 nm scale) TEM of this sample were made. The TEMs illustrate that the iodine / methanol treatment step of the present invention does not disrupt the epitaxial alignment of the Si overlayer on the lattice structure of the original SOI layer. The carbon and oxygen doses for the interface between the SOI layer and the Si overlayer were 1.1E14 atoms / cm2 and 1.1E13 atoms / cm2, respectively. The interface is not visible by TEM, and the lattice of the SOI substrate is not distinguishable from the epitaxial Si overlayer.

Form Intrinsic Epitaxial Layers Over SOI Regions

[0058]FIG. 3M shows the device 30 of FIG. 3L after formation of ultra-thin intrinsic ep...

first embodiment

of the Method of the Invention

[0061]FIG. 4 shows a flow chart of a first embodiment of the method of this invention. The process illustrated by FIG. 4 begins at Start 70 and continues to step 71 in which device 30 is processed. The SOI layer 33K on BOX substrate 31 which initially had a thickness of 55 nm or more in FIG. 3A is thinned to an ultra-thin thickness from about 10 nm to about 40 nm by a process of oxidation and stripping as described above with reference to FIG. 3B.

[0062] At the end of step 71, the desired thickness of the SOI layer 33 has been reached.

[0063] In step 72, pad oxide layer 34, pad nitride layer 35 were formed as shown in FIG. 3C over the thinned SOI layer 33. Then, as shown in FIG. 3D, an isolation patterning mask 36L / 36R with a central isolation opening 36W therethrough was formed over the pad nitride layer 35 (above the SOI layer 33).

[0064] In step 73, an isolation trench 37 was formed by etching from the top of the device 30 down through the isolation ...

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Abstract

A method of manufacture of a Super Steep Retrograde Well Field Effect Transistor device starts with an SOI layer formed on a substrate, e.g. a buried oxide layer. Thin the SOI layer to form an ultra-thin SOI layer. Form an isolation trench separating the SOI layer into N and P ground plane regions. Dope the N and P ground plane regions formed from the SOI layer with high levels of N-type and P-type dopant. Form semiconductor channel regions above the N and P ground plane regions. Form FET source and drain regions and gate electrode stacks above the channel regions. Optionally form a diffusion retarding layer between the SOI ground plane regions and the channel regions.

Description

BACKGROUND OF INVENTION [0001] This invention relates to and methods of manufacture of ultra-thin body Field Effect Transistor (FET) devices as well as the ultra-thin body FET devices produced thereby. [0002] In semiconductor devices Field Effect Transistors (FETs) such as Complementary Metal Oxide Semiconductor (MOS) FETs or Metal Insulator Semiconductor (MIS) FETs, the trend continues to be a steady reduction in the minimum feature size of the devices. The reduction of the minimum transistor gate length, realizable on a chip, has helped the microelectronic industry to produce products with a resultant spectacular increase in computational capability and integration density. [0003]FIG. 1 shows a conventional prior art MOSFET device 10 formed on a p-type doped silicon substrate 11. A gate dielectric layer 12 (e.g. gate oxide) and a gate electrode 14 (e.g. doped polysilicon) are formed as a gate electrode stack on the top surface of the substrate with an n+ doped source region 15 and...

Claims

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Application Information

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IPC IPC(8): H01L27/01
CPCH01L21/76283H01L21/823892H01L21/84H01L29/78696H01L29/66772H01L29/78609H01L29/78618H01L27/1203
Inventor BOYD, DIANE C.HOLT, JUDSON R.IEONG, MEIKEIMO, RENEE T.REN, ZHIBINSHAHIDI, GHAVAM G.
Owner GLOBALFOUNDRIES US INC
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