42 results about "Soi substrate" patented technology

A kind of heart sound sensing structure and its preparation method, the structure includes double SOI substrate, center mass, elastic support beam, piezoresistive sensing unit and capacitive sensing unit.The front surface of center mass is provided with additional mass layer, and the back surface is kept bottom layer silicon to increase thickness;Elastic support beam connects mass and frame;Piezoresistive sensing unit is composed of four piezoresistors to form wheatstone bridge, and capacitive sensing unit includes movable and fixed comb-tooth capacitive plate crossing each other.When the sound pressure gradient of heart sound signal drives mass to deviate, elastic support beam bends to change piezoresistive value, and at the same time, comb-tooth capacitive plate overlapping area changes to cause capacitive value change, to realize piezoresistive and capacitive dual-mode synchronous detection.Two kinds of detection mechanisms calibrate each other, which significantly improves the sensitivity and anti-interference ability of low-frequency heart sound signal.The preparation method is based on double SOI substrate, integrated by ion implantation, etching, metal deposition and 3D printing process, suitable for miniaturized wearable heart sound monitoring application.

A film structure comprises a substrate and a buffer film formed on the substrate. The substrate is a 36° to 48° rotated Y-cut Si substrate, or the substrate is a SOI substrate comprising a base substance made of the 36° to 48° rotated Y-cut Si substrate, an insulating layer on the base substance, and a SOI layer made of a Si film on the insulating layer, and a Miller index of a crystal plane of an upper surface of the SOI layer is equal to the Miller index of a crystal plane of an upper surface of the base substance. The buffer film comprises ZrO2 epitaxially grown on the substrate.

This invention provides a quasi-two-dimensional / two-dimensional van der Waals heterojunction based on SOI and Si / WS2, its preparation method, and its application. The method includes the following steps: cleaning the SOI substrate; using sulfur powder, tungsten oxide powder, sodium chloride powder as a catalyst, and erbium chloride and ytterbium chloride powder as dopants, chemical vapor deposition is performed on the SOI substrate to prepare an erbium- and ytterbium-doped monolayer WS2 material; the top silicon layer of the SOI substrate is an n-type silicon layer. This invention, employing the above-mentioned quasi-two-dimensional / two-dimensional van der Waals heterojunction based on SOI and Si / WS2, its preparation method, and its application, effectively reduces the defect density during material synthesis while significantly increasing the carrier concentration in the material. The prepared photodetector exhibits good photoelectric response performance, providing a simple and efficient new method for the preparation of high-performance heterojunction photodetectors.

Semiconductor-on-insulator substrate, SOI substrate, comprising: a handling substrate (104); a device layer (108) that lies above the handling substrate (104); and an insulating layer (106) separating the handling substrate (104) from the device layer (108), wherein the insulating layer (106) meets the device layer (108) at a first interface and meets the handling substrate (104) at a second interface, wherein the insulating layer (106) has a getter material with a getter concentration profile, the getter concentration profile having a first peak concentration at the first interface, a second peak concentration at the second interface and a trough concentration at a location between the first interface and the second interface, wherein the trough concentration is smaller than each of the first peak concentration and the second peak concentration, the getter material contains fluorine.

This application discloses a semiconductor device structure, a CMOS structure, and a method for fabricating the same, relating to the field of semiconductor device technology. The semiconductor device structure employs two buried oxide layers interleaved within a three-layer silicon SOI substrate. The epitaxial initiation layer of the source / drain regions is transferred from the top silicon layer of the SOI substrate to an intermediate or supporting silicon layer within the SOI substrate. This solves a series of process problems arising from the development of SOI technology nodes, particularly in epitaxially growing source / drain regions on a thinner top silicon layer, thus improving the epitaxial growth quality and structural stability of the source / drain regions. Furthermore, the parallel overlap length between the source / drain regions and the gate structure is reduced, significantly decreasing the parasitic capacitance between the source / drain regions and the gate structure. Moreover, the source / drain regions can directly contact the channel, enhancing the contact reliability between the source / drain regions and the channel, enabling stress control of the channel, and improving channel mobility, thus possessing significant application value.

The present disclosure relates to methods of forming silicon-on-insulator substrates. A method of forming an SOI substrate includes performing a hydrogen thermal treatment on a pretreated sacrificial wafer at an elevated temperature. A stop layer and a semiconductor layer can be sequentially formed on a first surface of the sacrificial wafer on which the hydrogen (H2) thermal treatment was performed. The stop layer and the semiconductor layer can be formed by an epitaxial growth process using a hybrid precursor including monosilane (MS) and dichlorosilane (DCS) sources.

The application provides a photoelectric detector and a manufacturing method thereof. The manufacturing method of the photoelectric detector comprises the following steps: providing an SOI substrate, wherein the SOI substrate comprises a lower substrate, an insulating buried layer and a semiconductor layer from bottom to top; forming a first insulating medium layer on the top surface and the sidewall of the semiconductor layer; removing the first insulating medium layer on the top surface of the semiconductor layer; forming a second insulating medium layer covering the semiconductor layer and the first insulating medium layer; etching part of the thickness of the second insulating medium layer by using a dry etching process to form an opening; etching the second insulating medium layer on the bottom wall of the opening by using a wet etching process to expose part of the top surface of the semiconductor layer; and forming a semiconductor absorption layer on the exposed semiconductor layer. The technical scheme of the application can improve the growth quality of the semiconductor absorption layer, thereby reducing the dark current of a silicon optical chip, improving the transmission bandwidth of the silicon optical chip and the like.

A method of forming an SOI substrate including a hydrogen thermal treatment performed on a pretreated sacrificial wafer, under high temperature. A stopper layer and a semiconductor layer may be sequentially formed on a first surface of the sacrificial wafer on which the hydrogen (H2) thermal treatment was performed. The stopper layer and the semiconductor layer may be formed by an epitaxial growth process using a mixed precursor including a monosilane (MS) source and a dichlorosilane (DCS) source.

The application discloses a dual-mode underwater acoustic sensor and a preparation method thereof. The sensor structure comprises an SOI substrate, a sensitive structure comprising a middle mass block, a rectangular beam and a frame supporting the mass block through the rectangular beam, a piezoresistive detection unit comprising a piezoresistive resistor arranged at the end of each rectangular beam and a metal lead and an electrode connected into a Wheatstone bridge, and a capacitive detection unit comprising movable comb-tooth capacitive plates arranged around the mass block except the side of the rectangular beam and fixed comb-tooth capacitive plates arranged on the frame and intersecting with the movable comb-tooth capacitive plates. When an underwater acoustic signal causes the mass block to be offset, the rectangular beam is bent to cause the piezoresistive resistor to change in resistance value, and the facing area of the comb-tooth capacitive plates is changed to cause the capacitance to change, so that piezoresistive and capacitive dual-mode signal detection is realized. The application integrates the advantages of high precision of piezoresistance and strong temperature drift resistance of capacitance through integrated design, the comb-tooth capacitive mode can calibrate the piezoresistive mode, and the measurement accuracy, stability and robustness in a complex marine environment are significantly improved.

A semiconductor device and a method for manufacturing the same are disclosed. According to an embodiment, the semiconductor device may include: an SOI substrate; a channel portion on the SOI substrate, the channel portion including a two-dimensional semiconductor material layer; a gate stack on the channel portion; and source / drain portions on the SOI substrate, located on opposite sides of the gate stack and disposed at opposite ends of the channel portion, wherein the two-dimensional semiconductor material layer is on the bottom surface and side surface of the gate stack, and extends on the side surface of the source / drain portion thereby being located between the side surface of the source / drain portion and the side surface of the gate stack.

A local oxidation of silicon (LOCOS) in a region 30 of SOI substrate 4 partially oxidises 34 the silicon first epitaxial layer 10. Etching the SOI substrate 4 in region 30 creates a trench 16 through

The application provides a dual-gate regulated two-dimensional heterostructure telluride infrared detector, which is characterized in that: a silicon photonic crystal cavity and a first air groove are arranged on an SOI substrate, and are separated into a first mesa and a second mesa arranged along a width direction; a dielectric layer is arranged above the silicon photonic crystal cavity, a first two-dimensional bipolar material layer is arranged above the dielectric layer of the first mesa, and a second two-dimensional bipolar material layer is arranged above the dielectric layer of the second mesa; the first two-dimensional bipolar material layer and the second two-dimensional bipolar material layer are stacked above the first air groove to form a Van der Waals heterojunction region; a drain electrode is prepared on the first two-dimensional bipolar material layer, and a source electrode is prepared on the second two-dimensional bipolar material layer; a first gate electrode is further prepared on the first mesa, and a second gate electrode is further prepared on the second mesa; the Van der Waals heterojunction region can be reversibly switched between a PN junction and an NP junction by respectively adjusting gate voltages of the first gate electrode and the second gate electrode.

The laminated structure (10) of the present application has a substrate (11) including a main surface (11p), a buffer film (12) formed on the main surface (11p), and a metal film (14) formed on the buffer film (12). The substrate (11) is composed of a Si substrate or an SOI substrate including a base composed of a Si substrate, an insulating layer on the base, and an SOI layer on the insulating layer. The buffer film (12) is composed of a first metal oxide represented by the following compositional formula (Chemical Formula 1), and x satisfies 0 ≤ x < 1 or x = 1. The metal film (14) contains, as a main component, Fe, Cu, Mo, W, Ag, Al, Ti, or Ir.(Hf 1‑x Zr x )O2···(Chemical Formula 1)

This invention provides a method for forming an SOI (Silicon on Insulator) substrate. [Solution] A method for forming an SOI substrate 100 according to an embodiment of the present invention includes the steps of performing a high-temperature H2 heat treatment on a pre-treated sacrificial wafer 110, and sequentially forming a stopper layer 111 and a semiconductor layer 112 on a first surface of the heat-treated sacrificial wafer 110. The stopper layer 111 and the semiconductor layer 112 are formed by epitaxial growth using a mixed precursor consisting of monosilane (MS) and dichlorosilane (DCS), respectively.

This invention provides a double-sided deep silicon etching method and a MEMS device. The double-sided deep silicon etching method includes: providing an SOI substrate, on which a top silicon layer, a buried oxide layer, and a bottom silicon layer are sequentially formed; performing a first deep silicon etching on the top silicon layer to form multiple blind vias stopping at the buried oxide layer; after completing the first deep silicon etching, depositing a protective layer on the top silicon layer, the protective layer being deposited on the surface of the top silicon layer and at the corners of the top silicon layer at the openings of the blind vias; after completing the protective layer deposition, attaching an electrostatic film to the top silicon layer, flipping the SOI substrate, and performing a second deep silicon etching on the bottom silicon layer to form vias communicating with the blind vias; after completing the second deep silicon etching, removing the protective layer of the top silicon layer. The double-sided deep silicon etching method provided by this invention can effectively improve the problem of damage to the front morphology of the silicon substrate during double-sided deep silicon etching.

This invention discloses a single-pole double-throw switch circuit based on an enhancement-mode GaN HEMT integrated device, belonging to the field of radio frequency integrated circuits. It includes first and second switching units integrated on a high-resistivity SOI substrate. Each unit is composed of series and parallel connection of enhancement-mode GaN HEMTs. The device employs a finned active region combined with a gate-around structure, and a p-type doped layer is provided under the gate to achieve normally-off characteristics. A deep trench isolation structure penetrating to the buried oxide layer and having a recessed bottom is provided between adjacent devices. The circuit also includes an auxiliary RC linearization branch. This invention can enhance channel control and reduce on-resistance by using a gate-around structure, and significantly improve high-frequency isolation by utilizing deep trench isolation and cutting off parasitic paths with the SOI substrate. Simultaneously, the RC branch improves linearity under high power, achieving single positive power supply logic control, thus improving the integration and communication reliability of the RF front-end.

The invention relates to a method for producing a microelectronic device on an FD-SOI substrate, wherein the method comprises: forming a first well in a substrate (11) of a first wafer made of insulating material suitable for forming a shallow trench isolation (STI) (14); forming a strained silicon film (23) (sSi) covered with an oxide layer (24) on a second wafer; bonding the second wafer, after a vertical flip, onto the first wafer so that the oxide layer becomes a buried oxide layer (BOX) covered with the sSi film, which thus becomes a strained silicon on insulator film; removing the donor substrate while retaining the BOX layer and the sSi film; and forming a second isolation trench SSTI (34) by local oxidation of the silicon of the sSi film, which is connected to the STI via the BOX, to form a composite isolation structure (STI-BOX-SSTI).

This invention discloses a configurable MOSFET device with SOI (Solar Injection) hardening process, relating to the field of semiconductor device technology. The MOSFET device includes an SOI substrate and a cross-gate structure unit disposed on the top silicon layer. The cross-gate structure unit includes at least one cross-gate structure, comprising a substrate lead-out layer disposed on the top silicon layer, four configurable gates disposed on the top silicon layer, and four channels. The four gates are arranged in a cross shape along the top, bottom, left, and right directions of the substrate lead-out layer, and the gates are attached to the substrate lead-out layer. Each gate has a channel below it. The MOSFET device of this invention can improve the stability, reliability, and functional flexibility of integrated circuits in high-radiation environments without significantly sacrificing area and power consumption.

An integrated circuit includes an SOI substrate having a semiconductor layer over a buried insulator layer. An electronic device has an NWELL region in the semiconductor layer, a dielectric over the NWELL region, and a polysilicon plate over the dielectric. A white space region adjacent the electronic device includes a first P-type region in the semiconductor layer and adjacent the surface. The P-type region has a first sheet resistance and the NWELL region has a second sheet resistance that is greater than the first sheet resistance.

A method for fabricating a MEMS thermoelectric device based on a phonon crystal includes: S1, etching a thermoelectric conversion structure (100) on the top silicon layer of an SOI substrate, the thermoelectric conversion structure (100) including a connecting portion and two ends connected to both ends of the connecting portion; S2, growing a silicon nitride film (102) on the upper surface of the structure obtained in step S1; S3, etching the silicon nitride film (102) to form a support arm and a support island; S4, depositing a first metal (103) on the support island and etching the first metal (104)... S3) Form a metal pattern; S5) Deposit a second metal (104) on the support arm and make the second metal (104) form an ohmic contact with the top silicon through an annealing process; S6) Prepare a phononic crystal at the connection of the thermoelectric conversion structure (100); S7) Grow a mask layer on the upper surface of the structure obtained in step S6 and the lower surface of the SOI substrate; S8) Etch the buried oxide layer (101) from the lower surface to the SOI substrate; S9) Remove the buried oxide layer (101); S10) Remove the mask layer on the upper surface.

This invention relates to the field of accelerometer chip technology, and discloses a sandwich-type triaxial accelerometer chip and its fabrication method. The fabrication method includes: forming a top electrode plate on a top glass substrate; fixing the top electrode plate to a first SOI substrate; thinning a first bottom silicon layer; forming a first accelerometer sub-assembly and a first Z-axis capacitor; forming a bottom electrode plate on a bottom glass substrate; fixing a second SOI substrate to the bottom electrode plate; thinning a second bottom silicon layer; forming a second accelerometer sub-assembly and a second Z-axis capacitor, which together with the first Z-axis capacitor forms a third differential capacitor; the movable mass blocks of the two accelerometer components along a first direction and the intermediate electrode block form the first differential capacitor; and the movable mass blocks of the two accelerometer components along a second direction and the intermediate electrode block form the second differential capacitor. The chip fabricated by the method disclosed in this invention has good integration, large capacitance, high sensitivity, and good linearity.

This disclosure relates to a silicon-on-insulator (SOI) substrate and a method for forming the same. In the method for forming an SOI substrate, a stop layer may be formed on a first wafer having a first surface and a second surface facing each other, the stop layer having an etch selectivity different from that of the first wafer. A semiconductor layer with an etch selectivity different from that of the stop layer may be formed on the stop layer. A buried insulating layer may be formed on the semiconductor layer. The buried insulating layer may be formed by applying compressive stress conditions such that the height of the central portion of the buried insulating layer is formed to be higher than the height of the edge portion of the buried insulating layer.

The application discloses a dual-mode underwater acoustic sensor and a preparation method thereof. The sensor structure comprises an SOI substrate, a sensitive structure comprising a middle mass block, a rectangular beam and a frame supporting the mass block through the rectangular beam, a piezoresistive detection unit comprising a piezoresistive resistor arranged at the end of each rectangular beam and a metal lead and an electrode connected into a Wheatstone bridge, and a capacitive detection unit comprising movable comb-tooth capacitive plates arranged around the mass block except the side of the rectangular beam and fixed comb-tooth capacitive plates arranged on the frame and intersecting with the movable comb-tooth capacitive plates. When an underwater acoustic signal causes the mass block to be offset, the rectangular beam is bent to cause the piezoresistive resistor to change in resistance value, and the facing area of the comb-tooth capacitive plates is changed to cause the capacitance to change, so that piezoresistive and capacitive dual-mode signal detection is realized. The application integrates the advantages of high precision of piezoresistance and strong temperature drift resistance of capacitance through integrated design, the comb-tooth capacitive mode can calibrate the piezoresistive mode, and the measurement accuracy, stability and robustness in a complex marine environment are significantly improved.

The application discloses a power-split high-order mode-passing filter based on a genetic heuristic direct binary search method reverse design and a design method thereof, and belongs to the field of silicon-based photonic integrated devices. The device comprises an SOI substrate, an input multimode waveguide, two output multimode waveguides and a silicon / air binary pixelated optimization region located therebetween. The pixel state distribution is determined through a genetic algorithm and a direct binary search algorithm, so that the TE0 mode is suppressed, the TE1 mode is passed and distributed to the two output multimode waveguides, and high-order mode-passing and 1x2 power splitting are integrated. The structure is compact in size, good in process compatibility and suitable for mode division multiplexing and on-chip optical interconnection systems.

The application provides a semiconductor device and a manufacturing method thereof, the manufacturing method of the semiconductor device comprising: providing an SOI substrate, the SOI substrate comprising a lower substrate, an insulating buried layer and a semiconductor layer from bottom to top, the SOI substrate comprising a detector region and a waveguide region; etching the semiconductor layer so that the semiconductor layer height of the detector region is higher than the semiconductor layer height of the waveguide region; forming a first waveguide in the semiconductor layer of the waveguide region; forming an insulating medium layer and a second waveguide, the insulating medium layer covering the semiconductor layer, and the second waveguide being formed in the insulating medium layer above the first waveguide; and forming a semiconductor absorption layer in the insulating medium layer on the semiconductor layer of the detector region. The technical scheme of the application can realize the integration of a photodetector and a waveguide.

Provided in the present application is a method for preparing an SOI substrate. The method comprises: providing a device substrate and a support substrate; forming an oxide layer on a surface of at least one of the device substrate and the support substrate; implanting blistering ions into the device substrate; implanting modifying ions above a region of the device substrate in which the blistering ions are implanted, wherein the modifying ions are Ar ions; bonding the device substrate to the support substrate; and performing annealing to strip the device substrate at the position where the blistering ions are implanted, so as to form an SOI substrate. In the present application, Ar ions are used as modifying ions and are implanted into a device layer, such that an effective bonding area between a device substrate and a support substrate can be increased, and the size of a suspended portion on the edge of the device layer can be relatively reduced, thereby reducing the risks of subsequent edge breakage and fragmentation.

This invention belongs to the field of analog integrated circuit technology, specifically relating to an edge modulation and demodulation circuit for optically isolated transmission. It includes an SOI substrate, a waveguide layer, and a cladding layer. The SOI substrate comprises a substrate layer and a buried oxide layer. The waveguide layer comprises a lower silicon waveguide, a middle silicon dioxide spacer layer, and an upper silicon nitride waveguide. The upper silicon nitride waveguide modulates the width of the etched regions and the grating duty cycle on both sides of the central silicon nitride waveguide according to the near-field uniform emission principle, forming a fishbone-like grating antenna structure. The proposed double-layer grating structure utilizes the strong optical confinement of silicon waveguides and the weak perturbation characteristics of silicon nitride waveguides through full etching, reducing etching difficulty, effectively extending the effective length of the grating, thereby reducing the far-field emission angle of the beam, and exhibiting high wavelength tuning efficiency and high upward diffraction efficiency. The structure is simple and relatively easy to fabricate.

The present disclosure provides a method of manufacturing an SOI substrate. A stop layer, a semiconductor layer, an insulating buried layer, and a first bonding insulating layer are formed in sequence on a sacrificial wafer. A second bonding insulating layer is formed on a reference wafer. The first bonding insulating layer and the second bonding insulating layer comprise silicon carbon nitride (SiCN) material. Si-OH bonds are formed in the first bonding insulating layer and the second bonding insulating layer by an O2 plasma treatment. The sacrificial wafer is bonded to the reference wafer such that the first bonding insulating layer contacts the second bonding insulating layer.

An infrared thermopile sensor and its formation method are disclosed. The infrared thermopile sensor includes: an SOI substrate comprising a bottom silicon layer, a buried oxide layer, and a top silicon layer stacked sequentially; the top silicon layer is patterned to form a deflecting mirror with a MEMS micro-mirror, and electrostatically driven comb teeth and a torsion shaft disposed around the deflecting mirror; a first dielectric layer, located at least on the top surface of the deflecting mirror; a thermopile including a plurality of thermocouples located on the first dielectric layer on the deflecting mirror; an infrared absorption layer located on the surface of the thermopile; a first cavity penetrating the bottom silicon layer and the buried oxide layer, the projection of the infrared absorption layer onto the bottom silicon layer being located within the range of the first cavity; a second cavity penetrating the bottom silicon layer and the buried oxide layer around the deflecting mirror, exposing the electrostatically driven comb teeth and the torsion shaft; and further including a driving electrode and a detection electrode. This invention can improve integration, increase detection range, enhance synchronization performance, and reduce the requirements for installation accuracy.

A memory device includes a SOI substrate comprising bulk silicon, an insulation layer vertically over the bulk silicon, and a silicon layer vertically over the insulation layer. A memory cell includes source and drain regions formed in the bulk silicon with a channel region of the bulk silicon extending therebetween, and a floating gate which includes a first portion of the silicon layer disposed vertically over and insulated from a first portion of the channel region by the insulation layer. The first portion of the silicon layer is epitaxially thickened or a layer of polysilicon is formed on the first portion of the silicon layer. A select gate is disposed vertically over and insulated from a second portion of the channel region. A control gate is disposed vertically over and insulated from the floating gate. An erase gate is disposed vertically over and insulated from the source region.