206 results about "Soi substrate" patented technology

The invention provides a semiconductor structure and a forming method thereof, the semiconductor structure comprises an SO I substrate, the SO I substrate comprises a bottom silicon layer, an insulating layer and a top silicon layer, the SO I substrate comprises a strip-shaped waveguide area and a ridge-shaped waveguide area, and a hard mask layer is formed on the surface of the SO I substrate; a strip-shaped waveguide is formed in the top silicon layer of the strip-shaped waveguide area, and a ridge-shaped waveguide is formed in the top silicon layer of the ridge-shaped waveguide area. According to the semiconductor structure and the forming method thereof, the influence of the etching load effect can be optimized, the etching depth accuracy of the ridge waveguide region and the grating region is improved, and the device performance is improved.

A semiconductor light emitting device includes a semiconductor light emitting laminate, and an SOI substrate including an upper semiconductor layer, an interlayer insulating film, and a lower semiconductor layer. The SOI substrate includes a first wiring electrode provided on the upper semiconductor layer through an insulating film and corresponding to a p-electrode, a second wiring electrode connected to the upper semiconductor layer and corresponding to an n-electrode, an anode that is provided on the lower semiconductor layer and connected to a first wiring electrode by a first via electrode passing through the SOI substrate, a cathode that is provided on the lower semiconductor layer through an insulating film and connected to the upper semiconductor layer by a second via electrode reaching the upper semiconductor layer. The p-electrode and the n-electrode are respectively bonded to the first wiring electrode and the second wiring electrode.

A kind of heart sound sensing structure and its preparation method, the structure includes double SOI substrate, center mass, elastic support beam, piezoresistive sensing unit and capacitive sensing unit.The front surface of center mass is provided with additional mass layer, and the back surface is kept bottom layer silicon to increase thickness;Elastic support beam connects mass and frame;Piezoresistive sensing unit is composed of four piezoresistors to form wheatstone bridge, and capacitive sensing unit includes movable and fixed comb-tooth capacitive plate crossing each other.When the sound pressure gradient of heart sound signal drives mass to deviate, elastic support beam bends to change piezoresistive value, and at the same time, comb-tooth capacitive plate overlapping area changes to cause capacitive value change, to realize piezoresistive and capacitive dual-mode synchronous detection.Two kinds of detection mechanisms calibrate each other, which significantly improves the sensitivity and anti-interference ability of low-frequency heart sound signal.The preparation method is based on double SOI substrate, integrated by ion implantation, etching, metal deposition and 3D printing process, suitable for miniaturized wearable heart sound monitoring application.

A film structure comprises a substrate and a buffer film formed on the substrate. The substrate is a 36° to 48° rotated Y-cut Si substrate, or the substrate is a SOI substrate comprising a base substance made of the 36° to 48° rotated Y-cut Si substrate, an insulating layer on the base substance, and a SOI layer made of a Si film on the insulating layer, and a Miller index of a crystal plane of an upper surface of the SOI layer is equal to the Miller index of a crystal plane of an upper surface of the base substance. The buffer film comprises ZrO2 epitaxially grown on the substrate.

The application belongs to the technical field of micro electro mechanical system sensors, and discloses an acceleration sensor chip with a DLC optimized structure and a preparation method thereof; in the piezoresistive acceleration sensor chip, an SOI substrate is bonded to boron glass through a substrate frame, and a center mass is connected to the substrate frame through four embedded micro-beams arranged in a cross shape; four piezoresistance strips are arranged on the four embedded micro-beams, and the four piezoresistance strips are connected into a Wheatstone full bridge through surface metal leads deposited on the SOI substrate and connected with pads deposited on the SOI substrate; wherein, a DLC film is deposited on the SOI substrate, and the DLC film covers the surface metal leads, the four piezoresistance strips and the area of the SOI substrate except the pads. The application can improve the sensitivity of the sensor while ensuring the strength of the sensitive structure; the protection of the piezoresistance strips is realized, and the reliability of the sensor can be improved.

This invention provides a quasi-two-dimensional / two-dimensional van der Waals heterojunction based on SOI and Si / WS2, its preparation method, and its application. The method includes the following steps: cleaning the SOI substrate; using sulfur powder, tungsten oxide powder, sodium chloride powder as a catalyst, and erbium chloride and ytterbium chloride powder as dopants, chemical vapor deposition is performed on the SOI substrate to prepare an erbium- and ytterbium-doped monolayer WS2 material; the top silicon layer of the SOI substrate is an n-type silicon layer. This invention, employing the above-mentioned quasi-two-dimensional / two-dimensional van der Waals heterojunction based on SOI and Si / WS2, its preparation method, and its application, effectively reduces the defect density during material synthesis while significantly increasing the carrier concentration in the material. The prepared photodetector exhibits good photoelectric response performance, providing a simple and efficient new method for the preparation of high-performance heterojunction photodetectors.

Provided is a light detection device in which an oxide film is formed on the bottom of a fin of a transistor in a bulk substrate without using an SOI substrate. The light detection device includes a first substrate portion and a second substrate portion. The first substrate portion has pixels that photoelectrically convert incident light. The second substrate portion is bonded to a surface of the first substrate portion opposite to a light incident surface. The second substrate portion has a plurality of elements constituting a readout circuit configured to output a pixel signal based on a charge output from the pixel. A pattern of an insulating film is formed on a bonding surface of the second substrate part that is bonded to the first substrate part.

The invention provides a semiconductor structure and a manufacturing method thereof, and the method comprises the steps: providing a substrate structure which comprises a back substrate, a buffer layer and a top silicon layer, a second groove is formed in the base structure, and the buffer layer is removed through etching of the second groove so that a cavity can be formed between the back substrate and the top silicon layer; according to the method, the top silicon layer is provided with a cavity, the cavity is filled with a buried oxide layer to form the SOI substrate, so that the thickness of the top silicon layer and the thickness of the buried oxide layer can be controlled to obtain the SOI substrate with the ideal thickness, the SOI substrate is prevented from being formed through an ion implantation process, correspondingly, ion implantation damage is avoided, and the quality and reliability of the formed SOI substrate are improved.

Semiconductor-on-insulator substrate, SOI substrate, comprising: a handling substrate (104); a device layer (108) that lies above the handling substrate (104); and an insulating layer (106) separating the handling substrate (104) from the device layer (108), wherein the insulating layer (106) meets the device layer (108) at a first interface and meets the handling substrate (104) at a second interface, wherein the insulating layer (106) has a getter material with a getter concentration profile, the getter concentration profile having a first peak concentration at the first interface, a second peak concentration at the second interface and a trough concentration at a location between the first interface and the second interface, wherein the trough concentration is smaller than each of the first peak concentration and the second peak concentration, the getter material contains fluorine.

The invention relates to the technical field of optical sensors, in particular to a super-multilayer dielectric film structure optical refractive index sensor based on Fano resonance. The device sequentially comprises a prism layer, a modified cerium oxide layer, a functional layer, an interface layer, a substrate layer and a to-be-detected dielectric layer from top to bottom, the prism layer is a rutile prism, the substrate layer is an SOI substrate, and in the to-be-detected dielectric layer, a to-be-detected medium comprises water and ethanol; the interface layer is arranged on the substrate layer in a coating manner, the functional layer comprises a plurality of groups of units obtained by alternate deposition, and each unit comprises a vanadium dioxide layer and an indium trichloride tetrahydrate doped SiO2 layer which are arranged in sequence. The invention provides an optical refractive index sensor with a super-multilayer dielectric film structure based on Fano resonance, and aims to solve the problems of relatively low sensor sensitivity caused by relatively high cost and poor binding force with oxide materials of precious metals used in traditional materials and relatively weak surface plasmons excited by some oxide materials in related technologies.

The invention provides a nitrogen-doped upright graphene heterojunction, a preparation method, application, a signal coding device, an image generation device and an image generation method. The preparation method comprises the following steps: placing an SOI substrate in a growth chamber; vacuumizing the growth chamber; heating the SOI substrate; introducing methane and ammonia gas into the growth chamber, and growing nitrogen-doped upright graphene on the surface of the SOI substrate by a PECVD (Plasma Enhanced Chemical Vapor Deposition) process; and spin-coating a gold nanocluster solution on the surface of the nitrogen-doped upright graphene, so that gold nanoclusters are attached to the interior of the nitrogen-doped upright graphene.

The invention provides a semiconductor device and a manufacturing method thereof, the semiconductor device comprises an SOI substrate, the SOI substrate comprises a lower substrate, an insulating buried layer and a semiconductor layer, the SOI substrate comprises a plurality of semiconductor devices, the plurality of semiconductor devices comprise first optical couplers, and the first optical couplers are arranged on the lower substrate; a first groove which penetrates through the lower substrate and the insulating buried layer and exposes the semiconductor layer of the first optical coupler is formed in the SOI substrate; and the insulating medium layer covers one surface, on which the semiconductor layer is formed, of the SOI substrate. According to the technical scheme, the packaging flexibility of the chip can be improved.

An epitaxial growth method of an FDSOI mixed region and an FDSOI, the method comprising: providing an SOI substrate, the SOI substrate comprising a bottom silicon layer, a buried oxide layer and a top silicon layer stacked in sequence, the SOI substrate having a first preset region and second preset regions adjacent to two sides of the first preset region; carrying out modification treatment on the top layer silicon in the first preset region and the second preset region in the SOI substrate to form a top layer silicon modified region; a groove is formed in the first preset area of the SOI substrate, the groove penetrates through the top layer silicon modified area and the buried oxide layer of the first preset area, the side wall of the groove exposes the top layer silicon modified area of the second preset area, and the bottom wall of the groove exposes the top surface of the bottom layer silicon; and forming a silicon epitaxial layer in the groove from the top surface of the bottom layer silicon by adopting a selective epitaxial growth process. According to the invention, the bump defect on the silicon surface can be improved.

This application discloses a semiconductor device structure, a CMOS structure, and a method for fabricating the same, relating to the field of semiconductor device technology. The semiconductor device structure employs two buried oxide layers interleaved within a three-layer silicon SOI substrate. The epitaxial initiation layer of the source / drain regions is transferred from the top silicon layer of the SOI substrate to an intermediate or supporting silicon layer within the SOI substrate. This solves a series of process problems arising from the development of SOI technology nodes, particularly in epitaxially growing source / drain regions on a thinner top silicon layer, thus improving the epitaxial growth quality and structural stability of the source / drain regions. Furthermore, the parallel overlap length between the source / drain regions and the gate structure is reduced, significantly decreasing the parasitic capacitance between the source / drain regions and the gate structure. Moreover, the source / drain regions can directly contact the channel, enhancing the contact reliability between the source / drain regions and the channel, enabling stress control of the channel, and improving channel mobility, thus possessing significant application value.

The present disclosure relates to methods of forming silicon-on-insulator substrates. A method of forming an SOI substrate includes performing a hydrogen thermal treatment on a pretreated sacrificial wafer at an elevated temperature. A stop layer and a semiconductor layer can be sequentially formed on a first surface of the sacrificial wafer on which the hydrogen (H2) thermal treatment was performed. The stop layer and the semiconductor layer can be formed by an epitaxial growth process using a hybrid precursor including monosilane (MS) and dichlorosilane (DCS) sources.

The application provides a photoelectric detector and a manufacturing method thereof. The manufacturing method of the photoelectric detector comprises the following steps: providing an SOI substrate, wherein the SOI substrate comprises a lower substrate, an insulating buried layer and a semiconductor layer from bottom to top; forming a first insulating medium layer on the top surface and the sidewall of the semiconductor layer; removing the first insulating medium layer on the top surface of the semiconductor layer; forming a second insulating medium layer covering the semiconductor layer and the first insulating medium layer; etching part of the thickness of the second insulating medium layer by using a dry etching process to form an opening; etching the second insulating medium layer on the bottom wall of the opening by using a wet etching process to expose part of the top surface of the semiconductor layer; and forming a semiconductor absorption layer on the exposed semiconductor layer. The technical scheme of the application can improve the growth quality of the semiconductor absorption layer, thereby reducing the dark current of a silicon optical chip, improving the transmission bandwidth of the silicon optical chip and the like.

A method for fabricating a semiconductor device, the method comprising the steps of: providing a silicon-on-insulator (SOI) substrate, the SOI substrate comprising a groove exposing different crystal facing a planar surface; depositing a buffer layer over the substrate; epitaxially growing a semiconductor layer over the buffer layer, whereby least a portion of the buffer layer exhibits a cubic crystalline phase structure.

A method of forming an SOI substrate including a hydrogen thermal treatment performed on a pretreated sacrificial wafer, under high temperature. A stopper layer and a semiconductor layer may be sequentially formed on a first surface of the sacrificial wafer on which the hydrogen (H2) thermal treatment was performed. The stopper layer and the semiconductor layer may be formed by an epitaxial growth process using a mixed precursor including a monosilane (MS) source and a dichlorosilane (DCS) source.

The invention belongs to the technical field of MEMS loudspeakers, and particularly relates to a preparation method of a PZT loudspeaker based on a back guide structure. Comprising the steps that a bottom electrode metal film and a PZT piezoelectric film are sequentially sputtered on the front face of a device at high temperature through a magnetron sputtering PVD technology; performing a bottom electrode layer structure photoetching process; performing a top electrode layer photoetching process; performing an upper and lower electrode isolation layer photoetching process, performing a front surface back guide hole structure photoetching process, and etching a top silicon layer of the SOI substrate material sheet through ICP (Inductively Coupled Plasma) to form a device back guide hole structure; depositing a Parylene protection material on the front side by a vacuum vapor deposition process; and performing a back photoetching process, and etching the back of the SOI substrate material sheet through ICP (Inductively Coupled Plasma) to form a device diaphragm cavity structure. According to the invention, the air circulation resistance of the rear cavity can be accurately controlled, the quality-spring property of the diaphragm can be matched, the rigidity and damping of the diaphragm can be balanced, the resonance peak can be effectively reduced, the low-frequency response bandwidth can be expanded, and the SPL can be improved.

The application relates to an integrated circuit electrostatic protection reliability design in the field of semiconductor technology, in particular to an H-shaped fin silicon structure ESD protection device applied to an SOI-FinFET process; a longitudinal fin silicon, a transverse fin silicon, a dielectric and a gate electrode are prepared based on an SOI substrate; the longitudinal fin silicon comprises longitudinal fin silicon one and longitudinal fin silicon two; the longitudinal fin silicon one comprises two kinds of doped regions of first and second semiconductor types, the longitudinal fin silicon two is of the second semiconductor type, the transverse fin silicon is of the second semiconductor type, the longitudinal fin silicon one, the longitudinal fin silicon two and the transverse fin silicon three jointly form an H-shaped fin silicon structure and are electrically connected, and a carrier control region is only a part of the longitudinal fin silicon one, the longitudinal fin silicon two and the transverse fin silicon; a novel ESD protection device can be implemented under the SOI-FinFET process, the device is different from a substrate under an insulating layer which must be used in the electrostatic protection technology related to the Bulk-FinFET process, and a good electrostatic protection method is provided for the SOI-FinFET process.

The invention belongs to the technical field of pulse characteristic measurement, and relates to an on-chip integrated single autocorrelator and a measurement method thereof. The autocorrelator comprises an SOI substrate, a photonic crystal waveguide is formed on the SOI substrate through etching, and an insulating layer, an indium selenide layer and a chromium gold electrode array are sequentially arranged on the photonic crystal waveguide; the photonic crystal waveguide is composed of a straight waveguide area in the middle area and photonic crystal areas on the two sides. The chromium-gold electrode array is composed of a plurality of pairs of chromium-gold electrodes which are arranged at equal intervals in the photonic crystal waveguide direction, and each pair of chromium-gold electrodes serve as a source electrode and a drain electrode respectively; a back gate electrode is arranged on an unetched region of the SOI substrate; during measurement, a p-i-n homojunction is formed in the indium selenide material; the source electrode is connected with the p-type region of the indium selenide layer, the drain electrode is connected with the n-type region of the indium selenide layer, and the indium selenide p-i-n homojunction photoelectric detector is formed by the source electrode and the drain electrode. The problem that an existing autocorrelator is difficult to integrate and cannot meet actual requirements is solved.

The invention discloses a semiconductor structure and a preparation method thereof. The method comprises the following steps: firstly, etching in an SOI substrate to form a groove which at least penetrates through a top semiconductor layer in the longitudinal direction; after isolation dielectric layers are formed on the side wall and the bottom of the groove, selectively removing the bottom isolation dielectric layer to expose the silicon substrate; if the bottom of the trench is located in the buried oxide layer, continuously etching the buried oxide layer until the silicon substrate is exposed after the isolation dielectric layer is removed; filling heavily-doped polycrystalline silicon or heavily-doped epitaxial monocrystalline silicon to form an electric conductor which is in ohmic contact with the silicon substrate; and finally forming a metal contact structure at the top of the conductor. According to the structure, the isolation dielectric layer on the side wall and the conductor in the center are integrated, integration of transverse electrical isolation and longitudinal conductive grounding is achieved, the integration degree and layout compactness of a chip are remarkably improved, meanwhile, high-voltage isolation, stable potential reference and an effective heat dissipation path are synchronously provided for an SOI-based high-voltage device, and the reliability of the chip is improved. And the voltage withstanding level, the anti-interference characteristic and the working reliability of the device are obviously improved.

To provide a laminate structure having an improved electromechanical coupling coefficient and an electronic device including the laminate structure.SOLUTION: A laminate structure 10 includes a substrate 11 including a main surface 11p, a buffer film 12 formed on the main surface 11p, and a piezoelectric film 13 formed on the buffer film 12. The substrate 11 is made of an Si (100) substrate including the main surface 11p made of an Si (100) plane or an SOI substrate including an SOI layer including a main surface made of the Si (100) plane. The buffer film 12 is epitaxially grown on the main surface 11p, is (100) oriented in a pseudo-cubic crystal display, and is made of a metal oxide represented by the following composition formula (Chemical Formula 1), and x satisfies 0≤x<1. The piezoelectric film 13 is made of a metal nitride containing AlN, and AlN contained in the metal nitride is oriented so that a (0001) plane is inclined with respect to the main surface 11p. (Hf1-xZrx)O2...(Chemical Formula 1)SELECTED DRAWING: Figure 1

The application relates to a silicon nanowire manufacturing method and belongs to the technical field of MEMS. The steps comprise the following: S1, providing an SOI substrate; S2, forming a mask layer on the SOI substrate; S3, patterning the mask layer to form an etching window; S4, performing isotropic etching on the SOI substrate through the etching window to form a cavity and a silicon nanocolumn; S5, oxidizing the silicon nanocolumn to form an oxide layer and a silicon nanowire; and S6, removing the buried oxygen layer and the oxide layer to obtain a suspended silicon nanowire. The application solves the problems of the prior art, such as complex preparation method of the silicon nanowire, high requirement for equipment and poor batch consistency.

According to the silicon-based epitaxial detector and the preparation method thereof provided by the invention, the tensile stress of the epitaxial layer crystal can be effectively improved, and the direct band gap of the crystal is narrowed, so that the absorption edge of the crystal can be widened to the C + L wave band, and the detection wave band of the detector is widened to the C + L wave band from the C wave band. The silicon-based epitaxial detector comprises an SOI substrate, the SOI substrate comprises a bottom silicon layer, a buried oxide layer and a top silicon layer, the buried oxide layer is deposited on the upper surface of the bottom silicon layer, and the top silicon layer is deposited on the upper surface of the buried oxide layer; the first middle silicon oxide layer grows on the upper surface of the top silicon layer, and a groove which penetrates through the first middle silicon oxide layer and at least reaches the upper surface of the top silicon layer is formed in the first middle silicon oxide layer; the epitaxial layer is formed in the groove; and the strain dielectric layer covers the upper surface of the epitaxial layer, has compression stress inside, and is used as a stress source to apply the compression stress to the epitaxial layer.

The present disclosure provides a heat spreading isolation structure for a semiconductor device. A structure includes an active device over a region of a substrate and a heat spreading isolation structure adjacent to the active device. The isolation structure includes a dielectric layer over a thermally conductive layer. The thermally conductive layer can include polycrystalline graphite. The thermally conductive layer provides a heat spreader that provides a high thermal conduction path with low electrical conduction. The thermally conductive layer can extend into the substrate. The substrate can include an SOI substrate, in which case the thermally conductive layer can extend through the buried insulator thereof.

The application provides a preparation method of a full-dielectric silicon-based micro-nano optical structural color thin film, which comprises the following steps: obtaining structural parameters of the optical structural color thin film by using a finite-difference time-domain method according to chromaticity and reflectivity of the optical structural color thin film to be prepared; performing ultrasonic cleaning on an SOI chip, plating a chromium adhesion layer with a thickness of 2 nm to obtain an SOI substrate, and uniformly coating photoresist with a thickness of 150 nm to obtain an SOI photoresist layer; adjusting parameters of a double-beam laser interference optical path to perform interference exposure on the SOI photoresist layer to obtain a micro-nano optical structure pattern; after evaporating a metal chromium film with a thickness of 30 nm on the micro-nano optical structure pattern, dissolving the photoresist with a developing solution to strip the metal chromium film, and forming a chromium mask with the micro-nano optical structure pattern; and etching the SOI chip by using an inductively coupled plasma etching technology to obtain a Si micro-nano optical structural color thin film. The Si micro-nano optical structural color thin film obtained by the method has high resolution and high brightness, and the color and processing area are adjustable.

The application discloses a dual-mode underwater acoustic sensor and a preparation method thereof. The sensor structure comprises an SOI substrate, a sensitive structure comprising a middle mass block, a rectangular beam and a frame supporting the mass block through the rectangular beam, a piezoresistive detection unit comprising a piezoresistive resistor arranged at the end of each rectangular beam and a metal lead and an electrode connected into a Wheatstone bridge, and a capacitive detection unit comprising movable comb-tooth capacitive plates arranged around the mass block except the side of the rectangular beam and fixed comb-tooth capacitive plates arranged on the frame and intersecting with the movable comb-tooth capacitive plates. When an underwater acoustic signal causes the mass block to be offset, the rectangular beam is bent to cause the piezoresistive resistor to change in resistance value, and the facing area of the comb-tooth capacitive plates is changed to cause the capacitance to change, so that piezoresistive and capacitive dual-mode signal detection is realized. The application integrates the advantages of high precision of piezoresistance and strong temperature drift resistance of capacitance through integrated design, the comb-tooth capacitive mode can calibrate the piezoresistive mode, and the measurement accuracy, stability and robustness in a complex marine environment are significantly improved.

A semiconductor device and a method for manufacturing the same are disclosed. According to an embodiment, the semiconductor device may include: an SOI substrate; a channel portion on the SOI substrate, the channel portion including a two-dimensional semiconductor material layer; a gate stack on the channel portion; and source / drain portions on the SOI substrate, located on opposite sides of the gate stack and disposed at opposite ends of the channel portion, wherein the two-dimensional semiconductor material layer is on the bottom surface and side surface of the gate stack, and extends on the side surface of the source / drain portion thereby being located between the side surface of the source / drain portion and the side surface of the gate stack.

The invention discloses an optical phased array transmitting system based on end face emergence. The optical phased array transmitting system comprises an antenna array composed of tip Si waveguides and a concave reflector based on a liquid crystal spatial light modulator. An SOI substrate in the antenna array comprises a substrate silicon layer and a buried oxide layer, a Si waveguide layer is located above the buried oxide layer and used for transmitting a light field, and the upper layer is covered with SiO2; similar cylindrical Fresnel lens phase distribution is applied to the LCOS-SLM liquid crystal spatial light modulator, so that the condensation performance similar to that of a cylindrical concave reflector is formed, and the longitudinal divergence angle of an emergent beam is reduced. Tip processing is carried out on the tail end of the Si waveguide, the emission efficiency is improved by introducing gradual change of the effective refractive index, meanwhile, an end face emission optical phased array antenna array is formed, the transverse light beam scanning capacity is achieved, deflection of different degrees is generated based on the main optical axis of the concave reflector, the longitudinal angle of reflected light is changed, and the reflection efficiency is improved. Therefore, the longitudinal scanning of the light beam is realized.