284 results about "Soi substrate" patented technology

Various embodiments of the present disclosure are directed towards an integrated chip (IC). The IC includes a substrate. The substrate includes a metal layer, a device layer disposed over the metal layer, and an insulating layer disposed vertically between the metal layer and the device layer. A semiconductor device is disposed on the device layer. An interlayer dielectric (ILD) layer is disposed over the semiconductor device and the substrate.

The invention belongs to the field of MEMS sensors, and discloses a high-temperature-resistant MEMS pressure sensor chip and a packaging structure thereof. The chip is provided with an SOI substrate, an AlN layer and a SiO2 layer from bottom to top, a plurality of P-type piezoresistors are arranged on the uppermost layer of the SOI substrate and are symmetrically distributed at the stress concentration position of the edge of the elastic diaphragm; a channel which continuously penetrates through the AlN layer and the SiO2 layer is arranged above the P-type piezoresistor; a metal Pad is arranged in the channel; the upper end of the metal Pad is located on the uppermost layer of the high-temperature-resistant MEMS pressure sensor chip, and the lower end of the metal Pad is in contact with the P-type piezoresistor. According to the invention, the relatively thick buried oxide layer can resist a high-temperature severe environment, and an AlN heat dissipation material with a high heat conductivity coefficient is deposited, so that rapid heat dissipation at a high temperature is ensured; and meanwhile, the stability and the reliability of the sensor are improved by adopting leadless packaging, and the packaging density is further optimized.

The invention discloses a preparation method of an FD-SOI substrate structure through a hydrogen, boron and nitrogen ion implantation process, and belongs to the technical field of semiconductor design and manufacturing. The preparation method comprises the following steps: preparing a first wafer and a second wafer; performing thermal oxidation treatment on the surface of the first wafer; performing hydrogen ion implantation and boron and nitrogen ion implantation processes on the first wafer to enable the first wafer to form a hydrogen implantation layer below the insulating oxide layer and form a boron and nitrogen implantation layer between the hydrogen implantation layer and the insulating oxide layer; combining the surface of the insulating oxide layer of the first wafer with a second wafer through a bonding process; stripping the first wafer, and recrystallizing the top silicon film through thermal annealing treatment; and etching the top-layer silicon film to be below the boron-nitrogen injection layer through wet etching treatment, so that the top-layer silicon film reaches the required thickness. According to the invention, the required ultrathin film structure can be obtained in a more controllable manner, and the single crystal property of the top silicon film is ensured.

The invention provides a semiconductor structure and a forming method thereof, the semiconductor structure comprises an SO I substrate, the SO I substrate comprises a bottom silicon layer, an insulating layer and a top silicon layer, the SO I substrate comprises a strip-shaped waveguide area and a ridge-shaped waveguide area, and a hard mask layer is formed on the surface of the SO I substrate; a strip-shaped waveguide is formed in the top silicon layer of the strip-shaped waveguide area, and a ridge-shaped waveguide is formed in the top silicon layer of the ridge-shaped waveguide area. According to the semiconductor structure and the forming method thereof, the influence of the etching load effect can be optimized, the etching depth accuracy of the ridge waveguide region and the grating region is improved, and the device performance is improved.

The present application discloses an optical chip and a preparation method for the optical chip. The optical chip includes a heat isolation substrate and an optical device structure layer formed based on a top silicon layer in an SOI substrate and located above the heat isolation substrate; where the heat isolation substrate is in a single-layer material structure or a laminated structure including a plurality of material layers, and the heat isolation substrate comprises at least one material layer formed of a material with a thermal conductivity less than 100 W / (m·K); the optical device structure layer sequentially from bottom to top includes: a protection layer; and a first optical device layer located on the protection layer and including at least one first optical device, where a light beam exiting through the optical device structure layer exits upward to a detection space.

The invention discloses a field-grinding direct-current modulation and coil induction integrated MEMS electric field sensor, and the sensor comprises a spiral coil induction electrode which is disposed on an SOI substrate, and converts the periodic change of an alternating-current electric field into a first signal; the comb tooth electrode structure is fixedly arranged on the SOI substrate and comprises a piezoelectric driving structure, at least two movable shielding electrodes and at least two fixed induction electrodes, and the piezoelectric driving structure is fixedly connected with the SOI substrate; the movable shielding electrode is elastically connected with the piezoelectric driving structure and generates periodic vertical displacement under the driving of the piezoelectric driving structure; the fixed induction electrode and the movable shielding electrode are correspondingly arranged to form an electrode group, and the low-frequency alternating-current and direct-current electric fields are modulated and converted into second signals. The invention has the beneficial effects that the full-band measurement of direct-current, low-frequency and high-frequency signals is realized, the measurement frequency range of the sensor is widened, the processing difficulty and the manufacturing cost are reduced, and the production efficiency is improved.

A semiconductor light emitting device includes a semiconductor light emitting laminate, and an SOI substrate including an upper semiconductor layer, an interlayer insulating film, and a lower semiconductor layer. The SOI substrate includes a first wiring electrode provided on the upper semiconductor layer through an insulating film and corresponding to a p-electrode, a second wiring electrode connected to the upper semiconductor layer and corresponding to an n-electrode, an anode that is provided on the lower semiconductor layer and connected to a first wiring electrode by a first via electrode passing through the SOI substrate, a cathode that is provided on the lower semiconductor layer through an insulating film and connected to the upper semiconductor layer by a second via electrode reaching the upper semiconductor layer. The p-electrode and the n-electrode are respectively bonded to the first wiring electrode and the second wiring electrode.

A kind of heart sound sensing structure and its preparation method, the structure includes double SOI substrate, center mass, elastic support beam, piezoresistive sensing unit and capacitive sensing unit.The front surface of center mass is provided with additional mass layer, and the back surface is kept bottom layer silicon to increase thickness;Elastic support beam connects mass and frame;Piezoresistive sensing unit is composed of four piezoresistors to form wheatstone bridge, and capacitive sensing unit includes movable and fixed comb-tooth capacitive plate crossing each other.When the sound pressure gradient of heart sound signal drives mass to deviate, elastic support beam bends to change piezoresistive value, and at the same time, comb-tooth capacitive plate overlapping area changes to cause capacitive value change, to realize piezoresistive and capacitive dual-mode synchronous detection.Two kinds of detection mechanisms calibrate each other, which significantly improves the sensitivity and anti-interference ability of low-frequency heart sound signal.The preparation method is based on double SOI substrate, integrated by ion implantation, etching, metal deposition and 3D printing process, suitable for miniaturized wearable heart sound monitoring application.

The invention relates to the technical field of photoelectric detector equipment, and discloses an ultra-high-speed silicon waveguide type photoelectric detector and a preparation method. The ultra-high-speed silicon waveguide type photoelectric detector comprises an SOI substrate, the SOI substrate is sequentially provided with a top silicon layer, a buried oxide layer and a bottom silicon substrate from top to bottom, the top silicon layer is etched to form a silicon waveguide structure, the silicon waveguide structure comprises a light absorption area and a spot size coupling area, and the spot size coupling area is formed in the light absorption area. A spot-size coupling structure is fixedly arranged on one side of the silicon waveguide structure, the spot-size coupling structure is of a rectangular pyramid structure, and the small-area surface of the frustum surface of the spot-size coupling structure is connected with a spot-size coupling area of the silicon waveguide structure; heavily-doped silicon areas are arranged on the buried oxide layers on the two sides, adjacent to the spot-size coupling structure, of the silicon waveguide structure, a plurality of metal electrode plates are arranged on the heavily-doped silicon areas, and a silicon oxide covering layer is arranged on the surface of the spot-size coupling structure; the invention has the advantages of realizing high-efficiency light absorption and high-frequency response.

The invention discloses a preparation method of an FD-SOI substrate structure through a hydrogen, carbon and germanium ion implantation process, and belongs to the technical field of semiconductor design and manufacturing, and the method comprises the steps: preparing a first wafer and a second wafer; performing thermal oxidation treatment on the surface of the first wafer; performing hydrogen ion implantation, carbon ion implantation and germanium ion implantation on the first wafer to enable the first wafer to form a hydrogen implantation layer below the insulating oxide layer, form a first implantation layer between the hydrogen implantation layer and the insulating oxide layer, and form a second implantation layer between the first implantation layer and the insulating oxide layer; combining the first wafer with the second wafer; stripping the first wafer to form a top silicon film on the second wafer, and recrystallizing the top silicon film through thermal annealing treatment; and etching the top silicon film to the required thickness through wet etching treatment. The top silicon film prepared by the method can be thinner and higher in size precision, and the process consistency is stable.

A film structure comprises a substrate and a buffer film formed on the substrate. The substrate is a 36° to 48° rotated Y-cut Si substrate, or the substrate is a SOI substrate comprising a base substance made of the 36° to 48° rotated Y-cut Si substrate, an insulating layer on the base substance, and a SOI layer made of a Si film on the insulating layer, and a Miller index of a crystal plane of an upper surface of the SOI layer is equal to the Miller index of a crystal plane of an upper surface of the base substance. The buffer film comprises ZrO2 epitaxially grown on the substrate.

The invention relates to a method and a device for cleaning the edge of an SOI (Silicon On Insulator) substrate. The method for cleaning the edge of the SOI substrate comprises the following steps of: providing the SOI substrate to be cleaned, wherein the SOI substrate comprises a front surface and a back surface which are oppositely distributed; spraying chemical cleaning liquid to the edge area of the front surface of the SOI substrate, and spraying gas to the back surface of the SOI substrate at the same time to form a gas protection layer covering the back surface of the SOI substrate; and washing the SOI substrate by using deionized water, and removing the residual chemical cleaning liquid. According to the invention, corrosion of chemical cleaning liquid to the back surface of the SOI substrate is reduced and even avoided, so that the cleaned SOI substrate meets strict quality requirements of an integrated circuit on the surface of the SOI substrate.

An integrated circuit device includes: a semiconductor on insulator (SOI) substrate layer including a base substrate layer, an insulating substrate layer, and a cover substrate layer; a semiconductor substrate layer; a plurality of first fin-type active areas and a plurality of second fin-type active areas each defined by a plurality of trenches, and extending in a first horizontal direction, in above the SOI substrate layer and the semiconductor substrate layer, respectively; a plurality of nanosheet stacked structures comprising nanosheets extending in parallel with each other and spaced apart from upper surfaces of the plurality of first fin-type active areas and the plurality of second fin-type active areas; a plurality of first source / drain regions extending into the SOI substrate layer; and a plurality of second source / drain regions extending into the semiconductor substrate layer. Lower surfaces of the first and second source / drain regions may not be coplanar with each other.

The application belongs to the technical field of micro electro mechanical system sensors, and discloses an acceleration sensor chip with a DLC optimized structure and a preparation method thereof; in the piezoresistive acceleration sensor chip, an SOI substrate is bonded to boron glass through a substrate frame, and a center mass is connected to the substrate frame through four embedded micro-beams arranged in a cross shape; four piezoresistance strips are arranged on the four embedded micro-beams, and the four piezoresistance strips are connected into a Wheatstone full bridge through surface metal leads deposited on the SOI substrate and connected with pads deposited on the SOI substrate; wherein, a DLC film is deposited on the SOI substrate, and the DLC film covers the surface metal leads, the four piezoresistance strips and the area of the SOI substrate except the pads. The application can improve the sensitivity of the sensor while ensuring the strength of the sensitive structure; the protection of the piezoresistance strips is realized, and the reliability of the sensor can be improved.

This invention provides a quasi-two-dimensional / two-dimensional van der Waals heterojunction based on SOI and Si / WS2, its preparation method, and its application. The method includes the following steps: cleaning the SOI substrate; using sulfur powder, tungsten oxide powder, sodium chloride powder as a catalyst, and erbium chloride and ytterbium chloride powder as dopants, chemical vapor deposition is performed on the SOI substrate to prepare an erbium- and ytterbium-doped monolayer WS2 material; the top silicon layer of the SOI substrate is an n-type silicon layer. This invention, employing the above-mentioned quasi-two-dimensional / two-dimensional van der Waals heterojunction based on SOI and Si / WS2, its preparation method, and its application, effectively reduces the defect density during material synthesis while significantly increasing the carrier concentration in the material. The prepared photodetector exhibits good photoelectric response performance, providing a simple and efficient new method for the preparation of high-performance heterojunction photodetectors.

Provided is a light detection device in which an oxide film is formed on the bottom of a fin of a transistor in a bulk substrate without using an SOI substrate. The light detection device includes a first substrate portion and a second substrate portion. The first substrate portion has pixels that photoelectrically convert incident light. The second substrate portion is bonded to a surface of the first substrate portion opposite to a light incident surface. The second substrate portion has a plurality of elements constituting a readout circuit configured to output a pixel signal based on a charge output from the pixel. A pattern of an insulating film is formed on a bonding surface of the second substrate part that is bonded to the first substrate part.

The invention provides a semiconductor structure and a manufacturing method thereof, and the method comprises the steps: providing a substrate structure which comprises a back substrate, a buffer layer and a top silicon layer, a second groove is formed in the base structure, and the buffer layer is removed through etching of the second groove so that a cavity can be formed between the back substrate and the top silicon layer; according to the method, the top silicon layer is provided with a cavity, the cavity is filled with a buried oxide layer to form the SOI substrate, so that the thickness of the top silicon layer and the thickness of the buried oxide layer can be controlled to obtain the SOI substrate with the ideal thickness, the SOI substrate is prevented from being formed through an ion implantation process, correspondingly, ion implantation damage is avoided, and the quality and reliability of the formed SOI substrate are improved.

Semiconductor-on-insulator substrate, SOI substrate, comprising: a handling substrate (104); a device layer (108) that lies above the handling substrate (104); and an insulating layer (106) separating the handling substrate (104) from the device layer (108), wherein the insulating layer (106) meets the device layer (108) at a first interface and meets the handling substrate (104) at a second interface, wherein the insulating layer (106) has a getter material with a getter concentration profile, the getter concentration profile having a first peak concentration at the first interface, a second peak concentration at the second interface and a trough concentration at a location between the first interface and the second interface, wherein the trough concentration is smaller than each of the first peak concentration and the second peak concentration, the getter material contains fluorine.

The invention relates to the technical field of optical sensors, in particular to a super-multilayer dielectric film structure optical refractive index sensor based on Fano resonance. The device sequentially comprises a prism layer, a modified cerium oxide layer, a functional layer, an interface layer, a substrate layer and a to-be-detected dielectric layer from top to bottom, the prism layer is a rutile prism, the substrate layer is an SOI substrate, and in the to-be-detected dielectric layer, a to-be-detected medium comprises water and ethanol; the interface layer is arranged on the substrate layer in a coating manner, the functional layer comprises a plurality of groups of units obtained by alternate deposition, and each unit comprises a vanadium dioxide layer and an indium trichloride tetrahydrate doped SiO2 layer which are arranged in sequence. The invention provides an optical refractive index sensor with a super-multilayer dielectric film structure based on Fano resonance, and aims to solve the problems of relatively low sensor sensitivity caused by relatively high cost and poor binding force with oxide materials of precious metals used in traditional materials and relatively weak surface plasmons excited by some oxide materials in related technologies.

The invention provides a nitrogen-doped upright graphene heterojunction, a preparation method, application, a signal coding device, an image generation device and an image generation method. The preparation method comprises the following steps: placing an SOI substrate in a growth chamber; vacuumizing the growth chamber; heating the SOI substrate; introducing methane and ammonia gas into the growth chamber, and growing nitrogen-doped upright graphene on the surface of the SOI substrate by a PECVD (Plasma Enhanced Chemical Vapor Deposition) process; and spin-coating a gold nanocluster solution on the surface of the nitrogen-doped upright graphene, so that gold nanoclusters are attached to the interior of the nitrogen-doped upright graphene.

The invention provides a semiconductor device and a manufacturing method thereof, the semiconductor device comprises an SOI substrate, the SOI substrate comprises a lower substrate, an insulating buried layer and a semiconductor layer, the SOI substrate comprises a plurality of semiconductor devices, the plurality of semiconductor devices comprise first optical couplers, and the first optical couplers are arranged on the lower substrate; a first groove which penetrates through the lower substrate and the insulating buried layer and exposes the semiconductor layer of the first optical coupler is formed in the SOI substrate; and the insulating medium layer covers one surface, on which the semiconductor layer is formed, of the SOI substrate. According to the technical scheme, the packaging flexibility of the chip can be improved.

An epitaxial growth method of an FDSOI mixed region and an FDSOI, the method comprising: providing an SOI substrate, the SOI substrate comprising a bottom silicon layer, a buried oxide layer and a top silicon layer stacked in sequence, the SOI substrate having a first preset region and second preset regions adjacent to two sides of the first preset region; carrying out modification treatment on the top layer silicon in the first preset region and the second preset region in the SOI substrate to form a top layer silicon modified region; a groove is formed in the first preset area of the SOI substrate, the groove penetrates through the top layer silicon modified area and the buried oxide layer of the first preset area, the side wall of the groove exposes the top layer silicon modified area of the second preset area, and the bottom wall of the groove exposes the top surface of the bottom layer silicon; and forming a silicon epitaxial layer in the groove from the top surface of the bottom layer silicon by adopting a selective epitaxial growth process. According to the invention, the bump defect on the silicon surface can be improved.

This application discloses a semiconductor device structure, a CMOS structure, and a method for fabricating the same, relating to the field of semiconductor device technology. The semiconductor device structure employs two buried oxide layers interleaved within a three-layer silicon SOI substrate. The epitaxial initiation layer of the source / drain regions is transferred from the top silicon layer of the SOI substrate to an intermediate or supporting silicon layer within the SOI substrate. This solves a series of process problems arising from the development of SOI technology nodes, particularly in epitaxially growing source / drain regions on a thinner top silicon layer, thus improving the epitaxial growth quality and structural stability of the source / drain regions. Furthermore, the parallel overlap length between the source / drain regions and the gate structure is reduced, significantly decreasing the parasitic capacitance between the source / drain regions and the gate structure. Moreover, the source / drain regions can directly contact the channel, enhancing the contact reliability between the source / drain regions and the channel, enabling stress control of the channel, and improving channel mobility, thus possessing significant application value.

The present disclosure relates to methods of forming silicon-on-insulator substrates. A method of forming an SOI substrate includes performing a hydrogen thermal treatment on a pretreated sacrificial wafer at an elevated temperature. A stop layer and a semiconductor layer can be sequentially formed on a first surface of the sacrificial wafer on which the hydrogen (H2) thermal treatment was performed. The stop layer and the semiconductor layer can be formed by an epitaxial growth process using a hybrid precursor including monosilane (MS) and dichlorosilane (DCS) sources.

The application provides a photoelectric detector and a manufacturing method thereof. The manufacturing method of the photoelectric detector comprises the following steps: providing an SOI substrate, wherein the SOI substrate comprises a lower substrate, an insulating buried layer and a semiconductor layer from bottom to top; forming a first insulating medium layer on the top surface and the sidewall of the semiconductor layer; removing the first insulating medium layer on the top surface of the semiconductor layer; forming a second insulating medium layer covering the semiconductor layer and the first insulating medium layer; etching part of the thickness of the second insulating medium layer by using a dry etching process to form an opening; etching the second insulating medium layer on the bottom wall of the opening by using a wet etching process to expose part of the top surface of the semiconductor layer; and forming a semiconductor absorption layer on the exposed semiconductor layer. The technical scheme of the application can improve the growth quality of the semiconductor absorption layer, thereby reducing the dark current of a silicon optical chip, improving the transmission bandwidth of the silicon optical chip and the like.

A method for fabricating a semiconductor device, the method comprising the steps of: providing a silicon-on-insulator (SOI) substrate, the SOI substrate comprising a groove exposing different crystal facing a planar surface; depositing a buffer layer over the substrate; epitaxially growing a semiconductor layer over the buffer layer, whereby least a portion of the buffer layer exhibits a cubic crystalline phase structure.

A method of forming an SOI substrate including a hydrogen thermal treatment performed on a pretreated sacrificial wafer, under high temperature. A stopper layer and a semiconductor layer may be sequentially formed on a first surface of the sacrificial wafer on which the hydrogen (H2) thermal treatment was performed. The stopper layer and the semiconductor layer may be formed by an epitaxial growth process using a mixed precursor including a monosilane (MS) source and a dichlorosilane (DCS) source.

The invention belongs to the technical field of MEMS loudspeakers, and particularly relates to a preparation method of a PZT loudspeaker based on a back guide structure. Comprising the steps that a bottom electrode metal film and a PZT piezoelectric film are sequentially sputtered on the front face of a device at high temperature through a magnetron sputtering PVD technology; performing a bottom electrode layer structure photoetching process; performing a top electrode layer photoetching process; performing an upper and lower electrode isolation layer photoetching process, performing a front surface back guide hole structure photoetching process, and etching a top silicon layer of the SOI substrate material sheet through ICP (Inductively Coupled Plasma) to form a device back guide hole structure; depositing a Parylene protection material on the front side by a vacuum vapor deposition process; and performing a back photoetching process, and etching the back of the SOI substrate material sheet through ICP (Inductively Coupled Plasma) to form a device diaphragm cavity structure. According to the invention, the air circulation resistance of the rear cavity can be accurately controlled, the quality-spring property of the diaphragm can be matched, the rigidity and damping of the diaphragm can be balanced, the resonance peak can be effectively reduced, the low-frequency response bandwidth can be expanded, and the SPL can be improved.

The invention discloses a silicon-based III-V group nano ridge waveguide laser and a preparation method thereof, and the preparation method comprises the steps: preparing an optical coupler and a silicon waveguide with a side grating by using a top silicon layer of an SOI substrate, depositing a silicon dioxide layer, preparing a rectangular groove in the silicon dioxide layer and a buried oxide layer of the SOI substrate, and preparing a silicon waveguide with a side grating. A V-shaped silicon groove is prepared in a substrate silicon layer of an SOI substrate at the bottom of a rectangular groove, III-V group nano ridge waveguides are epitaxially grown in the V-shaped silicon groove and the rectangular groove, metal electrodes are prepared at the top of the III-V group nano ridge waveguides and the top of the substrate silicon layer of the SOI substrate respectively, a chip is dissociated, and two end faces of the III-V group nano ridge waveguides are finely trimmed through FIB. And a high-reflective film is plated on the end surface of the III-V group nano ridge waveguide far away from the optical coupler. According to the invention, the N-type upper cladding layer and the N-type contact layer with low resistance are used to replace a traditional P-type upper cladding layer and a P-type contact layer; in addition, the grating structure is prepared on the side wall of the silicon waveguide, so that the silicon waveguide with the side grating can be synchronously prepared when silicon optical devices such as an optical coupler are prepared.

The application relates to an integrated circuit electrostatic protection reliability design in the field of semiconductor technology, in particular to an H-shaped fin silicon structure ESD protection device applied to an SOI-FinFET process; a longitudinal fin silicon, a transverse fin silicon, a dielectric and a gate electrode are prepared based on an SOI substrate; the longitudinal fin silicon comprises longitudinal fin silicon one and longitudinal fin silicon two; the longitudinal fin silicon one comprises two kinds of doped regions of first and second semiconductor types, the longitudinal fin silicon two is of the second semiconductor type, the transverse fin silicon is of the second semiconductor type, the longitudinal fin silicon one, the longitudinal fin silicon two and the transverse fin silicon three jointly form an H-shaped fin silicon structure and are electrically connected, and a carrier control region is only a part of the longitudinal fin silicon one, the longitudinal fin silicon two and the transverse fin silicon; a novel ESD protection device can be implemented under the SOI-FinFET process, the device is different from a substrate under an insulating layer which must be used in the electrostatic protection technology related to the Bulk-FinFET process, and a good electrostatic protection method is provided for the SOI-FinFET process.