9 results about "Back bias" patented technology

A method for making a cutting tool for machining titanium alloy or superalloy, including introducing pure N2 and Ar into a chamber comprising a heater and a substrate, keeping a temperature of the heater constant, applying a back bias voltage on the substrate, and forming a Me-B—N coating on the substrate by magnetron sputtering technology. The flow ratio of pure N2 to Ar is 0.06-0.25; the pressure in the chamber is 0.4-4 pascal; and the temperature of the heater in the chamber is in a range of 300-600° C. A Me-B target is adopted, and a planet carrier supporting the substrate is connected to a negative pole of a power supply. The rotating speed of the planet carrier is 3 rpm, the back bias voltage is −50 to −300 V, and the time for coating is 60-300 min.

The present application provides a method for optimizing a junctionless transistor. The junctionless transistor comprises a substrate, a buried oxide layer on the substrate, a core layer on the buried oxide layer, a shell layer on the core layer, a gate on the shell layer, and a source and a drain on two sides of the gate, wherein the doping concentration of the shell layer is less than the doping concentration of the core layer, and the value of a back bias can be determined for the junctionless transistor on the basis of the type of the junctionless transistor, wherein if the type of the junctionless transistor is an N-type device, the value of the back bias is a negative value, and if the type of the junctionless transistor is a P-type device, the value of the back bias is a positive value. When the junctionless transistor is in a working state, the back bias can be applied to the substrate, the electric field generated by the back bias is transmitted to the core layer and the shell layer by means of the buried oxide layer, and the generated electrostatic doping effect can flexibly control the carrier concentration distribution inside the source / drain and a channel, so as to reduce the source-drain series resistance of the junctionless transistor. Therefore, the conductivity of a device can be increased without changing the internal structure of the device, thereby increasing the output current.

According to one aspect of the disclosure, a sensor includes a substrate; a back bias magnet arranged to generate a bias field at least having components in a plane parallel to a surface of the substrate, the bias field having a horizontal symmetry axis within the plane; and a plurality of sensing element groups disposed at different locations on a surface of the substrate and laid out along a common line aligned with the horizontal symmetry axis of the back bias magnet, each of the plurality of sensing element groups having one or more tunneling magnetoresistance (TMR) vortices having an axis of maximum sensitivity aligned with the common line.

The invention provides a driving current adjusting method and circuit, a driving device and electronic equipment, and relates to the technical field of current adjustment. The resistance value of a series resistor of the short-channel FDSOI transistor is adjusted by applying a target back bias voltage to a substrate electrode of the short-channel FDSOI transistor, and finally the purpose of adjusting a driving current when a driving voltage is applied to the short-channel FDSOI transistor is achieved. Therefore, according to the technical scheme provided by the invention, the resistance value adjustment of the series resistor can be realized without changing the structure, the material and the preparation process of the FDSOI transistor, and finally the purpose of adjusting the driving current is achieved.

The invention relates to the technical field of wireless communication, in particular to a compact type dynamic polarization agility and wave beam two-dimensional reconfigurable antenna and a control method, the structure comprises a guide layer substrate, the surface of the guide layer substrate is provided with four groups of reconfigurable metal wires, and each group comprises five metal wire segments connected through microwave diodes and a back bias circuit; the parasitic layer substrate is provided with a circular metal patch of which the radius is 0.2 lambda 0; a multilayer substrate is driven, and a radiation patch, a grounding layer and a feed network layer with a single-pole six-throw switch are integrated. According to the system, the polarization state of the single-pole six-throw switch and the bias voltage of the four groups of leading metal wires are synchronously controlled through 12-bit digital codes, so that 96 working mode codes are generated, the azimuth angle of a wave beam covers 0-360 degrees, and the pitch angle of the wave beam covers-30 degrees to + 30 degrees. According to the invention, the beam radiation state theoretically has 96 polarization and beam states, the radiation beam can change in two dimensions, the azimuth angle ranges from 0 to 360 degrees, and the pitch angle ranges from-30 to + 30 degrees.

The invention provides an optimization method of a junction-free transistor, the junction-free transistor comprises a substrate, a buried oxide layer on the substrate, a core layer on the buried oxide layer, a shell layer on the core layer, a grid electrode on the shell layer, and a source electrode and a drain electrode at two sides of the grid electrode, and the doping concentration of the shell layer is smaller than that of the core layer. According to the type of the junction-free transistor, a back bias value can be determined for the junction-free transistor, if the type of the junction-free transistor is an N-type device, the back bias is a negative value, and if the type of the junction-free transistor is a P-type device, the back bias is a positive value, when the junction-free transistor is in a working state, the back bias can be applied to the substrate, and the back bias is applied to the substrate. An electric field generated by back bias is transmitted to the core layer and the shell layer through the buried oxide layer, and the generated electrostatic doping effect can flexibly control the carrier concentration distribution in the source drain and the channel so as to reduce the source drain series resistance of the junction-free transistor, so that the conductivity of the device can be improved under the condition that the internal structure of the device is not changed, and the output current is improved.

This invention provides a semiconductor structure and its manufacturing method. The semiconductor structure includes: a substrate; an insulating layer located on the substrate; an active layer located on the insulating layer, the active layer having an etch-back region, an inverted trapezoidal trench within the etch-back region, and platforms on both sides thereof, the thickness of the active layer at the bottom of the inverted trapezoidal trench being less than the thickness of the active layer at the platforms; a gate structure located within the inverted trapezoidal trench; and source and drain electrodes located on the platforms. This invention utilizes the inverted trapezoidal trench design, combined with the characteristics of thick silicon being sensitive to reverse bias to reduce leakage current and thin silicon being sensitive to forward bias to increase conduction current, thus expanding the adjustment range of the back bias. Simultaneously, the thicker platform effectively suppresses source and drain diffusion, providing a possibility for device layout miniaturization.

The application provides a two-bit resistance variable memory structure based on FDSOI, a process integration method and an operation method. The structure comprises a substrate, an insulating layer, a semiconductor layer, an ultra-shallow trench isolation structure and a transistor. A shared bit line structure is arranged above the ultra-shallow trench isolation structure and is arranged in the same layer as the gate. A first resistance variable memory unit is arranged between the shared bit line structure and the drain and is formed based on a high dielectric layer and a metal gate layer. A second resistance variable memory unit is arranged above the drain and is connected to a separate bit line. The application forms the shared bit line and the first resistance variable unit by multiplexing the front-end process, combines the second resistance variable unit in the back-end, realizes a single-transistor double-resistance structure, improves the storage density without additional masks, adjusts the read current by using a back bias voltage, improves the storage window and reduces the leakage, and solves the problems of the prior art, such as complex process and large power consumption.

A memory device includes a cell region including a plurality of channel structures; and a peripheral circuit region including peripheral circuits controlling the cell region. Each of the plurality of channel structures includes a back electrode layer, and a ferroelectric layer and a channel layer. In a program operation for a selected memory cell, the peripheral circuit region is configured to input a pass voltage to a selected word line and input a back bias voltage to the back electrode layer from a first point in time, maintain a voltage of the back electrode layer at the back bias voltage during a period from a second point in time to a third point in time after the first point in time, and input the pass voltage to unselected word lines, different from the selected word line after the third point in time.