794 results about "Logic state" patented technology

The invention discloses an interval occupation logic checking method, a train control system, a storage medium and electronic equipment, which are used for automatically blocking a standard railway line, and the method comprises the following steps: acquiring train position information and a train type; acquiring track circuit data, and judging a track section state; and generating a corresponding signal permission for the train based on the train position information, the train type and the track section state, and judging the logic state of the corresponding block partition based on the signal permission. The method has the advantages that the normal train, the fault train and the non-moving block train can be ensured to safely run on the automatic block system railway line at the same time, the normal train can still adopt the moving block system and does not need to be degraded into the automatic block system, the running density of the normal train is improved, and the running efficiency is improved. Therefore, the traffic capacity of the automatic block type railway line is improved.

A multirail-encoded qubit can be implemented using a quantum system having a state space that includes a number M of distinct modes, where M is an integer greater than 2. The M modes are logically partitioned into two disjoint subsets (or “bands”), with each mode assigned to exactly one of the bands. The multirail encoding is defined such that a state in which any one of the modes in the first band is occupied and all modes in the second band are unoccupied maps to a logical 0 state of the qubit, and a state in which any one of the modes in the second band is occupied and all modes of the first band are unoccupied maps to a logical 1 state. Systems and methods for generating, measuring, and operating on multirail-encoded qubits are disclosed.

A system and method for an electrostatic discharge (ESD) clamp circuit containing a disable circuit to selectively disable a discharge circuit is disclosed. An electrostatic discharge (ESD) clamp circuit including a discharge circuit to discharge a current flow during a transient ESD voltage event; a disable input to receive a disable input signal; and a disable circuit to, based upon the disable input signal, selectively disable the discharge circuit. When the disable input signal is a first logic state, the disable circuit is to allow the discharge circuit to be enabled; and when the disable input signal is in a second logic state, the disable circuit is to disable the discharge circuit.

The invention relates to the technical field of distributed computing, and discloses a heavy truck charging load scheduling-oriented distributed energy intelligent matching method, which comprises the following steps of: establishing a charging service computing power mapping table at a scheduling node; maintaining a shadow counter in a local memory, extracting a pre-estimated computing power consumption value according to an event type and accumulating the pre-estimated computing power consumption value to the shadow counter, and executing linear numerical deduction on the shadow counter according to a reference logic subtraction rate so as to simulate a scheduling data throughput evolution process; adjusting a linear deduction rate parameter according to the deviation between the state feedback data and the numerical value of the shadow counter; and distributing the charging matching task to a charging station edge computing node of which the shadow counter value does not exceed a preset logic saturation threshold value. According to the invention, through an open-loop estimation and closed-loop calibration mechanism of a local logic state, an instantaneous congestion risk caused by physical feedback lag is eliminated; and logic state consistency and self-adaptive distribution of the whole network computing power resources are realized.

The invention belongs to the field of electronic devices, particularly relates to an anti-SET reinforced phase frequency detector, and aims to solve the problems that the existing SET injection can change the output logic state of a PFD (phase frequency detector), and a post-stage circuit obtains a wrong phase difference indication signal. According to the invention, an output UP signal and an output DOWN signal of a first-stage unit are used as the input of an input control logic, and the input control logic outputs four indication signals; the input of the first output control logic is four indication signals, and the output of the first output control logic is a first conduction control signal; the second-stage unit is used for carrying out rising edge sampling on the UP signal and the DOWN signal respectively and outputting two indication signals; the input of the phase selector is a reference clock signal, a feedback clock signal and two indication signals, the output of the phase selector is the input of the second output control logic, and the second output control logic outputs a second conduction control signal. According to the invention, the output logic state is not changed during SET injection, and a correct phase difference indication signal is obtained at a rear stage.

A device includes a memory cell that randomly presents either a first logic state or a second logic state. The memory cell includes: a plurality of first nanostructures extending along a first lateral direction; a plurality of second nanostructures extending along the first lateral direction and disposed at a first side of the plurality of first nanostructures; a plurality of third nanostructures extending along the first lateral direction and disposed at a second side of the plurality of first nanostructures; a dielectric fin structure disposed immediately next to the plurality of first nanostructures along a second lateral direction, wherein a first sidewall of each of the plurality of first nanostructures facing toward or away from the second lateral direction is in contact with the dielectric fin structure; and a first gate structure wrapping around each of the plurality of first nanostructures except for the first sidewall.

The invention relates to the technical field of data processing, and discloses a college budget management system fused with a new quality productivity theory, comprising: a state characterization interface collects process characterization data and maps the process characterization data into a discrete innovation state bit vector; the differential efficiency mapping unit responds to the state bit jump to calculate an efficiency marginal increment and generate an injection instruction; the physical bypass monitoring channel collects physical consumption time sequence data, and the entropy analysis closed-loop unit calculates a metabolic entropy representing the resource consumption order degree; the budget dynamic response control unit generates a state locking instruction when the state bit is constant and the metabolic entropy meets the low-entropy convergence condition, the physical working condition entropy is used for correcting the logic state, and the project resource state is maintained by recognizing the low-entropy resource consumption characteristics when no dominant output exists; the problem that discrete evaluation indexes cannot represent blind areas of continuous scientific research activities is solved.

An apparatus includes a transmitter, a voltage regulator, an isolator, and a test controller. The transmitter has an input, an output, and a first supply voltage terminal. The input couples to the apparatus' input terminal. The voltage regulator's input couples to a second supply voltage terminal. The voltage regulator's output couples to the first supply terminal. The first terminal of the isolator couples to the output of the transmitter. A first test controller terminal couples to the second supply voltage terminal. A second test controller terminal couples to the input terminal of the apparatus. The first control output couples to the control input of the voltage regulator. The test controller changes a logic state of a control signal at the first control output from a first logic state to a second logic state.

A modular quantum key distribution system and relative modulation module and demodulation module. The system includes: a photon source module; a modulation module, physically separated from the source module and operatively connected to the source module by a first optical communication channel and including a first polarization stabilizer and a first retarder plate and a second retarder plate, placed downstream of the first polarization stabilizer and controlled by an actuator; and a receiving unit operatively connected to the modulation module by a second optical communication channel and including a second polarization stabilizer, a third retarder plate, placed downstream of the second polarization stabilizer and controlled by an actuator, a polarizing beam splitter, placed downstream of the third retarder plate, and a single photon photodetector configured to detect a logic state of each photon and transmit the detected logic state to a counting register.

Methods and systems are directed to protect a target logic circuit against optical probing attacks and conceal a logic state in the target logic circuit. The method comprises designing a concealing logic circuit. The concealing logic circuit can be coupled to complement of input signals of the target logic circuit, inserted as neighbor logic circuit of the target logic circuit, and placed in close optical proximity to the target logic circuit. The concealing logic circuit can operate in the opposite operation mode or logic state of the target logic circuit in response to the complement of the input signals to the target logic circuit. The method can further comprise designing an evaluation circuit that generates the complement of the input signals and minimizes a path delay between the target logic circuit input and the concealing logic circuit input.

The invention relates to the technical field of chip simulation, in particular to a voltage logic simulation design method and system for a passive internet-of-things tag chip. The method comprises the following steps: performing energy characteristic measurement on the tag chip, and calculating voltage fluctuation and logic gate triggering probability to obtain energy logic state mapping data; state transition probability distribution mapping is carried out according to the energy logic state mapping data, and a transition probability distribution tensor is constructed; collecting measurement environment parameters in the energy characteristic measurement process, and performing dynamic environment interference compensation on the transition probability distribution tensor to generate an interference compensation distribution tensor; carrying out simulation precision demand distribution based on the interference compensation distribution tensor, and constructing a layered simulation configuration file; and performing multi-precision parallel simulation execution based on the layered simulation configuration file, and generating a probabilistic verification report. Through precise and efficient logic simulation, the reliability of chip design is improved, and the fault probability is reduced.

A power stage includes parallel FETs including a reference FET. An input PWM signal has a switching period. A current sensor senses current flowing through the power stage during switch-on period. A first circuit generates a first PWM signal having a duty-cycle indicative of reference FET driving losses for a reference current. A second circuit generates a second PWM signal having a duty-cycle indicative of reference FET conduction losses for that reference current. The duty cycles of the first and second PWM signals are compared to generate a comparison signal. The reference current is changed until a logic state of the comparison signal changes. A respective enable signal for each FET is generated by comparing the reference current to the sensed current flowing through the power stage. A FET driver circuit generates a respective drive signal for each FET by combining the respective enable signal with the input PWM signal.

Systems, methods, and apparatus related to memory devices. In one approach, a memory device has a memory array including memory cells. A controller of the memory device applies multiple pre-read voltages to memory cells prior to performing write operations on the memory cells. The controller applies a first pre-read voltage to determine which of the memory cells have a sensed current that exceeds a threshold. In response to determining that a percentage of the memory cells exceeding the threshold is too low (e.g., below a fixed limit), the controller determines to apply a second pre-read voltage to the memory cells. The second pre-read voltage has a greater magnitude than the first pre-read voltage, and can be applied to ensure greater reliability in properly determining the existing programming state of the memory cells. The controller then applies write voltages to the memory cells as appropriate based on target logic states for each memory cell and the programming mode to be used by the controller.

A semiconductor device includes a memory cell randomly presenting a first logic state or a second logic state and formed on a first side of a substrate, and a first and a second bit lines formed on a second side of the substrate opposite to the first side. The memory cell includes: a programming transistor having a first and a second source / drain terminals; a first reading transistor having a first source / drain terminal coupled to the first source / drain terminal of the programming transistor; and a second reading transistor having a first source / drain terminal coupled to the second source / drain terminal of the programming transistor. The first bit line is operatively coupled to a second source / drain terminal of the first reading transistor, and the second bit line is operatively coupled to a second source / drain terminal of the second reading transistor.

Methods, systems, and devices for signal development caching in a memory device are described. In one example, a memory device in accordance with the described techniques may include a memory array, a sense amplifier array, and a signal development cache configured to store signals (e.g., cache signals, signal states) associated with logic states (e.g., memory states) that may be stored at the memory array (e.g., according to various read or write operations). In various examples, accessing the memory device may include accessing information from the signal development cache, or the memory array, or both, based on various mappings or operations of the memory device.

A memory device includes a memory cell array including a plurality of bit cells, each of the bit cells coupled to one of a plurality of bit lines and one of a plurality of word lines, respectively, wherein each of the plurality of bit cells is configured to: present an initial logic state during a random number generator (RNG) phase; and operate as a memory cell at a first voltage level during a SRAM phase; and a controller controlling bit line signals on the plurality of bit lines and word line signals on the plurality of word lines, wherein the controller is configured to: during the RNG phase, precharge the plurality of bit lines to a second voltage level, and determine the initial logic states of the plurality of bit cells to generate at least one random number, wherein the second voltage level is lower than the first voltage level.

A voltage provision circuit includes a first NMOS transistor gated with a first control signal and sourced with a ground voltage, a second NMOS transistor gated with a second control signal complementary to the first control signal and sourced with the ground voltage, a first PMOS transistor sourced with a first supply voltage, a second PMOS transistor sourced with the first supply voltage, and a voltage modulation circuit that is coupled between the first to second PMOS transistors and the first to second NMOS transistors, and is configured to provide a first intermediate signal based on the first and second control signals. The first intermediate signal has a first logic state corresponding to the first supply voltage and a second logic state corresponding to a second supply voltage that is a fraction of the first supply voltage.

The invention discloses a reliability test verification method for a CAN bus control module in an MCU, and relates to the field of chip test verification, and the method comprises the following steps: a CAN bus controller is integrated into the MCU through a bus interconnection mode, and the method is mainly divided into an interface management logic part, a state control logic part, an error detection logic part and an information buffer part; an MCU integrated with a CAN control module is used as a single node, a double-node frame information transmitting and receiving mode is adopted to build a test platform, a signal control module is added to apply interference to different positions where the nodes transmit the frame information, the error condition in real use is simulated, and the test efficiency is improved for different tests. And the correctness of the verification result of the CAN control module is determined by detecting the output signal of the MCU and the signal on the bus.

The invention provides an SRAM (Static Random Access Memory) storage unit anti-single particle radiation reinforcement method and system, and relates to the technical field of microelectronics and circuit structure design, a redundant node coupled with a main storage node of an SRAM storage unit is constructed, and the redundant node is used for redundant storage of the logic state of the main storage node; the polarity of a main storage node is reinforced by configuring the main storage node into a circuit structure fully surrounded by a single-type transistor; wherein the redundant node and the main storage node after polarity reinforcement are integrated into a reinforced SRAM (Static Random Access Memory) storage unit. According to the method, circuit-level fusion and collaborative design are carried out on redundancy reinforcement and polarity reinforcement, so that the single event upset resistance of the SRAM unit is improved, and an efficient and enforceable reinforcement design method is provided.

The utility model discloses a three-state switching signal acquisition system, which realizes low static loss and instant wake-up capability of a controller. The system comprises a three-state switching signal acquisition circuit and a wake-up circuit, the power supply end of the acquisition circuit is connected with a first power supply; the first power supply is turned on when the controller works normally and turned off when the controller is dormant; the power end of the wake-up circuit is connected to a second power supply; the acquisition circuit is connected between the output end of the three-state switch and the first input end of the controller and is used for converting different logic states output by the three-state switch into signals with different voltage values under the power supply of the first power supply; the wake-up circuit is connected between the output end of the three-state switch and the second input end of the controller, and is used for switching the logic state of the output end of the three-state switch from a suspended state to a high level or a low level under the power supply of the second power supply after the first power supply is turned off, and converting the logic state into a preset wake-up signal; the wake-up signal is used for waking up the controller from the dormant state to the normal working state.

The invention discloses an interconnection-line-free carrier synchronization method and device, equipment and a storage medium, and relates to the technical field of power systems. The method comprises the following steps: acquiring a voltage signal of a grid-connected point, and determining a first interruption triggering moment according to the state of the voltage signal by using a logic state capturing unit; determining a clock reference moment corresponding to a target phase in voltage phases by using phase-locked loop software, and determining an optimal time interval according to the first interrupt trigger moment and the clock reference moment; and determining the moment of the second interruption triggering moment after the optimal time interval as a carrier synchronization reference moment, and carrying out carrier synchronization at the carrier synchronization reference moment. According to the technical scheme provided by the embodiment of the invention, the high-precision determination of the reference moment is realized through the combination of software and hardware, the realization is simple, the problem that the reference time of the carrier synchronization without the interconnection line is inaccurate is solved, the carrier synchronization effect is improved, and the parallel circulating current is inhibited.

The invention discloses a multi-phase power supply and a control circuit thereof, and the circuit comprises a feedback control circuit which is used for generating a phase switching signal according to a feedback signal of an output voltage and a reference voltage signal; the switch control circuit is used for generating a plurality of frequency division signals according to the phase cutting signal and controlling the main power tube of the corresponding power level circuit to be conducted according to the logic state of the plurality of frequency division signals; and the turn-on time control circuit is used for generating a turn-off trigger signal when the turn-on time of the main power tube of the triggered power level circuit reaches a set time, and the switch control circuit controls the turn-off of the main power tube of the triggered power level circuit according to the turn-off trigger signal and the plurality of frequency division signals. According to the multi-phase power supply, phase dislocation control among a plurality of power level circuits can be realized only by adopting one control loop, the circuit structure is simple, and circuit design simplification and circuit cost reduction are facilitated.

A method for verifying a low-density parity-check (LDPC) unit capable of being applied in a memory system can include receiving original data corresponding to a memory device, encoding the original data by the LDPC unit to be verified, injecting errors into the encoded original data by a data pattern for generating verifying data, and verifying a soft decode capability of the LDPC unit by utilizing the verifying data. The data pattern can include the errors generated by threshold voltage (Vth) distributions interlaced between two neighboring logic states of 2n logic states of the memory device. The method and system can provide an error injection to accurately and efficiently verify a LDPC soft decode capability of the LDPC unit, decrease errors, increase error correction accuracy and efficiency, more accurately model actual threshold voltage (Vth) distributions, increase flexibility, increase speed, increase performance, and reduce firmware overhead.

A memory circuit includes a first memory cell operatively accessible through a first access line and a second access line; a first read pass-gate transistor and a second read pass-gate transistor coupled to the first access line and second access line, respectively; a first sense amplifier coupled to the first access line and the second access line; a first read enable control circuit configured to generate a first read enable signal based on a clock signal; and a second read enable control circuit configured to generate a second read enable signal. The first read enable signal selectively transitions to a different logic state based on a first sense enable signal. The second read enable signal is configured to activate or deactivate both the first and second read pass-gate transistors, and the first sense enable signal is configured to activate or deactivate the first sense amplifier.

A memory device includes an anti-fuse memory cell that randomly presents either a first logic state or a second logic state. The memory cell is formed on a frontside of a substrate and at least includes a first programming transistor that is formed in a first one of a plurality of metallization layers disposed over the frontside and gated by a first programming word line, and a first reading transistor that is formed in a second one of the plurality of metallization layers disposed over the frontside or along a major surface on the frontside, coupled to the first programming transistor and a first bit line in series, and gated by a first reading word line.

The invention provides a chip simulation waveform automatic analysis and analysis method and system, and belongs to the technical field of chip simulation testing. The method comprises the following steps: generating a waveform file for chip testing through a simulation tool, and preprocessing the obtained waveform file; building a deep learning model, training the deep learning model by using the waveform data, the deep learning model being a hybrid deep learning model, combining a deep convolutional neural network and a graph neural network, and introducing an attention mechanism; analyzing the waveform file by using the trained deep learning model, and extracting a digital logic state and a time sequence feature; and comparing the extracted features with a preset test expectation, and generating a comparison result by judging whether the waveform accords with the expectation. By introducing the deep learning model, automatic analysis and analysis of the waveform file are realized, and the test efficiency is remarkably improved.

A first request to allocate one or more memory blocks of a first plurality of memory blocks associated with a first memory is received by a processing device. A consecutive set of a first portion of bits of a first register with a first logical state is identified. The first logical state indicates that corresponding memory blocks of the one or more memory blocks are free. A first operation to adjust the consecutive set of the first portion of bits of the first register to a second logical state is performed. An allocation address comprising an index of the consecutive set of the first portion of bits of the first register is sent to the first request. The allocation address is useable to access the corresponding memory blocks.

The invention provides a chip verification method and device, electronic equipment and a storage medium, and relates to the technical field of chip design verification, and the method comprises the steps: synchronously operating a to-be-verified chip design and a chip verification model to execute a preset cache line processing method; respectively acquiring a first output signal and first additional information of the to-be-verified chip design, and a second output signal and second additional information of the chip verification model; the first additional information is used for representing intermediate state information of a cache line in the design of the to-be-verified chip; the second additional information is used for representing intermediate state information of a cache line in the chip verification model; and determining a function verification result of the to-be-verified chip design. According to the method and the device provided by the invention, the output signal and the additional information are compared, so that the design defect can be found in time in the early stage of deviation of the internal logic state of the chip, the verification completeness and accuracy are greatly improved, and the overall verification efficiency is improved.

A memory device including a first configuration bit group including a plurality of bits, the plurality of bits including: a plurality of configuration bits; at least one redundant configuration bit; a plurality of configuration bit multiplexers each configured to receive (i) a first input from a first bit in the plurality of bits and / or a second input from a second bit in the plurality of bits and (ii) a third input from a decoder, each of the first, second, and third inputs indicating a respective logical state, wherein the logical state includes a first state or a second state; and wherein, based on the logical state of the third input received from the decoder, each configuration bit multiplexer is configured to output: the logical state of the first input from the first bit, or the logical state of the second input from the second bit.

The invention discloses a single-pin trimming circuit, which relates to the technical field of analog circuit design and comprises a comparator module, a first input end of the comparator module is connected to a single pin, a second input end of the comparator module is connected to a reference voltage, and the comparator module is used for comparing an input voltage of the single pin with the reference voltage and outputting a comparison signal; the input end of the time sequence decoding module is connected to the output end of the comparator module, and the time sequence decoding module is configured as follows: a, the logic state of a trimming position is judged according to the duration time of the pulse in the comparison signal; and b, addressing different trimming positions according to the number of pulses in the comparison signal, and further generating a multi-position trimming control signal through a series of pulse signals input by the single pin. Accurate control of a multi-bit fuse trimming circuit in a chip is realized by using single-pin resources.