441 results about "Logic state" patented technology

The invention discloses an interval occupation logic checking method, a train control system, a storage medium and electronic equipment, which are used for automatically blocking a standard railway line, and the method comprises the following steps: acquiring train position information and a train type; acquiring track circuit data, and judging a track section state; and generating a corresponding signal permission for the train based on the train position information, the train type and the track section state, and judging the logic state of the corresponding block partition based on the signal permission. The method has the advantages that the normal train, the fault train and the non-moving block train can be ensured to safely run on the automatic block system railway line at the same time, the normal train can still adopt the moving block system and does not need to be degraded into the automatic block system, the running density of the normal train is improved, and the running efficiency is improved. Therefore, the traffic capacity of the automatic block type railway line is improved.

A multirail-encoded qubit can be implemented using a quantum system having a state space that includes a number M of distinct modes, where M is an integer greater than 2. The M modes are logically partitioned into two disjoint subsets (or “bands”), with each mode assigned to exactly one of the bands. The multirail encoding is defined such that a state in which any one of the modes in the first band is occupied and all modes in the second band are unoccupied maps to a logical 0 state of the qubit, and a state in which any one of the modes in the second band is occupied and all modes of the first band are unoccupied maps to a logical 1 state. Systems and methods for generating, measuring, and operating on multirail-encoded qubits are disclosed.

A system and method for an electrostatic discharge (ESD) clamp circuit containing a disable circuit to selectively disable a discharge circuit is disclosed. An electrostatic discharge (ESD) clamp circuit including a discharge circuit to discharge a current flow during a transient ESD voltage event; a disable input to receive a disable input signal; and a disable circuit to, based upon the disable input signal, selectively disable the discharge circuit. When the disable input signal is a first logic state, the disable circuit is to allow the discharge circuit to be enabled; and when the disable input signal is in a second logic state, the disable circuit is to disable the discharge circuit.

The invention relates to the technical field of distributed computing, and discloses a heavy truck charging load scheduling-oriented distributed energy intelligent matching method, which comprises the following steps of: establishing a charging service computing power mapping table at a scheduling node; maintaining a shadow counter in a local memory, extracting a pre-estimated computing power consumption value according to an event type and accumulating the pre-estimated computing power consumption value to the shadow counter, and executing linear numerical deduction on the shadow counter according to a reference logic subtraction rate so as to simulate a scheduling data throughput evolution process; adjusting a linear deduction rate parameter according to the deviation between the state feedback data and the numerical value of the shadow counter; and distributing the charging matching task to a charging station edge computing node of which the shadow counter value does not exceed a preset logic saturation threshold value. According to the invention, through an open-loop estimation and closed-loop calibration mechanism of a local logic state, an instantaneous congestion risk caused by physical feedback lag is eliminated; and logic state consistency and self-adaptive distribution of the whole network computing power resources are realized.

The invention relates to the technical field of data processing, and discloses a college budget management system fused with a new quality productivity theory, comprising: a state characterization interface collects process characterization data and maps the process characterization data into a discrete innovation state bit vector; the differential efficiency mapping unit responds to the state bit jump to calculate an efficiency marginal increment and generate an injection instruction; the physical bypass monitoring channel collects physical consumption time sequence data, and the entropy analysis closed-loop unit calculates a metabolic entropy representing the resource consumption order degree; the budget dynamic response control unit generates a state locking instruction when the state bit is constant and the metabolic entropy meets the low-entropy convergence condition, the physical working condition entropy is used for correcting the logic state, and the project resource state is maintained by recognizing the low-entropy resource consumption characteristics when no dominant output exists; the problem that discrete evaluation indexes cannot represent blind areas of continuous scientific research activities is solved.

An apparatus includes a transmitter, a voltage regulator, an isolator, and a test controller. The transmitter has an input, an output, and a first supply voltage terminal. The input couples to the apparatus' input terminal. The voltage regulator's input couples to a second supply voltage terminal. The voltage regulator's output couples to the first supply terminal. The first terminal of the isolator couples to the output of the transmitter. A first test controller terminal couples to the second supply voltage terminal. A second test controller terminal couples to the input terminal of the apparatus. The first control output couples to the control input of the voltage regulator. The test controller changes a logic state of a control signal at the first control output from a first logic state to a second logic state.

The invention relates to the technical field of chip simulation, in particular to a voltage logic simulation design method and system for a passive internet-of-things tag chip. The method comprises the following steps: performing energy characteristic measurement on the tag chip, and calculating voltage fluctuation and logic gate triggering probability to obtain energy logic state mapping data; state transition probability distribution mapping is carried out according to the energy logic state mapping data, and a transition probability distribution tensor is constructed; collecting measurement environment parameters in the energy characteristic measurement process, and performing dynamic environment interference compensation on the transition probability distribution tensor to generate an interference compensation distribution tensor; carrying out simulation precision demand distribution based on the interference compensation distribution tensor, and constructing a layered simulation configuration file; and performing multi-precision parallel simulation execution based on the layered simulation configuration file, and generating a probabilistic verification report. Through precise and efficient logic simulation, the reliability of chip design is improved, and the fault probability is reduced.

Methods, systems, and devices for signal development caching in a memory device are described. In one example, a memory device in accordance with the described techniques may include a memory array, a sense amplifier array, and a signal development cache configured to store signals (e.g., cache signals, signal states) associated with logic states (e.g., memory states) that may be stored at the memory array (e.g., according to various read or write operations). In various examples, accessing the memory device may include accessing information from the signal development cache, or the memory array, or both, based on various mappings or operations of the memory device.

The invention provides an SRAM (Static Random Access Memory) storage unit anti-single particle radiation reinforcement method and system, and relates to the technical field of microelectronics and circuit structure design, a redundant node coupled with a main storage node of an SRAM storage unit is constructed, and the redundant node is used for redundant storage of the logic state of the main storage node; the polarity of a main storage node is reinforced by configuring the main storage node into a circuit structure fully surrounded by a single-type transistor; wherein the redundant node and the main storage node after polarity reinforcement are integrated into a reinforced SRAM (Static Random Access Memory) storage unit. According to the method, circuit-level fusion and collaborative design are carried out on redundancy reinforcement and polarity reinforcement, so that the single event upset resistance of the SRAM unit is improved, and an efficient and enforceable reinforcement design method is provided.

The utility model discloses a three-state switching signal acquisition system, which realizes low static loss and instant wake-up capability of a controller. The system comprises a three-state switching signal acquisition circuit and a wake-up circuit, the power supply end of the acquisition circuit is connected with a first power supply; the first power supply is turned on when the controller works normally and turned off when the controller is dormant; the power end of the wake-up circuit is connected to a second power supply; the acquisition circuit is connected between the output end of the three-state switch and the first input end of the controller and is used for converting different logic states output by the three-state switch into signals with different voltage values under the power supply of the first power supply; the wake-up circuit is connected between the output end of the three-state switch and the second input end of the controller, and is used for switching the logic state of the output end of the three-state switch from a suspended state to a high level or a low level under the power supply of the second power supply after the first power supply is turned off, and converting the logic state into a preset wake-up signal; the wake-up signal is used for waking up the controller from the dormant state to the normal working state.

A method for verifying a low-density parity-check (LDPC) unit capable of being applied in a memory system can include receiving original data corresponding to a memory device, encoding the original data by the LDPC unit to be verified, injecting errors into the encoded original data by a data pattern for generating verifying data, and verifying a soft decode capability of the LDPC unit by utilizing the verifying data. The data pattern can include the errors generated by threshold voltage (Vth) distributions interlaced between two neighboring logic states of 2n logic states of the memory device. The method and system can provide an error injection to accurately and efficiently verify a LDPC soft decode capability of the LDPC unit, decrease errors, increase error correction accuracy and efficiency, more accurately model actual threshold voltage (Vth) distributions, increase flexibility, increase speed, increase performance, and reduce firmware overhead.

A memory circuit includes a first memory cell operatively accessible through a first access line and a second access line; a first read pass-gate transistor and a second read pass-gate transistor coupled to the first access line and second access line, respectively; a first sense amplifier coupled to the first access line and the second access line; a first read enable control circuit configured to generate a first read enable signal based on a clock signal; and a second read enable control circuit configured to generate a second read enable signal. The first read enable signal selectively transitions to a different logic state based on a first sense enable signal. The second read enable signal is configured to activate or deactivate both the first and second read pass-gate transistors, and the first sense enable signal is configured to activate or deactivate the first sense amplifier.

A memory device includes an anti-fuse memory cell that randomly presents either a first logic state or a second logic state. The memory cell is formed on a frontside of a substrate and at least includes a first programming transistor that is formed in a first one of a plurality of metallization layers disposed over the frontside and gated by a first programming word line, and a first reading transistor that is formed in a second one of the plurality of metallization layers disposed over the frontside or along a major surface on the frontside, coupled to the first programming transistor and a first bit line in series, and gated by a first reading word line.

A first request to allocate one or more memory blocks of a first plurality of memory blocks associated with a first memory is received by a processing device. A consecutive set of a first portion of bits of a first register with a first logical state is identified. The first logical state indicates that corresponding memory blocks of the one or more memory blocks are free. A first operation to adjust the consecutive set of the first portion of bits of the first register to a second logical state is performed. An allocation address comprising an index of the consecutive set of the first portion of bits of the first register is sent to the first request. The allocation address is useable to access the corresponding memory blocks.

The invention provides a chip verification method and device, electronic equipment and a storage medium, and relates to the technical field of chip design verification, and the method comprises the steps: synchronously operating a to-be-verified chip design and a chip verification model to execute a preset cache line processing method; respectively acquiring a first output signal and first additional information of the to-be-verified chip design, and a second output signal and second additional information of the chip verification model; the first additional information is used for representing intermediate state information of a cache line in the design of the to-be-verified chip; the second additional information is used for representing intermediate state information of a cache line in the chip verification model; and determining a function verification result of the to-be-verified chip design. According to the method and the device provided by the invention, the output signal and the additional information are compared, so that the design defect can be found in time in the early stage of deviation of the internal logic state of the chip, the verification completeness and accuracy are greatly improved, and the overall verification efficiency is improved.

The invention discloses a single-pin trimming circuit, which relates to the technical field of analog circuit design and comprises a comparator module, a first input end of the comparator module is connected to a single pin, a second input end of the comparator module is connected to a reference voltage, and the comparator module is used for comparing an input voltage of the single pin with the reference voltage and outputting a comparison signal; the input end of the time sequence decoding module is connected to the output end of the comparator module, and the time sequence decoding module is configured as follows: a, the logic state of a trimming position is judged according to the duration time of the pulse in the comparison signal; and b, addressing different trimming positions according to the number of pulses in the comparison signal, and further generating a multi-position trimming control signal through a series of pulse signals input by the single pin. Accurate control of a multi-bit fuse trimming circuit in a chip is realized by using single-pin resources.

The invention discloses memory management using registers. A first request to allocate one or more memory blocks of a first plurality of memory blocks associated with a first memory is received by a processing device. A contiguous set of first bit portions of a first register having a first logic state is identified. The first logic state indicates that a corresponding memory block of the one or more memory blocks is free. A first operation is performed that adjusts a contiguous set of first bit portions of the first register to a second logical state. An allocated address including an index of a contiguous set of first bit portions of the first register is sent to the first request, where the allocated address is available to access a corresponding memory block.

The present disclosure provides a semiconductor device which includes a multiplexer, a master latch, and a slave latch. The multiplexer outputs an inverse of an input data signal or an inverse scan input signal according to a scan enable signal. The master latch is coupled to an output terminal of the multiplexer, and is configured to latch the inverse of the input data signal based on an input clock signal in response to the scan enable signal being in a low-logic state. The slave latch is coupled to the output terminal of the multiplexer through a first clocked CMOS inverter, and is configured to receive the input data signal and to output a latched slave latch data based on the input clock signal. A leakage-free dummy cell is disposed in a non-critical path of the master latch and the slave latch.

The invention discloses a smart home multi-device linkage power utilization control method based on MOS tubes, and belongs to the technical field of smart home control. The digital processor is used as a core, the built-in numerical control module and the data processing unit are matched, the on-off state of the MOS tube is accurately regulated and controlled in combination with a program control algorithm, fine management of power utilization parameters of intelligent household equipment is achieved, the limitation that traditional control response is lagged and poor in adaptability is broken through, rated parameters and real-time requirements of the equipment are dynamically matched, and the power utilization efficiency is improved. The optimal operation of equipment is guaranteed to prolong the service life, invalid energy consumption is reduced, a high-precision foundation is laid for multi-equipment cooperative linkage, the stability and energy efficiency of a system are improved, multi-scene linkage logic is preset by means of a logic state machine, and rapid switching and reliable execution of multi-scene linkage are realized by matching with an application selection switch of an MOS tube array structure. Scene requirements are automatically adapted, and through independent loop control, fault detection and standby loop design, the problems that linkage switching is tedious and the fault influence is large are solved.

An aging monitoring circuit of a semiconductor memory device includes a threshold voltage sensing part including an aging monitoring transistor, enabled in response to activation of an aging monitoring signal, and generating a sensing threshold signal, a level of the sensing threshold signal depending on a threshold voltage of the aging monitoring transistor, a reference threshold storage part receiving the sensing threshold signal generated in response to activation of a reference sensing signal and storing a reference threshold voltage, a level of the reference threshold voltage depending on the level of the sensing threshold signal, and a level comparing part enabled in response to the activation of the aging monitoring signal and generating an aging flag signal, a logic state of the aging flag signal depending on a comparison result between the level of the sensing threshold signal and the level of the reference threshold voltage.

A voltage droop detection circuit can be used to detect a voltage droop in an integrated circuit (IC) device. The voltage droop detection circuit may include a chain of inverting stages, and each inverting stage may include a P-type transistor and an N-type transistor. The chain of inverting stages can be initialized to alternating logic states during an initialization phase of a clock cycle, and an evaluation pulse can be inputted into the chain of inverting stages during an evaluation phase of the clock cycle. A voltage droop may be detected if a number of inverting stages that are able to switch output logic states from their respective initialized logic states is smaller than a nominal value indicating a number of inverting stages that are able to switch their respective output logic states under normal voltage condition.

A multirail-encoded qubit can be implemented using a quantum system having a state space that includes a number M of distinct modes, where M is an integer greater than 2. The M modes are logically partitioned into two disjoint subsets (or “bands”), with each mode assigned to exactly one of the bands. The multirail encoding is defined such that a state in which any one of the modes in the first band is occupied and all modes in the second band are unoccupied maps to a logical 0 state of the qubit, and a state in which any one of the modes in the second band is occupied and all modes of the first band are unoccupied maps to a logical 1 state. Systems and methods for generating, measuring, and operating on multirail-encoded qubits are disclosed.

A display pixel including at least one light-emitting diode, and an electronic circuit including a storage circuit for storing at least one digital signal and a driver circuit configured to drive said light-emitting diode by pulse-width modulation, in a first operating mode, by switching on or off said light-emitting diode during first different durations according to the logical states of the bits of the digital signal or, in a second operating mode, by switching on or off said light-emitting diode during second different durations, at least partly different from the first durations, according to the logical states of the bits of the digital signal.

A memory structure including a three-dimensional NOR memory string and a method of operation are disclosed. In some embodiments, the memory device performs partial polarization to provide a reference signal for read operations. The reference signal implements a third logic state distinguishable from the first and second logic stages in the ferroelectric memory transistor, e.g., associated with a program state and an erase state. In another embodiment, the memory device provides a reference signal for a read operation by averaging a first signal associated with a program state of the ferroelectric memory transistor and a second signal associated with an erase state. In some embodiments, the memory device implements one or more partially polarized states to provide more than one logical bit stored in each memory cell to multi-level memory cells.

An 8T CFET SRAM is proposed to perform the parallel weighted-sum operation to speed-up the inference process. A circuit includes a memory array including memory cells, each of the memory cells including a plurality of transistors, and coupled to a first word line and a second word line, and configured to receive a first data element, store a second data element, and provide a multiplication value of the first data element and the second data element. The first word line is configured to receive a first logic state corresponding to the first data element being binarized, and the second word line is configured to receive a second logic state corresponding to the first data element being binarized. A first internal node among the transistors is configured to store a first logic state corresponding to the second data element being binarized, and a second internal node among the transistors is configured to store a second logic state corresponding to the second data element being binarized.

A voltage regulator receives a reference voltage and generates a regulated voltage using a MOSFET having a gate terminal configured to receive a control voltage. A charge pump receives the regulated voltage and generates a charge pump voltage in response to an enable signal and a clock signal generated in response to the enable signal. The voltage regulator further includes a first switched capacitor circuit coupled to the gate terminal and configured to selectively charge a first capacitor with a first current and impose a first voltage drop on the control voltage in response to assertion of the enable signal. The voltage regulator also includes a second switched capacitor circuit coupled to the gate terminal and configured to selectively charge a second capacitor with a second current and impose a second voltage drop on the control voltage in response to one logic state of the clock signal.

This application discloses an automatic calibration circuit and method for mismatch compensation current of a phase-locked loop (PLL) charge pump, relating to the field of integrated circuit technology. The calibration circuit includes: a frequency and phase detector, a charge pump, an XOR module, a filter capacitor, a digital-to-analog converter (DAC) module, and a digital logic state machine. The first output terminal of the frequency and phase detector is connected to the first input terminal of the charge pump and the first input terminal of the XOR module, respectively. The second output terminal of the frequency and phase detector is connected to the second input terminal of the charge pump and the second input terminal of the XOR module, respectively. The output terminal of the XOR module is connected to the first terminal of the filter capacitor and the input terminal of the DAC module, and the second terminal of the filter capacitor is grounded. The output terminal of the DAC module is connected to the input terminal of the digital logic state machine, and the output terminal of the digital logic state machine is connected to the third input terminal of the charge pump. The output terminal of the charge pump is used to connect to the input terminal of the low-pass filter in the PLL. This application can compensate for the mismatch current of the charge pump in real time.

The latch device includes an RS type latch flip-flop capable of being supplied between a first supply voltage and a second supply voltage which is lower than the first supply voltage and having first and second flip-flop inputs and a flip-flop output connected to the output terminal. A control module positions the latch flip-flop in a set state or in a reset state when the first supply voltage has a first value which is lower than the low voltage then, the latch flip-flop being positioned, confers the high voltage on the first supply voltage and the low voltage on the second supply voltage and outputs and maintains the high voltage or the low voltage on the flip-flop output while avoiding outputting a prohibited logic state at the two flip-flop inputs.

This invention discloses a starting point control method based on twin logic, relating to the field of integrated circuit technology. The method includes: after the chip is powered on, the logic generation circuit begins to establish the state of the target logic channel, and the twin logic channel internally monitors the establishment of this state synchronously; when the twin logic channel determines that the target logic state has been established, it outputs a starting point latch signal and generates a starting point control signal, triggering a timing circuit to sequentially generate a logic lock signal and a shutdown signal; the logic lock signal securely locks the target logic to the latch matrix, and the shutdown signal subsequently shuts down the logic generation circuit. This invention uses "logic-driven timing" instead of the traditional "power-driven timing," truly binding the timing starting point to the physical establishment state of the module, fundamentally avoiding timing races and locking errors; and it can adapt to process and temperature fluctuations, significantly improving system reliability while precisely reducing additional power consumption.

The application relates to the technical field of integrated circuit design, in particular to an inverter chain circuit shielding SET pulse signals and a module packaged based on the inverter chain circuit shielding SET pulse signals. The inverter chain is constructed based on a three-stage inverter structure, which not only has the basic function of an inverter, but also has the outstanding ability of shielding SET pulse signals through reasonable circuit design, can shield voltage jump in any direction, and ensures that the output node o3 can still output with correct logic state.