58 results about "Logic state" patented technology

This application discloses an automatic calibration circuit and method for mismatch compensation current of a phase-locked loop (PLL) charge pump, relating to the field of integrated circuit technology. The calibration circuit includes: a frequency and phase detector, a charge pump, an XOR module, a filter capacitor, a digital-to-analog converter (DAC) module, and a digital logic state machine. The first output terminal of the frequency and phase detector is connected to the first input terminal of the charge pump and the first input terminal of the XOR module, respectively. The second output terminal of the frequency and phase detector is connected to the second input terminal of the charge pump and the second input terminal of the XOR module, respectively. The output terminal of the XOR module is connected to the first terminal of the filter capacitor and the input terminal of the DAC module, and the second terminal of the filter capacitor is grounded. The output terminal of the DAC module is connected to the input terminal of the digital logic state machine, and the output terminal of the digital logic state machine is connected to the third input terminal of the charge pump. The output terminal of the charge pump is used to connect to the input terminal of the low-pass filter in the PLL. This application can compensate for the mismatch current of the charge pump in real time.

This invention discloses a starting point control method based on twin logic, relating to the field of integrated circuit technology. The method includes: after the chip is powered on, the logic generation circuit begins to establish the state of the target logic channel, and the twin logic channel internally monitors the establishment of this state synchronously; when the twin logic channel determines that the target logic state has been established, it outputs a starting point latch signal and generates a starting point control signal, triggering a timing circuit to sequentially generate a logic lock signal and a shutdown signal; the logic lock signal securely locks the target logic to the latch matrix, and the shutdown signal subsequently shuts down the logic generation circuit. This invention uses "logic-driven timing" instead of the traditional "power-driven timing," truly binding the timing starting point to the physical establishment state of the module, fundamentally avoiding timing races and locking errors; and it can adapt to process and temperature fluctuations, significantly improving system reliability while precisely reducing additional power consumption.

A transistor control logic circuit has a first and a second input and an output. The output is coupled to the control terminal of a transistor. A peak current detector has a reference input, a detection input, and an output. The peak current detector provides a first signal at its output in a first logic state in response to a detection signal exceeding a reference signal. A trigger buffer has a first and a second input and an output. The first input of the trigger buffer is coupled to the output of the peak current detector. The output of the trigger buffer is coupled to the first input of the transistor control logic circuit.The trigger buffer provides a third signal in the first logic state at the output of the trigger buffer in response to the fact that the first signal at the output of the peak current detector is in the first logic state and a second signal at the second input of the trigger buffer is in a second logic state.

The application provides a device and working method for AI chip system architecture verification, including a control center for logic control, timing coordination and data interaction of each module. A pulse writing module generates a writing signal with a special pulse form to realize state programming and conduct adjustment of storage or computing devices. A programming selection module accepts the signal of the pulse writing module, supports the structure requirements of various different memory devices of the measured unit, and performs different selective writing according to different array structures. A decoding module accepts the signal of the programming selection module and the feedback signal of the measured unit to be read, and is used for address space mapping, excitation line management and signal on-off control. The measured unit accepts the writing signal of the decoding module and feeds back the reading signal to the decoding module, and is used for storing neural network weights, logic states or continuous conduct grades. The application provides key test support and decision basis for AI chip system architecture research.

The present application belongs to the field of marine environment monitoring and signal processing technology, and relates to a real-time processing method for data denoising and time lag correction of a marine dissolved gas sensor, which comprises: identifying a steady-state interval of historical observation data of the sensor, fitting a steady-state jump with a Sigmoid function to generate a virtual true value of gas concentration; constructing a neural network model with observation data as input and a preliminary correction value of gas concentration as output, training the model with historical observation data as input and the virtual true value of gas concentration as a training target; using a sliding window mechanism to intercept observation data segments of the current and historical time of the sensor, inputting the data segments into the model to output a preliminary correction value of gas concentration at the current time; and using a logic state machine for post-processing to obtain a final correction value of gas concentration at the current time. The present application can provide the sensor with real-time compensation functions that take into account high dynamic response and zero steady-state drift, thereby realizing in-situ acquisition and real-time return of high-precision observation data.

A power MOSFET driver circuit includes a feedback circuit configured to supply a feedback signal that signals when a gate voltage of the power MOSFET crosses a plateau value and the power MOSFET switches conduction state. The feedback circuit includes a comparator with a replica MOSFET of the power MOSFET, with scaled down dimensions, whose gate is coupled to the gate electrode of the power MOSFET. A bistable circuit has an input coupled to an output of the replica MOSFET and is configured to change a logic state of the feedback signal following the transition of the switching signal when the gate voltage of the power MOSFET crosses the plateau value and the power MOSFET switches conduction state.

Various embodiments of this disclosure relate to low-power and fast memory reset. One memory reset method includes: pre-charging bit lines of a memory array; asserting a signal at a reset node to remove the pre-charge voltage; and selecting write drivers associated with bit lines, the bit lines being associated with columns of the memory array including memory cells to be reset; wherein the assertion signal at the reset node further causes a desired logic state to be applied to the input of the selected write drivers, causing those selected write drivers to change the logic state of the bit lines associated with those write drivers. The method continues to assert each word line associated with a row of memory containing the memory cells to be reset, to write the desired logic state to all memory cells to be reset in the column and row of memory during a single clock cycle, and then deasserting those word lines.

An object of the present invention is to provide a neuromorphic system including a synaptic unit capable of causing a gradual change in resistance for analog information processing, and an operating method therefor. In order to achieve the above object, an aspect of the present invention may provide a neuromorphic system including an input signal unit for generating an input signal, a synapse unit including a plurality of synaptic units that receive a signal of the input signal unit and cause a current to flow according to a set weight, an output signal unit for generating an output signal by receiving a current generated from the synapse unit, and a controller unit for controlling the input signal unit, the synapse unit, and the output signal unit, in which the input signal unit includes a digital-to-analog converter (DAC), the synaptic units include a plurality of memory cells that are connected to each other and are each capable of selectively storing a logic state, the plurality of memory cells are arranged in a cross-point structure including an input electrode line and an output electrode line that cross each other to form one or more memory arrays, the output signal unit includes an analog-to-digital converter (ADC), and the controller unit generates an analog input signal through the DAC in the input signal unit, allows the generated analog input signal to be applied to each of the plurality of memory cells included in the synaptic unit so that a current flows, and generates a sum of currents flowing from the plurality of memory cells as the output signal through the ADC in the output signal unit.

This application relates to a memory array with multiplexed select lines. In some cases, a memory cell of a memory device can include a storage component, a first transistor coupled with a word line, and a second transistor coupled with a first select line to selectively couple the memory cell with a first digit line. A third transistor can be coupled with the first digit line and a sensing component common to a set of digit lines and a set of select lines. A second select line can be coupled with the third transistor and configured to couple the sensing component with the first digit line and to couple the sensing component with a second digit line. The sensing component can determine a logic state stored by the memory cell based on a signal from the first digit line and a signal from the second digit line.

This disclosure provides a memory device including a NOR memory string and a method of operating the same. The memory device of this disclosure implements partial polarization to provide a reference signal for read operations. The reference signal realizes a third logic state in a ferroelectric memory transistor that is distinguishable from a first logic state and a second logic state (e.g., a logic state associated with a write state and an erase state). The memory device of this disclosure provides a reference signal for read operations by averaging a first signal associated with the write state and a second signal associated with the erase state of the ferroelectric memory transistor. The memory device of this disclosure also provides a multilevel memory cell that stores multiple logic bits in each memory cell by implementing one or more partial polarization states.

This invention discloses a LoRa chip adaptive spreading factor selection terminal device and method. The terminal device includes a main control microprocessor, an RF transceiver, and a mechanical state sensor connected to the main control microprocessor. The main control microprocessor extracts the first-order differential values ​​of RF parameters and simultaneously acquires vibration acceleration magnitude values, mapping them to a two-dimensional discrete state set. An environment mask is generated based on the comparison between the instantaneous rate of change of the vibration acceleration magnitude and a set threshold. In response to the environment mask being in a first logic state, the spreading factor is updated and issued according to an action value lookup table. In response to the environment mask being in a second logic state, the update operation is blocked, and a spreading factor locking command is issued. This application can achieve cross-domain feedforward intervention by fusing physical states, blocking the invalid spreading factor rise caused by instantaneous broadband noise, and reducing node ineffective power consumption.

This invention discloses a starting point control method based on twin logic, relating to the field of integrated circuit technology. The method includes: after the chip is powered on, the logic generation circuit begins to establish the state of the target logic channel, and the twin logic channel internally monitors the establishment of this state synchronously; when the twin logic channel determines that the target logic state has been established, it outputs a starting point latch signal and generates a starting point control signal, triggering a timing circuit to sequentially generate a logic lock signal and a shutdown signal; the logic lock signal securely locks the target logic to the latch matrix, and the shutdown signal subsequently shuts down the logic generation circuit. This invention uses "logic-driven timing" instead of the traditional "power-driven timing," truly binding the timing starting point to the physical establishment state of the module, fundamentally avoiding timing races and locking errors; and it can adapt to process and temperature fluctuations, significantly improving system reliability while precisely reducing additional power consumption.

A memory circuit and a control method thereof, the memory circuit comprising: a memory array including a plurality of memory cells configured across a first number (N) of word lines; a word line driver including a second number (N / 2) of logic gates, wherein each of the logic gates is to receive a first input signal corresponding to a first one of the word lines and a second input signal corresponding to a second one of the word lines, and to provide a boost signal based on respective logic states of the first and second input signals; and a pulser circuit including N / 2 pairs of first and second buffers, wherein each of the first buffers is to receive a corresponding boost signal and to deactivate a corresponding first word line, and each of the second buffers is to receive a corresponding boost signal and to activate a corresponding second word line.

A system and method for debugging logic elements in a configurable logic block using only one pin. A synchronization pulse is generated, and each logic element is connected, in turn, using a digital selector switch. The synchronization pulse and a logic state of each logic element are received, in turn, by an output buffer. First, second, and third digital outputs levels are enabled on a single output line using a voltage divider configuration of resistors connected to the output line of the output buffer. The output levels include the synchronization pulse, a low logic state, and a high logic state. The synchronization pulse and the logic state of each logic element are outputted as the different output levels, in turn, via a single debug pin connected to an oscilloscope or other display device for visualization. The debug pin may be shared with other functions when not being used for debugging.

The application discloses a dialogue type tool for generating intelligence products and an interactive method, and belongs to the technical field of large language model application and natural language processing. The application realizes the method as follows: 1, constructing an interactive framework for generating intelligence products; 2, integrating original materials, and initializing the logic state of a process navigator of an interactive presentation layer; 3, generating a structured outline in Markdown format; 4, constructing a chapter task list, generating chaptered intelligence content by batch asynchronous calling of an LLM model, and displaying the generation process in real time through a real-time editing feedback window of the interactive presentation layer; 5, automatically formatting and logically checking the generated intelligence content in sequence; 6, forming a complete intelligence product draft; 7, real-time editing in the whole process, re-generating and performing hot updating fine tuning on corresponding chapter content; compared with the prior art, the application solves the technical problem of realizing interactive and standardized intelligence product generation in intelligence compilation.

Systems, methods, and apparatus for a memory device. In one approach, known reference patterns are stored in a memory array. The patterns are associated with codewords stored in the memory array. A first pattern has all memory cells written to a first logic state (e.g., all logic ones), and a second pattern has all memory cells written to an opposite second logic state (e.g., all logic zeros). When a controller reads a codeword, the controller first reads memory cells of the associated reference patterns to determine data for estimating a threshold voltage distribution of memory cells in the codeword. Based on a number of memory cells of the reference patterns that snap when reading the first and second patterns, the controller selects a read voltage for reading the associated codeword.

The application discloses a programmable non-glitch period delay control circuit based on TSPC and belongs to the technical field of integrated circuits. In order to solve the problems of dynamic node leakage, logic state loss of existing TSPC dynamic circuits under long waiting periods, and easy generation of glitches in high-frequency clock switching, the application adopts a two-stage programmable multi-mode frequency divider architecture, forcibly locks all TSPC dynamic nodes to a fixed low level through a low-level effective asynchronous reset end in a waiting period, and ensures the stable establishment of a gating signal in a clock low-level window through a half-cycle timing constraint design. The application supports independent programmable configuration of waiting periods and release periods, can realize non-glitch clock control under a super-high frequency of more than 5GHz in a full PVT working condition, has super-low standby power consumption and high reliability, and is suitable for clock path management, read-write phase calibration and low-power mode switching of a DDR memory interface and the like.

The utility model discloses a kind of self-service car washer energy-saving light illumination system, including photosensitive signal acquisition module, signal decoding module, logic control module and push-pull drive module. Photosensitive signal acquisition module is used to collect car washer ambient light brightness, and exports photosensitive control signal. Signal decoding module receives photosensitive control signal and car washer input signal, and the encoding signal with three kinds of logic states is output through decoder. Logic control module uses logic chip, the input end of logic chip is connected with the output end of decoder, when only photosensitive control signal is effective, effective signal is output from the first output port of logic chip, when photosensitive control signal and car washer input signal are all effective, effective signal is output from the second output port of logic chip. Push-pull drive module receives the effective signal output by logic chip, and PMOS is driven to illuminate load using push-pull. Can avoid daytime invalid power consumption, save electric energy, save cost for operation management party.

The application discloses a kind of unified computing architecture and method based on quantum-classical ternary field, belong to quantum computing and computer architecture technical field.The architecture includes: quantum-classical unified field layer, for the computing resources of quantum state and classical state is mapped as a continuous ternary computing field;Ternary logic operation layer is connected with the quantum-classical unified field layer, using the three logic states of manifesting pole (+1), returning pole (-1) and operating central axis (0) to carry out unified logic operation to the data in the ternary computing field;Field balance control layer is connected with the ternary logic operation layer, and built-in single composite operation hardware module consisting of exponential operation, logarithmic operation and difference operation, for real-time monitoring the operation state deviation of the ternary computing field, and through closed loop feedback, the operation process converges to steady state.The application first unifies quantum state and classical state in a ternary field framework and carries out calculation, through the ternary collaborative mechanism of "manifesting pole execution, returning pole verification, operating central axis calibration", the seamless switching between quantum and classical two computing paradigms, collaborative operation and zeroing closed loop are realized, applicable to quantum-classical hybrid computing chip, all-optical computing system and next-generation general-purpose computing platform.

This disclosure relates to the field of computer technology, and in particular to a method, apparatus, device, medium, and product for node combination. In this disclosure, each node in a set to be processed is quantum-state encoded to obtain its quantum ground state. Based on the quantum ground state of each node, with the objective of minimizing the grouping error loss, the logical state of each node is determined. The logical state characterizes the grouping probability of a node relative to a candidate subset, and the grouping error loss characterizes the grouping error probability of two connected nodes. Based on the logical state of each node, a target combination is determined in the set to be processed. By using a small amount of qubit resources to encode the quantum state of each node, the logical state of each node that can characterize the grouping probability is determined in iterative optimization. The target combination can then be determined through the logical state, turning the determination of node combination into a continuous optimization problem, thus achieving node combination optimization. Therefore, the accuracy of node combination optimization can be improved.

A first power supply pad is configured to provide a first power supply to a power domain of the SoC in which the first power supply pad is configured to receive the first power supply from a source external to the SoC. A first signal pad is configured to receive a power ready signal from external the SoC which indicates when the first power supply to the power domain is fully powered up. A first power detector is configured to provide a first power detected output, which, when asserted, indicates presence of a power supply voltage on the first power supply pad. A fault detection circuit coupled to the first power detector and the first signal pad is configured to generate a set of fault flags in response to monitoring a relationship between the first power detected output and a logic state of the power ready signal.

The application relates to the technical field of data processing, and discloses a university budget management system fusing new quality productivity theory, which comprises the following steps: a state representation interface collects process representation data and maps the process representation data into a discrete innovation state bit vector; a differential efficiency mapping unit calculates an efficiency marginal increment in response to state bit jumping and generates an injection instruction; a physical bypass monitoring channel collects physical consumption time sequence data, and a closed-loop unit calculates metabolic entropy value representing resource consumption order from the physical consumption time sequence data; and a budget dynamic response control unit generates a state locking instruction when the state bit is constant and the metabolic entropy value meets a low-entropy convergence condition, wherein the application uses physical working condition entropy value correction logic state to maintain project resource state by identifying low-entropy resource consumption characteristics when there is no explicit output, so that the problem that discrete evaluation indexes cannot represent the blind area of continuous scientific research activities is solved.

Cell-aware defect characterization is disclosed by considering inter-cell timing. Also disclosed is a method and apparatus to determine whether a defect can be detected in a standard library cell used to design integrated circuits. A defect detection table is generated that indicates whether a particular defect can be detected using a particular combination of input logic states and under different load conditions. The results are merged to provide a single metric for each combination of input and output logic states that indicates one of three possible outcomes for each defect: (1) whether the defect can be detected under all load conditions, (2) whether the defect can only be detected under some load conditions; or (3) whether the defect cannot be detected for the particular combination of input logic states regardless of the load condition.

This invention discloses an integrated production and testing line control method for automotive modules, belonging to the field of industrial automation testing technology. It encapsulates vehicle transit information as event objects, obtains the vehicle's unique identification code, workstation identifier, acquisition terminal type, and on-site and server timestamps, and calculates the observation delay. It recursively generates a delay confidence bound by filtering the delay at each workshop and writes it into a parameter pool. Based on the delay confidence bound, it calculates the over-boundary quantity and delay attenuation factor, constructs a hidden Markov model of the vehicle's logical state for state probability inference, and performs evidence fusion to output the vehicle's logical state, confidence level, and conflict level when multiple terminals conflict. It determines scheduling feasibility based on robust statistical thresholds of confidence level and conflict level, and the routing controller issues transmission control actions to the programmable logic controller. It uses physical arrival feedback to form an arrival deviation sequence and performs accumulation and change point detection, updating the delay model and state model parameters upon triggering.

Methods, systems, and devices for read margin health evaluations for memory systems are described. A memory system may evaluate a read margin health for a set of memory cells (e.g., a page of memory cells, a block of memory cells) based on quantities of memory cells that activate in response to applying voltages to the set of memory cells. For example, the memory system may determine, for a pair of bias voltages between a first nominal voltage associated with a first logic state and a second nominal voltage associated with a second logic state, a respective quantity of memory cells of the set of memory cells that are activated in response to biasing the set of memory cells with each of the pair of voltages. Based on the quantities of activated memory cells, the memory system may determine whether to refresh the set of memory cells.

This invention discloses a method, apparatus, electronic device, storage medium, and program product for probabilistic prediction of RTL cycle power consumption for microcontrollers. The method includes: dividing the signal sequence output from RTL simulation into samples according to clock cycle indices, and obtaining power consumption labels aligned with each index; generating binary indicators of logic state changes in adjacent cycles based on the logic states of the same multi-channel RTL signals sampled in adjacent clock cycles; concatenating and trimming the logic states and binary indicators of the multi-channel RTL signals in each clock cycle according to a predetermined order; generating a first set of predicted cycle power consumption values ​​and cycle power consumption fluctuation amplitudes corresponding to intermediate random representations based on the standardized effective feature vectors in each clock cycle; and predicting the cycle power consumption and cycle power consumption fluctuation amplitude for each clock cycle based on the standardized effective feature vectors and intermediate random representations in each clock cycle. This invention avoids output instability introduced by random sampling.

A system may include a memory configured to store data of a first logic state in a ferroelectric capacitor when an electric polarization of the ferroelectric capacitor is in a first direction. A system may include a controller configured to erase the data from the memory by commanding the electric polarization of the ferroelectric capacitor in a second direction, opposite of the first direction and skipping a subsequent write operation of a null value to the memory.

The application provides a power distribution automation fault operation and maintenance management method and system, relating to the technical field of power distribution. The method comprises the following steps: collecting electrical data of a power grid intelligent terminal; extracting real-time electrical characteristics of non-fault electrical disturbance; comparing the real-time electrical characteristics with an electrical characteristic disturbance fingerprint library, and inferring manual operation behavior according to the comparison result; updating the logical state of the corresponding equipment in the power grid digital model according to the inferred manual operation behavior; verifying the updated power grid digital model, and performing fault diagnosis and generating an isolation strategy based on the verified power grid digital model. The method aims to solve the problem of inability to identify manual operation behavior and model disconnection, can effectively identify manual operation behavior of equipment without communication function, ensure the consistency of the power grid digital model and the physical reality, thereby reducing fault diagnosis errors and power outage time.