302 results about "Logic state" patented technology

The invention relates to the technical field of distributed computing, and discloses a heavy truck charging load scheduling-oriented distributed energy intelligent matching method, which comprises the following steps of: establishing a charging service computing power mapping table at a scheduling node; maintaining a shadow counter in a local memory, extracting a pre-estimated computing power consumption value according to an event type and accumulating the pre-estimated computing power consumption value to the shadow counter, and executing linear numerical deduction on the shadow counter according to a reference logic subtraction rate so as to simulate a scheduling data throughput evolution process; adjusting a linear deduction rate parameter according to the deviation between the state feedback data and the numerical value of the shadow counter; and distributing the charging matching task to a charging station edge computing node of which the shadow counter value does not exceed a preset logic saturation threshold value. According to the invention, through an open-loop estimation and closed-loop calibration mechanism of a local logic state, an instantaneous congestion risk caused by physical feedback lag is eliminated; and logic state consistency and self-adaptive distribution of the whole network computing power resources are realized.

The invention relates to the technical field of data processing, and discloses a college budget management system fused with a new quality productivity theory, comprising: a state characterization interface collects process characterization data and maps the process characterization data into a discrete innovation state bit vector; the differential efficiency mapping unit responds to the state bit jump to calculate an efficiency marginal increment and generate an injection instruction; the physical bypass monitoring channel collects physical consumption time sequence data, and the entropy analysis closed-loop unit calculates a metabolic entropy representing the resource consumption order degree; the budget dynamic response control unit generates a state locking instruction when the state bit is constant and the metabolic entropy meets the low-entropy convergence condition, the physical working condition entropy is used for correcting the logic state, and the project resource state is maintained by recognizing the low-entropy resource consumption characteristics when no dominant output exists; the problem that discrete evaluation indexes cannot represent blind areas of continuous scientific research activities is solved.

The invention relates to the technical field of chip simulation, in particular to a voltage logic simulation design method and system for a passive internet-of-things tag chip. The method comprises the following steps: performing energy characteristic measurement on the tag chip, and calculating voltage fluctuation and logic gate triggering probability to obtain energy logic state mapping data; state transition probability distribution mapping is carried out according to the energy logic state mapping data, and a transition probability distribution tensor is constructed; collecting measurement environment parameters in the energy characteristic measurement process, and performing dynamic environment interference compensation on the transition probability distribution tensor to generate an interference compensation distribution tensor; carrying out simulation precision demand distribution based on the interference compensation distribution tensor, and constructing a layered simulation configuration file; and performing multi-precision parallel simulation execution based on the layered simulation configuration file, and generating a probabilistic verification report. Through precise and efficient logic simulation, the reliability of chip design is improved, and the fault probability is reduced.

The invention provides an SRAM (Static Random Access Memory) storage unit anti-single particle radiation reinforcement method and system, and relates to the technical field of microelectronics and circuit structure design, a redundant node coupled with a main storage node of an SRAM storage unit is constructed, and the redundant node is used for redundant storage of the logic state of the main storage node; the polarity of a main storage node is reinforced by configuring the main storage node into a circuit structure fully surrounded by a single-type transistor; wherein the redundant node and the main storage node after polarity reinforcement are integrated into a reinforced SRAM (Static Random Access Memory) storage unit. According to the method, circuit-level fusion and collaborative design are carried out on redundancy reinforcement and polarity reinforcement, so that the single event upset resistance of the SRAM unit is improved, and an efficient and enforceable reinforcement design method is provided.

A method for verifying a low-density parity-check (LDPC) unit capable of being applied in a memory system can include receiving original data corresponding to a memory device, encoding the original data by the LDPC unit to be verified, injecting errors into the encoded original data by a data pattern for generating verifying data, and verifying a soft decode capability of the LDPC unit by utilizing the verifying data. The data pattern can include the errors generated by threshold voltage (Vth) distributions interlaced between two neighboring logic states of 2n logic states of the memory device. The method and system can provide an error injection to accurately and efficiently verify a LDPC soft decode capability of the LDPC unit, decrease errors, increase error correction accuracy and efficiency, more accurately model actual threshold voltage (Vth) distributions, increase flexibility, increase speed, increase performance, and reduce firmware overhead.

A memory device includes an anti-fuse memory cell that randomly presents either a first logic state or a second logic state. The memory cell is formed on a frontside of a substrate and at least includes a first programming transistor that is formed in a first one of a plurality of metallization layers disposed over the frontside and gated by a first programming word line, and a first reading transistor that is formed in a second one of the plurality of metallization layers disposed over the frontside or along a major surface on the frontside, coupled to the first programming transistor and a first bit line in series, and gated by a first reading word line.

The invention provides a chip verification method and device, electronic equipment and a storage medium, and relates to the technical field of chip design verification, and the method comprises the steps: synchronously operating a to-be-verified chip design and a chip verification model to execute a preset cache line processing method; respectively acquiring a first output signal and first additional information of the to-be-verified chip design, and a second output signal and second additional information of the chip verification model; the first additional information is used for representing intermediate state information of a cache line in the design of the to-be-verified chip; the second additional information is used for representing intermediate state information of a cache line in the chip verification model; and determining a function verification result of the to-be-verified chip design. According to the method and the device provided by the invention, the output signal and the additional information are compared, so that the design defect can be found in time in the early stage of deviation of the internal logic state of the chip, the verification completeness and accuracy are greatly improved, and the overall verification efficiency is improved.

The invention discloses a single-pin trimming circuit, which relates to the technical field of analog circuit design and comprises a comparator module, a first input end of the comparator module is connected to a single pin, a second input end of the comparator module is connected to a reference voltage, and the comparator module is used for comparing an input voltage of the single pin with the reference voltage and outputting a comparison signal; the input end of the time sequence decoding module is connected to the output end of the comparator module, and the time sequence decoding module is configured as follows: a, the logic state of a trimming position is judged according to the duration time of the pulse in the comparison signal; and b, addressing different trimming positions according to the number of pulses in the comparison signal, and further generating a multi-position trimming control signal through a series of pulse signals input by the single pin. Accurate control of a multi-bit fuse trimming circuit in a chip is realized by using single-pin resources.

The invention discloses a smart home multi-device linkage power utilization control method based on MOS tubes, and belongs to the technical field of smart home control. The digital processor is used as a core, the built-in numerical control module and the data processing unit are matched, the on-off state of the MOS tube is accurately regulated and controlled in combination with a program control algorithm, fine management of power utilization parameters of intelligent household equipment is achieved, the limitation that traditional control response is lagged and poor in adaptability is broken through, rated parameters and real-time requirements of the equipment are dynamically matched, and the power utilization efficiency is improved. The optimal operation of equipment is guaranteed to prolong the service life, invalid energy consumption is reduced, a high-precision foundation is laid for multi-equipment cooperative linkage, the stability and energy efficiency of a system are improved, multi-scene linkage logic is preset by means of a logic state machine, and rapid switching and reliable execution of multi-scene linkage are realized by matching with an application selection switch of an MOS tube array structure. Scene requirements are automatically adapted, and through independent loop control, fault detection and standby loop design, the problems that linkage switching is tedious and the fault influence is large are solved.

A multirail-encoded qubit can be implemented using a quantum system having a state space that includes a number M of distinct modes, where M is an integer greater than 2. The M modes are logically partitioned into two disjoint subsets (or “bands”), with each mode assigned to exactly one of the bands. The multirail encoding is defined such that a state in which any one of the modes in the first band is occupied and all modes in the second band are unoccupied maps to a logical 0 state of the qubit, and a state in which any one of the modes in the second band is occupied and all modes of the first band are unoccupied maps to a logical 1 state. Systems and methods for generating, measuring, and operating on multirail-encoded qubits are disclosed.

A display pixel including at least one light-emitting diode, and an electronic circuit including a storage circuit for storing at least one digital signal and a driver circuit configured to drive said light-emitting diode by pulse-width modulation, in a first operating mode, by switching on or off said light-emitting diode during first different durations according to the logical states of the bits of the digital signal or, in a second operating mode, by switching on or off said light-emitting diode during second different durations, at least partly different from the first durations, according to the logical states of the bits of the digital signal.

A memory structure including a three-dimensional NOR memory string and a method of operation are disclosed. In some embodiments, the memory device performs partial polarization to provide a reference signal for read operations. The reference signal implements a third logic state distinguishable from the first and second logic stages in the ferroelectric memory transistor, e.g., associated with a program state and an erase state. In another embodiment, the memory device provides a reference signal for a read operation by averaging a first signal associated with a program state of the ferroelectric memory transistor and a second signal associated with an erase state. In some embodiments, the memory device implements one or more partially polarized states to provide more than one logical bit stored in each memory cell to multi-level memory cells.

An 8T CFET SRAM is proposed to perform the parallel weighted-sum operation to speed-up the inference process. A circuit includes a memory array including memory cells, each of the memory cells including a plurality of transistors, and coupled to a first word line and a second word line, and configured to receive a first data element, store a second data element, and provide a multiplication value of the first data element and the second data element. The first word line is configured to receive a first logic state corresponding to the first data element being binarized, and the second word line is configured to receive a second logic state corresponding to the first data element being binarized. A first internal node among the transistors is configured to store a first logic state corresponding to the second data element being binarized, and a second internal node among the transistors is configured to store a second logic state corresponding to the second data element being binarized.

This application discloses an automatic calibration circuit and method for mismatch compensation current of a phase-locked loop (PLL) charge pump, relating to the field of integrated circuit technology. The calibration circuit includes: a frequency and phase detector, a charge pump, an XOR module, a filter capacitor, a digital-to-analog converter (DAC) module, and a digital logic state machine. The first output terminal of the frequency and phase detector is connected to the first input terminal of the charge pump and the first input terminal of the XOR module, respectively. The second output terminal of the frequency and phase detector is connected to the second input terminal of the charge pump and the second input terminal of the XOR module, respectively. The output terminal of the XOR module is connected to the first terminal of the filter capacitor and the input terminal of the DAC module, and the second terminal of the filter capacitor is grounded. The output terminal of the DAC module is connected to the input terminal of the digital logic state machine, and the output terminal of the digital logic state machine is connected to the third input terminal of the charge pump. The output terminal of the charge pump is used to connect to the input terminal of the low-pass filter in the PLL. This application can compensate for the mismatch current of the charge pump in real time.

The latch device includes an RS type latch flip-flop capable of being supplied between a first supply voltage and a second supply voltage which is lower than the first supply voltage and having first and second flip-flop inputs and a flip-flop output connected to the output terminal. A control module positions the latch flip-flop in a set state or in a reset state when the first supply voltage has a first value which is lower than the low voltage then, the latch flip-flop being positioned, confers the high voltage on the first supply voltage and the low voltage on the second supply voltage and outputs and maintains the high voltage or the low voltage on the flip-flop output while avoiding outputting a prohibited logic state at the two flip-flop inputs.

This invention discloses a starting point control method based on twin logic, relating to the field of integrated circuit technology. The method includes: after the chip is powered on, the logic generation circuit begins to establish the state of the target logic channel, and the twin logic channel internally monitors the establishment of this state synchronously; when the twin logic channel determines that the target logic state has been established, it outputs a starting point latch signal and generates a starting point control signal, triggering a timing circuit to sequentially generate a logic lock signal and a shutdown signal; the logic lock signal securely locks the target logic to the latch matrix, and the shutdown signal subsequently shuts down the logic generation circuit. This invention uses "logic-driven timing" instead of the traditional "power-driven timing," truly binding the timing starting point to the physical establishment state of the module, fundamentally avoiding timing races and locking errors; and it can adapt to process and temperature fluctuations, significantly improving system reliability while precisely reducing additional power consumption.

The application relates to the technical field of integrated circuit design, in particular to an inverter chain circuit shielding SET pulse signals and a module packaged based on the inverter chain circuit shielding SET pulse signals. The inverter chain is constructed based on a three-stage inverter structure, which not only has the basic function of an inverter, but also has the outstanding ability of shielding SET pulse signals through reasonable circuit design, can shield voltage jump in any direction, and ensures that the output node o3 can still output with correct logic state.

A transistor control logic circuit has a first and a second input and an output. The output is coupled to the control terminal of a transistor. A peak current detector has a reference input, a detection input, and an output. The peak current detector provides a first signal at its output in a first logic state in response to a detection signal exceeding a reference signal. A trigger buffer has a first and a second input and an output. The first input of the trigger buffer is coupled to the output of the peak current detector. The output of the trigger buffer is coupled to the first input of the transistor control logic circuit.The trigger buffer provides a third signal in the first logic state at the output of the trigger buffer in response to the fact that the first signal at the output of the peak current detector is in the first logic state and a second signal at the second input of the trigger buffer is in a second logic state.

The present disclosure discloses an electronic apparatus having low power wake-up mechanism that includes an upper layer circuit and a physical layer. The upper layer circuit is powered off in a sleep state. The physical layer wakes up the upper layer circuit in the sleep state according to a logic state transition event that switches a pair of differential signal lines of a USB interface from a sleep logic state to a wakeup logic state such that a power of the upper layer circuit is restored. The physical layer modifies a voltage state of the differential signal lines to drive a host apparatus to detect a pull-out event and a plug-in event in series. The physical layer controls the upper layer circuit to perform initialization and enumeration process with the host apparatus to reconnect with the host apparatus.

The application provides a device and working method for AI chip system architecture verification, including a control center for logic control, timing coordination and data interaction of each module. A pulse writing module generates a writing signal with a special pulse form to realize state programming and conduct adjustment of storage or computing devices. A programming selection module accepts the signal of the pulse writing module, supports the structure requirements of various different memory devices of the measured unit, and performs different selective writing according to different array structures. A decoding module accepts the signal of the programming selection module and the feedback signal of the measured unit to be read, and is used for address space mapping, excitation line management and signal on-off control. The measured unit accepts the writing signal of the decoding module and feeds back the reading signal to the decoding module, and is used for storing neural network weights, logic states or continuous conduct grades. The application provides key test support and decision basis for AI chip system architecture research.

The present application belongs to the field of marine environment monitoring and signal processing technology, and relates to a real-time processing method for data denoising and time lag correction of a marine dissolved gas sensor, which comprises: identifying a steady-state interval of historical observation data of the sensor, fitting a steady-state jump with a Sigmoid function to generate a virtual true value of gas concentration; constructing a neural network model with observation data as input and a preliminary correction value of gas concentration as output, training the model with historical observation data as input and the virtual true value of gas concentration as a training target; using a sliding window mechanism to intercept observation data segments of the current and historical time of the sensor, inputting the data segments into the model to output a preliminary correction value of gas concentration at the current time; and using a logic state machine for post-processing to obtain a final correction value of gas concentration at the current time. The present application can provide the sensor with real-time compensation functions that take into account high dynamic response and zero steady-state drift, thereby realizing in-situ acquisition and real-time return of high-precision observation data.

A memory device of a first array of memory cells configured as quad-level cell (QLC) memory or penta-level cell (PLC) memory and including one or more first planes. A second array of memory cells configured as second memory that is less-densely programmed than the first array, the second array including one or more second planes. Control logic receives a first command to program a first set of memory cells of the first array with a first logical state and a second command to program a second set of memory cells of the second array with a second logical state corresponding in threshold voltage range to the first logical state. The first and second sets of memory cells are associated with a shared wordline. The control logic causes the first and second sets of memory cells to be concurrently programmed with a threshold voltage distribution corresponding to the first logical state.

An ADC (50) is disclosed. It has two VTCs (110a, 110b) for converting a first and a second input voltage, respectively, to pulses with delays corresponding to the magnitudes of these voltages. It further has a pulse-detector circuit (120) coupled to outputs (114a, 114b) of the two VTCs (110a, 110b). The pulse-detector circuit (120) is configured to make a transition from a first logic state (‘0’) to a second logic state (‘F) at a first output (124a) of the pulse-detector circuit (120) in response to the start of the pulse from one of the VTCs (110a) and to make a transition from the first logic state (‘0’) to the second logic state (‘F) at a second output (124b) of the pulse-detector circuit (120) in response to the start of the pulse from the other VTC. Furthermore, the pulse-detector circuit (120) is configured to reset both the first and the second output (124a, 124b) to the first logic state (‘0’) in response to both the first output (124a) and the second output (124b) of the pulse-detector circuit (120) being set in the second logic state (‘1’). The ADC (50) further has a first TDC (130a) coupled to the first output (124a) of the pulse-detector circuit (120) and a second TDC (130b) coupled to the second output (124b) of the pulse-detector circuit (120).

A power MOSFET driver circuit includes a feedback circuit configured to supply a feedback signal that signals when a gate voltage of the power MOSFET crosses a plateau value and the power MOSFET switches conduction state. The feedback circuit includes a comparator with a replica MOSFET of the power MOSFET, with scaled down dimensions, whose gate is coupled to the gate electrode of the power MOSFET. A bistable circuit has an input coupled to an output of the replica MOSFET and is configured to change a logic state of the feedback signal following the transition of the switching signal when the gate voltage of the power MOSFET crosses the plateau value and the power MOSFET switches conduction state.

A circuitry for generating output clock signals with increasing phase delays comprises: an input receiving input clock signals with increasing phase delays, wherein the output clock signals are twice as many as the input clock signals; logic components connected in a loop with an output from a component connected as a first input to a following component, wherein the output is further connected as a second input to an oppositely positioned component; wherein each component receives the first, the second and a third input signal; wherein pairs of oppositely positioned components receive a common input clock signal and mask out the third input clock signal based on logic state of first and second input signals such that the outputs are phase shifted by 180 degrees; and wherein the circuitry outputs the output clock signals based on outputs from each component.

The invention provides a method and a device for updating a knowledge graph of power transformation primary equipment, and aims to determine the state variation of the power transformation primary equipment by integrating physical topology logic and operation and maintenance rule data of the equipment, perform incremental updating by taking the equipment as a starting point when an event is updated, and perform knowledge graph updating. And thus, the accurate transformer main equipment knowledge graph is obtained. The method for updating the knowledge graph of the power transformation main equipment comprises the following steps: acquiring the knowledge graph of the power transformation main equipment, and determining equipment physical topology logic state data based on equipment physical topology logic data in the knowledge graph and a message passing mechanism of a power physical topology layer graph neural network; based on the operation and maintenance operation rule data and the operation and maintenance operation dependency relationship rule, determining operation and maintenance operation state data; and on the basis of the determined state data, after the state variation of the power transformation main equipment in the preset time is calculated, updating the knowledge graph by using an incremental graph updating algorithm to obtain a target knowledge graph.

The invention relates to the technical field of integrated circuits, and provides a pulse trigger type level shift circuit which comprises a double-pulse current generation circuit, a high-low level shift conversion holding circuit, a high-voltage domain output shaping filter circuit and an RS trigger which are connected in sequence. The double-pulse current generating circuit responds to the jump edge of the low-voltage domain input signal to generate a transient double-pulse current signal; the high-low level shift conversion holding circuit is combined with the current signal and an input signal to generate a complementary pulse voltage signal of a high-voltage domain; the shaping and filtering circuit performs shaping and filtering on the pulse voltage; and the RS trigger finally latches the logic state and outputs a stable burr-free high-voltage domain signal. Through a pulse current triggering mode, an extremely short pulse is generated only when a signal jumps, a quiescent current path is eliminated, and low static power consumption is achieved; meanwhile, fast level flipping under high voltage difference is achieved through pulse driving, the requirement for the input signal driving capacity is low, and the characteristics of high speed and low power consumption are considered.

Methods, systems, and devices for methods for performing voltage sweep operations are described. Based on detecting a failure at a portion of a memory device, the memory system controller may initialize a voltage sweep operation to identify threshold voltages of the memory cells at the portion of the memory device. In one example, the memory system controller may identify and store a value (e.g., a delta value) that represents a difference between a quantity of transitions experienced by a first memory cell at a first voltage iteration and a quantity of transitions experienced by the first memory cell at a second voltage iteration. In another example, the memory system controller may identify the quantity of transitions from a first logic state to a second logic state and a quantity of transitions from the second logic state to a first logic state and store such values in respective memory arrays.

The invention discloses a six-vehicle-type main splicing clamp switching system, and relates to the technical field of automobile body welding manufacturing, and the six-vehicle-type main splicing clamp switching system is characterized in that a working area and a buffer area are arranged on one side of a roller bed in a layered manner, and an inner space and an outer space are connected through a polyhedral rotary table assembly. An inner side transfer trolley runs in the working area, an outer side transfer trolley runs in the cache area, and on the basis that four sets of online clamps are stored, two sets of spare clamps are additionally stored through the outer side trolley. The control unit collects trolley bearing information to construct a real-time state vector, identifies three logic states A, B and C, and calls preset 16 switching processes through multi-level logic judgment in combination with an external instruction. And the control unit drives the outside trolley to execute cross-region or fixed-point maneuvering and is matched with the rotation of the rotary table to complete injection, replacement and recovery of the clamp. Through state abstract control and layered physical layout, deterministic flexible switching of six vehicle model clamps is realized in a limited space, and collinear flexibility of a production line is improved.

A memory device includes a plurality of memory cells, each of the plurality of memory cells configured to store a data bit; a first interconnect structure operatively configured as a bit line and coupled to each of the plurality of memory cells; and a second interconnect structure operatively configured to carry a supply voltage and coupled to each of the plurality of memory cells. The data bit stored by a first one of the plurality of memory cells presents a first logic state when the first memory cell includes a first channel structure, with a first end and a second end of the first channel structure connected to a first epitaxial structure and a second epitaxial structure, respectively, and wherein the first epitaxial structure is overlaid by a dielectric structure and the second epitaxial structure is overlaid by a first contact structure.