185 results about "Logic state" patented technology

The invention relates to the technical field of distributed computing, and discloses a heavy truck charging load scheduling-oriented distributed energy intelligent matching method, which comprises the following steps of: establishing a charging service computing power mapping table at a scheduling node; maintaining a shadow counter in a local memory, extracting a pre-estimated computing power consumption value according to an event type and accumulating the pre-estimated computing power consumption value to the shadow counter, and executing linear numerical deduction on the shadow counter according to a reference logic subtraction rate so as to simulate a scheduling data throughput evolution process; adjusting a linear deduction rate parameter according to the deviation between the state feedback data and the numerical value of the shadow counter; and distributing the charging matching task to a charging station edge computing node of which the shadow counter value does not exceed a preset logic saturation threshold value. According to the invention, through an open-loop estimation and closed-loop calibration mechanism of a local logic state, an instantaneous congestion risk caused by physical feedback lag is eliminated; and logic state consistency and self-adaptive distribution of the whole network computing power resources are realized.

The invention provides an SRAM (Static Random Access Memory) storage unit anti-single particle radiation reinforcement method and system, and relates to the technical field of microelectronics and circuit structure design, a redundant node coupled with a main storage node of an SRAM storage unit is constructed, and the redundant node is used for redundant storage of the logic state of the main storage node; the polarity of a main storage node is reinforced by configuring the main storage node into a circuit structure fully surrounded by a single-type transistor; wherein the redundant node and the main storage node after polarity reinforcement are integrated into a reinforced SRAM (Static Random Access Memory) storage unit. According to the method, circuit-level fusion and collaborative design are carried out on redundancy reinforcement and polarity reinforcement, so that the single event upset resistance of the SRAM unit is improved, and an efficient and enforceable reinforcement design method is provided.

A method for verifying a low-density parity-check (LDPC) unit capable of being applied in a memory system can include receiving original data corresponding to a memory device, encoding the original data by the LDPC unit to be verified, injecting errors into the encoded original data by a data pattern for generating verifying data, and verifying a soft decode capability of the LDPC unit by utilizing the verifying data. The data pattern can include the errors generated by threshold voltage (Vth) distributions interlaced between two neighboring logic states of 2n logic states of the memory device. The method and system can provide an error injection to accurately and efficiently verify a LDPC soft decode capability of the LDPC unit, decrease errors, increase error correction accuracy and efficiency, more accurately model actual threshold voltage (Vth) distributions, increase flexibility, increase speed, increase performance, and reduce firmware overhead.

The invention discloses a single-pin trimming circuit, which relates to the technical field of analog circuit design and comprises a comparator module, a first input end of the comparator module is connected to a single pin, a second input end of the comparator module is connected to a reference voltage, and the comparator module is used for comparing an input voltage of the single pin with the reference voltage and outputting a comparison signal; the input end of the time sequence decoding module is connected to the output end of the comparator module, and the time sequence decoding module is configured as follows: a, the logic state of a trimming position is judged according to the duration time of the pulse in the comparison signal; and b, addressing different trimming positions according to the number of pulses in the comparison signal, and further generating a multi-position trimming control signal through a series of pulse signals input by the single pin. Accurate control of a multi-bit fuse trimming circuit in a chip is realized by using single-pin resources.

The invention discloses a smart home multi-device linkage power utilization control method based on MOS tubes, and belongs to the technical field of smart home control. The digital processor is used as a core, the built-in numerical control module and the data processing unit are matched, the on-off state of the MOS tube is accurately regulated and controlled in combination with a program control algorithm, fine management of power utilization parameters of intelligent household equipment is achieved, the limitation that traditional control response is lagged and poor in adaptability is broken through, rated parameters and real-time requirements of the equipment are dynamically matched, and the power utilization efficiency is improved. The optimal operation of equipment is guaranteed to prolong the service life, invalid energy consumption is reduced, a high-precision foundation is laid for multi-equipment cooperative linkage, the stability and energy efficiency of a system are improved, multi-scene linkage logic is preset by means of a logic state machine, and rapid switching and reliable execution of multi-scene linkage are realized by matching with an application selection switch of an MOS tube array structure. Scene requirements are automatically adapted, and through independent loop control, fault detection and standby loop design, the problems that linkage switching is tedious and the fault influence is large are solved.

An 8T CFET SRAM is proposed to perform the parallel weighted-sum operation to speed-up the inference process. A circuit includes a memory array including memory cells, each of the memory cells including a plurality of transistors, and coupled to a first word line and a second word line, and configured to receive a first data element, store a second data element, and provide a multiplication value of the first data element and the second data element. The first word line is configured to receive a first logic state corresponding to the first data element being binarized, and the second word line is configured to receive a second logic state corresponding to the first data element being binarized. A first internal node among the transistors is configured to store a first logic state corresponding to the second data element being binarized, and a second internal node among the transistors is configured to store a second logic state corresponding to the second data element being binarized.

This application discloses an automatic calibration circuit and method for mismatch compensation current of a phase-locked loop (PLL) charge pump, relating to the field of integrated circuit technology. The calibration circuit includes: a frequency and phase detector, a charge pump, an XOR module, a filter capacitor, a digital-to-analog converter (DAC) module, and a digital logic state machine. The first output terminal of the frequency and phase detector is connected to the first input terminal of the charge pump and the first input terminal of the XOR module, respectively. The second output terminal of the frequency and phase detector is connected to the second input terminal of the charge pump and the second input terminal of the XOR module, respectively. The output terminal of the XOR module is connected to the first terminal of the filter capacitor and the input terminal of the DAC module, and the second terminal of the filter capacitor is grounded. The output terminal of the DAC module is connected to the input terminal of the digital logic state machine, and the output terminal of the digital logic state machine is connected to the third input terminal of the charge pump. The output terminal of the charge pump is used to connect to the input terminal of the low-pass filter in the PLL. This application can compensate for the mismatch current of the charge pump in real time.

This invention discloses a starting point control method based on twin logic, relating to the field of integrated circuit technology. The method includes: after the chip is powered on, the logic generation circuit begins to establish the state of the target logic channel, and the twin logic channel internally monitors the establishment of this state synchronously; when the twin logic channel determines that the target logic state has been established, it outputs a starting point latch signal and generates a starting point control signal, triggering a timing circuit to sequentially generate a logic lock signal and a shutdown signal; the logic lock signal securely locks the target logic to the latch matrix, and the shutdown signal subsequently shuts down the logic generation circuit. This invention uses "logic-driven timing" instead of the traditional "power-driven timing," truly binding the timing starting point to the physical establishment state of the module, fundamentally avoiding timing races and locking errors; and it can adapt to process and temperature fluctuations, significantly improving system reliability while precisely reducing additional power consumption.

The application relates to the technical field of integrated circuit design, in particular to an inverter chain circuit shielding SET pulse signals and a module packaged based on the inverter chain circuit shielding SET pulse signals. The inverter chain is constructed based on a three-stage inverter structure, which not only has the basic function of an inverter, but also has the outstanding ability of shielding SET pulse signals through reasonable circuit design, can shield voltage jump in any direction, and ensures that the output node o3 can still output with correct logic state.

A transistor control logic circuit has a first and a second input and an output. The output is coupled to the control terminal of a transistor. A peak current detector has a reference input, a detection input, and an output. The peak current detector provides a first signal at its output in a first logic state in response to a detection signal exceeding a reference signal. A trigger buffer has a first and a second input and an output. The first input of the trigger buffer is coupled to the output of the peak current detector. The output of the trigger buffer is coupled to the first input of the transistor control logic circuit.The trigger buffer provides a third signal in the first logic state at the output of the trigger buffer in response to the fact that the first signal at the output of the peak current detector is in the first logic state and a second signal at the second input of the trigger buffer is in a second logic state.

The present disclosure discloses an electronic apparatus having low power wake-up mechanism that includes an upper layer circuit and a physical layer. The upper layer circuit is powered off in a sleep state. The physical layer wakes up the upper layer circuit in the sleep state according to a logic state transition event that switches a pair of differential signal lines of a USB interface from a sleep logic state to a wakeup logic state such that a power of the upper layer circuit is restored. The physical layer modifies a voltage state of the differential signal lines to drive a host apparatus to detect a pull-out event and a plug-in event in series. The physical layer controls the upper layer circuit to perform initialization and enumeration process with the host apparatus to reconnect with the host apparatus.

The application provides a device and working method for AI chip system architecture verification, including a control center for logic control, timing coordination and data interaction of each module. A pulse writing module generates a writing signal with a special pulse form to realize state programming and conduct adjustment of storage or computing devices. A programming selection module accepts the signal of the pulse writing module, supports the structure requirements of various different memory devices of the measured unit, and performs different selective writing according to different array structures. A decoding module accepts the signal of the programming selection module and the feedback signal of the measured unit to be read, and is used for address space mapping, excitation line management and signal on-off control. The measured unit accepts the writing signal of the decoding module and feeds back the reading signal to the decoding module, and is used for storing neural network weights, logic states or continuous conduct grades. The application provides key test support and decision basis for AI chip system architecture research.

The present application belongs to the field of marine environment monitoring and signal processing technology, and relates to a real-time processing method for data denoising and time lag correction of a marine dissolved gas sensor, which comprises: identifying a steady-state interval of historical observation data of the sensor, fitting a steady-state jump with a Sigmoid function to generate a virtual true value of gas concentration; constructing a neural network model with observation data as input and a preliminary correction value of gas concentration as output, training the model with historical observation data as input and the virtual true value of gas concentration as a training target; using a sliding window mechanism to intercept observation data segments of the current and historical time of the sensor, inputting the data segments into the model to output a preliminary correction value of gas concentration at the current time; and using a logic state machine for post-processing to obtain a final correction value of gas concentration at the current time. The present application can provide the sensor with real-time compensation functions that take into account high dynamic response and zero steady-state drift, thereby realizing in-situ acquisition and real-time return of high-precision observation data.

A memory device of a first array of memory cells configured as quad-level cell (QLC) memory or penta-level cell (PLC) memory and including one or more first planes. A second array of memory cells configured as second memory that is less-densely programmed than the first array, the second array including one or more second planes. Control logic receives a first command to program a first set of memory cells of the first array with a first logical state and a second command to program a second set of memory cells of the second array with a second logical state corresponding in threshold voltage range to the first logical state. The first and second sets of memory cells are associated with a shared wordline. The control logic causes the first and second sets of memory cells to be concurrently programmed with a threshold voltage distribution corresponding to the first logical state.

A power MOSFET driver circuit includes a feedback circuit configured to supply a feedback signal that signals when a gate voltage of the power MOSFET crosses a plateau value and the power MOSFET switches conduction state. The feedback circuit includes a comparator with a replica MOSFET of the power MOSFET, with scaled down dimensions, whose gate is coupled to the gate electrode of the power MOSFET. A bistable circuit has an input coupled to an output of the replica MOSFET and is configured to change a logic state of the feedback signal following the transition of the switching signal when the gate voltage of the power MOSFET crosses the plateau value and the power MOSFET switches conduction state.

A circuitry for generating output clock signals with increasing phase delays comprises: an input receiving input clock signals with increasing phase delays, wherein the output clock signals are twice as many as the input clock signals; logic components connected in a loop with an output from a component connected as a first input to a following component, wherein the output is further connected as a second input to an oppositely positioned component; wherein each component receives the first, the second and a third input signal; wherein pairs of oppositely positioned components receive a common input clock signal and mask out the third input clock signal based on logic state of first and second input signals such that the outputs are phase shifted by 180 degrees; and wherein the circuitry outputs the output clock signals based on outputs from each component.

A memory device includes a plurality of memory cells, each of the plurality of memory cells configured to store a data bit; a first interconnect structure operatively configured as a bit line and coupled to each of the plurality of memory cells; and a second interconnect structure operatively configured to carry a supply voltage and coupled to each of the plurality of memory cells. The data bit stored by a first one of the plurality of memory cells presents a first logic state when the first memory cell includes a first channel structure, with a first end and a second end of the first channel structure connected to a first epitaxial structure and a second epitaxial structure, respectively, and wherein the first epitaxial structure is overlaid by a dielectric structure and the second epitaxial structure is overlaid by a first contact structure.

The invention discloses a multi-level current source inverter and a control method thereof, and relates to the field of electric energy conversion control, the multi-level current source inverter is composed of an MCSI module, a direct current side inductor, a coupling capacitor, a ripple filter and a control module, and the three-phase voltage and the load current of a power grid are measured; calculating a reference phase under a synchronous rotating coordinate system by using a three-phase digital phase-locked loop, and further decomposing the reference phase into a current mean value and an alternating current component; a current error is obtained by establishing an additional control loop, and a DC component is separated from the current error by using a PI controller; generating a reference current under the synchronous rotating coordinate system, converting the reference current back to the three-phase coordinate system, and generating an actual gate driving signal of the MCSI module; based on an actual gate pole driving signal, the actual gate pole driving signal serves as a reference of phase shift carrier SPWM, and zero-state selection and inductive current balance are optimized in cooperation with a logic state machine. The method is used for power quality management of the power distribution network, harmonic waves and reactive power can be suppressed, and switching loss is reduced.

The present application relates to the field of integrated circuit technology, and provides a pulse trigger type level shift circuit, which comprises a double pulse current generating circuit, a high-low level shift conversion holding circuit, a high voltage domain output shaping filter circuit and an RS flip-flop connected in sequence. The double pulse current generating circuit generates a short double pulse current signal in response to a jump edge of a low voltage domain input signal; the high-low level shift conversion holding circuit combines the current signal with the input signal to generate a complementary pulse voltage signal in a high voltage domain; the shaping filter circuit shapes and filters the pulse voltage; and the RS flip-flop finally latches the logic state and outputs a stable high voltage domain signal without glitches. The present application generates an extremely short pulse only when the signal jumps by means of pulse current trigger, eliminates the static current path, and has low static power consumption. Meanwhile, the pulse driving is used to realize fast level inversion under high voltage difference, and the input signal driving capability requirement is low, so that the high speed and low power consumption characteristics are taken into account.

Clock phase tuning method including supplying a current (lout) to a capacitor (CL) when first and second clock signals (CK1, CK2) are at a first logic state to generate an voltage (Vout) across the capacitor during a first interval; supplying or drawing a current (lout) to or from the capacitor based on an enable signal when the first and second clock signals are at first and second logic states to generate the voltage across the capacitor during a second interval; drawing a current from the capacitor when the first and second clock signals are at the second logic state to generate the voltage during a third interval; drawing or supplying current from or to the capacitor based on the enable signal when the first and second clock signals are at second and first second logic states to generate the voltage across the capacitor during a fourth interval; and generating a clock signal (Ckout) based on the voltage.

This invention provides a low-power battery monitor and a method for doing so. [Solution] The oscillator has an enable input and an oscillator output. The voltage regulator has an enable input. The logic circuit has a counter having a control input, a control output, a status output, and a clock input coupled to the oscillator output. The control output is coupled to the enable inputs of the oscillator and the voltage regulator. The logic circuit is configured to enable the oscillator by asserting a control signal at the control output to a first logic state in response to a first control value at the control input, causing the counter to count and disabling the voltage regulator. In response to the counter reaching a final value, it sets a status signal at the status output to a first logic state and asserts a control signal at the control output to a second logic state, disabling the oscillator and enabling the voltage regulator.

The invention provides a non-destructive data reading method for a ferroelectric memory, and relates to the technical field of semiconductor memories, and the method comprises the steps: S1, applying a subthreshold reading voltage; s2, detecting a polarization response signal; s3, comparing and judging a logic state; the method has thorough non-destructiveness, the polarization direction of the ferroelectric capacitor cannot be overturned in the whole read operation process, and original storage data can be completely reserved. The write-back operation necessary for the traditional method is fundamentally eliminated. Delay and power consumption can be reduced, energy consumed by write-back operation is avoided, and dynamic power consumption is remarkably reduced; the read-write service life of the ferroelectric memory is greatly prolonged; and the design flexibility and robustness are improved.

The invention provides a multi-mode collaborative lithium battery protection circuit control method. The method comprises the following steps: acquiring voltage, current and surface temperature of a battery pack and a relay state signal in real time, and constructing a standardized time sequence tensor through preprocessing; inverting the core temperature of each single battery based on an electricity-heat-aging coupling model; the aging rate index is dynamically calibrated by combining the joint extended Kalman filtering and the real-time core temperature; a dynamic adjacency matrix is constructed through voltage correlation and temperature gradient, and a topological weakness risk is identified by using a lightweight graph convolutional network; according to the core temperature, the aging index, the risk score and the SOC difference, a protection mode is dynamically switched in a multi-mode logic state machine, and a control instruction is generated; and finally, the time sequence of a power tube is adjusted through PWM phase compensation, and a distributed model prediction control algorithm is adopted to drive an equalization circuit, so that lithium battery system protection with safety, service life and performance collaborative optimization is realized.

An image transmission / reception system, a program product, and an image transmission / reception method are provided with: an image reception device provided with: a reception circuit that extracts a clock signal from transmission data, acquires image data, and changes a lock signal from a first logic state to a second logic state; and a lock signal transmission control unit that adds error detection information to code information including information about the logic state of the lock signal and notification information other than the logic state of the lock signal, and outputs the code information as serial data to the image transmission device. And an image transmission device provided with: a transmission circuit that transmits, to the image reception device, transmission data obtained by superimposing the clock signal on the image data; an image transmission control unit that controls transmission of the image data; and a lock signal reception control unit that receives the serial data, outputs notification information corresponding to the code information to the image transmission control unit, and outputs a lock signal of the logic state indicated by the code information to the transmission circuit.

Various embodiments of this disclosure relate to low-power and fast memory reset. One memory reset method includes: pre-charging bit lines of a memory array; asserting a signal at a reset node to remove the pre-charge voltage; and selecting write drivers associated with bit lines, the bit lines being associated with columns of the memory array including memory cells to be reset; wherein the assertion signal at the reset node further causes a desired logic state to be applied to the input of the selected write drivers, causing those selected write drivers to change the logic state of the bit lines associated with those write drivers. The method continues to assert each word line associated with a row of memory containing the memory cells to be reset, to write the desired logic state to all memory cells to be reset in the column and row of memory during a single clock cycle, and then deasserting those word lines.

An object of the present invention is to provide a neuromorphic system including a synaptic unit capable of causing a gradual change in resistance for analog information processing, and an operating method therefor. In order to achieve the above object, an aspect of the present invention may provide a neuromorphic system including an input signal unit for generating an input signal, a synapse unit including a plurality of synaptic units that receive a signal of the input signal unit and cause a current to flow according to a set weight, an output signal unit for generating an output signal by receiving a current generated from the synapse unit, and a controller unit for controlling the input signal unit, the synapse unit, and the output signal unit, in which the input signal unit includes a digital-to-analog converter (DAC), the synaptic units include a plurality of memory cells that are connected to each other and are each capable of selectively storing a logic state, the plurality of memory cells are arranged in a cross-point structure including an input electrode line and an output electrode line that cross each other to form one or more memory arrays, the output signal unit includes an analog-to-digital converter (ADC), and the controller unit generates an analog input signal through the DAC in the input signal unit, allows the generated analog input signal to be applied to each of the plurality of memory cells included in the synaptic unit so that a current flows, and generates a sum of currents flowing from the plurality of memory cells as the output signal through the ADC in the output signal unit.

A memory sub-system having a memory device with a plurality of cells and a processing device operatively coupled to the memory device, the processing device to perform the operations of: responsive to detecting a power off event, programming, to a predefined logical state, a dummy subset of the plurality of cells; responsive to detecting a power-up event, determining a voltage shift associated with the dummy subset of the plurality of cells; and identifying, based on the voltage shift, a voltage offset bin shift corresponding to a voltage offset bin associated with a specified subset of the plurality of cells.

The present disclosure relates to in-memory computing, high-density arrays. A memory cell to perform in-memory computing operations includes a pair of cross-coupled inverters and a pair of transistors to selectively perform read / write / hold operations associated with a logic state of the pair of cross-coupled inverters. The memory cell further includes a set of transistors coupled to the pair of cross-coupled inverters and symmetrically arranged with respect to the pair of cross-coupled inverters. An output node of the memory cell is at a terminal of the set of transistors and provides an output based on logic states of the pair of cross-coupled inverters and an input node disposed between pairs of the set of transistors. An array of memory cells can be generated with high-density arrangements of memory cells capable of performing in-memory computing operations. The memory cells can be arranged as a neural network including a set of networks of memory cells to provide a logic output operation based on logic states of respective memory cells.

The application provides a monitoring circuit, an integrated circuit and a monitoring protection method thereof. The monitoring circuit comprises a quieting filter, a voltage sensor and a latch. The quieting filter is configured to absorb energy of a first voltage signal terminal and a second voltage signal terminal. The voltage sensor is configured to detect a voltage fluctuation between the first voltage signal terminal and the second voltage signal terminal after the quieting filter absorbs the energy of the first voltage signal terminal and the second voltage signal terminal, and output an adjustment signal to the latch when the voltage fluctuation meets a set condition. The latch is configured to output a first logic state at an output end after receiving the adjustment signal, so as to determine that an electrostatic discharge event occurs. The monitoring circuit of the application monitors the electrostatic discharge event by identifying the change of the power supply voltage, and then triggers a protection mechanism to protect the integrated circuit, thereby avoiding damage to the integrated circuit caused by the electrostatic discharge event.

The utility model provides a high-power double-fed wind power converter hardware-in-the-loop simulation test tool, which comprises a bottom platform, a middle platform and a top platform which are arranged on a frame of a test vehicle, the low-voltage manager is respectively in circuit connection with the communication switch, the master control analog machine, the logic state switch, the control unit, the photoelectric converter, the distributed controller and the signal conversion panel, the signal conversion panel is respectively in circuit connection with the distributed controller and the photoelectric converter, and the photoelectric converter is in circuit connection with the distributed controller. The main control analog machine is in circuit connection with the communication switch, the communication switch and the logic state switch are respectively connected with the distributed controller, and the distributed controller is connected with the control unit through an optical fiber. The beneficial effects of the utility model are that the device integrates the distributed controller, the photoelectric converter, the low-voltage manager, the master control analog machine, the communication switch and the signal interface conversion panel, and is compatible with a plurality of doubly-fed models for hardware-in-the-loop simulation tests.