7 results about "Resistive switching memory" patented technology

The application discloses a resistive switching memory structure and a manufacturing method thereof. The resistive switching memory structure comprises, from bottom to top, a bottom electrode, a resistive switching layer and a top electrode. The upper surface of the bottom electrode and the lower surface of the resistive switching layer are in Schottky contact, and the lower surface of the top electrode and the upper surface of the resistive switching layer are in Ohmic contact. The resistive switching layer is a single oxide film layer. The materials of the bottom electrode and the top electrode are the same metal nitride, and the atomic number ratio of metal elements to nitrogen elements in the top electrode is greater than that in the bottom electrode. The application can simplify the structure of the memory, reduce the process complexity and manufacturing cost.

This invention relates to a self-gated resistive switching memory (SRAM). By using niobium oxide, which is less prone to oxygen vacancy accumulation, as the storage layer, the on-state current density is improved. At the same time, by setting a titanium oxide layer with a peak-shaped band structure as the gating layer, the nonlinearity of the device is improved. Thus, the self-gated resistive switching memory has both high nonlinearity and high on-state current density, solving the problem that high nonlinearity and high on-state current density cannot be achieved simultaneously in the prior art.

Resistive switching memory cells having filament-based switching mechanisms are provided. By way of example, resistive switching memory cells having resistive filaments constrained to a core of the cell are disclosed. In other examples, methods for fabricating resistive switching memory cells to constrain a conductive filament formed in the resistive switching memory cell to a central portion of core of the cell are disclosed.

The application relates to a convolution calculation circuit and a calculation method based on a resistive switching memory, wherein the calculation circuit comprises a memory calculation array, a digital-to-analog converter, an analog-to-digital converter, a word / bit line decoder and a controller; the memory calculation array is connected with the digital-to-analog converter in the bit line direction and connected with the analog-to-digital converter in the word line direction; the input of the digital-to-analog converter is a convolution input digital signal, and the output is connected to the memory calculation array; the input of the analog-to-digital converter is connected to the memory calculation array, and the output is a convolution output digital signal; the output of the word / bit line decoder is connected to the memory calculation array and used for selecting part or all of the memory calculation array; and the output of the controller is respectively connected to the memory calculation array, the digital-to-analog converter and the analog-to-digital converter and used for generating a control signal for realizing convolution calculation. The application can greatly improve the efficiency of convolution calculation.

This application relates to the field of semiconductor memory device technology, and discloses a 3D memory device and its fabrication process. The 3D memory device includes a substrate, a multilayer stacked structure, a contact lead-out structure, a via, a resistive switching functional layer, and a top electrode. The multilayer stacked structure includes multiple alternating layers of two-dimensional conductive material and multiple layers of insulating dielectric material arranged in a vertical direction. The two-dimensional conductive material layers serve as interlayer contact electrodes or memory cell electrodes. The via penetrates at least a portion of the multilayer stacked structure and exposes the edge regions of the two-dimensional conductive material layers. The resistive switching functional layer is disposed on the inner wall and / or inside the via and contacts the edge regions of the two-dimensional conductive material layers. The top electrode is electrically connected to the resistive switching functional layer. This structure utilizes the two-dimensional conductive material layers to reduce the vertical thickness of the interlayer electrodes and forms multiple resistive switching memory cells on the sidewalls of the vias, thereby increasing the storage density of the 3D memory device.

This application provides a resistive switching memory cell, a resistive switching memory array, a resistive switching memory, and an operating method, relating to the field of memory technology. The resistive switching memory cell includes: multiple resistive switching devices forming multiple rows and columns; multiple gating devices, each gating device connected to a first electrode of each resistive switching device in a row, the gating devices being adapted to be connected to word lines and global source lines respectively, and electrically connecting or disconnecting the global source lines connected to the gating devices and the first electrodes of the resistive switching devices; and multiple isolation devices, each isolation device connected to a second electrode of each resistive switching device in a column, the isolation devices being adapted to be connected to control word lines and global bit lines respectively, and electrically connecting or disconnecting the global bit lines connected to the isolation devices and the second electrodes of the resistive switching devices.

This invention discloses a data processing method and an electronic device. The data processing method is used in an integrated circuit device, the integrated circuit device including a plurality of processing cores formed on a substrate of the integrated circuit device, a resistive memory array structure formed above the substrate of the integrated circuit device, access circuitry at least partially formed on the substrate of the integrated circuit device, and a plurality of memory controllers. The resistive memory array structure includes a plurality of resistive memory subarrays, each resistive memory subarray including a non-volatile two-terminal resistive switching memory cell. The access circuitry provides independent operative access to a corresponding resistive memory subarray of the plurality of resistive memory subarrays. Each memory controller is communicatively coupled to a corresponding processing core among the plurality of processing cores. The method includes: at least one memory controller receiving a memory instruction from a corresponding processing core; and in response to the memory instruction, the at least one memory controller executing the memory instruction on a corresponding resistive memory subarray. Based on monolithic integration, a close physical proximity is provided between the processing cores and main memory. This method promotes significant memory parallelism, reduces power consumption, and eliminates off-chip main memory access requests.