21 results about "Resistive switching memory" patented technology

An electronic device can be validated at a circuit-level or device-level to provide supply chain verification of an integrated circuit (IC) product. A modern integrated circuit package can comprise multiple dies, systems and circuitry built from a variety of device-level structures. Device-level verification disclosed herein can confirm that a device-level (sub-) component of an integrated circuit product is sourced by a known or otherwise valid manufacturer. This serves to mitigate or avoid a hacking attempt involving illicit replacement of a component of an IC product by an intermediate handler of the IC product within a supply chain.

Leveraging stochastic physical characteristics of resistive switching devices to generate data having very low cross correlation among bits of that data is disclosed. Data generated from stochastic physical characteristics can also be referred to as physical unclonable feature—or function—(PUF) data. Additionally, error correction functions for PUF data generated from resistive switching memory cells are provided. The error correction functions facilitate additional redundancy and longevity of PUF data, among other benefits. Different embodiments include addressing arrangements to incorporate ECC parity bits among generated PUF data bits, even for differential PUF bits respectively defined by multiple memory cells in different portions of a resistive memory array.

The invention relates to a lead-free perovskite composite material, a preparation method thereof and application of the lead-free perovskite composite material in a resistive random access memory, and belongs to the technical field of preparation of the resistive random access memory. The lead-free perovskite composite material comprises a doped Sb element, the chemical formula of the lead-free perovskite composite material is Cs3Cu2I5: Sb, the molar ratio of Sb to Cu is (0.1-1): 1, the perovskite Cs3Cu2I5 is doped and modified through the element Sb, the content of iodine vacancy (VI) in cesium-iodine-copper perovskite can be reduced, the stability of conductive filaments can be improved, and therefore the resistance change performance of the resistive random access memory is improved.

The application discloses a resistive switching memory structure and a manufacturing method thereof. The resistive switching memory structure comprises, from bottom to top, a bottom electrode, a resistive switching layer and a top electrode. The upper surface of the bottom electrode and the lower surface of the resistive switching layer are in Schottky contact, and the lower surface of the top electrode and the upper surface of the resistive switching layer are in Ohmic contact. The resistive switching layer is a single oxide film layer. The materials of the bottom electrode and the top electrode are the same metal nitride, and the atomic number ratio of metal elements to nitrogen elements in the top electrode is greater than that in the bottom electrode. The application can simplify the structure of the memory, reduce the process complexity and manufacturing cost.

The application discloses a kind of based on dithio metal complex doped polymer resistance change storage material and its preparation method and application, belong to data storage technical field.The storage material is with cadmium halide synthesis complex with bipyridine (Bpy) as ligand, and with polyvinylpyrrolidone (PVP) compound and obtained composite material.Based on the storage performance of pure cadmium complex device is poor, and the switch ratio is only 10 2.32 ~10 3.18 , with halogen from I to SCN, storage performance gradually improves.After being compounded with PVP, Cl base and SCN base device exhibits good ternary storage behavior (ternary yield is 65% and 55%), and the current switch ratio reaches 10 6.13 :10 3.80 :1, and good device stability is shown, and it is expected to be applied to construct high-performance halogen-based memory.Raw material is widely sourced, and the preparation method is simple, and the product has excellent performance, and has significant economic and social benefits.

This invention relates to a self-gated resistive switching memory (SRAM). By using niobium oxide, which is less prone to oxygen vacancy accumulation, as the storage layer, the on-state current density is improved. At the same time, by setting a titanium oxide layer with a peak-shaped band structure as the gating layer, the nonlinearity of the device is improved. Thus, the self-gated resistive switching memory has both high nonlinearity and high on-state current density, solving the problem that high nonlinearity and high on-state current density cannot be achieved simultaneously in the prior art.

Resistive switching memory cells having filament-based switching mechanisms are provided. By way of example, resistive switching memory cells having resistive filaments constrained to a core of the cell are disclosed. In other examples, methods for fabricating resistive switching memory cells to constrain a conductive filament formed in the resistive switching memory cell to a central portion of core of the cell are disclosed.

The application relates to a convolution calculation circuit and a calculation method based on a resistive switching memory, wherein the calculation circuit comprises a memory calculation array, a digital-to-analog converter, an analog-to-digital converter, a word / bit line decoder and a controller; the memory calculation array is connected with the digital-to-analog converter in the bit line direction and connected with the analog-to-digital converter in the word line direction; the input of the digital-to-analog converter is a convolution input digital signal, and the output is connected to the memory calculation array; the input of the analog-to-digital converter is connected to the memory calculation array, and the output is a convolution output digital signal; the output of the word / bit line decoder is connected to the memory calculation array and used for selecting part or all of the memory calculation array; and the output of the controller is respectively connected to the memory calculation array, the digital-to-analog converter and the analog-to-digital converter and used for generating a control signal for realizing convolution calculation. The application can greatly improve the efficiency of convolution calculation.

The application discloses a multi-mode temperature correction scheme for resistive switching memory, which firstly performs mathematical modeling on the temperature characteristics of a resistive switching device, deduces a relationship between column current and actual current of a memory array, and then obtains a corresponding temperature correction formula to correct the reading current. The correction scheme is suitable for both single-device selection mode and multi-device selection mode, and can effectively improve the reliability of memory reading under high temperature conditions. The application further introduces a parallel structure to save the additional time cost caused by implementing the correction scheme. The application has important value in high-density storage and computing-in-memory applications.

This application relates to the field of semiconductor memory device technology, and discloses a 3D memory device and its fabrication process. The 3D memory device includes a substrate, a multilayer stacked structure, a contact lead-out structure, a via, a resistive switching functional layer, and a top electrode. The multilayer stacked structure includes multiple alternating layers of two-dimensional conductive material and multiple layers of insulating dielectric material arranged in a vertical direction. The two-dimensional conductive material layers serve as interlayer contact electrodes or memory cell electrodes. The via penetrates at least a portion of the multilayer stacked structure and exposes the edge regions of the two-dimensional conductive material layers. The resistive switching functional layer is disposed on the inner wall and / or inside the via and contacts the edge regions of the two-dimensional conductive material layers. The top electrode is electrically connected to the resistive switching functional layer. This structure utilizes the two-dimensional conductive material layers to reduce the vertical thickness of the interlayer electrodes and forms multiple resistive switching memory cells on the sidewalls of the vias, thereby increasing the storage density of the 3D memory device.

An embodiment of the present disclosure provides a resistive switching memory device including: a lower electrode; an amorphous metal oxide-based first active layer positioned on the lower electrode; an amorphous metal oxide-based second active layer positioned on the first active layer; and an upper electrode positioned on the second active layer, wherein the first active layer and the second active layer are made of the same substance but are different in electrical characteristic, thereby having a voluntary compliance current characteristic and a voluntary current rectification characteristic as a single device having a stable electrical characteristic, a method of manufacturing the resistive switching memory device, and an array including the resistive switching memory device.

This application provides a resistive switching memory cell, a resistive switching memory array, a resistive switching memory, and an operating method, relating to the field of memory technology. The resistive switching memory cell includes: multiple resistive switching devices forming multiple rows and columns; multiple gating devices, each gating device connected to a first electrode of each resistive switching device in a row, the gating devices being adapted to be connected to word lines and global source lines respectively, and electrically connecting or disconnecting the global source lines connected to the gating devices and the first electrodes of the resistive switching devices; and multiple isolation devices, each isolation device connected to a second electrode of each resistive switching device in a column, the isolation devices being adapted to be connected to control word lines and global bit lines respectively, and electrically connecting or disconnecting the global bit lines connected to the isolation devices and the second electrodes of the resistive switching devices.

The invention discloses an LDPC (Low Density Parity Check) codec based on a resistive random access memory array and a design method of the LDPC codec, and belongs to the crossing field of microelectronics and communication technologies. The codec comprises a resistive memory array, a peripheral control circuit and a signal processing module. The resistive random access memory array is configured by adopting 1T1R units, stores an LDPC (Low Density Parity Check) generation matrix / check matrix and executes multiplication and addition operation based on Ohm's law and Kirchhoff's law; the peripheral control circuit schedules the whole process of encoding and decoding; the signal processing module preprocesses an input signal and converts and verifies an array output current. The design method comprises a coding stage and a decoding stage, and an analog-to-digital conversion result adapts to binary Galois field operation through parity judgment. According to the invention, storage and calculation are integrated to break through the limitation of the von Noiemann architecture, power consumption and delay are reduced, 256-8448 bit code length dynamic adjustment is supported, and 5G-Advanced and 6G communication requirements are adapted.

This invention belongs to the field of microelectronic device technology and relates to a method for fabricating a ferroelectric heterojunction-based resistive switching memory, comprising: sequentially cleaning a Si wafer with anhydrous ethanol and hydrofluoric acid; placing the cleaned Si wafer into the vacuum chamber of an atomic layer deposition system, and cyclically depositing Al2O3 and HfO2 layers at a cycle ratio of Al2O3:HfO2 = 1:19, with a thickness of 10-20 nm; rapid thermal annealing in an oxygen-free environment; and covering the ferroelectric layer with a 0.01 mm thick layer. 2 Using a small-aperture mask, a MoS2 layer is deposited on the surface of an Al-doped HfO2 thin film that has already formed a ferroelectric phase via radio frequency magnetron sputtering. Without moving the mask, an Au electrode is then deposited on the MoS2 layer surface via DC magnetron sputtering. This invention enables the fabrication of a ferroelectric heterojunction resistive switching memory (RSM) for application in electronic devices. Based on HfO2-based ferroelectric materials, and leveraging their compatibility with CMOS processes, an n-Si substrate is used as the bottom electrode, resulting in more miniaturized devices. The MoS2 layer prepared by magnetron sputtering improves the device's on / off ratio and better meets the requirements of large-scale industrial production.

This invention belongs to the field of new materials technology, specifically relating to a benzotriazine diradical compound, its preparation method, and its applications in organic resistive switching memory (RSM), near-infrared detectors, and temperature-controlled films. The benzotriazine diradical organic magnetic compound prepared by this invention possesses excellent magnetic properties, reversible redox characteristics, and film-forming properties, making it suitable for use in organic RSM. Furthermore, it exhibits good thermal stability and excellent photothermal conversion capabilities, making it applicable to near-infrared detectors and temperature-controlled films. The prepared organic RSM demonstrates excellent storage performance; the prepared near-infrared detector exhibits ultra-high electro-response efficiency; and the prepared temperature-controlled film provides excellent temperature control and energy-saving effects.

This invention discloses a data processing method and an electronic device. The data processing method is used in an integrated circuit device, the integrated circuit device including a plurality of processing cores formed on a substrate of the integrated circuit device, a resistive memory array structure formed above the substrate of the integrated circuit device, access circuitry at least partially formed on the substrate of the integrated circuit device, and a plurality of memory controllers. The resistive memory array structure includes a plurality of resistive memory subarrays, each resistive memory subarray including a non-volatile two-terminal resistive switching memory cell. The access circuitry provides independent operative access to a corresponding resistive memory subarray of the plurality of resistive memory subarrays. Each memory controller is communicatively coupled to a corresponding processing core among the plurality of processing cores. The method includes: at least one memory controller receiving a memory instruction from a corresponding processing core; and in response to the memory instruction, the at least one memory controller executing the memory instruction on a corresponding resistive memory subarray. Based on monolithic integration, a close physical proximity is provided between the processing cores and main memory. This method promotes significant memory parallelism, reduces power consumption, and eliminates off-chip main memory access requests.

The invention provides a neuron circuit, and a calculation method, device and equipment based on the neuron circuit. The neuron circuit comprises a first structure which comprises a write transistor and a read transistor, and the write transistor and the read transistor form a 2T0C dynamic memory structure; the first end of the second structure is connected to the drain end of the reading transistor in the first structure, the second end of the second structure is used for being connected with an input signal, the second structure comprises a resistive random access memory and a threshold switch, and the resistive random access memory and the threshold switch are arranged in series between the first end of the second structure and the second end of the second structure. Therefore, the LIF type spiking neuron is simple in circuit implementation mode and easy to integrate, and the integration density can be improved.

The utility model provides a reading circuit of a resistive random access memory array and a memory. The reading circuit comprises a reading enable signal end, a pre-charging end, a reference array, N first delay chains, a comparator, a second delay chain and a latch comparator, wherein the reference array comprises a reference bit line, a reference source line, a reference word line, N-1 redundant units and one reference unit. According to the reading circuit disclosed by the utility model, the reading accuracy and the reading speed of the resistive random access memory array can be improved.

The present invention relates to a resistive switching memory device that can exhibit the characteristics of a non-volatile memory, due to an internal electric field of a diode-type thin film, even when an external electric field is removed, a driving method thereof, and a manufacturing method thereof. In particular, the resistive switching memory device may include: a first electrode; a resistive switching layer disposed on the first electrode; a diode-type thin film disposed on the resistive switching layer; a hydrogen supply layer disposed on the diode-type thin film; and a second electrode disposed on the hydrogen supply layer.

The invention belongs to the technical field of electronic part manufacturing, and particularly relates to a controllable crystal orientation SnS2 resistive random access memory and a preparation method thereof. The preparation method comprises the following steps: evaporating the Au bottom electrode with the thickness of 300 nm on the surface of the SiO2 / Si substrate by adopting a vacuum evaporation method; and preparing the SnS2 resistive random access layer by adopting a tube sealing vulcanization method: evaporating a layer of Ag metal film by adopting a hard mask technology and a vacuum thermal evaporation method to complete the preparation of the controllable crystal orientation SnS2 resistive random access memory. According to the method, the required energy is low, and the generation of byproducts in a reaction system is further inhibited due to a high-vacuum closed environment in the sealing pipe, so that the process stability is improved; the requirement on equipment is low, and the production cost is effectively reduced.

The invention provides a resistive random access memory and a manufacturing method thereof, and relates to the technical field of resistive random access memories. The method comprises the following steps: firstly, providing a substrate structure which comprises a vertical through hole and an interlayer dielectric layer above the through hole, then etching the substrate structure, and forming an inverted trapezoidal groove in a vertical through hole area; depositing a lower electrode based on the bottom of the inverted trapezoidal groove; sequentially depositing a resistive layer, a barrier layer and an oxygen exchange layer based on the surface of the lower electrode, and depositing a metal film; wherein the resistive layer, the barrier layer, the oxygen exchange layer and the metal films are all located in the groove, and the thickness of the metal film located at the bottom is larger than that of the metal film located on the side wall; performing high-temperature annealing to enable the metal film to form uniform metal nanoparticles; and finally depositing an upper electrode based on the surface of the oxygen exchange layer. The method has the advantages that accurate induction of the nucleation position of the conductive filament is achieved, and the precision and reliability of the device are improved.