44 results about "Resistive switching memory" patented technology

An electronic device can be validated at a circuit-level or device-level to provide supply chain verification of an integrated circuit (IC) product. A modern integrated circuit package can comprise multiple dies, systems and circuitry built from a variety of device-level structures. Device-level verification disclosed herein can confirm that a device-level (sub-) component of an integrated circuit product is sourced by a known or otherwise valid manufacturer. This serves to mitigate or avoid a hacking attempt involving illicit replacement of a component of an IC product by an intermediate handler of the IC product within a supply chain.

Leveraging stochastic physical characteristics of resistive switching devices to generate data having very low cross correlation among bits of that data is disclosed. Data generated from stochastic physical characteristics can also be referred to as physical unclonable feature—or function—(PUF) data. Additionally, error correction functions for PUF data generated from resistive switching memory cells are provided. The error correction functions facilitate additional redundancy and longevity of PUF data, among other benefits. Different embodiments include addressing arrangements to incorporate ECC parity bits among generated PUF data bits, even for differential PUF bits respectively defined by multiple memory cells in different portions of a resistive memory array.

The invention relates to a lead-free perovskite composite material, a preparation method thereof and application of the lead-free perovskite composite material in a resistive random access memory, and belongs to the technical field of preparation of the resistive random access memory. The lead-free perovskite composite material comprises a doped Sb element, the chemical formula of the lead-free perovskite composite material is Cs3Cu2I5: Sb, the molar ratio of Sb to Cu is (0.1-1): 1, the perovskite Cs3Cu2I5 is doped and modified through the element Sb, the content of iodine vacancy (VI) in cesium-iodine-copper perovskite can be reduced, the stability of conductive filaments can be improved, and therefore the resistance change performance of the resistive random access memory is improved.

The application provides a forming method of a conductive channel of a resistive random access memory (RRAM), comprising the following steps: firstly, connecting a RRAM element to a drain of a field effect transistor; and secondly, applying a forming voltage to a gate, the drain and a source of the field effect transistor until a conductive channel of the RRAM element is formed, wherein the forming voltage of the gate and the drain is a pulse voltage with opposite peak variation trends, the forming voltage of the source is constant, and the field effect transistor works in a saturation region. The application also provides a RRAM unit and a RRAM for implementing the forming method of the conductive channel of the RRAM, comprising a RRAM element and a field effect transistor, and the RRAM element is connected to the drain of the field effect transistor. By using the special pulse form of the gate voltage and the drain voltage and the superimposed current limiting resistor and other optimization means, the problems of uncontrollable current, excessive electric field, large device damage, low yield and MOS transistor failure in the prior art can be solved.

The invention discloses a high-yield storage and calculation integrated array and a preparation method thereof. The array comprises a substrate, a field effect transistor, a barrier layer and a resistive random access memory. The preparation method comprises the following steps: preparing a bottom electrode with a designed pattern on a substrate; depositing hafnium oxide on the surface of the bottom electrode by using an atomic layer as a dielectric layer; transferring a single-layer two-dimensional MoS2 material on the surface of the deposited hafnium oxide; the transferred two-dimensional MoS2 material is subjected to patterning preparation, and the MoS2 array preparation with multiple channels is completed; after barrier layer deposition is carried out on the MoS2 transistor array on the bottom layer, local etching is carried out, then resistive layer deposition and top electrode overlay are carried out, and the prepared 1T1R device has excellent electrical switching performance and remarkably improved resistance value uniformity.

The invention relates to an etching method of a semiconductor device and the semiconductor device, the semiconductor device has a laminated structure and comprises a lower electrode layer, a resistive layer, an upper electrode layer, an organic dielectric layer and a mask layer which are sequentially arranged from bottom to top; the etching method comprises the following steps: etching the organic dielectric layer until the upper electrode layer is exposed to form a patterned organic dielectric layer; etching the upper electrode layer and the resistive layer in sequence until the lower electrode layer is exposed; wherein in the process of etching the upper electrode layer and the resistive layer, at least part of the thickness of the patterned organic dielectric layer is not etched. Taking the semiconductor device as a resistive random access memory as an example, according to the etching method of the semiconductor device provided by the invention, in the process of etching the upper electrode layer and the resistive random access layer, at least part of the thickness of the patterned organic dielectric layer is not etched, so that the thickness of the upper electrode layer is protected to improve the performance and reliability of the resistive random access memory.

The application discloses a resistive switching memory structure and a manufacturing method thereof. The resistive switching memory structure comprises, from bottom to top, a bottom electrode, a resistive switching layer and a top electrode. The upper surface of the bottom electrode and the lower surface of the resistive switching layer are in Schottky contact, and the lower surface of the top electrode and the upper surface of the resistive switching layer are in Ohmic contact. The resistive switching layer is a single oxide film layer. The materials of the bottom electrode and the top electrode are the same metal nitride, and the atomic number ratio of metal elements to nitrogen elements in the top electrode is greater than that in the bottom electrode. The application can simplify the structure of the memory, reduce the process complexity and manufacturing cost.

The application discloses a kind of based on dithio metal complex doped polymer resistance change storage material and its preparation method and application, belong to data storage technical field.The storage material is with cadmium halide synthesis complex with bipyridine (Bpy) as ligand, and with polyvinylpyrrolidone (PVP) compound and obtained composite material.Based on the storage performance of pure cadmium complex device is poor, and the switch ratio is only 10 2.32 ~10 3.18 , with halogen from I to SCN, storage performance gradually improves.After being compounded with PVP, Cl base and SCN base device exhibits good ternary storage behavior (ternary yield is 65% and 55%), and the current switch ratio reaches 10 6.13 :10 3.80 :1, and good device stability is shown, and it is expected to be applied to construct high-performance halogen-based memory.Raw material is widely sourced, and the preparation method is simple, and the product has excellent performance, and has significant economic and social benefits.

This invention relates to a self-gated resistive switching memory (SRAM). By using niobium oxide, which is less prone to oxygen vacancy accumulation, as the storage layer, the on-state current density is improved. At the same time, by setting a titanium oxide layer with a peak-shaped band structure as the gating layer, the nonlinearity of the device is improved. Thus, the self-gated resistive switching memory has both high nonlinearity and high on-state current density, solving the problem that high nonlinearity and high on-state current density cannot be achieved simultaneously in the prior art.

The present invention discloses a thiopyridine-based cadmium complex-doped polymer resistive random access memory material, its preparation method, and application, belonging to the field of data storage technology. The storage material is a composite material prepared by synthesizing a cadmium thiocyanate complex using 2-thiopyridine (2Spy) and 4-thiopyridine (4Spy) as ligands and compounding it with polyvinylcarbazole (PVK). The FTO / Cd-4Spy@PVK / Ag device exhibits ternary RRAM storage behavior, with an ON2 / ON1 / OFF state current ratio of 10 6.10 :10 3.33 :1, V Set1 / V Set2 The ratios of the active layer traps to the binary RRAM type are 1.27 / 1.87, with a ternary yield of 61%. At 100°C, the storage behavior transforms into a binary RRAM type due to shallow traps in the active layer. The device exhibits excellent stability under 365 nm ultraviolet radiation, providing a new strategy for the fabrication of high-performance memories that are resistant to high temperatures and UV radiation.

The invention discloses an analog memristor based on an amorphous gallium oxide film and a preparation method and application thereof, and belongs to the field of nonvolatile memory devices. The method comprises the following steps: depositing a bottom conductive film on a highly flat insulating substrate as a bottom electrode of the analog memristor; gallium oxide films with different oxygen concentration gradients are deposited on the bottom electrode by adopting a physical vapor deposition method to serve as a resistive random access memory layer of the analog memristor; and depositing a top conductive thin film on the resistive random access memory layer by adopting a magnetron sputtering method to serve as a top electrode of the analog resistive random memory resistor, thereby obtaining the analog memory resistor based on the amorphous gallium oxide thin film. The preparation process is simple, the device structure is simple, the cost is low, and the resistance change simulation performance is good. The method shows continuous, stable and accurately controllable conductivity value change characteristics, can effectively simulate short-term and long-term plasticity of biological synapses, and has a good application prospect in the fields of neural network calculation and the like.

A resistive switching memory device comprises an active layer comprising an ionic conducting material. The active layer is disposed on a substrate. The device further comprises: a first electrode, a second electrode and optionally a first semiconductor layer. One of the first electrode, second electrode and first semiconductor layer, when present, is the substrate for the active layer and wherein the active layer and the first semiconductor layer, when present, contact each other at an interface. The device exhibits hysteretic I-V behaviour to permit switching of the electrical resistance of the device between different resistance states. The active layer is non-epitaxial with respect to the substrate.

Resistive switching memory cells having filament-based switching mechanisms are provided. By way of example, resistive switching memory cells having resistive filaments constrained to a core of the cell are disclosed. In other examples, methods for fabricating resistive switching memory cells to constrain a conductive filament formed in the resistive switching memory cell to a central portion of core of the cell are disclosed.

The invention relates to a vanadium pentoxide-doped resistive material as well as a construction method and a performance simulation method thereof, and belongs to the technical field of resistive materials. Aiming at the problems of strong randomness and unstable electrical properties of the existing vanadium pentoxide resistive material conductive filament, the invention provides the resistive material improved by atom substitution doping. The material adopts vanadium pentoxide with a 1 * 2 * 2 cell expansion structure, and aluminum, silicon or gallium atoms replace vanadium atoms to realize doping. According to the technical scheme, the method comprises the steps of constructing a doped crystal model, carrying out structure optimization based on a first principle, and carrying out electrical property simulation calculation. According to the invention, the electrical stability of the resistive random access material can be effectively improved, the forming uniformity and directivity of the conductive filament can be obviously improved, the oxygen vacancy migration efficiency can be improved, the thermal stability is good, and an important theoretical basis is provided for the design of a high-performance resistive random access memory.

The application relates to a convolution calculation circuit and a calculation method based on a resistive switching memory, wherein the calculation circuit comprises a memory calculation array, a digital-to-analog converter, an analog-to-digital converter, a word / bit line decoder and a controller; the memory calculation array is connected with the digital-to-analog converter in the bit line direction and connected with the analog-to-digital converter in the word line direction; the input of the digital-to-analog converter is a convolution input digital signal, and the output is connected to the memory calculation array; the input of the analog-to-digital converter is connected to the memory calculation array, and the output is a convolution output digital signal; the output of the word / bit line decoder is connected to the memory calculation array and used for selecting part or all of the memory calculation array; and the output of the controller is respectively connected to the memory calculation array, the digital-to-analog converter and the analog-to-digital converter and used for generating a control signal for realizing convolution calculation. The application can greatly improve the efficiency of convolution calculation.

A device is provided that includes a memory cell and a control circuit coupled to the memory cell. The memory cell includes a reversible resistive switching memory element coupled in series with a selection element having a threshold voltage. The control circuit is configured to use a first pulse having a first polarity for the first access to the memory cell and a second pulse having the first polarity for the second access to the memory cell and reading of the memory cell. The first pulse is configured to reduce the rate of threshold voltage drift of the selection element.

The application discloses a multi-mode temperature correction scheme for resistive switching memory, which firstly performs mathematical modeling on the temperature characteristics of a resistive switching device, deduces a relationship between column current and actual current of a memory array, and then obtains a corresponding temperature correction formula to correct the reading current. The correction scheme is suitable for both single-device selection mode and multi-device selection mode, and can effectively improve the reliability of memory reading under high temperature conditions. The application further introduces a parallel structure to save the additional time cost caused by implementing the correction scheme. The application has important value in high-density storage and computing-in-memory applications.

This application relates to the field of semiconductor memory device technology, and discloses a 3D memory device and its fabrication process. The 3D memory device includes a substrate, a multilayer stacked structure, a contact lead-out structure, a via, a resistive switching functional layer, and a top electrode. The multilayer stacked structure includes multiple alternating layers of two-dimensional conductive material and multiple layers of insulating dielectric material arranged in a vertical direction. The two-dimensional conductive material layers serve as interlayer contact electrodes or memory cell electrodes. The via penetrates at least a portion of the multilayer stacked structure and exposes the edge regions of the two-dimensional conductive material layers. The resistive switching functional layer is disposed on the inner wall and / or inside the via and contacts the edge regions of the two-dimensional conductive material layers. The top electrode is electrically connected to the resistive switching functional layer. This structure utilizes the two-dimensional conductive material layers to reduce the vertical thickness of the interlayer electrodes and forms multiple resistive switching memory cells on the sidewalls of the vias, thereby increasing the storage density of the 3D memory device.

A resistive random access memory (ReRAM) device is provided. The ReRAM device includes a first electrode including a first conductive layer sandwiching a second conductive layer, the second conductive layer being wider than the first conductive layer; a resistive switching element layer formed in contact with sidewalls of the first electrode, a first portion of the resistive switching element layer that is in contact with the sidewalls of the first conductive layer having a width that is greater than a second portion of the resistive switching element layer that is in contact with the sidewalls of the second conductive layer; and a second electrode that is in contact with the resistive switching element layer.

The invention discloses a resistive random access memory array testing device, which belongs to the technical field of semiconductor memory device testing and comprises an upper computer, a control logic module based on a ZYNQ platform, a multi-channel analog-to-digital / digital-to-analog conversion module and a resistive random access memory array to be tested. The upper computer is in communication connection with the control logic module based on the ZYNQ platform; the control logic module based on the ZYNQ platform is in communication connection with the multi-channel analog-to-digital / digital-to-analog conversion module; the output end of the multi-channel analog-to-digital / digital-to-analog conversion module is in communication connection with the resistive random access memory array to be tested; the input end of the multi-channel analog-to-digital / digital-to-analog conversion module is in communication connection with the resistive random access memory array to be tested. According to the invention, the precision of excitation signal generation and response signal measurement is ensured, high precision and high performance are realized, the high flexibility and configurability of the system are ensured, the test efficiency is greatly improved, and the cost is remarkably reduced.

An embodiment of the present disclosure provides a resistive switching memory device including: a lower electrode; an amorphous metal oxide-based first active layer positioned on the lower electrode; an amorphous metal oxide-based second active layer positioned on the first active layer; and an upper electrode positioned on the second active layer, wherein the first active layer and the second active layer are made of the same substance but are different in electrical characteristic, thereby having a voluntary compliance current characteristic and a voluntary current rectification characteristic as a single device having a stable electrical characteristic, a method of manufacturing the resistive switching memory device, and an array including the resistive switching memory device.

The invention discloses an analog resistive random access memory based on an amorphous MoS2 / TiO2 thin film laminated structure and a preparation method thereof, and belongs to the technical field of nonvolatile memories. The method comprises the following steps: depositing a first conductive film on an insulating substrate by adopting a magnetron sputtering method to serve as a bottom electrode of the analog memristor; sequentially depositing a TiO2 thin film and a MoS2 thin film on the bottom electrode by adopting a physical vapor deposition method to obtain an amorphous MoS2 / TiO2 heterojunction which is used as a resistive layer of the analog memristor; and depositing a second conductive thin film on the resistive layer by adopting a magnetron sputtering method to serve as a top electrode of the analog resistive random access memory to obtain the analog resistive random access memory based on the amorphous MoS2 / TiO2 thin film laminated structure. The analog resistive random access memory based on the amorphous MoS2 / TiO2 thin film laminated structure is simple in structure and low in cost, the MoS2 layer is used as a buffer layer, the influence caused by overshoot current is weakened through the non-crystal-boundary uniformity characteristic of amorphous TiO2, and the analog resistive random access memory with high stability and long-time data retention capacity is obtained.

The invention belongs to the technical field of resistive random access memories, and particularly relates to a PMC resistive random access memory unit model supporting historical state memory of a conductive wire. Comprising an anode and a cathode which are respectively used as a port an and a port ca; the conductive wire dynamic module is used for tracking the dynamic state of conductive wire growth SET or conductive wire dissolution RESET in real time by taking the conductive wire height h and the conductive wire radius r as core state variables and using an integrator; the state switching logic module is used for triggering the state switching of the SET or the RESET through a voltage threshold value based on the anode-cathode, and only switching the working state when the RESET is quitted without resetting the parameters of the conductive wire; and the resistance calculation and current output module is used for calculating the total resistance of the conductive wire based on the real-time state of the conductive wire and outputting safe current in combination with current-limiting protection. According to the invention, the physical process of partial growth-partial dissolution-secondary growth in a residual state of the conductive wire in a real device can be accurately reproduced.

A device is provided that includes a memory cell and a control circuit coupled to the memory cell. The memory cell includes a reversible resistive switching memory element coupled in series with a selection element having a threshold voltage. The control circuit is configured to use a first pulse having a first polarity for the first access to the memory cell, a second pulse having a second polarity opposite to the first polarity for the second access to the memory cell, and a third pulse having the first polarity for the third access to the memory cell. The third pulse is configured to reduce the threshold voltage drift rate of the selection element.

Provided is a memristor including an active electrode made of a first conductive material including an active metal; an inert electrode spaced from and facing toward the active electrode and made of a second conductive material having an ionization energy greater than the ionization energy of the first conductive material; and a resistive switching layer including: a porous insulating layer disposed between the active electrode and the inert electrode, wherein the porous insulating layer has through-channel holes defined therein extending from a bottom face to a top face thereof; and conductive filaments respectively formed inside the through-channel holes.

This application provides a resistive switching memory cell, a resistive switching memory array, a resistive switching memory, and an operating method, relating to the field of memory technology. The resistive switching memory cell includes: multiple resistive switching devices forming multiple rows and columns; multiple gating devices, each gating device connected to a first electrode of each resistive switching device in a row, the gating devices being adapted to be connected to word lines and global source lines respectively, and electrically connecting or disconnecting the global source lines connected to the gating devices and the first electrodes of the resistive switching devices; and multiple isolation devices, each isolation device connected to a second electrode of each resistive switching device in a column, the isolation devices being adapted to be connected to control word lines and global bit lines respectively, and electrically connecting or disconnecting the global bit lines connected to the isolation devices and the second electrodes of the resistive switching devices.

The application discloses a novel storage array structure and an operating method thereof, and belongs to the technical field of semiconductor integrated circuits. The novel storage array structure comprises storage units arranged in an array, each of the storage units is composed of two 1T1R structures connected in series, and the storage units share a plurality of P-type substrates. A deep N-well DNW is deposited below the P-type substrates, and all the storage units share one deep N-well DNW. The BJT triode formed by the N-well, the P-type substrate and the transistor drain is utilized to complete the RESET operation of the resistive switching memory unit. In the case of unchanged performance, the restriction on the minimum gate width of the transistor is relaxed, the area waste caused by the interval between the transistors is reduced, and thus the storage density of the resistive switching memory array is effectively improved. Only a small input signal needs to be applied, and high current output can be realized, so that the performance and reliability of the storage unit are significantly improved while the power consumption is reduced.

A device is provided that includes a memory cell and control circuitry coupled to the memory cell. The memory cell includes a reversible resistive switching memory element coupled in series with a select element having a threshold voltage. The control circuitry is configured to use a first pulse having a first polarity for the first access to the memory cell and a second pulse having a second polarity opposite the first polarity for the second access to and reading of the memory cell, the second pulse being adjacent to the first pulse. The first pulse is configured to reduce the rate of threshold voltage drift of the select element.

This invention discloses a resistive switching memory (RSM) and its fabrication method. The RSM includes: a substrate layer; a first electrode layer located on one side of the substrate layer; a resistive switching layer located on the side of the first electrode layer away from the substrate layer; and a second electrode layer located on the side of the resistive switching layer away from the first electrode layer. The lattice mismatch f1 between the first electrode layer and the resistive switching layer satisfies 0% ≤ f1 < 7%, and the lattice mismatch f2 between the second electrode layer and the resistive switching layer satisfies 0% ≤ f2 < 7%. By employing a first electrode and a second electrode with low lattice mismatch with the resistive switching layer, this invention can alleviate lattice mismatch stress, reduce interface stress accumulation, and improve the stability and reliability of the RSM.

An apparatus is provided that includes a memory cell and a control circuit coupled to the memory cell. The memory cell includes a reversible resistance-switching memory element coupled in series with a selector element, the selector element having a threshold voltage. The control circuit is configured to access the memory cell for a first time using a first pulse having a first polarity, access the memory cell for a second time using a second pulse having a second polarity opposite the first polarity, and access the memory cell for a third time using a third pulse having the first polarity. The third pulse is configured to reduce a threshold voltage drift rate of the selector element.