99 results about "Cross point" patented technology

The invention relates to the technical field of visual sensing modules, and discloses a sensing-storage-calculation integrated bionic visual sensing module in-storage calculation method and system.The method comprises the steps that photo-induced electrons excited by incident photons are directly injected into memristor oxygen vacancy conductive filaments through a shared electrode interface, and photocurrent driving signals are obtained; in a forward SET mode, driving memristor oxygen vacancy conductive filaments to form cross array conductivity distribution, and calculating row line driving voltage of a memristor cross array; applying the current to each cross point of cross array conductance distribution in a reverse RESET mode to obtain a flowing current of each cross point; and converging and summing the flowing current of each cross point at a column line node to obtain a column line output current, performing capacitor charging integration on the column line output current, and converting the column line output current into an analog domain convolution operation voltage, thereby avoiding intermediate multiple analog-to-digital and digital-to-analog conversion loss. And end-to-end low-delay and low-power-consumption processing from photon sensing to feature calculation is realized.

An apparatus may include a plurality of bit lines, a plurality of word lines, a plurality of source lines, and a plurality of cross-point devices connecting to the bit lines, the word lines, and the source lines. A first cross-point device of the plurality of cross-point devices is connected to a first bit line and a second bit line of the plurality of bit lines, a first word line of the plurality of word lines, and a first source line of the plurality of source lines. The first cross-point device may include a first RRAM device, an NMOS transistor connected to the first RRAM device, a PMOS transistor connected to the NMOS transistor, and a second RRAM device connected to the PMOS transistor. The NMOS transistor and the PMOS transistor are connected to the first source line and can be arranged in a side-by-side structure or a stacked-up structure.

Technology for reading memory cells in a cross-point memory array. Each memory cell may have a threshold switching selector in series with a programmable resistance memory element. The memory system has control circuitry adjacent to the cross-bar memory array that is used to generate and deliver currents to the cross-bar memory array. The memory system temporarily provides capacitive isolation of the selected memory cell from capacitance of the adjacent circuitry while the snapback current is present. The memory system provides a discharge path to a node between the control circuitry and the selected memory cell during a period in which the capacitive isolation is removed.

The utility model discloses a Mark point structure, which adopts at least two rectangular parts which are arranged in a crossed manner to form a bonding pad area, and compared with a traditional circular structure, the composite geometric shape of the bonding pad area can provide higher feature vector dimension in a machine vision system, the HOG feature value is improved by at least 30%, the algorithm identification accuracy is greatly improved, and the reliability of the structure is improved. Especially in a high-density BGA packaging area, the positioning precision of the center coordinates of the cross points can reach + / -0.01 mm, the identification degree of the Mark points on the PCB is greatly improved, and the problem that the Mark points are difficult to distinguish due to the low identification degree is effectively solved.

An apparatus may include a plurality of bit lines, a plurality of word lines, a plurality of source lines, and a plurality of cross-point devices connecting to the bit lines, the word lines, and the source lines. A first cross-point device of the plurality of cross-point devices is connected to a first bit line and a second bit line of the plurality of bit lines, a first word line of the plurality of word lines, and a first source line of the plurality of source lines. The first cross-point device may include a first RRAM device, an NMOS transistor connected to the first RRAM device, a PMOS transistor connected to the NMOS transistor, and a second RRAM device connected to the PMOS transistor. The NMOS transistor and the PMOS transistor are connected to the first source line and can be arranged in a side-by-side structure or a stacked-up structure.

The present disclosure provides for crossbar circuits with minimized write disturbance. A crossbar circuit may include a plurality of bit lines intersecting with a plurality of word lines, a plurality of select lines, a plurality of cross-point devices, and a ramp-rate adjustable DAC that comprises a control circuit and an operational amplifier. An input of the operational amplifier is connected to a capacitor. The control circuit may generate, based on a digital input, a control signal. To program a cross-point device of the crossbar circuit, the capacitor may be charged using a reference current. As the charging rate of the capacitor is limited by the reference current, and the charging duration is controlled by the control signal, thus the output of the operational amplifier corresponds to the digital input and may be applied to the cross-point device as a programming signal with limited slew-rate adjustable by the reference current.

Methods, systems, and devices for cross point array architecture for multiple decks are described. A memory array may include multiple decks, such as six or eight decks. The memory array may also include sockets for coupling access lines with associated decoders. The sockets may be included in sub-blocks of the array. A sub-block may be configured to include sockets for multiple access lines. A socket may intersect an access line in the middle of the access line, or at an end of the access line. Sub-blocks containing sockets for an access line may be separated by a period based on the access line.

Described herein are techniques to enable tracking circuits for crossbar circuits. One embodiment provides an apparatus including a crossbar array comprising: a plurality of bit lines intersecting with a plurality of word lines; and a plurality of cross-point devices, wherein each of the cross-point devices is connected to at least one of the word lines and at least one of the bit lines; a read-out circuit selectively connected to at least one of the bit lines, wherein the read-out circuit is to generate an output representative of the memristor conductance; a tracking circuit comprising a first replica cell that emulates at least one of the cross-point devices, wherein the tracking circuit is to produce a reference voltage; and a converter configured to convert the output of the read-out circuit into a digital output or a pulse-width-modulated signal, wherein the reference voltage is provided to the converter as an input.

An object of the present invention is to provide a neuromorphic system including a synaptic unit capable of causing a gradual change in resistance for analog information processing, and an operating method therefor. In order to achieve the above object, an aspect of the present invention may provide a neuromorphic system including an input signal unit for generating an input signal, a synapse unit including a plurality of synaptic units that receive a signal of the input signal unit and cause a current to flow according to a set weight, an output signal unit for generating an output signal by receiving a current generated from the synapse unit, and a controller unit for controlling the input signal unit, the synapse unit, and the output signal unit, in which the input signal unit includes a digital-to-analog converter (DAC), the synaptic units include a plurality of memory cells that are connected to each other and are each capable of selectively storing a logic state, the plurality of memory cells are arranged in a cross-point structure including an input electrode line and an output electrode line that cross each other to form one or more memory arrays, the output signal unit includes an analog-to-digital converter (ADC), and the controller unit generates an analog input signal through the DAC in the input signal unit, allows the generated analog input signal to be applied to each of the plurality of memory cells included in the synaptic unit so that a current flows, and generates a sum of currents flowing from the plurality of memory cells as the output signal through the ADC in the output signal unit.

A memory device including a three dimensional crosspoint memory array comprising a plurality of memory cells, wherein a memory cell of the plurality of memory cells comprises a conductive ferroelectric material and wherein the conductive ferroelectric material is in series with a dielectric material.

A capacitive touch screen display operates by: receiving a plurality of sensed signals indicating variations in mutual capacitance associated with a plurality of cross points formed by a plurality of electrodes; generating capacitance image data associated with the plurality of cross points that includes positive capacitance variation data corresponding to positive variations of the capacitance image data from a nominal value and negative capacitance variation data corresponding to negative variations of the capacitance image data from the nominal value; determining, based on the positive capacitance variation data and the negative capacitance variation data, an upper threshold and a lower threshold; generating compensated capacitance image data, based on the upper threshold and the lower threshold; and processing the compensated capacitance image data to determine a proximal condition of the touch screen display.

The invention discloses a cross-point array memory of a high-density three-dimensional ferroelectric capacitor, and belongs to the field of semiconductor memories. According to the invention, a horizontal BL / vertical WL cross-point array type three-dimensional ferroelectric memory architecture is designed by utilizing the three-dimensional stacking capability and the character / bit line symmetry characteristic of the cross-point array type three-dimensional ferroelectric memory, and compared with the traditional vertical BL / horizontal WL type three-dimensional memory architecture, the cross-point array type three-dimensional ferroelectric memory architecture has the advantages that the structure is simple; according to the invention, the influence of the limitation of signal margin on the extension of the three-dimensional ferroelectric memory in the vertical direction is eliminated, so that the three-dimensional cross-point array type ferroelectric memory is supported to realize the stacking of higher layers, and the bit density potential is ultrahigh.

A method of forming a memory device includes forming vertical stacks each including a respective first electrically conductive line and a respective selector rail over a substrate, such that the vertical stacks laterally extend along a first horizontal direction and are laterally spaced apart from each other along a second horizontal direction, forming magnetic tunnel junction material layers over the vertical stacks, and patterning the magnetic tunnel junction material layers and an upper portion of each of the selector rails to form a two-dimensional array of magnetic tunnel junctions and periodic notches at least in an upper portion of each of the selector rails.

Techniques for programming selector-only memory cells in a cross-point memory structure. The threshold switch memory element may include, but is not limited to, a bi-directional threshold switch (OTS). The memory system removes the Vth drift of the threshold switch memory element prior to programming. The Vth drift is removed by applying a first voltage and a second voltage having opposite polarities to all of the SOM cells to be programmed. Then, two programming voltages having two polarities are applied to program the cell into two states.

The utility model discloses large displacement friction damping device of multidirectional sliding, including first friction plate and second friction plate, second friction plate all sets up between two first friction plates, first friction plate all is cross -shaped, and the cross point position of cross -shaped is equipped with first friction piece, and four end portions all are first anchor nail connecting part for first anchor nail of wearing and setting, every second friction plate all is circular, and the position of the center of a circle coincides with the cross point position of all cross -shaped on a straight line, and the periphery annularly distributes second anchor nail connecting part for second anchor nail of wearing and setting, and every second anchor nail connecting part distance corresponding one side any first friction plate's two first anchor nail connecting part is equal, and the first anchor nail connecting part of a straight line arrangement is connected with same first anchor nail, and all second anchor nail connecting parts of a straight line arrangement all are connected with same second anchor nail. The utility model has the construction form of playing the damping effect in each direction of horizontal plane, can realize the effect of bridge in longitudinal and transverse isolation.

This invention discloses a switchless redundant fault-tolerant memristor cross array circuit for resolving bridging faults, comprising a main array, two redundant word lines, two redundant bit lines, and a controller. The main array consists of N word lines, M bit lines, and cross-point memristor cells. The redundant word lines cross with all bit lines, and the redundant bit lines cross with all word lines. The controller is directly connected to all word lines, redundant word lines, bit lines, and redundant bit lines. This circuit does not contain any physical switches for fault isolation, has a simple structure, low hardware overhead, and is easy to integrate.

The application relates to a seat comprising at least one padding. The padding comprises a first part of a clamping device as well as a three-dimensional network structure with irregularly bound meshes of one or more continuous linear structures. The continuous linear structures are welded together at crossing points and contain at least one thermoplastic elastomer. A first clamping device is formed from the material of the three-dimensional network structure. The application further relates to a method for producing the said seat.

The present disclosure provides memristor-based crossbar circuits. A crossbar circuit may include a crossbar array of cross-point devices connecting to intersecting word lines and bit lines. The crossbar circuit further includes a first readout circuit configured to generate an output voltage representing a sum of currents flowing through a bit line connecting to one or more of the cross-point devices. The crossbar circuit further includes a voltage replica circuit connected to the first readout circuit. The voltage replica circuit includes a replica cell configured to produce a reference cell current, an operational amplifier, and a second readout circuit connected to the replica cell and the operational amplifier. The output of the operational amplifier is connected to the first readout circuit to provide a bias voltage to the first readout circuit.

The utility model discloses a storage back-to-back goods shelf connecting device, the goods shelf is provided with a cross-shaped back net, the cross-shaped back net of the back-to-back goods shelf is overlapped, the storage back-to-back goods shelf comprises a base and an upper cover, the base and the upper cover are both cylindrical, the base is provided with a cross-shaped groove, and the cross-shaped groove is connected with the cross-shaped back net. A cross groove is formed in the base, the cross groove is used for containing one cross connecting point of the cross back net, the upper cover is in threaded connection with the base, a pressing column is arranged in the upper cover, and the pressing column can press the cross connecting point. The base and the upper cover are used for clamping the cross point of the back net of the goods shelf, so that the two goods shelves are stably connected together, the structure is cylindrical, and goods cannot be scratched.

The utility model relates to an in-plant coal conveying system cross point coal drop pipe on-line unblocking device which comprises a driving device, a rotating piece, an unblocking piece and a protection device, the driving device is fixedly connected with a coal drop pipe, the output end of the driving device is provided with the rotating piece, one end of the unblocking piece is fixedly connected with the rotating piece, the middle of the unblocking piece is wound on the rotating piece, and the other end of the unblocking piece is connected with the protection device. The protection device is arranged outside the driving device, the rotating piece and the blockage clearing piece, a guide opening is formed in one side of the protection device, a connector is formed in the coal falling pipe, the guide opening is formed in the connector, and the other end of the blockage clearing piece penetrates through the guide opening and extends into the coal falling pipe through the connector. By means of the structure, the problems that in an existing coal drop pipe, only check after blockage can be achieved, prevention cannot be achieved in advance, and the coal blockage phenomenon cannot be avoided are solved.

A magnetoresistive memory device includes a substrate, a bottom pinned spin-orbit torque (SOT) memory cell located over the substrate, and including a first magnetic tunnel junction and a common SOT layer located on the first magnetic tunnel junction, and a top pinned SOT memory cell located over the bottom pinned SOT memory cell, and including a second magnetic tunnel junction located on the common SOT layer. The common SOT layer is shared between the top pinned SOT memory cell and the bottom pinned SOT memory cell.

The invention discloses an ideal waveform recovery method and device, a terminal and a medium, and the method comprises the steps: obtaining a reference cross time point data sequence corresponding to an input serial signal, and enabling the reference cross time point data sequence to comprise at least two cross points; based on high and low level voltage values corresponding to input serial signals and the cross points, traversing the reference cross time point data sequence, and determining ideal waveform data corresponding to a target search value; and determining a target ideal waveform data sequence based on the ideal waveform data. According to the method, the ideal reference waveform is recovered according to the reference cross time point data sequence obtained by actually collecting the serial signals, the recovered ideal waveform is compared with the actually collected serial signal waveform, and the signal deterioration degree caused by links and the like can be visually obtained.

Technology for reading memory cells in a cross-point architecture. A memory system reads one memory cell in each module in parallel. The memory system performs two reads of the memory cells with a first read using a first reference signal and a second read using a second reference signal instead of the first reference signal. The second reference signal has a different magnitude from the first reference signal in order to compensate for differences between the modules.

The article to which this design pertains is used as a waist string when dressing in Japanese clothing. This design has a structure that is wide in the middle and narrows at both ends, with an opening at a position wider than both ends. When dressing, one end of the string is passed through this opening and wrapped around the waist, so that the string and the kimono are always tightly fastened together. Since there are no crossing points of the string, the kimono is less likely to slip off, which is more effective in preventing it from becoming loose. In addition, both ends of the string are thinner than the center, making it easier to tie and securely fasten.

The technical problem to be solved by the present application is to provide a transverse tunnel reconstruction method suitable for the elevation adjustment of a main tunnel, so as to solve the problem that the transverse tunnel form still needs to be used to play the drainage and transportation functions after the adjustment of the main tunnel line position, and to avoid the problem that the constructed transverse tunnel becomes a "waste project". The method comprises the following steps: adjusting the main tunnel line position in the form of avoiding crossing or crossing as short as possible according to the distribution characteristics of the adverse geology; determining the position of the intersection point of the transverse tunnel and the main tunnel after the adjustment of the line position, and then determining the elevation H of the transverse tunnel bottom at the intersection point; according to the elevation H of the transverse tunnel bottom at the intersection point of the main tunnel and the transverse tunnel after the adjustment, judging whether the elevation H is in the following range, and then selecting a reconstruction technical scheme: if H is in the limit lowering range H0-H1, a transverse tunnel lowering slope small slope reconstruction technical scheme is selected; if H is in the reasonable range H1-H2, a transverse tunnel slope adaptability reconstruction technical scheme is selected; and if H is in the limit lifting range H2-H3, a transverse tunnel spiral large slope reconstruction technical scheme is selected.

A magnetoresistive memory device includes a substrate, a bottom pinned spin-orbit torque (SOT) memory cell located over the substrate, and including a first magnetic tunnel junction and a common SOT layer located on the first magnetic tunnel junction, and a top pinned SOT memory cell located over the bottom pinned SOT memory cell, and including a second magnetic tunnel junction located on the common SOT layer. The common SOT layer is shared between the top pinned SOT memory cell and the bottom pinned SOT memory cell.

Various embodiments are directed to a method for adjusting cross point gains of a matrix mixer. For example, the method may receive one or more characteristics associated with an audio system comprising a plurality of microphone arrays each having one or more lobes, a plurality of loudspeakers, and a matrix mixer comprising one or more cross points each configured to connect each of the one or more lobes of the plurality of microphone arrays with each of the plurality of loudspeakers; calculate a potential gain and a desired achievable gain for each of the one or more cross points based on the one or more characteristics and a desired reinforcement level; and apply the desired achievable gain as a gain of the one or more cross points when the potential gain is greater than or equal to the desired achievable gain.

Column read enabled three dimensional cross-point memory is optimized to reduce delay time due to partition busy times incurred when reading from a same partition. A column read enabled memory media stores each entry of a logical column of an array of bits in contiguous different physical rows and different physical columns of the cross-point memory array than any other entry of the logical column. Subsets of the contiguous different physical rows are stored in different partitions to reduce the delay time incurred when performing column reads from a same partition to improve media management operation performance.

Various embodiments are directed to a method for adjusting cross point gains of a matrix mixer. For example, the method may receive one or more characteristics associated with an audio system comprising a plurality of microphone arrays each having one or more lobes, a plurality of loudspeakers, and a matrix mixer comprising one or more cross points each configured to connect each of the one or more lobes of the plurality of microphone arrays with each of the plurality of loudspeakers; calculate a potential gain and a desired achievable gain for each of the one or more cross points based on the one or more characteristics and a desired reinforcement level; and apply the desired achievable gain as a gain of the one or more cross points when the potential gain is greater than or equal to the desired achievable gain.

The application discloses a cross-lane line detection method, an electronic device and a storage medium. The method comprises the following steps: determining a feature point set of each lane line contained in a target image and a fitting straight line of each lane line; determining whether each lane line satisfies a preset detection condition based on the feature point set and the fitting straight line of each lane line; taking the lane line satisfying the preset detection condition as a target lane line; and obtaining a cross detection result of any two target lane lines based on the fitting straight line of the target lane line, wherein the cross detection result comprises a target intersection point between any two target lane lines and / or a cross type. In the foregoing manner, the application can accurately detect the intersection point and the cross type of any two lane lines.