1679 results about "Contact hole" patented technology

A display device includes a substrate including a first contact hole, an etching stopper disposed on a surface of the substrate and including the first contact hole, a metal pattern disposed on another surface opposite to the surface of the substrate and surrounding the first contact hole in a plan view, a first pad unit overlapping a part of the metal pattern and inserted into the first contact hole, a lead line disposed on the another surface of the substrate and electrically connected to another part of the metal pattern, a second pad unit disposed on the another surface of the substrate and electrically connected to the lead line, a protective film overlapping the another surface of the substrate and the lead line, and a protection part overlapping the first pad unit.

The invention discloses a manufacturing method of a semiconductor device, and belongs to the technical field of semiconductors. The manufacturing method comprises the following steps: providing a substrate, forming a dummy gate on the substrate, and forming a hard mask layer on the dummy gate; forming side wall structures on two sides of the dummy gate; forming a contact hole etching stop layer on the substrate, the side wall structure and the pseudo gate, wherein the material of the contact hole etching stop layer is the same as that of the hard mask layer; forming an interlayer dielectric layer on the contact hole etching stop layer, and planarizing the interlayer dielectric layer to the residual preset thickness of the hard mask layer; oxidizing the hard mask layer, a part of the contact hole etching stop layer and a part of the side wall structure to form a surface oxide layer; synchronously removing the surface oxide layer and a part of the interlayer dielectric layer, wherein the surface of the dummy gate is flush with the surfaces of the interlayer dielectric layers on the two sides; and removing the dummy gate to form a metal gate. According to the manufacturing method of the semiconductor device provided by the invention, the height of the formed metal gate can be ensured, the manufacturing process is simple, and the controllability is high.

Various embodiments of improved process flows and methods are provided herein for etching high aspect ratio (HAR) features in carbon-containing hard mask layers. In the disclosed embodiments, the improved process flows and methods combine sidewall passivation and mask de-clogging steps in a single plasma process step to improve throughput when etching HAR features (such as vias, contact holes, trenches, etc.) within a carbon-containing hard mask layer. In doing so, the improved process flows and methods disclosed herein protect the sidewall surfaces of the carbon-containing hard mask layer and prevent bowing during the HAR etch process, while also reducing processing time and improving throughput.

To provide a semiconductor device having a transistor part and a diode part, in which a reverse recovery loss is reduced.SOLUTION: A semiconductor device includes: an interlayer insulating film 38 provided over a semiconductor substrate 10; an emitter electrode 52 being a front surface electrode provided over the semiconductor substrate; contact parts where the front surface electrode and mesa parts 61 to 64 are connected in contact holes 54 of the interlayer insulating film; and a lifetime adjustment region 206 provided on a front surface side of the semiconductor substrate. The contact parts have a first contact part 77 provided in a transistor part, and a second contact part 87 provided in a diode part. The first contact part is disposed over the second contact part.SELECTED DRAWING: Figure 3A

A display device includes first to fourth pixels, wherein each of the first to fourth pixels includes first to third sub-pixels, a first data connection pattern electrically connected to a first data line by a first contact hole and electrically connected to the second sub-pixel of the second pixel, and a second data connection pattern electrically connected to a second data line by a second contact hole and electrically connected to the second sub-pixel of the fourth pixel, wherein, in a plan view, the first contact hole is disposed between the emission area of the third sub-pixel of the first pixel and the emission area of the third sub-pixel of the second pixel, and in a plan view, the first contact hole and the second contact hole are disposed in a row in the second direction.

A display device comprises a first substrate including a first contact hole, fan-out lines included in a first metal layer on the first substrate, first and second pad parts exposed to a lower portion of the first substrate, a display layer disposed on the fan-out lines, and a flexible film disposed below the first substrate, inserted into the first contact hole, and electrically connected to the first and second pad parts. The fan-out lines comprise first fan-out lines extending from the first contact hole in a first direction, and second fan-out lines extending from the first contact hole in a direction opposite to the first direction. The first fan-out lines and the first pad parts are integral with each other. The second fan-out lines and the second pad parts are integral with each other.

The utility model discloses a drain-shared double-SGT MOSFET device, and relates to the technical field of semiconductors, the drain-shared double-SGT MOSFET device comprises a substrate and an epitaxial layer, the top surface of the epitaxial layer is provided with a plurality of grooves side by side, the bottom side walls and the inner bottoms of the grooves are provided with shield gate oxide layers, and the shield gate oxide layers on the bottom side walls of the grooves are filled with first polycrystalline silicon; a trench middle shielding oxide layer is deposited at the top end of the first polycrystalline silicon, a gate oxide layer is arranged at the top end of the trench middle shielding oxide layer and located on the side wall of the trench, and the gate oxide layer is filled with second polycrystalline silicon; a source region and a base region are formed between every two adjacent grooves from top to bottom, communicated first top layer contact holes are formed in the source regions and the base regions, the first top layer contact holes are filled with conductive materials to form MOS structures, and connecting layers are formed on the surfaces of the MOS structures; and a groove middle insulating column is vertically arranged in the middle in the groove. According to the utility model, the on-resistance is greatly reduced.

Disclosed is a thin film transistor substrate comprising a substrate; a first thin film transistor on the substrate, the first thin film transistor including a first active layer and a first gate electrode; a second thin film transistor on the substrate, the second thin film transistor including a second active layer and a second gate electrode above the first active layer and the first gate electrode; a first insulating layer between the first gate electrode and the second active layer; and; and a first connection electrode connecting together the first active layer and the second active layer, the first connection electrode extending through a first contact hole in the first insulating layer and is in contact with each of the first active layer and the second active layer and a display apparatus including the same.

A display apparatus includes a base substrate including a display area and a peripheral area, a conductive layer formed on the base substrate in an entirety of the peripheral area and the display area, a buffer layer on the conductive layer, a thin film transistor on the buffer layer in the display area, an electrode in a contact hole that is formed through the buffer layer to expose a side surface of the conductive layer in the peripheral area, the electrode making contact the conductive layer, an insulating pattern in the contact hole on the electrode, and a wiring on the insulating pattern and electrically connected to the electrode.

A display device includes: a display panel comprising a plurality of light emitting areas; and an input sensing panel including: a first sensing insulating layer on the display panel; a second sensing insulating layer on the first sensing insulating layer and having a first opening and a contact hole; an insulating pattern; and a plurality of conductive patterns including a first conductive layer and a second conductive layer, the first conductive layer includes: a first-first conductive portion in the first opening; and a first-second conductive portion exposed through the contact hole, the second conductive layer includes: a second-first conductive portion electrically connected to the first-first conductive portion; a second-second conductive portion electrically connected to the first-second conductive portion; and a second-third conductive portion spaced apart from the first conductive layer in a plan view, and the insulating pattern is on the second-first conductive portion and in the first opening.

The invention provides a micro light emitting diode chip, comprising a micro mesa array comprising a plurality of micro mesas; the light emitting diode is characterized in that each micro-mesa comprises a first type semiconductor layer, a light emitting layer and a second type semiconductor layer which are sequentially stacked from bottom to top; the first type is different from the second type; the bottom metal layer is located at the bottom of the micro mesa; the bottom dielectric layer is located at the bottom of the bottom metal layer; the bottom dielectric layer is provided with a groove; the first bottom contact hole is located in the bottom dielectric layer and located at the bottom of the bottom metal layer, and the first bottom contact hole is in contact with the bottom metal layer; the side wall dielectric layer is positioned on the side wall of the micro mesa and the side wall of the bottom metal layer; the top conductive layer continuously covers the top surfaces of the micro mesas, the surfaces of the side wall cut-off layers and the areas between the adjacent micro mesas; and the second bottom contact structure is positioned in the groove, is positioned in the bottom dielectric layer between the adjacent micro mesas, and is not in contact with the bottom metal layer.

A semiconductor device, including: a semiconductor substrate having a main surface; an interlayer insulating film provided on the main surface of the semiconductor substrate; a contact hole penetrating through the interlayer insulating film to reach the semiconductor substrate; a plug electrode embedded in the contact hole; a first barrier metal provided on the interlayer insulating film, the first barrier metal being apart from the plug electrode; and a front electrode provided on the first barrier metal and the plug electrode.

The invention discloses a high-voltage fast recovery diode with a positive temperature characteristic and a manufacturing method of the high-voltage fast recovery diode. A central region of the device is a P-type doped active region which is used as an anode when the device works in the forward direction; p-type doped field limiting rings are arranged on the two sides of the active region and serve as voltage dividing rings of the device, and the field limiting rings and the active region are doped independently; an N-type doped cut-off ring is arranged on the outermost periphery of the device and provides an electric field cut-off effect; a metal field plate is arranged above each field limiting ring to improve the distribution of a peripheral electric field and improve the stability of the device; except for the position of the contact hole, CVD, silicon nitride and polyimide in the vertical direction of the device are used as passivation layers of the device to isolate the influence of external moisture, charges and the like, so that the reliability of the device is improved; metal is directly deposited above the active region to serve as an anode of the device; and a layer of metal is evaporated on the back of the device after being thinned to serve as a device cathode. A platinum diffusion and electron irradiation process is used as a minority carrier lifetime control technology to adjust the temperature characteristic of the device.

A display device includes a substrate, a first metal layer on the substrate, a first barrier insulating layer on the first metal layer, an etching control layer on the first barrier insulating layer, a first contact hole passing through the substrate, the first barrier insulating layer, and the etching control layer, a second barrier insulating layer on the etching control layer and including a second contact hole, a fan-out line on the second barrier insulating layer and included in a second metal layer, a pad part inserted into the second contact hole and included in the second metal layer, the pad part integral with the fan-out line, a display layer on the fan-out line, and a flexible film under the substrate and inserted into the first contact hole to be electrically connected to the pad part. The first metal layer includes an etching mark adjacent to the first contact hole.

The invention relates to a semiconductor device with a temperature sensor and a preparation method thereof, and the key points of the technical scheme are that the method comprises the steps: constructing a super-junction charge balance region on the surface of a substrate, and forming a body region at the top of the super-junction charge balance region; generating a first shallow trench and a second shallow trench on the body region; sequentially depositing an oxidation dielectric layer and first polycrystalline silicon in each of the first shallow trench and the second shallow trench; etching the first polycrystalline silicon in the second shallow trench, and depositing second polycrystalline silicon above the first polycrystalline silicon in the second shallow trench; depositing a dielectric layer on the surface of the body region, and etching in the dielectric layer to form a contact hole; the contact hole is communicated with the first polycrystalline silicon and the second polycrystalline silicon; the temperature detection diode structure is integrated in the epitaxial material of the device, and the problem that the internal thermal characteristics of the device cannot be fed back in time is solved by improving the manufacturing process under the condition that the characteristics of the device are not influenced by utilizing the linear relation between the forward conduction voltage and the temperature of the diode.

The invention relates to a fast recovery diode and a manufacturing method thereof. The fast recovery diode comprises a substrate; the first epitaxial layer is located on one side of the substrate, at least one floating region is formed in the first epitaxial layer, the doping type of the first epitaxial layer is the same as that of the substrate, and the doping type of the floating region is different from that of the first epitaxial layer; the active layer is located on the side, away from the substrate, of the first epitaxial layer, the active layer comprises an anode region and a terminal region, the anode region and the terminal region are both in contact with the first epitaxial layer, the terminal region is arranged around the anode region, and the doping types of the anode region and the floating region are the same; the isolation layer is located on the side, away from the substrate, of the active layer, the isolation layer comprises a contact hole, and the contact hole exposes part of the anode region; the first metal layer is located on the side, away from the substrate, of the isolation layer, and the first metal layer makes contact with the anode region through the contact hole; therefore, the reverse recovery speed of the fast recovery diode with the positive temperature coefficient is improved.

The invention provides an OPC (Optical Proximity Correction) method for regulating and controlling the resistance of a high-resistance sheet, which comprises the following steps of: 1, delimiting a layout area where a high-resistance layer and a silicide barrier layer are located in an original layout, and determining the resistance value of the high-resistance sheet according to the layout area; and 2, according to the resistance value of the sheet resistor of the high-resistance layer determined in the step 1, reducing the width of the overlapped part of the high-resistance layer and the silicide barrier layer. The resistance value of the high-resistance layer sheet resistor is regulated and controlled by changing the shape of the high-resistance layer in the layout, the position of a contact hole does not need to be adjusted, and more flexible layout design elasticity under different manufacturing processes is provided.

The invention discloses a contact hole forming method in a BCD and SGT integration process, and the method comprises the steps: S1, providing a substrate which comprises an SGT device region and a BCD device region; s2, performing an ion implantation process on the surface layer of the substrate to form source regions and a body lead-out region on the surface layer of the substrate in the SGT device region, and forming a substrate lead-out doped region, a body lead-out doped region, a source doped region and a drain doped region on the surface layer of the substrate in the BCD region, the source regions being located at two sides of the body lead-out region, the body lead-out doped region being located at two sides of the body lead-out region, the source doped region being located at two sides of the body lead-out region, and the drain doped region being located at two sides of the body lead-out region; the source region and the body lead-out region form a common connection structure; s3, forming a polycrystalline silicon gate structure on the surface of the substrate in the BCD device area; s4, forming a dielectric layer on the surface of the substrate, wherein the dielectric layer covers the polycrystalline silicon gate structure; and S5, simultaneously forming a contact hole of the SGT device and a contact hole of the BCD device in the dielectric layer. According to the scheme, the forming efficiency of the contact hole in the BCD and SGT integrated device can be improved.

According to the field effect transistor, a first JFET is formed in a first epitaxial layer, and a second MOSFET is formed in a second epitaxial layer. The forbidden band width of the material of the first epitaxial layer is greater than that of the material of the second epitaxial layer; the second epitaxial layer is formed on the top surface of the first epitaxial layer, and the contact surface of the first epitaxial layer and the second epitaxial layer is heterojunction; a first source region of the first JFET and a second drain region of the second MOSFET are connected through a first floating metal contact hole penetrating through the heterojunction. A first gate region of the first JFET is connected to a source consisting of a front metal layer through a deep contact hole penetrating through the heterojunction; the second source region is connected with the source electrode. The back face of the first drain region is connected to a drain electrode composed of a back face metal layer. The invention further discloses a manufacturing method of the field effect transistor. The invention has the advantages of a wide bandgap semiconductor material device, and can overcome the problems of high channel carrier mobility, high driving voltage and poor reliability of the gate dielectric layer of the wide bandgap semiconductor material device.

Provided are a display apparatus including: a substrate; a pixel circuit disposed over the substrate and comprising a thin film transistor and a storage capacitor; an insulating layer covering the pixel circuit; a bridge electrode disposed over the insulating layer and electrically connected to the pixel circuit through a contact hole formed in the insulating layer; a pixel electrode disposed over the insulating layer and electrically connected to the bridge electrode; a pixel definition layer disposed over the pixel electrode and including an opening overlapping a portion of the pixel electrode; an opposite electrode over the pixel electrode; and an emission layer disposed between the pixel electrode and the opposite electrode, wherein the pixel electrode does not overlap the contact hole of the insulating layer in a plan view.

A display device includes a base layer; a pixel circuit layer disposed on the base layer, the pixel circuit layer including a first transistor; and an insulating layer overlapping the first transistor; a first electrode disposed on the pixel circuit layer, the first electrode electrically connected to the first transistor via a contact hole of the insulating layer; a cover layer disposed on the first electrode, the cover layer overlapping at least a portion of the first electrode; a light emitting element including a first end and a second end electrically connected to the first electrode; a second electrode disposed on the light emitting element, the second electrode electrically connected to the second end of the light emitting element; and a third electrode disposed on the cover layer, the third electrode electrically contacting at least a portion of the first electrode.

The invention discloses a mosquito killer finished product detection device. The mosquito killer finished product detection device comprises a base and a rotating disc. Eleven stations of feeding, resistance detection, voltage resistance detection, riveting, rivet leakage detection, forward rotation detection, traceability code, reverse rotation detection, marking, light detection and discharging are sequentially arranged on the rotating disc in the circumferential direction, a mounting groove for containing a mosquito killer to be detected is formed in the disc, and a notch groove is formed in the position, corresponding to a switch touch button, of the groove. The base is provided with touch button test seats at the resistor, forward rotation, reverse rotation and light detection stations, and the seats are provided with touch button test motors and touch button test benches. An air blowing cavity is formed between the through hole and the abutting hole, a suspension ball and an air nozzle are arranged in the cavity, and a matching groove in the end of the output shaft of the motor corresponds to the abutting rod in position. The device is reasonable in structural layout, efficient and convenient in detection, high in automation degree and good in detection reliability.

A semiconductor device includes a cell portion and a peripheral portion. The cell portion has a semiconductor element including a drift layer, a first impurity region, a second impurity region, trench-gate structures, a high-concentration layer, an interlayer insulating film, a first electrode and a second electrode. The interlayer insulating film is located on the trench-gate structures, the first impurity region and the second impurity region, and has a first contact hole communicating with the first impurity region and the second impurity region. The peripheral portion has a section facing the cell portion in one direction, and the interlayer insulating film further has a second contact hole at the section of the peripheral portion. The second contact hole exposes the first impurity region, and the first electrode is electrically connected to the first impurity region through the second contact hole in the peripheral portion.

The invention relates to a manufacturing method of a semiconductor device, and the method comprises the steps: providing a substrate, forming at least two gate structures which are mutually spaced on the substrate, and forming a groove between the two adjacent gate structures; forming a contact hole etching stop layer on the substrate and the gate structure, wherein a part, covering the opening of the groove, in the contact hole etching stop layer is provided with an overhang part; performing an ion implantation process on the overhanging part, and implanting doping ions into the overhanging part; plasma processing is carried out on the contact hole etching stop layer, the part, far away from the substrate, in the contact hole etching stop layer is converted into a sacrificial oxide layer, and the part, far away from the substrate, in the contact hole etching stop layer comprises at least one part of overhanging part; and removing the sacrificial oxide layer to enlarge the width of the opening. According to the invention, the negative influence of the overhang phenomenon generated in the contact hole etching stop layer on the subsequent process is reduced or eliminated, and the risk of generating a cavity when the trench is filled with the interlayer dielectric layer is avoided.

A MOSFET includes a gate electrode and an etching stopper layer formed on a field insulating film of a gate pad region, and an interlayer insulating film formed on the gate electrode and the etching stopper layer. The etching stopper layer is made from a substance having a selectivity of 5.0 or more with respect to etching of the interlayer insulating film and the field insulating film, and is provided at a position farthest from the well contact hole of the under-gate well contact region at least in the gate pad region.

The embodiments of the disclosure provide a semiconductor structure and a method for forming the same. The method includes that: a substrate is provided; bit line contact holes arranged at intervals, a bit line contact in partial contact with the bit line contact hole and a bit line structure are formed on the substrate; a first insulating layer is formed on surfaces of the substrate, the bit line contact hole, the bit line contact and the bit line structure, the first insulating layer not completely filling the bit line contact holes; a second insulating layer is formed on a surface of the first insulating layer located on the surface of the bit line contact and part of the surface of the bit line structure; and a third insulating layer covering the first insulating layer and the second insulating layer is formed.

The invention provides a micro light-emitting diode chip, which is provided with a micro mesa array area and comprises a plurality of micro mesas, each micro mesa comprises a first type semiconductor layer, a light-emitting layer and a second type semiconductor layer which are sequentially stacked from bottom to top; the first type is different from the second type; the first metal layer is located at the bottom of the micro mesa; the second metal layer is located at the bottom of the first metal layer; the third metal layer is located at the bottom of the second metal layer; the bottom dielectric layer is located at the bottom of the whole micro-mesa array area and the bottom of the third metal layer; and the metal contact hole is located in the bottom dielectric layer, located at the bottom of the third metal layer and in contact connection with the bottom of the third metal layer.

The invention provides an optical proximity correction method, electronic equipment and a storage medium, and the method comprises the steps: carrying out the initial correction processing of an initial mask layout, obtaining a corrected mask layout, determining a first mask pattern and a second mask pattern, which violate a standard mask rule, in the corrected mask patterns, and determining the rollback distance of the first mask pattern and the second mask pattern according to the violation information, the first contact hole, the first through hole, the second contact hole and the second through hole and the violation information between the first mask pattern and the second mask pattern, and moving the first mask pattern and the second mask pattern based on the rollback distance to obtain a target mask layout. By considering the distance between the mask pattern through hole and the contact hole, the coverage rate and the electrical property of the metal interconnection layer to the contact hole and the through hole are ensured.

A manufacturing method of a semiconductor device includes a step of preparing a semiconductor substrate having a first main surface and a second main surface, a step of forming a recess in the first main surface and embedding an insulating film in the recess, a step of forming a polysilicon film on the insulating film, a step of forming an interlayer insulating film on the first main surface so as to cover the insulating film and the polysilicon film, and a step of forming a first contact hole and a second contact hole. The semiconductor substrate has a first impurity diffusion region formed in the first main surface, and a second impurity diffusion region in contact with a portion of the first impurity diffusion region, the portion being closer to the second main surface.

The invention discloses a method for optimizing the contour of a contact hole and a semiconductor structure, and belongs to the technical field of semiconductor manufacturing. The method comprises the following steps: introducing a silicon-containing precursor gas and a carbon-containing precursor gas on a substrate, and depositing to form a first amorphous silicon layer serving as an etching deceleration layer; and depositing on the first amorphous silicon layer to form a second amorphous silicon layer by stopping introducing the carbon-containing precursor gas and continuing introducing the silicon-containing precursor gas. Through in-situ deposition of the laminated structure of the carbon-containing layer and the pure amorphous silicon layer, the intrinsic etching selection ratio is constructed by using the property difference of materials, and an additional ion implantation step is not needed. According to the method, the technological process is simplified, the cost and the thermal budget are reduced, the etching bias load effect can be effectively improved, the contour of the contact hole is optimized, the contact hole is closer to be vertical and is uniform up and down, and therefore the yield and the reliability of the device are improved.