8849 results about "Contact hole" patented technology

A method for forming a contact hole of a semiconductor device according to the present invention forms a contact hole which is defined as a new contact hole region (a second contact hole region), between spacers as well as a contact hole defined within the spacer (a first contact hole region) by a spacer patterning technology (SPT). The present invention with this method can help to form a fine contact hole as a double patterning is used, even with one mask.

A transparent thin film transistor (TFT) and its method of manufacture includes: a substrate, a transparent semiconductor layer formed by coating the substrate with an oxide, a nitride, or a carbide to pattern the material, a gate insulating layer formed on the transparent semiconductor layer, a gate electrode formed on the gate insulating layer to correspond to the transparent semiconductor layer, an interlayer insulating layer formed on the gate electrode, and source and drain electrodes electrically connected to the transparent semiconductor layer through contact holes formed in the interlayer insulating layer and the gate insulating layer.

A method of fabricating a landing plug in a semiconductor memory device, which in one embodiment includes forming a landing plug contact hole on a semiconductor substrate having an impurity region to expose the impurity region; forming a landing plug by filling the landing plug contact hole with a polysilicon layer, wherein the landing plug is divided into a first region, a second region, a third region, and a fourth region from a lower portion of the landing plug, and the first region is doped with a first doping concentration that is relatively lowest, the second region is doped with a second doping concentration that is higher than the first doping concentration, the third region is doped with a third doping concentration that is higher than the second doping concentration and the fourth region is not doped; and annealing the resulting product formed with the landing plug.

A method for fabricating a semiconductor device including surface cleaning includes forming a gate stack on a semiconductor substrate, cleaning contaminants present on the surface of the semiconductor substrate exposed through a contact hole using an etchant including a fluorine (F)-containing species dispersed in an alcohol, and filling a contact hole with a conductive layer to form a connection contact. The etchant preferably has a low selectivity of 1 or less.

A phase changeable memory cell is provided. The phase changeable memory cell includes a lower interlayer dielectric layer formed on a semiconductor substrate and a lower conductive plug passing through the lower interlayer dielectric layer. The lower conductive plug is in contact with a phase change material pattern disposed on the lower interlayer dielectric layer. The phase change material pattern and the lower interlayer dielectric layer are covered with an upper interlayer dielectric layer. The phase change material pattern is in direct contact with a conductive layer pattern, which is disposed in a plate line contact hole passing through the upper interlayer dielectric layer. Methods of fabricating the phase changeable memory cell is also provided.

A example method of forming of a contact hole by removing residue and oxide spacer beside a nitride spacer after a CF containing etch. We provide a gate structure with nitride spacers on the sidewalls of the gate. We provide a dielectric layer (oxide) over the substrate and gate structure. We form a contact photoresist pattern over the oxide dielectric layer. We etch the oxide dielectric layer using fluorocarbons (CxFy) to form contact openings and residual spacer. The photoresist is striped. Preferably, a NF₃ and N₂ and H₂ plasma treatment is performed to deposit a byproducts layer over the residual spacer. The byproducts layer and residual spacer are removed preferably using one of the following processes: (1) heat (2) DI rinse or (3) IR or UV radiation.

Provided is a method and system for developing a lithographic mask layout. The lithographic mask layout is adapted for configuring an array of micro-mirrors in a maskless lithography system. The method includes generating an ideal mask layout representative of image characteristics associated with a desired image. Next, an equivalent mask is produced in accordance with an average intensity of the ideal mask layout.

A metal contact structure of a semiconductor device and a method for forming the same are provided. The diameter of the upper portion of a contact hole that exposes a region of a lower conductive layer is formed to be larger than the diameter of the lower portion of the contact hole. The metal contact structure is formed without a void or a key hole. This is accomplished by forming at least two metal layers to fill the contact hole by performing a first deposition, an etch back, and a second deposition. The metal layer which fills the contact hole is etched back using a barrier metal layer formed on the entire surface of the contact hole as an etching stop layer. Thus, a void or key hole is not generated by making the upper portion of the contact hole to be wider than the lower portion of the contact hole and by depositing the metal which fills the contact hole through the processes of firstly depositing the metal, etching back the metal, and secondly depositing the metal.

A tungsten nucleation film is formed on a surface of a semiconductor substrate by alternatively providing to that surface, reducing gases and tungsten-containing gases. Each cycle of the method provides for one or more monolayers of the tungsten film. The film is conformal and has improved step coverage, even for a high aspect ratio contact hole.

The object is to pattern extremely fine integrated circuits by forming fine contact holes. The dry etching method is employed to form contact holes to pattern a wiring (114), using a mask made of metallic film (112) and an organic material as an inter-layer insulating film (111) for covering switching elements and each of the wirings.

A thin film transistor of the present invention includes a semiconductor thin film (8); a gate insulating film (7) formed on one surface of the semiconductor thin film (8); a gate electrode (6) formed to be opposite to the semiconductor thin film (8) through the gate insulating film (7); a source electrode (15) and a drain electrode (16) electrically connected to the semiconductor thin film (8); a source region; a drain region; and a channel region. The thin film transistor further includes an insulating film (9) formed on a peripheral portion corresponding to at least the source region and the drain region of the semiconductor thin film (8), and having a contact hole (10, 11) through which at least a part of each of the source region and the drain region is exposed wherein the source electrode (15) and the drain electrode (16) are connected to the semiconductor thin film (8) through the contact hole (10, 11).

A method for fabricating a semiconductor device includes forming a buried gate electrode in a semiconductor substrate. An insulating layer is formed over the buried gate electrode and is etched to form a contact hole exposing the semiconductor substrate. A sacrificial spacer is formed on sidewalls of the insulating layer defining the contact hole. A polysilicon layer pattern is formed in the contact hole. The sacrificial spacer is removed to form an air gap around the polysilicon layer pattern. A thermal process is performed to remove a seam existing in the polysilicon layer pattern.

The present invention discloses A transflective liquid crystal display device including a first substrate having a color filter; a second substrate having: a)a gate electrode formed on the second substrate; b) a first insulating layer formed on the exposed surface of the second substrate while covering the gate electrode; c) a semiconductor layer formed on the first insulating layer and over the gate electrode; d)a source electrode overlapping one end portion of the semiconductor layer; e) a drain electrode overlapping the other end portion of the semiconductor layer and spaced apart from the source electrode; f) a second insulating layer formed on the exposed surface of the first insulating layer while covering the source and drain electrode, having a first contact hole formed on a portion of the drain electrode; g) a pixel electrode formed on the second insulating layer and electrically connected with the drain electrode through the first contact hole; h) a third insulating layer on the pixel electrode and having a second contact hole over the first contact hole; and i) a reflective electrode formed on the third insulating layer and having a light transmitting hole and electrically connected with the pixel electrode through the second contact hole, the light transmitting hole transmitting light and covered by the pixel electrode; a liquid crystal display layer interposed between the first and second substrates; and a back light device for supplying light and located under the second substrate.

A disposable surgical device is constructed to include a shell, a smart block mounted in one end of the shell, the smart block electronic having components mounted to a circuit embedded therein, front contact pins for insertion into respective contact holes in the connector of an industry standard connector interface, and rear wire terminal points, a medical treatment terminal installed in the other side of the shell and adapted for performing surgery and treatments, and a flex circuit termination electrically connected between the smart block and the medical treatment terminal, the flex circuit termination having embedded conductor lines respectively connected to the medical treatment terminal and wire terminal points at the ends of the conductor lines respectively soldered to the wire terminal points of the smart block.

Integrated circuit devices are provided having a vertical diode therein. The devices include an integrated circuit substrate and an insulating layer on the integrated circuit substrate. A contact hole penetrates the insulating layer. A vertical diode is in a lower region of the contact hole and a bottom electrode in the contact hole has a bottom surface on a top surface of the vertical diode. The bottom electrode is self-aligned with the vertical diode. A top surface area of the bottom electrode is less than a horizontal section area of the contact hole. Methods of forming the integrated circuit devices and phase change memory cells are also provided.