2855 results about "Contact hole" patented technology

A display device includes a substrate including a first contact hole, an etching stopper disposed on a surface of the substrate and including the first contact hole, a metal pattern disposed on another surface opposite to the surface of the substrate and surrounding the first contact hole in a plan view, a first pad unit overlapping a part of the metal pattern and inserted into the first contact hole, a lead line disposed on the another surface of the substrate and electrically connected to another part of the metal pattern, a second pad unit disposed on the another surface of the substrate and electrically connected to the lead line, a protective film overlapping the another surface of the substrate and the lead line, and a protection part overlapping the first pad unit.

The invention discloses a cellular structure of a shield gate trench MOSFET and a manufacturing method thereof, the cellular structure of the shield gate trench MOSFET comprises a substrate, a drift region and an interlayer dielectric layer, the drift region is provided with a deep trench, and the deep trench is internally provided with a shield gate, an intermediate oxide layer and a control gate; a body region and a source region are formed at the upper part of the drift region through injection, the interlayer dielectric is provided with a source electrode contact hole which penetrates through the source region and extends into the body region, and highly doped contact regions are formed on the side wall and the bottom of the source electrode contact hole through injection; and a charge balance region is formed below the source electrode contact hole through high-energy ion implantation. According to the invention, by arranging the charge balance region, the lateral depletion of the shield gate to the adjacent drift region can be enhanced when the shield gate trench MOSFET device is in a reverse bias state, the specific on-resistance of the device is reduced, the depletion of the drift region of the epitaxial layer is accelerated, and the reliability and radiation resistance of the device are improved.

The invention provides a method for manufacturing a semiconductor device and a vertically stacked semiconductor device, which can be applied to the technical field of semiconductors. The manufacturing method includes: disposing a lower field effect transistor and an upper field effect transistor on a substrate, the lower field effect transistor and the upper field effect transistor being stacked in a vertical direction; the upper surface of the substrate is connected with the lower surface of the lowermost gate stack in the lower field effect transistor and the lower surface of the source / drain layer; forming a full silicide layer on the exposed lower surface of the gate stack in the lower field effect transistor and the exposed lower surface of the source / drain layer; patterning the full silicide layer to form an opening which exposes the lower surface of the lowermost gate stack in the lower field effect transistor, and forming silicide layer patterns which are arranged on the two sides of the opening in the first direction and are connected with the lower surface of a source / drain layer in the lower field effect transistor at the same time; filling a dielectric material in the opening so that the dielectric material filled in the opening is used as a lower isolation layer of the gate stack; a contact hole is provided in contact with the silicification layer pattern.

The invention discloses an SJ-MOSFET device. The SJ-MOSFET device comprises a first conductive type substrate; a first conductive type epitaxial layer; a source region; a body region; a second conductive type doped column; the trench gate is arranged on the side surface of the second conductive type doped column and penetrates through the source region and the body region; and the trench pseudo gate is arranged on the side surface of the second conductive type doped column and penetrates through the source region and the body region. On the other hand, the invention discloses a manufacturing method. According to the invention, the grid electrode and the grid electrode groove are arranged on the side surface of the doped column, and a part of the grid electrode groove is arranged in the doped column, so that the area of the grid electrode groove occupying the MESA is small, and the grid electrode groove is arranged towards the interior of the doped column, so that the cell size and the pitch between two source electrode contact holes can be reduced to the greatest extent, and the performance of the MESA is improved. And meanwhile, no JFET resistor exists, so that the optimization of the on-resistance is realized.

The invention provides a packaging substrate structure and a preparation method thereof. The preparation method comprises the following steps: providing a core plate layer; forming a multilayer substrate adding layer covering two opposite surfaces of the core plate layer and electrically connected with the core plate layer; providing an interconnection structure layer which comprises a bottom circuit layer, a bottom dielectric layer and a middle interconnection layer; pressing the interconnection structure layer in a preset area of the substrate adding layer in an inverted manner to obtain a required substrate structure layer; solder mask layers are formed on the two opposite faces of the substrate structure layer, contact holes are formed in the preset positions of the solder mask layers, and at least one contact hole exposes the conductive part of the interconnection structure layer. According to the invention, packaging with finer lines, lighter and lighter weight and higher line density can be realized, and signal transmission loss can be substantially reduced at the same time. Besides, the packaging substrate structure has high design flexibility, and the thickness and the circuit density of the interconnection structure layer can be accurately controlled by adjusting the thickness, the number of layers and the circuit design of each dielectric layer and each circuit layer so as to meet specific packaging requirements.

A display device includes a first substrate including an open portion, a first barrier insulating layer disposed on the first substrate and including a first contact hole overlapping the open portion, a first fan-out line disposed on the first barrier insulating layer, a pad part integrally formed with the first fan-out line and exposed through the open portion, a second substrate disposed on the first fan-out line, a connection part disposed on the second substrate and connected to the first fan-out line, a second fan-out line disposed on a layer between the first fan-out line and the connection part and connected to the connection part, a data line disposed on the same layer as the connection part and electrically connected to the second fan-out line, a flexible film including a lead electrode, and a contact part electrically connecting the lead electrode and the pad part.

The invention discloses a silicon carbide step groove MOSFET and a manufacturing method thereof. The MOSFET comprises a semiconductor drain region, a semiconductor drift region, a second conductive type semiconductor well region, a first conductive type semiconductor source region, a second conductive type semiconductor contact region, a first groove, a first conductive type carrier diffusion layer, a second groove, a second conductive type semiconductor shielding region, a gate dielectric layer, a gate electrode, an interlayer dielectric layer and a contact hole. And a source end metal electrode and a drain end metal electrode. A first conductive type semiconductor carrier diffusion layer (CSL) is prepared in a local region of the bottom and the side wall of a first groove, so that the specific on-resistance (Ron, sp) of the device is reduced; second conductive type semiconductor shielding regions short-circuited with the source end metal electrode are prepared in all regions of the bottom and the side wall of the second groove, so that the gate-oxide electric field can be remarkably reduced compared with a shielding region introduced only at the bottom of the groove, and the reliability of the device is improved.

The invention provides an electric field enhancement type shield gate MOSFET (Metal-Oxide-Semiconductor Field Effect Transistor), which comprises a substrate, an epitaxial layer formed on the substrate, a gate trench formed on a cellular region on the epitaxial layer, and a first gate dielectric layer formed at the bottom of the gate trench and a first polycrystalline silicon layer located in the first gate dielectric layer, a P-type epitaxial layer is formed on the first gate dielectric layer and the first polycrystalline silicon layer, and an isolation dielectric layer is formed on the P-type epitaxial layer; a second gate dielectric layer is formed on the side wall of the residual gate trench, and a second polycrystalline silicon layer is formed in the residual gate trench; a well region and a source region of a cellular region are formed on the epitaxial layer, and a contact hole dielectric layer is formed on the epitaxial layer; and contact holes communicated with the well region are formed on the contact hole dielectric layer and the epitaxial layer below the contact hole dielectric layer. By adding the shield grid P-type epitaxial layer, the electric field intensity in the middle of the drift region is effectively improved, the breakdown voltage is improved, and meanwhile, the conduction loss can be further reduced by adjusting epitaxy.

The invention discloses a manufacturing method of a semiconductor device, and belongs to the technical field of semiconductors. The manufacturing method comprises the following steps: providing a substrate, forming a dummy gate on the substrate, and forming a hard mask layer on the dummy gate; forming side wall structures on two sides of the dummy gate; forming a contact hole etching stop layer on the substrate, the side wall structure and the pseudo gate, wherein the material of the contact hole etching stop layer is the same as that of the hard mask layer; forming an interlayer dielectric layer on the contact hole etching stop layer, and planarizing the interlayer dielectric layer to the residual preset thickness of the hard mask layer; oxidizing the hard mask layer, a part of the contact hole etching stop layer and a part of the side wall structure to form a surface oxide layer; synchronously removing the surface oxide layer and a part of the interlayer dielectric layer, wherein the surface of the dummy gate is flush with the surfaces of the interlayer dielectric layers on the two sides; and removing the dummy gate to form a metal gate. According to the manufacturing method of the semiconductor device provided by the invention, the height of the formed metal gate can be ensured, the manufacturing process is simple, and the controllability is high.

Various embodiments of improved process flows and methods are provided herein for etching high aspect ratio (HAR) features in carbon-containing hard mask layers. In the disclosed embodiments, the improved process flows and methods combine sidewall passivation and mask de-clogging steps in a single plasma process step to improve throughput when etching HAR features (such as vias, contact holes, trenches, etc.) within a carbon-containing hard mask layer. In doing so, the improved process flows and methods disclosed herein protect the sidewall surfaces of the carbon-containing hard mask layer and prevent bowing during the HAR etch process, while also reducing processing time and improving throughput.

To provide a semiconductor device having a transistor part and a diode part, in which a reverse recovery loss is reduced.SOLUTION: A semiconductor device includes: an interlayer insulating film 38 provided over a semiconductor substrate 10; an emitter electrode 52 being a front surface electrode provided over the semiconductor substrate; contact parts where the front surface electrode and mesa parts 61 to 64 are connected in contact holes 54 of the interlayer insulating film; and a lifetime adjustment region 206 provided on a front surface side of the semiconductor substrate. The contact parts have a first contact part 77 provided in a transistor part, and a second contact part 87 provided in a diode part. The first contact part is disposed over the second contact part.SELECTED DRAWING: Figure 3A

A display device includes first to fourth pixels, wherein each of the first to fourth pixels includes first to third sub-pixels, a first data connection pattern electrically connected to a first data line by a first contact hole and electrically connected to the second sub-pixel of the second pixel, and a second data connection pattern electrically connected to a second data line by a second contact hole and electrically connected to the second sub-pixel of the fourth pixel, wherein, in a plan view, the first contact hole is disposed between the emission area of the third sub-pixel of the first pixel and the emission area of the third sub-pixel of the second pixel, and in a plan view, the first contact hole and the second contact hole are disposed in a row in the second direction.

The invention provides a semiconductor device and a manufacturing method thereof, and the method comprises the steps: providing a substrate, and forming a gate structure, a side wall and an active / drain region on the substrate; forming a protective layer which covers the substrate and at least covers part of the side wall, close to the substrate, of the side wall; removing a part of the side wall which is not covered by the protective layer; removing the protective layer; forming metal silicide on the gate structure and / or the source / drain region; and forming a dielectric layer covering the gate structure, the side wall, the source / drain region and the substrate, and forming a contact hole exposing the metal silicide in the dielectric layer. The stress proximity technology is arranged before the metal silicide is formed, and when part of the side wall is removed, the protection layer is adopted to protect the substrate and part of the side wall close to the substrate, so that the loss of the substrate can be avoided on the basis of improving the filling window and improving the stress, and the reliability of the device is improved. Therefore, the loss of the metal silicide caused by the removal of the side wall is avoided, the etching through phenomenon of the metal silicide is avoided, and finally the performance of the semiconductor device is improved.

The tellurium-cadmium-mercury double-layer component heterogeneous planar junction detector comprises a substrate material layer, an n-type absorption layer, a surface n-type wide band gap heterogeneous layer, a passivation layer and a contact electrode layer which are arranged in a stacked mode. The surface n-type wide band gap heterogeneous layer is a wide band gap heterogeneous layer prepared on the surface of the n-type absorption layer based on a mercury-rich vertical liquid phase epitaxy technology, and the residual impurities are n-type; the passivation layer covers at least partial areas of the isolation region and the p-type injection region in the orthographic projection direction, and the part, not covering the p-type injection region, of the passivation layer is a contact hole; the contact electrode layer is in contact with the p-type injection region, and the orthographic projection area of a contact electrode is larger than and covers the contact hole. According to the invention, interface mutual diffusion is realized in the growth process of the n-type wide bandgap heterogeneous layer, and the mercury cadmium telluride p-on-n planar heterojunction device is realized through As ion implantation. Tunneling current and surface electric leakage can be effectively suppressed, dark current can be reduced, and device performance can be improved.

The invention discloses a thin film resistor device and a preparation method thereof. The preparation method comprises the following steps: forming a second insulating layer on a first metal interconnection layer and an exposed first insulating layer; forming a thin-film resistor structure in a partial region of the upper surface of the second insulating layer; forming a third insulating layer on the thin-film resistor structure and the exposed upper surface of the second insulating layer; forming a first contact hole extending from the upper surface of the third insulating layer to the first metal interconnection layer, and filling the first contact hole with first contact metal; forming a second metal interconnection layer on the upper surface of the third insulating layer; forming a fourth insulating layer on the second metal interconnection layer and the exposed third insulating layer; and forming a second contact hole extending from the upper surface of the fourth insulating layer to the second metal interconnection layer and a third contact hole extending from the upper surface of the fourth insulating layer to the thin-film resistor structure, and filling second contact metal and third contact metal in the second contact hole and the third contact hole respectively. According to the thin film resistor device and the preparation method thereof, the stability of the device can be improved.

A display device comprises a first substrate including a first contact hole, fan-out lines included in a first metal layer on the first substrate, first and second pad parts exposed to a lower portion of the first substrate, a display layer disposed on the fan-out lines, and a flexible film disposed below the first substrate, inserted into the first contact hole, and electrically connected to the first and second pad parts. The fan-out lines comprise first fan-out lines extending from the first contact hole in a first direction, and second fan-out lines extending from the first contact hole in a direction opposite to the first direction. The first fan-out lines and the first pad parts are integral with each other. The second fan-out lines and the second pad parts are integral with each other.

The utility model discloses a drain-shared double-SGT MOSFET device, and relates to the technical field of semiconductors, the drain-shared double-SGT MOSFET device comprises a substrate and an epitaxial layer, the top surface of the epitaxial layer is provided with a plurality of grooves side by side, the bottom side walls and the inner bottoms of the grooves are provided with shield gate oxide layers, and the shield gate oxide layers on the bottom side walls of the grooves are filled with first polycrystalline silicon; a trench middle shielding oxide layer is deposited at the top end of the first polycrystalline silicon, a gate oxide layer is arranged at the top end of the trench middle shielding oxide layer and located on the side wall of the trench, and the gate oxide layer is filled with second polycrystalline silicon; a source region and a base region are formed between every two adjacent grooves from top to bottom, communicated first top layer contact holes are formed in the source regions and the base regions, the first top layer contact holes are filled with conductive materials to form MOS structures, and connecting layers are formed on the surfaces of the MOS structures; and a groove middle insulating column is vertically arranged in the middle in the groove. According to the utility model, the on-resistance is greatly reduced.

A display device is disclosed that includes a display panel and an input sensor including a plurality of conductive patterns. The conductive patterns include a first sensing electrode including first sensing patterns and bridge patterns, a second sensing electrode spaced apart from the first sensing electrode, and dummy patterns each overlapping the second sensing electrode and a first sensing pattern adjacent to the second sensing electrode in the first direction. Each of the bridge patterns is connected to two first sensing patterns through first contact holes. When a region, in which each of the plurality of dummy patterns overlaps each of the corresponding first sensing pattern and the second sensing electrode, is defined as an overlapping region, a dummy hole, which passes through a conductive pattern disposed on an upper part among the corresponding first sensing pattern, the second sensing electrode, and the plurality of dummy patterns, in a thickness direction, is defined in the overlapping region. Each of the bridge patterns is disposed between two dummy patterns in the second direction. Distances between the two dummy patterns and the bridge pattern, disposed between the two dummy patterns, are uniform in the second direction.

The invention discloses a novel super-junction trench MOS power device and a preparation method thereof, and relates to the technical field of semiconductor devices. The base layer region is arranged on the upper surface of the substrate; the first P-type column and the second P-type column are arranged in the base layer area and are not adjacent to each other; the P-type layer is arranged on the upper surfaces of the first P-type column and the second P-type column; the first groove and the second groove penetrate through the P-type layer and are correspondingly arranged in the first P-type column and the second P-type column; the dielectric layer is arranged on the upper surfaces of the first groove and the second groove; the first contact hole, the second contact hole and the third contact hole penetrate through the dielectric layer and are correspondingly formed in one side of the first groove, one side of the second groove and the P-type layer between the two grooves; and the metal region is arranged in the first contact hole, the second contact hole, the third contact hole and the upper surface of the dielectric layer. The conduction and switching loss of the MOS power device can be reduced, and the impact resistance can be improved at the same time.

The invention discloses a trench-type power semiconductor device with a gate protrusion structure and a preparation method thereof. The preparation method comprises the following steps: depositing an epitaxial layer on a silicon substrate; sequentially preparing a silicon dioxide cushion layer, a first mask layer and a second mask layer on the epitaxial layer; etching to form a gate trench; forming a gate oxide layer; depositing grid polycrystalline silicon; removing the grid polycrystalline silicon on the surface of the first mask layer through chemical mechanical grinding; etching to remove the first mask layer, and adjusting the morphology of the grid polycrystalline silicon on the silicon platform region; forming a body region and a source region through ion implantation; and preparing a source region contact hole and a tungsten bolt. According to the invention, the grid protrusion structure is formed in the preparation process of the groove type power semiconductor device, the problem that the channel electric leakage is increased after the polycrystalline silicon is etched is solved, the grid resistance is reduced by increasing the cross sectional area of the grid polycrystalline silicon, the switching speed and the linear region capability are improved, and the device performance is optimized.

The invention provides an IGBT (Insulated Gate Bipolar Translator) device structure and a preparation method thereof. The preparation method comprises the following steps: forming a plurality of gate trenches in an active region, and forming a gate oxide layer and a polycrystalline silicon layer; forming a grid line mask pattern; forming a polysilicon gate line, and reserving a gate line mask pattern on the polysilicon gate line; a hard mask medium is deposited, a first window and a second window which expose the surface of the active area are formed, and the second window exposes the grid line mask pattern on the grid line; etching is carried out, based on the etching selection ratio, the semiconductor substrate in the first window is partially removed to form an emitter region contact hole, and the grid line mask pattern in the second window is not removed to protect the grid line; and removing the grid line mask pattern in the second window by a wet method to form a grid line contact hole. According to the invention, the preparation of the emitter region contact hole and the line contact hole only needs to use one mask plate for photoetching and etching, compared with the traditional process, one mask plate is effectively reduced, the process flow is simplified, the production period is shortened, and the production efficiency is improved while the tape-out cost is reduced.

The invention provides a multilayer heterogeneous material ultrafast laser integrated connection method and device, and the method specifically comprises the steps: stacking and fixing a chip bonding pad, a spring pin and quartz glass on a three-dimensional motion platform, and adjusting the platform to enable a laser focal plane to be located at the center of the pin; aiming at the connection of a bonding pad and a pin, high-repetition-frequency ultrafast laser with a high Rayleigh length is obtained through spatial shaping, a two-dimensional galvanometer is used for carrying out spiral line or concentric circular ring scanning to act on the periphery of the pin, metal plasma is excited, molten metal is formed and deposited in a contact hole of the pin and the bonding pad, and the molten metal is continuously accumulated along with reverse heating, so that the metal is formed. Dissimilar metal welding is achieved; aiming at the connection of the pin and the glass, laser penetrates through the quartz glass, plasma is excited on a metal interface, molten metal with increased volume is formed, a material interface gap is filled, and welding from non-optical contact to optical contact is regulated and controlled; and two heterogeneous materials are successfully welded through single scanning until welding of the whole pin array is completed, and efficient integrated packaging is achieved.

Disclosed is a thin film transistor substrate comprising a substrate; a first thin film transistor on the substrate, the first thin film transistor including a first active layer and a first gate electrode; a second thin film transistor on the substrate, the second thin film transistor including a second active layer and a second gate electrode above the first active layer and the first gate electrode; a first insulating layer between the first gate electrode and the second active layer; and; and a first connection electrode connecting together the first active layer and the second active layer, the first connection electrode extending through a first contact hole in the first insulating layer and is in contact with each of the first active layer and the second active layer and a display apparatus including the same.

A semiconductor device may include a backside wiring line in a first backside interlayer insulating film, a fin-type pattern on the backside wiring line, a second backside interlayer insulating film between the fin-type pattern and the first backside interlayer insulating film, a gate electrode on the fin-type pattern, a first source / drain pattern on a side of the gate electrode, and a backside source / drain contact in a backside contact hole defined by the fin-type pattern and the second backside interlayer insulating film. The backside source / drain contact may connect the backside wiring line and the first source / drain pattern. The backside source / drain contact may include an upper pattern and a lower pattern. The upper pattern may be between the lower pattern and the first source / drain pattern, and may fill at least a portion of the first backside contact hole. The upper pattern may have a single conductive film structure.

According to an aspect, a detection device includes: photodiodes provided on a substrate; transistors corresponding to the photodiodes; a first organic insulating film that covers the transistors; first electrodes that are between the first organic insulating film and the photodiodes in a direction orthogonal to the substrate and are provided corresponding to the photodiodes; a second electrode provided so as to extend across the photodiodes; an insulating film between adjacent first electrodes, and a second organic insulating film that covers an inside of a contact hole provided in the first organic insulating film. The photodiodes includes a first carrier transport layer, an active layer, and a second carrier transport layer that are stacked on the substrate. The first carrier transport layer, the active layer, and the second carrier transport layer are provided so as to cover each of the first electrodes, the insulating film, and the second organic insulating film.

A display device with improved light-emitting efficiency is disclosed. The display device includes a plurality of pixels, a light emitting device provided in each of the pixels, the light emitting device having first and second surfaces which are opposite to each other, first and second electrodes electrically and respectively connected to the first and second surfaces of the light emitting device, and a metal oxide pattern interposed between the second surface of the light emitting device and the second electrode. The metal oxide pattern includes first and second regions. The first region encloses the second region, and the second region has a contact hole exposing at least a portion of the second surface. The second electrode is coupled to the second surface through the contact hole, and the first and second regions have crystalline phases different from each other.

A display apparatus includes a base substrate including a display area and a peripheral area, a conductive layer formed on the base substrate in an entirety of the peripheral area and the display area, a buffer layer on the conductive layer, a thin film transistor on the buffer layer in the display area, an electrode in a contact hole that is formed through the buffer layer to expose a side surface of the conductive layer in the peripheral area, the electrode making contact the conductive layer, an insulating pattern in the contact hole on the electrode, and a wiring on the insulating pattern and electrically connected to the electrode.

A display device includes: a display panel comprising a plurality of light emitting areas; and an input sensing panel including: a first sensing insulating layer on the display panel; a second sensing insulating layer on the first sensing insulating layer and having a first opening and a contact hole; an insulating pattern; and a plurality of conductive patterns including a first conductive layer and a second conductive layer, the first conductive layer includes: a first-first conductive portion in the first opening; and a first-second conductive portion exposed through the contact hole, the second conductive layer includes: a second-first conductive portion electrically connected to the first-first conductive portion; a second-second conductive portion electrically connected to the first-second conductive portion; and a second-third conductive portion spaced apart from the first conductive layer in a plan view, and the insulating pattern is on the second-first conductive portion and in the first opening.

The invention discloses a silicon carbide step groove MOSFET and a manufacturing method thereof. Comprising a semiconductor drain region, a semiconductor drift region, a second conductive type semiconductor well region, a first conductive type semiconductor source region, a second conductive type semiconductor body contact region, a first conductive type carrier diffusion layer, a first groove, a second conductive type semiconductor shielding region, a second groove, a gate dielectric layer, a gate electrode, an interlayer dielectric layer and a contact hole, a source end metal electrode and a drain end metal electrode; according to the invention, the first conductive type semiconductor carrier diffusion layer is prepared at the bottom of the semiconductor well region, so that the specific on-resistance of the device is reduced; second conductive type semiconductor shielding regions which are in short circuit connection with the source end metal electrode are prepared in all regions of the bottom and the side wall of the first groove, and the gate-oxide electric field can be remarkably reduced compared with a shielding region introduced only at the bottom of the groove, so that the reliability of the device is improved; according to the invention, the static and dynamic electrical performance parameters of the device are optimized, and the reliability of the device is also optimized.

A semiconductor device includes a substrate including a first active region, a bit line on the substrate to cross the first active region, a bit line contact between the bit line and the first active region and in a bit line contact hole extending into the substrate, a bit line contact spacer on a sidewall of the bit line contact within the bit line contact hole, a bit line spacer on a sidewall of the bit line, an anti-oxidation layer between the sidewall of the bit line and the bit line spacer and between the sidewall of the bit line contact and the bit line spacer, and a buried contact in a buried contact hole, passing through the bit line contact spacer, and contacting the first active region, in which the anti-oxidation layer includes a silicon-containing material including SiOx, where 0<x≤2.