1137 results about "Contact hole" patented technology

A semiconductor device, including: a semiconductor substrate having a main surface; an interlayer insulating film provided on the main surface of the semiconductor substrate; a contact hole penetrating through the interlayer insulating film to reach the semiconductor substrate; a plug electrode embedded in the contact hole; a first barrier metal provided on the interlayer insulating film, the first barrier metal being apart from the plug electrode; and a front electrode provided on the first barrier metal and the plug electrode.

A display device includes a substrate, a first metal layer on the substrate, a first barrier insulating layer on the first metal layer, an etching control layer on the first barrier insulating layer, a first contact hole passing through the substrate, the first barrier insulating layer, and the etching control layer, a second barrier insulating layer on the etching control layer and including a second contact hole, a fan-out line on the second barrier insulating layer and included in a second metal layer, a pad part inserted into the second contact hole and included in the second metal layer, the pad part integral with the fan-out line, a display layer on the fan-out line, and a flexible film under the substrate and inserted into the first contact hole to be electrically connected to the pad part. The first metal layer includes an etching mark adjacent to the first contact hole.

A display device includes a base layer; a pixel circuit layer disposed on the base layer, the pixel circuit layer including a first transistor; and an insulating layer overlapping the first transistor; a first electrode disposed on the pixel circuit layer, the first electrode electrically connected to the first transistor via a contact hole of the insulating layer; a cover layer disposed on the first electrode, the cover layer overlapping at least a portion of the first electrode; a light emitting element including a first end and a second end electrically connected to the first electrode; a second electrode disposed on the light emitting element, the second electrode electrically connected to the second end of the light emitting element; and a third electrode disposed on the cover layer, the third electrode electrically contacting at least a portion of the first electrode.

The invention discloses a mosquito killer finished product detection device. The mosquito killer finished product detection device comprises a base and a rotating disc. Eleven stations of feeding, resistance detection, voltage resistance detection, riveting, rivet leakage detection, forward rotation detection, traceability code, reverse rotation detection, marking, light detection and discharging are sequentially arranged on the rotating disc in the circumferential direction, a mounting groove for containing a mosquito killer to be detected is formed in the disc, and a notch groove is formed in the position, corresponding to a switch touch button, of the groove. The base is provided with touch button test seats at the resistor, forward rotation, reverse rotation and light detection stations, and the seats are provided with touch button test motors and touch button test benches. An air blowing cavity is formed between the through hole and the abutting hole, a suspension ball and an air nozzle are arranged in the cavity, and a matching groove in the end of the output shaft of the motor corresponds to the abutting rod in position. The device is reasonable in structural layout, efficient and convenient in detection, high in automation degree and good in detection reliability.

A MOSFET includes a gate electrode and an etching stopper layer formed on a field insulating film of a gate pad region, and an interlayer insulating film formed on the gate electrode and the etching stopper layer. The etching stopper layer is made from a substance having a selectivity of 5.0 or more with respect to etching of the interlayer insulating film and the field insulating film, and is provided at a position farthest from the well contact hole of the under-gate well contact region at least in the gate pad region.

The invention discloses a method for optimizing the contour of a contact hole and a semiconductor structure, and belongs to the technical field of semiconductor manufacturing. The method comprises the following steps: introducing a silicon-containing precursor gas and a carbon-containing precursor gas on a substrate, and depositing to form a first amorphous silicon layer serving as an etching deceleration layer; and depositing on the first amorphous silicon layer to form a second amorphous silicon layer by stopping introducing the carbon-containing precursor gas and continuing introducing the silicon-containing precursor gas. Through in-situ deposition of the laminated structure of the carbon-containing layer and the pure amorphous silicon layer, the intrinsic etching selection ratio is constructed by using the property difference of materials, and an additional ion implantation step is not needed. According to the method, the technological process is simplified, the cost and the thermal budget are reduced, the etching bias load effect can be effectively improved, the contour of the contact hole is optimized, the contact hole is closer to be vertical and is uniform up and down, and therefore the yield and the reliability of the device are improved.

The invention provides a trench MOSFET and a manufacturing method thereof, and the method comprises the steps: forming a trench, a shield gate oxide layer, a control gate oxide layer, an isolation oxide layer, a shield gate, a control gate, a body region, a source region, and a dielectric layer; a first contact hole penetrating through the dielectric layer and the source region and extending into the body region and a second contact hole penetrating through the dielectric layer, the control gate and the isolation oxide layer and exposing the shield gate are formed, a subsequently formed source metal layer is electrically connected with the source region and the body region through the first contact hole, and a gate metal layer is electrically connected with the control gate and the shield gate through the second contact hole. When the trench MOSFET provided by the invention is in forward conduction, because the shield grid is connected to the control grid, an electron accumulation layer is formed on the side wall of the shield grid, so that the conduction resistance is reduced. Besides, in the manufacturing process of the trench MOSFET, the number of photomasks can be reduced, for example, only three photomasks corresponding to the trench, the contact hole and the metal layer respectively are needed, and the production cost can be reduced.

The invention discloses a display device. The present disclosure includes: a substrate; a circuit layer disposed on the substrate; a plurality of banks disposed on the circuit layer; a plurality of light emitting elements disposed on the bank and each having a first electrode and a second electrode; a contact electrode disposed on the bank to be electrically connected with the first electrode and having a contact opening; and an optical layer covering side surfaces of the plurality of light emitting elements and the contact electrode and having a contact hole in a contact opening of the contact electrode, in which the contact electrode is electrically connected with the second electrode through the contact hole of the optical layer without the transparent conductive layer.

The disclosure discloses a display device including a substrate, a circuit layer disposed on the substrate, and a plurality of banks disposed on the circuit layer. A plurality of light-emitting elements is disposed on the banks, each having a first electrode and a second electrode. A contact electrode is disposed on the bank and is electrically connected to the first electrode. The contact electrode includes a contact opening. An optical layer covers side surfaces of the plurality of light-emitting elements and the contact electrode, and includes a contact hole aligned with the contact opening of the contact electrode. The contact electrode is electrically connected with the second electrode through the contact hole of the optical layer. A transparent conductive layer is not present in the region of electrical connection between the contact electrode and the second electrode. This structure improves adhesion and maintains the structural integrity of the optical layer.

A display device is disclosed that includes a display panel and an input sensor including a plurality of conductive patterns. The conductive patterns include a first sensing electrode including first sensing patterns and bridge patterns, a second sensing electrode spaced apart from the first sensing electrode, and dummy patterns each overlapping the second sensing electrode and a first sensing pattern adjacent to the second sensing electrode in the first direction. Each of the bridge patterns is connected to two first sensing patterns through first contact holes. When a region, in which each of the plurality of dummy patterns overlaps each of the corresponding first sensing pattern and the second sensing electrode, is defined as an overlapping region, a dummy hole, which passes through a conductive pattern disposed on an upper part among the corresponding first sensing pattern, the second sensing electrode, and the plurality of dummy patterns, in a thickness direction, is defined in the overlapping region. Each of the bridge patterns is disposed between two dummy patterns in the second direction. Distances between the two dummy patterns and the bridge pattern, disposed between the two dummy patterns, are uniform in the second direction.

The invention discloses a manufacturing method of a semiconductor device, and belongs to the technical field of semiconductors. The manufacturing method comprises the following steps: providing a substrate, and forming a dummy gate and a hard mask layer on the substrate; forming side wall structures on two sides of the dummy gate; forming a contact hole etching stop layer, wherein the material of the contact hole etching stop layer is the same as that of the hard mask layer; forming an interlayer dielectric layer on the contact hole etching stop layer, and planarizing the interlayer dielectric layer to the residual preset thickness of the hard mask layer by adopting a first planarization process; performing first plasma modification treatment, and at least forming a first modified layer on the surface of the interlayer dielectric layer; second plasma modification processing is carried out, and at least the hard mask layer and a part of the contact hole etching stop layer are modified into a second modified layer; synchronously removing the first modified layer and the second modified layer, and exposing the dummy gate; and removing the dummy gate to form a metal gate. According to the invention, residual metal in the interlayer dielectric layer is avoided, the height consistency of the metal gate is improved, and the reliability of the semiconductor device is improved.

A display device includes a display layer including pixels. An input sensing layer is on the display layer, and includes a first conductive pattern layer, a second conductive pattern layer and a sensing insulating layer. The second conductive pattern layer includes a first sensing electrode array extending in a first direction, and second-first and second-second sensing electrodes that are separated in a second direction with the first sensing electrode array interposed therebetween. The first conductive pattern layer includes a bridge wiring connected to the second-first and second-second sensing electrodes through bridge contact holes defined in the sensing insulating layer and is electrically insulated from and intersects the first sensing electrode array. The bridge wiring includes a bridge opening exposing an insulating layer disposed under the bridge wiring. The first sensing electrode array directly contacts the insulating layer exposed by the bridge opening, through a dummy contact hole.

Disclosed are a display device and a manufacturing method thereof. The display device may comprise a substrate having a display region and a non-display region outside the display region; a circuit layer including a plurality of lines disposed on the substrate, wherein the plurality of lines are separated with a first insulating layer therebetween; and an second insulating layer including a first contact hole that exposes an uppermost layer line in the display region and a second contact hole that exposes an uppermost layer line in the non-display region, wherein a thickness of the second insulating layer in the non-display region is different from a thickness of the second insulating layer in the display region.

The invention provides a semiconductor structure and a manufacturing method thereof, the semiconductor structure at least comprises a bottom conducting layer and a blocking part, the plane where the blocking part is located is located above the plane where the bottom conducting layer is located, and the projection of the blocking part and the projection of the bottom conducting layer in the vertical direction have an overlapping area; the three-dimensional structure comprises a first part and a second part, the top surface of the blocking part is higher than the bottom surface of the second part and lower than or flush with the bottom surface of the first part, and at least part of the first part is located over the overlapping area; the plane where the first conducting layer is located is higher than the top face of the three-dimensional structure, the contact hole is directly connected with the first conducting layer, the bottom conducting layer is electrically connected with the first conducting layer through the contact hole, and the contact hole is located in the side, away from the second part, of the first part; and the first isolation layer is used for filling areas between the contact holes and the three-dimensional structure and areas among different contact holes.

An active matrix substrate includes a plurality of gate bus lines, a plurality of source bus lines located closer to the substrate side; a lower insulating layer that covers the source bus lines; an interlayer insulating layer that covers the gate bus lines; a plurality of oxide semiconductor TFTs disposed in association with respective pixel regions; a pixel electrode disposed in each of the pixel regions; and a plurality of source contact portions each of which electrically connects one of the oxide semiconductor TFTs to the corresponding one of the source bus lines, in which each of the oxide semiconductor TFTs includes an oxide semiconductor layer disposed on the lower insulating layer, a gate electrode disposed on a portion of the oxide semiconductor layer, and a source electrode formed of a conductive film, and each of the source contact portions includes a source contact hole, and a connection electrode.

This application discloses a semiconductor structure, a method for fabricating a semiconductor structure, and a memory. The semiconductor structure includes: a substrate comprising a substrate, a first isolation layer, a first dielectric layer, and a stop layer formed by stacking; wherein a first contact hole is formed on the substrate, the opening of the first contact hole being flush with the upper surface of the stop layer; a first insulating layer and a first barrier layer are sequentially formed on the inner wall of the first contact hole, and a first contact structure is disposed within the first contact hole; a protective layer is formed to cover the upper surface of the first contact structure; a second dielectric layer and a second isolation layer are sequentially stacked on the protective layer; wherein a second contact hole is formed on the substrate, the second contact hole being formed to penetrate the second dielectric layer, the second isolation layer, and the protective layer, and stopping at the first contact structure; a second barrier layer and a second contact structure are also included, the second barrier layer being formed on the inner wall of the second contact hole, and the second contact structure being disposed within the second contact hole.

The application discloses an integrated super-junction power MOS device with corrugated gate oxide and a preparation method thereof, and belongs to the technical field of semiconductors. The device comprises a substrate, a buffer layer and an epitaxial layer which are sequentially stacked from bottom to top; wherein the epitaxial layer is provided with a plurality of vertically spaced super-junction columns, and the top of each super-junction column is provided with a body region; the surface layer of the body region is provided with a contact hole doped region and a source doped region which are in contact with each other; the upper surface of the epitaxial layer is further provided with a gate oxide layer; the gate oxide layer is in a corrugated structure, and the lower surface of the gate oxide layer is adapted to and contacts with a corrugated groove located on the upper surface of the epitaxial layer, the body region and part of the source doped region; the upper surface of the gate oxide layer and part of the source doped region is covered with a polysilicon layer, and the gate oxide layer and the polysilicon layer form a corrugated gate structure. The integrated super-junction power MOS device with corrugated gate oxide has good single-particle burnout resistance and single-particle gate penetration resistance.

A fingerprint sensor and a display device including the same are disclosed. The fingerprint sensor includes a substrate, a circuit element layer on a first surface of the substrate and including a plurality of conductive layers, a light emitting element layer on the circuit element layer and including a light emitting element and a light blocking layer, and a light sensor layer on a second surface of the substrate and including a light sensor, wherein the light blocking layer includes a contact hole exposing a first electrode of the light emitting element and a first opening portion exposing a portion of the circuit element layer, and the circuit element layer includes a second opening portion formed in the plurality of conductive layers and includes a light transmission hole of which at least a portion overlaps the first opening portion.

A display device comprises a substrate divided into emission and non-emission areas, a storage capacitor, a first insulating layer, a first light emitting element and a second light emitting element, a bank in the non-emission area, and defining an opening corresponding to the emission area, a first pixel electrode electrically connected to a first end of the first light emitting element, a second pixel electrode electrically connected to a second end of the second light emitting element, an intermediate electrode between the first pixel electrode and the second pixel electrode, surrounding at least a portion of the first pixel electrode, and electrically connected to a second end of the first light emitting element and to a first end of the second light emitting element, and a sub-electrode electrically connected to a lower electrode of the storage capacitor through a contact hole, and overlapping the first pixel electrode.

The invention discloses an IGBT device, a preparation method and a preparation system thereof, and a storage medium. The device comprises a substrate; the second groove region and the first groove region are formed in the substrate; the semi-insulating material layer is formed in the first groove region and the second groove region; a CS layer, a Pwell layer and an NSD layer; a contact hole penetrating from top to bottom; the contact hole is filled with a metal contact layer. According to the invention, the first groove region and the second groove region are formed on the side wall of the first HM layer, gate oxidation, polysilicon filling and the second HM layer are carried out in sequence, ion implantation and annealing are carried out, and the gate oxide layer between the grooves is used as a barrier mask to realize etching of the contact hole. The method is suitable for forming the contact hole under the condition that the cellular mesa is small, photoetching sleeve deviation between the contact hole and the groove can be effectively avoided, so that the in-chip consistency of saturation voltage drop is greatly improved, and meanwhile, a wider upper opening can be formed so as to be beneficial to further reducing the conduction voltage drop of a device.

A display apparatus in which a voltage drop is sufficiently suppressed is provided. The display apparatus includes a first light-emitting device including a first lower electrode and a first organic compound layer positioned over the first lower electrode; a second light-emitting device including a second lower electrode and a second organic compound layer positioned over the second lower electrode; a common electrode included in the first light-emitting device and the second light-emitting device; and an auxiliary wiring electrically connected to the common electrode. The auxiliary wiring includes a first wiring layer and a second wiring layer; the second wiring layer is electrically connected to the first wiring layer through a contact hole in an insulating layer; and the second wiring layer has a lattice shape in a top view.

The application provides a semiconductor device preparation method and a semiconductor device, relates to the technical field of semiconductor devices, and can reduce the risk of disconnection in a shared contact hole. The method comprises the following steps: providing a semiconductor initial structure, which comprises an insulating layer and spaced gate initial structures, the insulating layer comprises first insulating structures and second insulating structures, the first insulating structures are located on the side of the gate initial structures, the second insulating structures are located between the two first insulating structures, and the first insulating structures have first openings therebetween; forming an etching stop layer on one side of the gate initial structures; forming a first dielectric layer on one side of the second insulating structures; removing the etching stop layer and part of the first insulating structures according to the first dielectric layer, so that the first insulating structures have second openings therebetween, and the opening size of the first openings is smaller than that of the second openings; forming a second dielectric layer on one side of the first dielectric layer and one side of the gate initial structures; and removing part of the first dielectric layer and the second dielectric layer to obtain a shared contact hole.

The invention discloses a semiconductor device and a preparation method thereof, a power module, a power conversion circuit and a vehicle. The semiconductor device comprises a semiconductor body which comprises a first surface and a second surface which are oppositely arranged, and further comprises a first region, a well region and a second region; the gate insulating layer is located on the first surface; the gate layer is located on the side, away from the first surface, of the gate insulating layer; the first dielectric layer is located on the side, away from the first surface, of the gate layer; the semiconductor device further comprises a plurality of first contact holes and a second dielectric layer, and the first contact holes penetrate through the gate insulating layer, the gate layer and the first dielectric layer and expose the side wall of the gate insulating layer, the side wall of the gate layer and the side wall of the first dielectric layer. The second dielectric layer is located on the side wall of the first contact hole, the second dielectric layer located in the same first contact hole forms a second contact hole, and the second contact hole exposes at least part of the surface, located on the first surface, of the first area. The problem that the position deviation of the contact hole is large can be solved.

A display device includes: a substrate; and a circuit layer on the substrate and including a semiconductor layer and conductive layers, wherein the circuit layer includes: a lower pattern included in one of the semiconductor layer and the conductive layers; a plurality of insulating layers on the lower pattern; a first contact hole penetrating the plurality of insulating layers and exposing a portion of the lower pattern; and a first conductive pattern on the plurality of insulating layers, filling the first contact hole, and including conductive particles.

A method for fabricating semiconductor device may include forming a source / drain pattern on a fin-type pattern, forming an etch stop film and an interlayer insulating film on the source / drain pattern, forming a contact hole in the interlayer insulating film, forming a sacrificial liner along a sidewall and a bottom surface of the contact hole, performing an ion implantation process while the sacrificial liner is present, removing the sacrificial liner and forming a contact liner along the sidewall of the contact hole, and forming a source / drain contact on the contact liner. The ion implantation process may include implant impurities into the source / drain pattern. The source / drain contact may be connected to the source / drain pattern.

A display device can include a display panel configured to display an image, and a touchscreen disposed on the display panel, the touchscreen including a first touch routing line layer, an insulating layer covering the first touch routing line layer, a second touch routing line layer disposed on the insulating layer, and a plurality of touch routing lines including a contact hole configured to interconnect the first touch routing line layer and the second touch routing line layer. Also, the plurality of touch routing lines include at least two interlayer structure change sections where interlayer wiring positions of the first touch routing line layer and the second routing line layer are changed.

To provide an IGBT (Insulative Gate Bipolar Transistor) which can reduce turn-on power loss and perform screening of a gate insulator.SOLUTION: An insulative gate bipolar transistor comprises: a gate trench 7a which extends in a specified extension direction set in advance in a plane view; a first insulator film 8a which is arranged at a bottom face of the gate trench 7a and at least a part of lateral face; a bottom gate conductive component 9a which is embedded in the gate trench 7a through the first insulator film 8a; a first split insulator film 10a which is arranged on the bottom gate conductive component 9a; an upper gate conductive component 11a which is embedded in the gate trench 7a through the first split insulator film 10a; a gate surface electrode 16 which is overlapped with one end of the gate trench 7a in the extension direction; a first contact hole 13c which electrically connects the gate surface electrode 16 with the bottom gate conductive component 9a; and a second contact hole 13a which electrically connects the gate surface electrode 16 with the upper gate conductive component 11a.SELECTED DRAWING: Figure 1

The application discloses an SGT device and a process method thereof, which comprises the following steps: first, forming a composite layer on the surface of a semiconductor substrate; etching the semiconductor substrate to form a groove; second, depositing a first oxide layer, then depositing a first polysilicon layer; filling the groove; third, performing back etching on the first polysilicon layer to form a source electrode of the SGT device; fourth, etching the first oxide layer in the groove; fifth, forming a pad oxide layer, then depositing a second polysilicon layer and performing back etching; sixth, depositing a dielectric layer; then removing the composite layer on the surface of the semiconductor substrate; performing etching to form an upper space in the groove; seventh, forming a gate dielectric layer and a gate electrode; eighth, respectively performing ion implantation to form a well region and a source region; forming a contact hole; and after the top metal layer is made, completing subsequent processes. The SGT device disclosed by the application comprises a floating electrode forming a lateral field plate, which optimizes the electric field of a drift region and improves the breakdown voltage.

A display device includes a substrate including an emission area and a non-emission area surrounding the emission area; a bank structure located on the emission area of the substrate and comprising a tip protruding toward the non-emission area; an anode contact hole penetrating the bank structure; an anode located on the bank structure and electrically connected to a transistor located on the substrate through the anode contact hole; a pixel defining layer located on the anode; and a light emitting layer located on the pixel defining layer, wherein the light emitting layer is spaced apart from the anode with the pixel defining layer therebetween in a portion overlapping the anode contact hole in a plan view and contacts the anode in a portion not overlapping the anode contact hole in the plan view.

The embodiment of the invention provides a semiconductor device, a chip and electronic equipment. The semiconductor device includes: a substrate; the dielectric layer is arranged on the substrate; at least part of the groove is located in the dielectric layer; a first metal layer, a dielectric material and a second metal layer which are sequentially stacked are arranged in the groove, the first metal layer and the second metal layer are isolated through the dielectric material, at least part of the first metal layer climbs out of the groove along the inner wall of the groove and extends towards the groove to form a first extension part, and a conductive first connecting bridge is clamped between the dielectric layer; the first connection bridge is at least partially located between the first extension part and the substrate, and the first connection bridge is electrically connected with the first extension part. The first metal layer is electrically led out through the first connecting bridge instead of being electrically led out through a contact hole, so that the first metal layer does not need to be etched, the dielectric material is not exposed, and the possibility that equipment on a semiconductor device production line is polluted by the dielectric material is reduced.