2053 results about "Contact hole" patented technology

A display device includes a substrate including a first contact hole, an etching stopper disposed on a surface of the substrate and including the first contact hole, a metal pattern disposed on another surface opposite to the surface of the substrate and surrounding the first contact hole in a plan view, a first pad unit overlapping a part of the metal pattern and inserted into the first contact hole, a lead line disposed on the another surface of the substrate and electrically connected to another part of the metal pattern, a second pad unit disposed on the another surface of the substrate and electrically connected to the lead line, a protective film overlapping the another surface of the substrate and the lead line, and a protection part overlapping the first pad unit.

The invention discloses a cellular structure of a shield gate trench MOSFET and a manufacturing method thereof, the cellular structure of the shield gate trench MOSFET comprises a substrate, a drift region and an interlayer dielectric layer, the drift region is provided with a deep trench, and the deep trench is internally provided with a shield gate, an intermediate oxide layer and a control gate; a body region and a source region are formed at the upper part of the drift region through injection, the interlayer dielectric is provided with a source electrode contact hole which penetrates through the source region and extends into the body region, and highly doped contact regions are formed on the side wall and the bottom of the source electrode contact hole through injection; and a charge balance region is formed below the source electrode contact hole through high-energy ion implantation. According to the invention, by arranging the charge balance region, the lateral depletion of the shield gate to the adjacent drift region can be enhanced when the shield gate trench MOSFET device is in a reverse bias state, the specific on-resistance of the device is reduced, the depletion of the drift region of the epitaxial layer is accelerated, and the reliability and radiation resistance of the device are improved.

The invention discloses an SJ-MOSFET device. The SJ-MOSFET device comprises a first conductive type substrate; a first conductive type epitaxial layer; a source region; a body region; a second conductive type doped column; the trench gate is arranged on the side surface of the second conductive type doped column and penetrates through the source region and the body region; and the trench pseudo gate is arranged on the side surface of the second conductive type doped column and penetrates through the source region and the body region. On the other hand, the invention discloses a manufacturing method. According to the invention, the grid electrode and the grid electrode groove are arranged on the side surface of the doped column, and a part of the grid electrode groove is arranged in the doped column, so that the area of the grid electrode groove occupying the MESA is small, and the grid electrode groove is arranged towards the interior of the doped column, so that the cell size and the pitch between two source electrode contact holes can be reduced to the greatest extent, and the performance of the MESA is improved. And meanwhile, no JFET resistor exists, so that the optimization of the on-resistance is realized.

The invention provides an electric field enhancement type shield gate MOSFET (Metal-Oxide-Semiconductor Field Effect Transistor), which comprises a substrate, an epitaxial layer formed on the substrate, a gate trench formed on a cellular region on the epitaxial layer, and a first gate dielectric layer formed at the bottom of the gate trench and a first polycrystalline silicon layer located in the first gate dielectric layer, a P-type epitaxial layer is formed on the first gate dielectric layer and the first polycrystalline silicon layer, and an isolation dielectric layer is formed on the P-type epitaxial layer; a second gate dielectric layer is formed on the side wall of the residual gate trench, and a second polycrystalline silicon layer is formed in the residual gate trench; a well region and a source region of a cellular region are formed on the epitaxial layer, and a contact hole dielectric layer is formed on the epitaxial layer; and contact holes communicated with the well region are formed on the contact hole dielectric layer and the epitaxial layer below the contact hole dielectric layer. By adding the shield grid P-type epitaxial layer, the electric field intensity in the middle of the drift region is effectively improved, the breakdown voltage is improved, and meanwhile, the conduction loss can be further reduced by adjusting epitaxy.

The invention discloses a manufacturing method of a semiconductor device, and belongs to the technical field of semiconductors. The manufacturing method comprises the following steps: providing a substrate, forming a dummy gate on the substrate, and forming a hard mask layer on the dummy gate; forming side wall structures on two sides of the dummy gate; forming a contact hole etching stop layer on the substrate, the side wall structure and the pseudo gate, wherein the material of the contact hole etching stop layer is the same as that of the hard mask layer; forming an interlayer dielectric layer on the contact hole etching stop layer, and planarizing the interlayer dielectric layer to the residual preset thickness of the hard mask layer; oxidizing the hard mask layer, a part of the contact hole etching stop layer and a part of the side wall structure to form a surface oxide layer; synchronously removing the surface oxide layer and a part of the interlayer dielectric layer, wherein the surface of the dummy gate is flush with the surfaces of the interlayer dielectric layers on the two sides; and removing the dummy gate to form a metal gate. According to the manufacturing method of the semiconductor device provided by the invention, the height of the formed metal gate can be ensured, the manufacturing process is simple, and the controllability is high.

Various embodiments of improved process flows and methods are provided herein for etching high aspect ratio (HAR) features in carbon-containing hard mask layers. In the disclosed embodiments, the improved process flows and methods combine sidewall passivation and mask de-clogging steps in a single plasma process step to improve throughput when etching HAR features (such as vias, contact holes, trenches, etc.) within a carbon-containing hard mask layer. In doing so, the improved process flows and methods disclosed herein protect the sidewall surfaces of the carbon-containing hard mask layer and prevent bowing during the HAR etch process, while also reducing processing time and improving throughput.

To provide a semiconductor device having a transistor part and a diode part, in which a reverse recovery loss is reduced.SOLUTION: A semiconductor device includes: an interlayer insulating film 38 provided over a semiconductor substrate 10; an emitter electrode 52 being a front surface electrode provided over the semiconductor substrate; contact parts where the front surface electrode and mesa parts 61 to 64 are connected in contact holes 54 of the interlayer insulating film; and a lifetime adjustment region 206 provided on a front surface side of the semiconductor substrate. The contact parts have a first contact part 77 provided in a transistor part, and a second contact part 87 provided in a diode part. The first contact part is disposed over the second contact part.SELECTED DRAWING: Figure 3A

A display device includes first to fourth pixels, wherein each of the first to fourth pixels includes first to third sub-pixels, a first data connection pattern electrically connected to a first data line by a first contact hole and electrically connected to the second sub-pixel of the second pixel, and a second data connection pattern electrically connected to a second data line by a second contact hole and electrically connected to the second sub-pixel of the fourth pixel, wherein, in a plan view, the first contact hole is disposed between the emission area of the third sub-pixel of the first pixel and the emission area of the third sub-pixel of the second pixel, and in a plan view, the first contact hole and the second contact hole are disposed in a row in the second direction.

The invention provides a semiconductor device and a manufacturing method thereof, and the method comprises the steps: providing a substrate, and forming a gate structure, a side wall and an active / drain region on the substrate; forming a protective layer which covers the substrate and at least covers part of the side wall, close to the substrate, of the side wall; removing a part of the side wall which is not covered by the protective layer; removing the protective layer; forming metal silicide on the gate structure and / or the source / drain region; and forming a dielectric layer covering the gate structure, the side wall, the source / drain region and the substrate, and forming a contact hole exposing the metal silicide in the dielectric layer. The stress proximity technology is arranged before the metal silicide is formed, and when part of the side wall is removed, the protection layer is adopted to protect the substrate and part of the side wall close to the substrate, so that the loss of the substrate can be avoided on the basis of improving the filling window and improving the stress, and the reliability of the device is improved. Therefore, the loss of the metal silicide caused by the removal of the side wall is avoided, the etching through phenomenon of the metal silicide is avoided, and finally the performance of the semiconductor device is improved.

The invention discloses a thin film resistor device and a preparation method thereof. The preparation method comprises the following steps: forming a second insulating layer on a first metal interconnection layer and an exposed first insulating layer; forming a thin-film resistor structure in a partial region of the upper surface of the second insulating layer; forming a third insulating layer on the thin-film resistor structure and the exposed upper surface of the second insulating layer; forming a first contact hole extending from the upper surface of the third insulating layer to the first metal interconnection layer, and filling the first contact hole with first contact metal; forming a second metal interconnection layer on the upper surface of the third insulating layer; forming a fourth insulating layer on the second metal interconnection layer and the exposed third insulating layer; and forming a second contact hole extending from the upper surface of the fourth insulating layer to the second metal interconnection layer and a third contact hole extending from the upper surface of the fourth insulating layer to the thin-film resistor structure, and filling second contact metal and third contact metal in the second contact hole and the third contact hole respectively. According to the thin film resistor device and the preparation method thereof, the stability of the device can be improved.

A display device comprises a first substrate including a first contact hole, fan-out lines included in a first metal layer on the first substrate, first and second pad parts exposed to a lower portion of the first substrate, a display layer disposed on the fan-out lines, and a flexible film disposed below the first substrate, inserted into the first contact hole, and electrically connected to the first and second pad parts. The fan-out lines comprise first fan-out lines extending from the first contact hole in a first direction, and second fan-out lines extending from the first contact hole in a direction opposite to the first direction. The first fan-out lines and the first pad parts are integral with each other. The second fan-out lines and the second pad parts are integral with each other.

The utility model discloses a drain-shared double-SGT MOSFET device, and relates to the technical field of semiconductors, the drain-shared double-SGT MOSFET device comprises a substrate and an epitaxial layer, the top surface of the epitaxial layer is provided with a plurality of grooves side by side, the bottom side walls and the inner bottoms of the grooves are provided with shield gate oxide layers, and the shield gate oxide layers on the bottom side walls of the grooves are filled with first polycrystalline silicon; a trench middle shielding oxide layer is deposited at the top end of the first polycrystalline silicon, a gate oxide layer is arranged at the top end of the trench middle shielding oxide layer and located on the side wall of the trench, and the gate oxide layer is filled with second polycrystalline silicon; a source region and a base region are formed between every two adjacent grooves from top to bottom, communicated first top layer contact holes are formed in the source regions and the base regions, the first top layer contact holes are filled with conductive materials to form MOS structures, and connecting layers are formed on the surfaces of the MOS structures; and a groove middle insulating column is vertically arranged in the middle in the groove. According to the utility model, the on-resistance is greatly reduced.

The invention discloses a trench-type power semiconductor device with a gate protrusion structure and a preparation method thereof. The preparation method comprises the following steps: depositing an epitaxial layer on a silicon substrate; sequentially preparing a silicon dioxide cushion layer, a first mask layer and a second mask layer on the epitaxial layer; etching to form a gate trench; forming a gate oxide layer; depositing grid polycrystalline silicon; removing the grid polycrystalline silicon on the surface of the first mask layer through chemical mechanical grinding; etching to remove the first mask layer, and adjusting the morphology of the grid polycrystalline silicon on the silicon platform region; forming a body region and a source region through ion implantation; and preparing a source region contact hole and a tungsten bolt. According to the invention, the grid protrusion structure is formed in the preparation process of the groove type power semiconductor device, the problem that the channel electric leakage is increased after the polycrystalline silicon is etched is solved, the grid resistance is reduced by increasing the cross sectional area of the grid polycrystalline silicon, the switching speed and the linear region capability are improved, and the device performance is optimized.

The invention provides a multilayer heterogeneous material ultrafast laser integrated connection method and device, and the method specifically comprises the steps: stacking and fixing a chip bonding pad, a spring pin and quartz glass on a three-dimensional motion platform, and adjusting the platform to enable a laser focal plane to be located at the center of the pin; aiming at the connection of a bonding pad and a pin, high-repetition-frequency ultrafast laser with a high Rayleigh length is obtained through spatial shaping, a two-dimensional galvanometer is used for carrying out spiral line or concentric circular ring scanning to act on the periphery of the pin, metal plasma is excited, molten metal is formed and deposited in a contact hole of the pin and the bonding pad, and the molten metal is continuously accumulated along with reverse heating, so that the metal is formed. Dissimilar metal welding is achieved; aiming at the connection of the pin and the glass, laser penetrates through the quartz glass, plasma is excited on a metal interface, molten metal with increased volume is formed, a material interface gap is filled, and welding from non-optical contact to optical contact is regulated and controlled; and two heterogeneous materials are successfully welded through single scanning until welding of the whole pin array is completed, and efficient integrated packaging is achieved.

Disclosed is a thin film transistor substrate comprising a substrate; a first thin film transistor on the substrate, the first thin film transistor including a first active layer and a first gate electrode; a second thin film transistor on the substrate, the second thin film transistor including a second active layer and a second gate electrode above the first active layer and the first gate electrode; a first insulating layer between the first gate electrode and the second active layer; and; and a first connection electrode connecting together the first active layer and the second active layer, the first connection electrode extending through a first contact hole in the first insulating layer and is in contact with each of the first active layer and the second active layer and a display apparatus including the same.

A semiconductor device may include a backside wiring line in a first backside interlayer insulating film, a fin-type pattern on the backside wiring line, a second backside interlayer insulating film between the fin-type pattern and the first backside interlayer insulating film, a gate electrode on the fin-type pattern, a first source / drain pattern on a side of the gate electrode, and a backside source / drain contact in a backside contact hole defined by the fin-type pattern and the second backside interlayer insulating film. The backside source / drain contact may connect the backside wiring line and the first source / drain pattern. The backside source / drain contact may include an upper pattern and a lower pattern. The upper pattern may be between the lower pattern and the first source / drain pattern, and may fill at least a portion of the first backside contact hole. The upper pattern may have a single conductive film structure.

According to an aspect, a detection device includes: photodiodes provided on a substrate; transistors corresponding to the photodiodes; a first organic insulating film that covers the transistors; first electrodes that are between the first organic insulating film and the photodiodes in a direction orthogonal to the substrate and are provided corresponding to the photodiodes; a second electrode provided so as to extend across the photodiodes; an insulating film between adjacent first electrodes, and a second organic insulating film that covers an inside of a contact hole provided in the first organic insulating film. The photodiodes includes a first carrier transport layer, an active layer, and a second carrier transport layer that are stacked on the substrate. The first carrier transport layer, the active layer, and the second carrier transport layer are provided so as to cover each of the first electrodes, the insulating film, and the second organic insulating film.

A display device with improved light-emitting efficiency is disclosed. The display device includes a plurality of pixels, a light emitting device provided in each of the pixels, the light emitting device having first and second surfaces which are opposite to each other, first and second electrodes electrically and respectively connected to the first and second surfaces of the light emitting device, and a metal oxide pattern interposed between the second surface of the light emitting device and the second electrode. The metal oxide pattern includes first and second regions. The first region encloses the second region, and the second region has a contact hole exposing at least a portion of the second surface. The second electrode is coupled to the second surface through the contact hole, and the first and second regions have crystalline phases different from each other.

A display apparatus includes a base substrate including a display area and a peripheral area, a conductive layer formed on the base substrate in an entirety of the peripheral area and the display area, a buffer layer on the conductive layer, a thin film transistor on the buffer layer in the display area, an electrode in a contact hole that is formed through the buffer layer to expose a side surface of the conductive layer in the peripheral area, the electrode making contact the conductive layer, an insulating pattern in the contact hole on the electrode, and a wiring on the insulating pattern and electrically connected to the electrode.

A display device includes: a display panel comprising a plurality of light emitting areas; and an input sensing panel including: a first sensing insulating layer on the display panel; a second sensing insulating layer on the first sensing insulating layer and having a first opening and a contact hole; an insulating pattern; and a plurality of conductive patterns including a first conductive layer and a second conductive layer, the first conductive layer includes: a first-first conductive portion in the first opening; and a first-second conductive portion exposed through the contact hole, the second conductive layer includes: a second-first conductive portion electrically connected to the first-first conductive portion; a second-second conductive portion electrically connected to the first-second conductive portion; and a second-third conductive portion spaced apart from the first conductive layer in a plan view, and the insulating pattern is on the second-first conductive portion and in the first opening.

A semiconductor device includes a substrate including a first active region, a bit line on the substrate to cross the first active region, a bit line contact between the bit line and the first active region and in a bit line contact hole extending into the substrate, a bit line contact spacer on a sidewall of the bit line contact within the bit line contact hole, a bit line spacer on a sidewall of the bit line, an anti-oxidation layer between the sidewall of the bit line and the bit line spacer and between the sidewall of the bit line contact and the bit line spacer, and a buried contact in a buried contact hole, passing through the bit line contact spacer, and contacting the first active region, in which the anti-oxidation layer includes a silicon-containing material including SiOx, where 0<x≤2.

The invention provides a micro light emitting diode chip, comprising a micro mesa array comprising a plurality of micro mesas; the light emitting diode is characterized in that each micro-mesa comprises a first type semiconductor layer, a light emitting layer and a second type semiconductor layer which are sequentially stacked from bottom to top; the first type is different from the second type; the bottom metal layer is located at the bottom of the micro mesa; the bottom dielectric layer is located at the bottom of the bottom metal layer; the bottom dielectric layer is provided with a groove; the first bottom contact hole is located in the bottom dielectric layer and located at the bottom of the bottom metal layer, and the first bottom contact hole is in contact with the bottom metal layer; the side wall dielectric layer is positioned on the side wall of the micro mesa and the side wall of the bottom metal layer; the top conductive layer continuously covers the top surfaces of the micro mesas, the surfaces of the side wall cut-off layers and the areas between the adjacent micro mesas; and the second bottom contact structure is positioned in the groove, is positioned in the bottom dielectric layer between the adjacent micro mesas, and is not in contact with the bottom metal layer.

A semiconductor device, including: a semiconductor substrate having a main surface; an interlayer insulating film provided on the main surface of the semiconductor substrate; a contact hole penetrating through the interlayer insulating film to reach the semiconductor substrate; a plug electrode embedded in the contact hole; a first barrier metal provided on the interlayer insulating film, the first barrier metal being apart from the plug electrode; and a front electrode provided on the first barrier metal and the plug electrode.

The invention provides a display device and a method of manufacturing the same. The display device includes a substrate including a first pad electrode and a second pad electrode; a bank defining a first opening through which at least a portion of the first pad electrode and at least a portion of the second pad electrode are exposed; an inter-electrode planarization layer between the first pad electrode and the second pad electrode; a first reflective electrode extending from the bank to the inter-electrode planarization layer along the first pad electrode; a second reflective electrode extending from the bank to the inter-electrode planarization layer along the second pad electrode; an organic pattern layer in the first opening; a light emitting element having a first contact electrode and a second contact electrode on a top surface thereof; a via layer covering the light emitting element and defining a contact hole; a first lead over the via layer and electrically connecting the first contact electrode and the first reflective electrode; and a second lead over the via layer and electrically connecting the second contact electrode and the second reflective electrode.

The invention discloses a high-voltage fast recovery diode with a positive temperature characteristic and a manufacturing method of the high-voltage fast recovery diode. A central region of the device is a P-type doped active region which is used as an anode when the device works in the forward direction; p-type doped field limiting rings are arranged on the two sides of the active region and serve as voltage dividing rings of the device, and the field limiting rings and the active region are doped independently; an N-type doped cut-off ring is arranged on the outermost periphery of the device and provides an electric field cut-off effect; a metal field plate is arranged above each field limiting ring to improve the distribution of a peripheral electric field and improve the stability of the device; except for the position of the contact hole, CVD, silicon nitride and polyimide in the vertical direction of the device are used as passivation layers of the device to isolate the influence of external moisture, charges and the like, so that the reliability of the device is improved; metal is directly deposited above the active region to serve as an anode of the device; and a layer of metal is evaporated on the back of the device after being thinned to serve as a device cathode. A platinum diffusion and electron irradiation process is used as a minority carrier lifetime control technology to adjust the temperature characteristic of the device.

A display device comprises a first substrate comprising an opening, a pad part on the first substrate and exposed through the opening, a second substrate on the pad part and comprising a first contact hole, a first connection line on the second substrate, and inserted into the first contact hole to be connected to the pad part, a second connection line in a layer between the second substrate and the first connection line and connected to the first connection line, a pixel circuit electrically connected to the second connection line, a driver substrate inserted into the opening of the first substrate, and comprising a base part below the pad part and having a side surface tapered from a top surface, and a lead line extending on a bottom surface and the side surface of the base part, and a contact portion electrically connecting the pad part to the lead line.

A display device includes a substrate, a first metal layer on the substrate, a first barrier insulating layer on the first metal layer, an etching control layer on the first barrier insulating layer, a first contact hole passing through the substrate, the first barrier insulating layer, and the etching control layer, a second barrier insulating layer on the etching control layer and including a second contact hole, a fan-out line on the second barrier insulating layer and included in a second metal layer, a pad part inserted into the second contact hole and included in the second metal layer, the pad part integral with the fan-out line, a display layer on the fan-out line, and a flexible film under the substrate and inserted into the first contact hole to be electrically connected to the pad part. The first metal layer includes an etching mark adjacent to the first contact hole.

The invention provides a semiconductor device and a preparation method thereof, and the method comprises the following steps: providing a substrate, forming a gate structure on the substrate, and forming a drain doped region and a source doped region in the substrate at two sides of the gate structure; epitaxial layers are formed on the substrate of the source doped region and the drain doped region, the epitaxial layers are metalized to form a conductive contact layer, and the surface of the conductive contact layer is flush with the surface of the gate structure; an interlayer dielectric layer is formed on the conductive contact layer and the gate structure, a conductive contact hole is formed in the interlayer dielectric layer, and the conductive contact hole penetrates through the interlayer dielectric layer and makes contact with the conductive contact layer and the gate structure so that the gate structure, the source electrode and the drain electrode can be located on the same horizontal plane, the process difficulty of a contact hole photoetching and etching process can be reduced, and the problems occurring in contact hole etching are solved.

The invention provides a chip, a manufacturing method thereof and electronic equipment, the chip comprises a transistor, a metal silicide layer, an etching stop layer, an interlayer dielectric layer and a plurality of first contact holes, the metal silicide layer is at least arranged on a source electrode and a drain electrode of the transistor, and the first contact holes penetrate through the etching stop layer and the interlayer dielectric layer; the chip further comprises a barrier layer, the barrier layer is arranged between the metal silicide layer and the etching stop layer, and under the etching condition of the etching stop layer, the etching rate of the etching stop layer is larger than that of the barrier layer. Therefore, when the etching stop layer is etched, the barrier layer can be prevented from being etched, so that the barrier layer can play a role in stopping etching, the metal silicide layer is prevented from being etched, the metal silicide layer is protected, a source electrode and a drain electrode in the transistor cannot be influenced even if the metal silicide layer is thin, and the reliability of the transistor is improved. And the source electrode and the drain electrode are protected, so that the manufacturing yield of the chip is improved.

The invention relates to a semiconductor device with a temperature sensor and a preparation method thereof, and the key points of the technical scheme are that the method comprises the steps: constructing a super-junction charge balance region on the surface of a substrate, and forming a body region at the top of the super-junction charge balance region; generating a first shallow trench and a second shallow trench on the body region; sequentially depositing an oxidation dielectric layer and first polycrystalline silicon in each of the first shallow trench and the second shallow trench; etching the first polycrystalline silicon in the second shallow trench, and depositing second polycrystalline silicon above the first polycrystalline silicon in the second shallow trench; depositing a dielectric layer on the surface of the body region, and etching in the dielectric layer to form a contact hole; the contact hole is communicated with the first polycrystalline silicon and the second polycrystalline silicon; the temperature detection diode structure is integrated in the epitaxial material of the device, and the problem that the internal thermal characteristics of the device cannot be fed back in time is solved by improving the manufacturing process under the condition that the characteristics of the device are not influenced by utilizing the linear relation between the forward conduction voltage and the temperature of the diode.