217 results about "Contact hole" patented technology

A method for fabricating semiconductor device may include forming a source / drain pattern on a fin-type pattern, forming an etch stop film and an interlayer insulating film on the source / drain pattern, forming a contact hole in the interlayer insulating film, forming a sacrificial liner along a sidewall and a bottom surface of the contact hole, performing an ion implantation process while the sacrificial liner is present, removing the sacrificial liner and forming a contact liner along the sidewall of the contact hole, and forming a source / drain contact on the contact liner. The ion implantation process may include implant impurities into the source / drain pattern. The source / drain contact may be connected to the source / drain pattern.

A display device can include a display panel configured to display an image, and a touchscreen disposed on the display panel, the touchscreen including a first touch routing line layer, an insulating layer covering the first touch routing line layer, a second touch routing line layer disposed on the insulating layer, and a plurality of touch routing lines including a contact hole configured to interconnect the first touch routing line layer and the second touch routing line layer. Also, the plurality of touch routing lines include at least two interlayer structure change sections where interlayer wiring positions of the first touch routing line layer and the second routing line layer are changed.

A method for forming a semiconductor structure, the method comprising: providing a substrate, the substrate having a source region and a drain region formed therein, a drift region formed in the substrate between the source region and the drain region, the drift region being in contact with the drain region, a gate structure formed on a top of the substrate at an interface of the source region and the drift region; forming a first dielectric layer on the top of the substrate at the source region, the drain region and the drift region, the first dielectric layer also covering sidewalls of the gate structure; forming a recess in a middle region of a top surface of the first dielectric layer at the drift region; after forming the recess, forming a first trench in a portion of the first dielectric layer at the drift region, the first trench being in communication with the recess, forming a second trench through the first dielectric layer at the source region and the drain region; forming a field plate contact hole in the first trench, the field plate contact hole covering the first dielectric layer at a bottom of the first trench, forming an interconnection via structure in the second trench, the interconnection via structure being in electrical connection with the source region and the drain region. The thickness uniformity of the first dielectric layer below the bottom of the first trench is improved.

This invention discloses a mercury cadmium telluride infrared detector and its fabrication method. The method innovatively employs negative photoresist and a lift-off process to grow a metal mask and define contact hole patterns. This metal mask layer serves as both an ion implantation mask and a contact hole etching mask, solving the problems of implantation region positioning deviation and size mismatch in traditional processes. It enables ultra-small cell spacing, improves the detector's photoelectric performance and array uniformity, and is suitable for the large-scale fabrication of high-density infrared detector planar arrays.

The present application relates to a display panel and a display device. The display panel is provided with a plurality of first contact holes corresponding to a plurality of first data lines, the first data lines extend into the first contact holes and are connected to pixel driving circuits, and first fan-out lines extend into the first contact holes and are connected to the corresponding first data lines.

Embodiments of the present disclosure relate to a display device, since a storage capacitor provided on a sub-pixel and an active pattern are arranged by using an active layer in which a semiconductor layer and a conductive layer are stacked, an area of the storage capacitor can be efficiently increased, and a method of using an area overlapping a contact hole located on the active pattern as an area of the storage capacitor can be provided. Further, since a position of the contact hole is easily adjusted, by not providing the contact hole on a region adjacent to a driving transistor, a size of the driving transistor can be increased, and an aperture ratio of the sub-pixel can be improved.

A semiconductor device including high-integrated memory cells and a method for fabricating the semiconductor device are provided. The method for fabricating a semiconductor device includes forming an alternating stack of sacrificial pad sheets and inter-pad dielectric layers, which are stacked vertically spaced apart from each other over a substrate; forming preliminary contact holes penetrating the alternating stack; forming sacrificial plugs filling the preliminary contact holes; performing post-treatment processes on the sacrificial plugs and forming sacrificial plug patterns having different heights and sacrificial recesses having different depths; forming contact liner layers on sidewalls of the sacrificial recesses; removing the sacrificial plug patterns and forming contact holes; forming contact plugs filling the contact holes; removing the sacrificial pad sheets and forming pad openings; and forming each pad of a plurality of pads in a different one of the pad openings.

A semiconductor device and a manufacturing method thereof, the method comprising: providing a semiconductor substrate, the semiconductor substrate comprising an active region, a gate structure formed on the active region, and a gate sidewall formed on a sidewall of the gate structure; forming a metal silicide blocking layer; performing a first etching on the metal silicide blocking layer to form a field plate dielectric layer and a sidewall covering layer, the sidewall covering layer covering the gate sidewall; forming a metal silicide layer on a surface of the semiconductor substrate and the gate structure exposed by the metal silicide blocking layer remaining after the first etching; forming an interlayer dielectric layer; and performing a second etching to synchronously form a field plate contact hole and a shared contact hole, the field plate contact hole exposing part of the field plate dielectric layer, and the shared contact hole exposing part of the sidewall covering layer, the metal silicide layer on a top surface of the gate structure, and the metal silicide layer on a top surface of the active region. The application can increase the process window when multiple contact holes are etched together.

A p++-type outer peripheral contact region is provided in an edge termination region and surrounds a periphery of an active region in a rectangular shape having rounded corners, in a plan view. The p++-type outer peripheral contact region faces a gate runner on a front surface of a semiconductor substrate via an insulating layer. In the active region, a p++-type region is provided facing a gate pad on the front surface of the semiconductor substrate via the insulating layer. The p++-type outer peripheral contact region and the p++-type region are provided apart from p++-type contact regions that form source contacts with a source electrode. The p++-type contact regions and contact holes in which the source contacts are formed are disposed in a uniform layout spanning an entire area of the active region so that an end side and a center side of the active region have the same layout.

The application relates to the technical field of image sensors, and provides an image sensor and a manufacturing method.The image sensor comprises a semiconductor substrate, a plurality of pixel regions, a metal interconnection layer and a blocking structure.The blocking structure is composed of an isolation structure arranged in the semiconductor substrate, a crosstalk modulation structure and a first contact hole structure which are sequentially arranged in a dielectric layer and correspond to the isolation structure.The blocking structure can form an effective light blocking wall structure on one hand, preventing light of one pixel region from being reflected by the metal interconnection layer and crosstalking into an adjacent pixel region; and on the other hand, the blocking structure can prevent over-etching of the isolation structure during processing of the first contact hole structure, thereby reducing the enrichment and diffusion of charges in the isolation structure, effectively improving the dark current performance of the device, and simultaneously reducing optical crosstalk and electrical crosstalk of the image sensor, which is conducive to improving the imaging quality of the image sensor.

An array substrate is manufactured by five time patterning processes and includes connecting electrodes. The connecting electrodes include a first connecting electrode and a second connecting electrode. The first connecting electrode is in contact with the source electrode contact area through the first contact hole and in contact with the source electrode through the third contact hole. The second connecting electrode is in contact with the drain electrode contact area through the second contact hole, and in contact with the drain electrode through the fourth contact hole.

An electronic device may include signal lines and pads. Each of the pads may include a first lower conductive pattern on the base layer, a first insulating pattern through which a contact hole is defined to expose a portion of the first lower conductive pattern, the first insulating pattern covering the first lower conductive pattern, a second lower conductive pattern including a first portion covering the first lower conductive pattern exposed through the contact hole and a second portion extending from a side surface of the first insulating pattern, which defines the contact hole, and the first portion to cover an upper surface of the first insulating pattern, a second-first insulating pattern on the first portion, a first upper conductive pattern on the second-first insulating pattern, and a second upper conductive pattern on the first upper conductive pattern and being in contact with the first upper conductive pattern.

A display panel including an interconnection structure and an electronic device including the display panel are disclosed. The display panel includes a substrate, a light emitting diode arranged above the substrate, and a circuit layer between the substrate and the light emitting diode. The circuit layer includes an interconnection structure including a first conductive material layer, a first insulating layer above the first conductive material layer, a first conductor including a side portion on an inner wall of the first insulating layer defining a first contact hole and a lower portion integrally formed with the side portion and directly contacting a portion of an upper surface of the first conductive material layer, an inorganic filler including an inorganic insulating material in a recess surrounded by the side portion, a second insulating layer above the first insulating layer, and a second conductor directly contacting an upper surface of the side portion of the first conductor through a second contact hole in the second insulating layer.

The application provides a medium-high voltage shield gate power device layout and device. By optimizing a gate contact hole connection mode, the first grooves where the gate contact hole areas are located are arranged at intervals, that is, gate polysilicon interval connection gate contact holes. The safety operating area (SOA) performance of the application can be improved by several times. The first grooves where the gate contact hole areas are located can be selected to be separated by several first grooves according to the required safety operating area (SOA) performance. In addition, a mask plate does not need to be increased, and there is a certain advantage in cost.

This application discloses a packaging structure and packaging method, belonging to the field of power electronic device technology. The packaging structure includes: a substrate; a chip disposed on a first surface of the substrate; a pin base disposed on the first surface of the substrate; a molding compound covering the first surface of the substrate and exposing a concave groove of the pin base; a pin, one end of which extends into the concave groove and engages with the pin base; and a printed circuit board (PCB) with contact holes, the other end of which extends into the contact holes and is electrically connected to the PCB. This packaging structure uses pins instead of leads for connection, effectively reducing the risk of failure due to stress concentration and improving module reliability and space utilization.

A display panel capable of displaying a high quality image and an electronic device including the display panel are provided. The display panel includes: a substrate; a first capacitor electrode disposed over the substrate; a second capacitor electrode disposed over the first capacitor electrode, overlapping with the first capacitor electrode when viewed in a direction perpendicular to the substrate, and having a first recessed portion recessed inward at one side of the second capacitor electrode and exposing a portion of the first capacitor electrode when viewed in the direction perpendicular to the substrate; and a first connection electrode disposed over the second capacitor electrode and connected to the first capacitor electrode through a contact hole located in the first recessed portion.

A display panel and a display device are provided. The display panel includes a substrate, which includes a first display area and a second display area adjacent to each other. The first display area includes a plurality of first pixel units and a plurality of transmissive portions between the plurality of first pixel units. Each first pixel unit includes a first light-emitting element configured to emit light of a first color and a transistor for driving the first light-emitting element. The second display area includes a plurality of second pixel units, each second pixel unit including a first conventional light-emitting element configured to emit light of a first color and a transistor for driving the first conventional light-emitting element. The number of contact holes between the first light-emitting elements in the first display area and the transistors for driving the first light-emitting elements is greater than the number of contact holes between the first conventional light-emitting elements in the second display area and the transistors for driving the first conventional light-emitting elements.

The application provides a method for forming a semiconductor structure, comprising: providing a substrate; forming a first insulating medium layer on the substrate; forming a through-silicon via and a contact plug; wherein, before etching a via for forming the through-silicon via and / or a contact hole for forming the contact plug, an intermediate medium layer is formed on the first insulating medium layer; a sacrificial structure is formed in the via or the contact hole before the via or the contact hole is filled with a conductive material, and the intermediate medium layer and the sacrificial structure are sequentially removed; forming a metal layer; wherein, the through-silicon via and the contact plug are both in contact with the metal layer; the height difference between the top surface of the through-silicon via and the top surface of the contact plug in a first direction is less than the thickness of the metal layer in the first direction.

The application provides a semiconductor device and a preparation method thereof. The method comprises the following steps: providing a semiconductor substrate, including a conductive channel region; forming a gate structure on the surface of the semiconductor substrate; forming a mask on the surface opposite to the gate structure, and the mask corresponds to the conductive channel region; the mask is provided with a first recessed part; removing the mask and the gate structure on both sides of the conductive channel region, and the gate structure corresponding to the conductive channel region is formed with a second recessed part; doping the substrate on both sides of the gate structure to form a doped region; forming a metal silicide layer on the surface of the gate structure and the doped region; forming a dielectric layer on the surface of the metal silicide layer, and the dielectric layer is provided with a first contact hole corresponding to the doped region and a second contact hole corresponding to the second recessed part; forming a first metal contact body in the first contact hole and a second metal contact body in the second contact hole. The application can increase the process window of etching the contact hole and reduce the abnormal rate of etching through the metal silicide layer.

This invention provides a semiconductor structure and its manufacturing method. The semiconductor structure includes: a semiconductor substrate on which a gate structure with an internal top recess is formed; a bottom metal structure filling the top recess; an interlayer dielectric layer covering the semiconductor substrate and the surface of the gate structure, with a gate contact hole through which the bottom metal structure is exposed; and a contact metal layer filling the gate contact hole, with its outer sidewalls directly and physically bonded to the inner sidewalls of the interlayer dielectric layer. The manufacturing method includes forming a recess on top of the gate and filling it with the bottom metal structure, followed by forming the interlayer dielectric layer and the contact hole, and finally growing the contact metal layer from bottom to top using a selective deposition process. This invention eliminates the high-resistivity adhesive layer and barrier layer within the contact hole, increases the filling volume of the low-resistivity metal, significantly reduces the gate contact resistance, and improves device performance.

The application relates to the technical field of optoelectronic manufacturing, and particularly discloses a flip LED chip and a preparation method thereof. The flip LED chip comprises a substrate, an epitaxial layer, a first insulating layer, a reflecting layer, a second insulating layer, a P-type metal interconnection layer, an N-type metal interconnection layer, a third insulating layer, a P-type pad layer and an N-type pad layer; the third insulating layer is formed with a first contact hole for exposing the P-type metal interconnection layer and a second contact hole for exposing the N-type metal interconnection layer, and the first contact hole and the second contact hole are formed through a wet etching process; the P-type metal interconnection layer comprises a first bottom layer and a first etching-resistant layer which are stacked in sequence; the N-type metal interconnection layer comprises a second bottom layer and a second etching-resistant layer which are stacked in sequence; and the first etching-resistant layer and the second etching-resistant layer are made of one or more of Cr, Ni, Pt, Au and Ti. The flip LED chip has the advantages of high light-emitting efficiency, low working voltage and high reliability.

This invention discloses a semiconductor device, a power module, and an electronic device, relating to the field of semiconductor technology. The semiconductor device includes a first gate material, a gate, and a dummy gate. The first gate material is connected to a first contact hole. A gate portion is formed on the first gate material and electrically connected to a metal electrode through the first contact hole. A dummy gate is formed between the first gate material and the gate and connected to a second contact hole, electrically connected to a metal electrode through the second contact hole. The dummy gate is disposed at a distance from the first gate material and the gate. The semiconductor device provided by this invention has a second contact hole directly etched on the dummy gate, eliminating the connection method through the gate material and the second contact hole. This avoids the size of the semiconductor device being affected by the minimum dimension between the gate material of the dummy gate and the first gate material, thus facilitating miniaturization design.

A semiconductor device manufacturing method includes: providing a substrate having a memory cell array area; forming a word line trench; forming a word line conductive layer in the word line trench; forming a photoresist on the substrate surface, and patterning it to protect the word line conductive layer in the contact areas but exposes the word line conductive layer outside the word line contact area, and etching the conductive layer. The resulting thickness of the word line conductive structure in the word line contact area is greater than outside the word line contact area. Thereby the opening of the word line contact hole is reduced. The depth of the window position reduces the process time in forming the contact hole, which reduces the excessive erosion of the sidewalls of contact hole having a shallower opening depth, so to avoid the device short circuit.

The application provides a semiconductor device and a preparation method thereof. The preparation method comprises the following steps: providing a semiconductor substrate, wherein a first gate structure is formed on the semiconductor substrate; forming a hard mask layer to form a first sidewall layer and a recess; forming a filling layer in the recess, wherein a gap exists between the part of the filling layer which is higher than the semiconductor substrate and the first sidewall layer; forming a second sidewall material, wherein the second sidewall material fills the gap, and the material of the second sidewall material is silicon oxide; removing part of the thickness of the second sidewall material; forming a third sidewall material, wherein the third sidewall material covers the second sidewall material, and the material of the third sidewall material is silicon nitride; etching the second sidewall material and the third sidewall material to form a second sidewall layer and a third sidewall layer. In this way, the sidewall material with a small dielectric constant is filled into the gap between the filling layer and the gate sidewall, so that the capacitance value of the gate-contact hole (CGC) is reduced, and the device performance is improved.

The application relates to an etching method of a contact hole and a manufacturing method of a DRAM, and belongs to the technical field of semiconductors. The application solves the problems that the existing HARC etching formula only has a time etching step and does not have an EPD etching step, and the wavelength signal emitted during etching of the contact hole is too small to cause the EPD etching to be ineffective. The etching method comprises the following steps: providing a semiconductor substrate, wherein the semiconductor substrate is formed with a conductive component; sequentially forming, from bottom to top, an etching stop layer, a layer to be etched, a first mask layer and a second mask layer above the semiconductor substrate; performing a photoetching process on the second mask layer to form a second mask layer pattern; transferring the second mask layer pattern to the first mask layer to form a first mask layer pattern; and taking the first mask layer pattern as a mask, etching the layer to be etched and the etching stop layer to form a contact hole and expose the conductive component, wherein endpoint detection EPD is adopted in etching of the layer to be etched. The HARC etching menu is realized by improving the EPD etching, and technical prejudice is overcome.

A display device includes a display panel having a plurality of pixels disposed in a display area, a touch sensing unit having a plurality of touch electrodes arranged on a front surface of the display panel, and a touch driving circuit supplying driving signals to the touch electrodes through touch lines and detecting coordinates of a touch position of the touch sensing unit. The touch lines are formed and disposed in a rear surface direction of at least one touch electrode so as to overlap the at least one touch electrode of the touch electrodes. The touch electrodes are respectively connected to the touch lines through at least one touch contact hole, and the touch lines are formed of a same metal material on a same process layer as at least one electrode included in the plurality of pixels formed in the display area.

The application provides a test structure and a test method of a parasitic capacitance. The test structure comprises a first test structure, a second test structure and a third test structure. The first test structure, the second test structure and the third test structure each comprise a gate structure on a substrate, a source-drain structure in the substrate and a contact hole structure. The gate structure is electrically connected to a first test pad and forms a first parasitic capacitance with the substrate. The source-drain structure forms a second parasitic capacitance with the gate structure. The contact hole structure is electrically connected to a second test pad and forms a third parasitic capacitance with the gate structure. The first test structure is used for testing the sum of the first parasitic capacitance and the second parasitic capacitance. The second test structure is used for testing the second parasitic capacitance. The third test structure is used for testing the second parasitic capacitance. The test structure and the test method of the technical solution of the application can test a single parasitic capacitance.