284 results about "Resistive random-access memory" patented technology

The present application discloses a computing-in-memory circuit, chip and electronic device, wherein the computing-in-memory circuit comprises: a resistive random access memory array, a clamping circuit, a current mirror and an analog-to-digital conversion circuit; the clamping circuit is connected between a signal input terminal and the resistive random access memory array, configured to input clamping voltage signal to the N resistive random access memories selected of the resistive random access memory array, wherein N is an integer and N≥2; the current mirror is connected between the resistive random access memory array and the analog-to-digital conversion circuit, configured to output convergence current to the analog-to-digital conversion circuit based on the N-way currents output from the N resistive random access memories selected; the analog-to-digital conversion circuit configured to convert the convergence current to a digital signal.

The invention discloses an analog memristor based on a Ga2O3 / TiO2 heterojunction structure and a preparation method of the analog memristor, and belongs to the field of nonvolatile resistive random access memorizers, the preparation method comprises the following steps: under a vacuum condition, depositing a conductive film on a pretreated insulating substrate by adopting a physical vapor deposition method to serve as a bottom electrode; sequentially depositing a Ga2O3 thin film and a TiO2 thin film on the bottom electrode by adopting a magnetron sputtering method, and constructing a Ga2O3 / TiO2 heterojunction as a resistive layer; and depositing a conductive thin film on the surface of the resistive layer by adopting a physical vapor deposition method to serve as a top electrode to obtain the analog memristor based on the Ga2O3 / TiO2 heterojunction structure. A Ga2O3 semiconductor material with a wide forbidden band and high electron mobility and a TiO2 material with a high dielectric constant, stability and reliability are adopted, and the excellent and high-stability heterojunction memristor is prepared through a specific sputtering process. Bionic behaviors such as synaptic plasticity can be realized, and the method has important application potential in the fields of high-density storage, neural network calculation, biological synaptic simulation and the like.

Provided is a semiconductor structure including a one-transistor-one-capacitor (1T1R) device having an embedded resistive random access memory (ReRAM) with a width greater than 1 gate pitch present at the front or back of the structure, wherein a front-side contact structure is electrically connected to a source region of the transistor of the 1T1R device and a back-side contact structure is electrically connected to a drain region of the transistor of the 1T1R device.

A semiconductor structure including a one-transistor one-capacitor (1T1R) device is provided that includes an embedded resistive random access memory (ReRAM) having a width larger than 1 gate pitch, that is present in a frontside or the backside of the structure, a frontside contact structure electrically connected to a source region of the transistor of the 1T1R device and a backside contact structure electrically connected to a drain region of the transistor of the 1T1R device.

A semiconductor structure is provided that includes a resistive random access memory on a surface of a bit line (28) embedded in a shallow trench isolation structure (12). The structure may also include a source line (SL) over the bit line (28) or embedded in the shallow trench isolation structure (12).

A MRAM circuit is provided in the present invention, wherein each memory cell includes a first transistor with a first gate, a first source and a first drain and the first gate is connected to a first word line, a second transistor with a second gate, a second source and a second drain and a second gate is connected to a second word line, and the second source and the second drain are connected respectively with the first source and the first drain, a first MTJ with one terminal connected to the first source and the second source and another terminal connected to a source line, and a second MTJ with one terminal connected to the first drain and the second drain and another terminal connected to a bit line.

The invention discloses a resistive random access memory structure and a manufacturing method thereof. The resistive random access memory structure comprises a bottom electrode, a resistive random layer and a top electrode which are sequentially stacked from bottom to top, the upper surface of the bottom electrode is in Schottky contact with the lower surface of the resistive layer, and the lower surface of the top electrode is in ohmic contact with the upper surface of the resistive layer; the resistive layer is a single oxide film layer; the bottom electrode and the top electrode are made of the same metal nitride, and the atomic number ratio of metal elements to nitrogen elements in the top electrode is larger than the atomic number ratio of metal elements to nitrogen elements in the bottom electrode. The structure of the memory can be simplified, and the process complexity and the manufacturing cost can be reduced.

The invention discloses an in-memory encryption circuit, encryption method and system based on a resistive random access memory, and relates to the technical field of semiconductors and in-memory encryption, the in-memory encryption circuit comprises an in-memory calculation chip integrating a true random number generator, a physical unclonable function, a logic calculation function and a storage function, the computing macro unit is used for storing and processing bit data containing an encrypted plaintext and a key; the master control unit is used for uniformly managing control signals of the computing macro-units and ensuring cooperative work of the computing macro-units; the switch matrix is used for realizing external input and output of logic signals and data interaction among the computing macro units; and the input and output module is used for realizing external driving and internal driving of the in-memory computing chip and completing signal and data butt joint between the in-memory computing chip and external equipment. According to the method, deep integration of encryption algorithms can be realized, and the security of in-memory encryption is improved while the area overhead is reduced.

The invention discloses a display driving chip. The display driving chip comprises a resistive random access memory module which is used for storing default register information, mura data and burn in data, and the register information is used for configuring a register; a data input interface of the Demura module is connected to the resistive random access memory module, and the Demura module is configured to extract mura data from the resistive random access memory module and perform Demura compensation by using the mura data; a data input interface of the Gamma calibration module is connected to the resistive random access memory module, and the Gamma calibration module is configured to extract burn in data from the resistive random access memory module and perform Deburn in compensation by using the burn in data. Through the scheme of the embodiment of the invention, the requirements of the DDIC and the TDDI on the storage medium in an upgrading iteration scene can be met, and the plug-in device is simplified, so that the power consumption and the production cost of the DDIC / TDDI are further reduced.

The present application relates to a method, device, electronic device, and storage medium for processing a resistive random access memory (RRAM). The method includes: determining whether there is a need to process a RRAM; if there is a need to process a RRAM, performing a forward forming operation on the RRAM to be processed to obtain a RRAM after forward processing; if the conductance of the RRAM after forward processing is greater than or equal to a first preset conductance threshold, repeatedly applying a first RESET pulse to the RRAM after forward processing until the conductance of the RRAM after forward processing is less than the first preset conductance threshold, thereby obtaining a RRAM after reverse processing; and repeatedly applying a second RESET pulse to the RRAM after reverse processing until the conductance of the RRAM after reverse processing is greater than the second preset conductance threshold, thereby obtaining a target RRAM. This solves the problem of relaxation of the target memory after programming and enhances the stability of the conductance state of the RRAM after programming.

The application discloses a homopolymolybdate hybrid resistive random access memory material based on a tetraphenylstyrene molecule and a preparation method and application thereof. The preparation method comprises the following steps: dissolving a mixture of 0.05 mmol of homopolymolybdate and 0.1 mmol of the tetraphenylstyrene molecule in 10 mL of water, stirring for 2 hours, adjusting the pH to 5.0 by using HCl to obtain a mixed solution; moving the mixed solution into a 25 mL stainless steel reaction kettle lined with polytetrafluoroethylene, reacting at 160 DEG C for 3 days, and obtaining a colorless block crystal after cooling; and after filtration, washing and drying, the homopolymolybdate hybrid resistive random access memory material based on the tetraphenylstyrene molecule is obtained. The method is simple and easy to operate, raw materials are easy to obtain, and the method is easy to realize. No harmful product is generated in the preparation process, and the method is an environment-friendly green synthesis. A multi-level controllable memory storage material is prepared, and the material can be applied to a multi-level memristor.

The invention discloses an electroencephalogram signal classification method, device and equipment and a medium, and is applied to the field of signal processing.The electroencephalogram signal classification method comprises the steps that nonlinear features of target electroencephalogram signals are mapped to a two-dimensional plane, and a recurrence plot of the target electroencephalogram signals is obtained; performing recursive quantitative analysis on the recursive plot to obtain quantitative data of the target electroencephalogram signal; the target electroencephalogram signals are classified by utilizing a pre-trained electroencephalogram signal classification model in combination with the quantized data, a classification result of the target electroencephalogram signals is obtained, the electroencephalogram signal classification model is constructed based on a resistive random access memory array, and the resistive random access memory array comprises a first column used for storing positive weights and a second column used for storing negative weights. According to the method, the nonlinear features in the target electroencephalogram signals can be fully combined, the classification accuracy and classification efficiency of the target electroencephalogram signals can be improved, and the electroencephalogram signals of the epileptic in different states can be accurately classified from a large number of electroencephalogram signals.

The application relates to the field of resistive random access memory (RRAM), and specifically discloses a total dose radiation test method for RRAM, which comprises the following steps: grouping a plurality of RRAMs to obtain M groups of RRAMs, each group of RRAMs comprising N RRAMs, and the M groups of RRAMs corresponding to M initial resistance states respectively; performing a total dose radiation experiment on the M groups of RRAMs; and performing a cycle endurance experiment on the M groups of RRAMs, wherein the result of the cycle endurance experiment is used to indicate a test result of the RRAMs related to the total dose radiation. Through the test method, the change in the endurance of the RRAMs after being subjected to total dose radiation can be simulated, so as to provide an optimization scheme for the application of the RRAMs in a total dose radiation environment.

The invention belongs to the technical field of semiconductors, discloses a silicon carbide substrate Mn-doped gallium oxide-based resistive random access memory and a preparation method thereof, and solves the problems of difficult thermal management, insufficient substrate heat dissipation capability, to-be-improved switch ratio, complex preparation process and the like of the existing gallium oxide resistive random access memory. The resistive random access memory comprises a SiC substrate, a Mn-doped beta-Ga2O3 thin film, a tungsten electrode layer and a top electrode, wherein the tungsten electrode layer is superposed on a first surface of the SiC substrate, and the Mn doped beta-Ga2O3 thin film is superposed on a second surface of the SiC substrate; and the top electrode is formed on the Mn doped beta-Ga2O3 thin film.

A memory device includes a first memory array including a plurality of first memory bits. Each of the plurality of first memory bits is configured as a one-time-programmable (OTP) memory bit. A second memory array includes a plurality of second memory bits, each of the plurality of second memory bits being configured as a multi-time-programmable (MTP) memory bit. A lock bit circuit operatively coupled to the first memory array and not the second memory array. The lock bit circuit is configured to generate a lock bit indicative of whether at least one of the plurality of first memory bits has been programmed.

Provided are a resistive random-access memory (RRAM)-based blood test system and method. The system comprises: a computing chip, an RRAM chip, a power supply module, and a sensor module; the computing chip is connected to the RRAM chip; the RRAM chip is connected to the sensor module; and the power supply module is connected to the computing chip and the RRAM chip; the sensor module is configured to test a substance in blood and convert test result data into a plurality of pieces of first voltage data; the RRAM chip is configured to preprocess the received plurality of pieces of first voltage data and obtain second current data; and the computing chip is configured to, based on the second current data, perform a function computation on the second current data according to a preset function computation model, and obtain a blood-based classification result.

The present invention discloses an embedded storage structure, a resistive random access memory and a method for preparing the same, belonging to the field of semiconductors. The present invention first prepares a first intermetallic dielectric layer on an interlayer dielectric layer of a first semiconductor structure; prepares a first metal circuit and a first electrode plate in the first intermetallic dielectric layer; continues to prepare a first barrier layer; uses an etching process to open the first intermetallic dielectric in an area on one side of the first electrode plate to form a first groove; deposits resistive random access material and conductive metal material in sequence; flattens and rests on the first barrier layer to obtain an embedded storage structure. The present invention prepares a resistive random access memory unit that changes the orientation of the electrode plate through a completely new process sequence, and prepares a resistive random access memory using this structure, making the resistive random access memory compact as a whole and compatible with the MOS process in the prior art. After simulation verification, the present invention has strong reliability and operability, and has a high production yield.

A method includes causing a first information bit to be written into a first bit cell in a first plurality of bit cells as an original logic state of the first information bit. The method also includes causing a second information bit to be written into a second bit cell in a second plurality of bit cells as an original logic state of the second information bit. The method also includes causing a third information bit to be written into a third bit cell in a third plurality of bit cells as a logically complementary state of the first information bit.

Structures including an access transistor and a resistive memory element, and methods of forming such structures. The structure comprises an access transistor including a semiconductor layer, a first source / drain region, a second source / drain region, a gate dielectric layer on the semiconductor layer, and a gate electrode overlapped with the gate dielectric layer. The gate dielectric layer has a first portion with a first thickness adjacent to the first source / drain region and a second portion with a second thickness adjacent to the second source / drain region, and the first thickness is greater than the second thickness. The structure further comprises a resistive memory element that is coupled to the first source / drain region of the access transistor.

This application provides a neural network system and a neural network calculation method, relating to the field of electronic technology, which can save chip area and power consumption. The neural network system includes a first memristor array, multiple current-to-voltage converters, and multiple resistive random access memories (RRAMs). The first memristor array includes multiple rows and columns of memristors for receiving first input data and performing multiplication and addition operations on the first input data according to configured first weights to obtain current. Each current-to-voltage converter is connected to the output terminal of at least one column of memristors in the first memristor array, for receiving the current of the corresponding column of memristors and converting the received current into voltage. Each RRAM is connected to at least one current-to-voltage converter, for receiving the voltage of the corresponding current-to-voltage converter, and obtaining one of the calculation results from the first calculation results based on the received voltage and the initial resistance state of the corresponding RRAM. The initial resistance state of each RRAM is a high resistance state.

The present disclosure provides mechanisms for reducing and suppressing random telegraph noise (RTN) in crossbar circuits. The processing device may perform a programming process to program a resistive random access memory (RRAM) device in the crossbar circuit to a target conductance value. The processing device may then determine whether a telegraph noise (RTN) value associated with the RRAM device is within a predetermined range of acceptable RTN values. If the RTN value associated with the RRAM device is not within a predetermined range of acceptable RTN values, one or more noise reduction voltages may be applied to the RRAM device until the RTN value associated with the RRAM device is within the predetermined range of acceptable RTN values.

A semiconductor device capable of increasing readout margin in a nonvolatile resistive random access memory is provided. A clamping circuit applies fixed potential to each of a memory element and a reference resistive element. A pre-charge circuit pre-charges first and second nodes to power-source potential. A sense amplifier amplifies the potential difference between the potential of the first node and the potential of the second node generated after a discharge period based on cell current and reference current after pre-charging made by the pre-charge circuit. A third node is coupled to the first and second nodes through a capacitor. An electric-charge supply circuit is connected to the third node, and supplies electric charge to the third node in the discharge period.

Provided in the present application are an electroencephalogram signal classification method and apparatus, and a device. The method comprises: a first resistive random access memory in a resistive random access memory array acquiring an electroencephalogram signal to be classified, and extracting a signal feature of said electroencephalogram signal; when the similarity between the signal feature and a preset normal electroencephalogram signal feature is not greater than a preset threshold value, calling a target operation program and a target weight value that corresponds to each signal abnormality type to process said electroencephalogram signal, so as to obtain an electric-current feature value corresponding to each target weight value; and determining a signal abnormality type corresponding to the largest electric-current feature value among all electric-current feature values to be a target signal abnormality type of said electroencephalogram signal, wherein the target weight value is the difference between a first weight value and a second weight value that correspond to a signal abnormality type. By means of the present application, the data processing volume and power consumption of a neural network are effectively reduced, and the classification efficiency is improved.

The application provides a pulse neural network structure, comprising a first neuron, a synaptic unit and a second neuron connected in sequence, and a probability selection unit connected with the first neuron, the probability selection unit is used for generating a random number, the first neuron is used for determining a required action of the synaptic unit as a long-term potentiation action or a long-term depression action according to an actual time difference of a first pulse emitted by the first neuron and a second pulse emitted by the second neuron, when the random number is a preset random number, an adjusting pulse is sent to the synaptic unit according to the required action of the synaptic unit, the synaptic unit is used for storing a synaptic weight, and the synaptic weight is adjusted according to the adjusting pulse. In the embodiment of the application, the probability selection unit is designed based on a resistive random access memory, a large amount of resources is saved, and the stability is relatively high without depending on the device characteristics of the resistive random access memory, so that higher device consistency can be realized by using limited resources.

The application discloses a two-dimensional resistance change memory and a preparation method thereof. 2‑x O x The materials of the first resistance change layer and the second resistance change layer are MoS2 and MoO3 respectively, the oxygen concentration difference between the first resistance change layer and the second resistance change layer facilitates oxygen ion migration, and the interface oxide layer between the top electrode and the second resistance change layer provides an oxygen ion source. The technical scheme of the application solves the problems of a small on-off ratio and high power consumption of the existing resistance change memory.

Aspects of the present disclosure provide a method of fabricating a resistive random access memory (RRAM). For example, the method can include providing a substrate, forming a first electrode on the substrate, and forming a first metal oxide layer on the first electrode. The first metal oxide layer can act as a sink or reservoir of oxygen atoms that interact with a current conducting filament. The method can further include forming a second metal oxide layer on the first metal oxide layer. The second metal oxide layer can be configured to form conduction paths. The method can further include forming a second electrode on the second metal oxide layer. In an embodiment, the first metal oxide layer can be formed on a portion of the first electrode.

A fabricating method of a resistive random access memory unit with one-way conduction characteristic includes performing an initializing step, a forming step and a reverse resetting step. The initializing step includes providing the resistive random access memory unit. The forming step includes applying a setting voltage on a lower metal layer, and coupling an upper metal layer to a ground voltage to transform the resistive random access memory unit to a low resistive state. The reverse resetting step includes coupling the lower metal layer to the ground voltage and applying a resetting voltage to the upper metal layer to transform the resistive random access memory unit to a one-way conduction state. A forward reading current is greater than a reverse reading current, and the forward reading current is less than 3000 times of the reverse reading current.

A method of manufacturing a resistive random access memory includes the following steps. An interlayer dielectric layer is formed on a semiconductor substrate. A first conductive material layer is formed in a through hole of the interlayer dielectric layer. At least one interface layer is formed in the through hole. The interface layer covers a bottom surface of the first conductive material layer and exposes a portion of a side surface of the first conductive material layer. A resistive material layer is formed in the through hole and covers the interface layer and the first conductive material layer. A second conductive material layer is formed in the through hole and covers the resistive material layer. A planarization is performed on the first conductive material layer, the resistive material layer and the second conductive material layer to form an embedded resistive random access memory in the through hole.

A method for fabricating a resistive random access memory (RRAM) includes the steps of first forming an interlayer dielectric (ILD) layer on a substrate, forming a first stop layer on the ILD layer, forming a recess in the first stop layer, forming a bottom electrode in the recess, forming a metal oxide layer on the bottom electrode, forming a top electrode on the metal oxide layer, patterning the top electrode and the metal oxide layer, and then forming a spacer adjacent to the top electrode and the metal oxide layer.