384 results about "Resistive random-access memory" patented technology

The invention provides a resistive random access memory ReRAM data judgment method based on sneak path correlation. The method comprises the implementation steps that parameters are initialized; calculating a reading resistance value of the ReRAM storage unit; classifying the ReRAM storage units based on the sneak path correlation; calculating a log-likelihood ratio and a judgment threshold of each type of storage unit; and obtaining a ReRAM data judgment result. The storage units are classified according to the sneak path correlation values of the row and the column where each storage unit is located, and the likelihood ratio function of each category of storage units is calculated according to the conditional probability distribution of the resistance value read by the storage data of each storage unit under different value conditions. According to the method for calculating the likelihood ratio function by using the sneak path correlation, the influence of the difference of interference suffered by different storage units on the bit error rate is fully considered, and the judgment precision is effectively improved.

The present application discloses a computing-in-memory circuit, chip and electronic device, wherein the computing-in-memory circuit comprises: a resistive random access memory array, a clamping circuit, a current mirror and an analog-to-digital conversion circuit; the clamping circuit is connected between a signal input terminal and the resistive random access memory array, configured to input clamping voltage signal to the N resistive random access memories selected of the resistive random access memory array, wherein N is an integer and N≥2; the current mirror is connected between the resistive random access memory array and the analog-to-digital conversion circuit, configured to output convergence current to the analog-to-digital conversion circuit based on the N-way currents output from the N resistive random access memories selected; the analog-to-digital conversion circuit configured to convert the convergence current to a digital signal.

A semiconductor structure comprises a first transistor, a second transistor vertically stacked over the first transistor, a source / drain region shared between the first transistor and the second transistor, and a resistive random-access memory device connected to the shared source / drain region.

A resistive random access memory is provided including an asymmetrical or symmetrical bottom electrode which has an angled profile which forms an interface with a memory switching layer. The angled profile can include a slanted surface or one including a plurality of slanted surfaces that converge into a point. Bottom electrodes having such angled profiles provide more forming area, which can reduce forming voltage without area penalty. In some embodiments in which the slanted surfaces converge into a point, bottom electrodes having such an angled profile can also provide a more controlled area for the forming process to occur.

The embodiment of the invention provides a resistive random access memory device and a manufacturing method and an operation method thereof. The resistive random access memory device comprises a substrate structure and a memory stack structure, the storage stack structure is arranged on one side of the substrate structure and comprises a first electrode, a second electrode, a resistance change reaction layer and an interface layer, the resistance change reaction layer is located between the first electrode and the second electrode and is configured to be converted from a first resistance state to a second resistance state when a level higher than that of the first electrode is applied to the second electrode, and the interface layer is configured to be connected with the first resistance state. When a level higher than that of the second electrode is applied to the first electrode, the resistance change reaction layer is converted from the second resistance state to the first resistance state, and the resistance of the resistance change reaction layer in the first resistance state is higher than that in the second resistance state; the interface layer is located between the first electrode and the resistive reaction layer and serves as an oxygen diffusion barrier layer. By arranging the interface layer, the erasing resistance and the device performance of the resistive random access memory device can be improved.

The invention discloses an analog memristor based on a Ga2O3 / TiO2 heterojunction structure and a preparation method of the analog memristor, and belongs to the field of nonvolatile resistive random access memorizers, the preparation method comprises the following steps: under a vacuum condition, depositing a conductive film on a pretreated insulating substrate by adopting a physical vapor deposition method to serve as a bottom electrode; sequentially depositing a Ga2O3 thin film and a TiO2 thin film on the bottom electrode by adopting a magnetron sputtering method, and constructing a Ga2O3 / TiO2 heterojunction as a resistive layer; and depositing a conductive thin film on the surface of the resistive layer by adopting a physical vapor deposition method to serve as a top electrode to obtain the analog memristor based on the Ga2O3 / TiO2 heterojunction structure. A Ga2O3 semiconductor material with a wide forbidden band and high electron mobility and a TiO2 material with a high dielectric constant, stability and reliability are adopted, and the excellent and high-stability heterojunction memristor is prepared through a specific sputtering process. Bionic behaviors such as synaptic plasticity can be realized, and the method has important application potential in the fields of high-density storage, neural network calculation, biological synaptic simulation and the like.

Provided is a semiconductor structure including a one-transistor-one-capacitor (1T1R) device having an embedded resistive random access memory (ReRAM) with a width greater than 1 gate pitch present at the front or back of the structure, wherein a front-side contact structure is electrically connected to a source region of the transistor of the 1T1R device and a back-side contact structure is electrically connected to a drain region of the transistor of the 1T1R device.

A semiconductor structure including a one-transistor one-capacitor (1T1R) device is provided that includes an embedded resistive random access memory (ReRAM) having a width larger than 1 gate pitch, that is present in a frontside or the backside of the structure, a frontside contact structure electrically connected to a source region of the transistor of the 1T1R device and a backside contact structure electrically connected to a drain region of the transistor of the 1T1R device.

The invention discloses a sensing, storage and calculation integrated three-dimensional integrated chip, a preparation method of the sensing, storage and calculation integrated three-dimensional integrated chip and a calculation method of the sensing, storage and calculation integrated three-dimensional integrated chip. The sensing memory unit comprises a stacked resistive random access memory device group, a sensing device and a gating device; the stacked resistive random access memory device group comprises at least two resistive random access memory devices which are stacked in the thickness direction; the sensing device is used for receiving an external signal and converting the external signal into an input signal, and the output end of the sensing device is coupled with the top electrode of the stacked resistive random access memory device group; the gating device is configured to receive a control signal and switch on and off according to the control signal, and the gating device is coupled with the top electrode of the stacked resistive random access memory device group; wherein the stacked resistive random access memory device group is arranged between the sensing device and the gating device along the width direction, and the at least two resistive random access memory devices share one top electrode, so that the at least two resistive random access memory devices synchronously receive an input signal or are synchronously switched on and off.

The present application discloses a resistive random access memory and an erasing compilation method, a chip, and an electronic device. The erasing compilation method for the resistive random access memory comprises: performing a first erasing compilation operation on memory cells of the resistive random access memory; when the first erasing compilation operation ends and a preset waiting time has elapsed, verifying the memory cells for which the first erasing compilation operation ends, so as to determine problematic memory cells among the memory cells for which the first erasing compilation operation ends; and performing a second erasing compilation operation on the problematic memory cells. The erasing compilation method in the present application can improve the accuracy and integrity of the erasing operation, reduce the erasing failure rate, and thus enhance the durability of the resistive random access memory.

A semiconductor structure is provided that includes a resistive random access memory on a surface of a bit line (28) embedded in a shallow trench isolation structure (12). The structure may also include a source line (SL) over the bit line (28) or embedded in the shallow trench isolation structure (12).

A MRAM circuit is provided in the present invention, wherein each memory cell includes a first transistor with a first gate, a first source and a first drain and the first gate is connected to a first word line, a second transistor with a second gate, a second source and a second drain and a second gate is connected to a second word line, and the second source and the second drain are connected respectively with the first source and the first drain, a first MTJ with one terminal connected to the first source and the second source and another terminal connected to a source line, and a second MTJ with one terminal connected to the first drain and the second drain and another terminal connected to a bit line.

The invention discloses a resistive random access memory structure and a manufacturing method thereof. The resistive random access memory structure comprises a bottom electrode, a resistive random layer and a top electrode which are sequentially stacked from bottom to top, the upper surface of the bottom electrode is in Schottky contact with the lower surface of the resistive layer, and the lower surface of the top electrode is in ohmic contact with the upper surface of the resistive layer; the resistive layer is a single oxide film layer; the bottom electrode and the top electrode are made of the same metal nitride, and the atomic number ratio of metal elements to nitrogen elements in the top electrode is larger than the atomic number ratio of metal elements to nitrogen elements in the bottom electrode. The structure of the memory can be simplified, and the process complexity and the manufacturing cost can be reduced.

The invention discloses an in-memory encryption circuit, encryption method and system based on a resistive random access memory, and relates to the technical field of semiconductors and in-memory encryption, the in-memory encryption circuit comprises an in-memory calculation chip integrating a true random number generator, a physical unclonable function, a logic calculation function and a storage function, the computing macro unit is used for storing and processing bit data containing an encrypted plaintext and a key; the master control unit is used for uniformly managing control signals of the computing macro-units and ensuring cooperative work of the computing macro-units; the switch matrix is used for realizing external input and output of logic signals and data interaction among the computing macro units; and the input and output module is used for realizing external driving and internal driving of the in-memory computing chip and completing signal and data butt joint between the in-memory computing chip and external equipment. According to the method, deep integration of encryption algorithms can be realized, and the security of in-memory encryption is improved while the area overhead is reduced.

The invention discloses a stability-enhanced flexible self-supporting resistive random access memory and a preparation method thereof. The preparation method comprises the following steps: synthesizing MXene solid powder by taking MAX-phase Ti3AlC2 powder as a raw material; carrying out suction filtration by using MXene solid powder to obtain a bottom electrode composed of an MXene self-supporting film; preparing an oxide thin film on the MXene self-supporting thin film to form an oxide semiconductor layer; and preparing a top electrode on the upper surface of the oxide semiconductor layer. The flexible MXene self-supporting thin film is used as the bottom electrode to be applied to the resistive random access memory, so that the flexibility, the conductivity and the long-term stability of the resistive random access memory can be remarkably improved.

A memory device includes a trench to a first conductive structure; a first electrode comprising a conformal conductive material within the trench, the first electrode in electrical communication with the first conductive structure and present on a sidewall of the trench; the switch layer exists in the groove on the first electrode and extends to the outside of the groove; and a second electrode on the switching layer and overfilling the trench. The memory device also includes a contact on a portion of the second electrode that overfills the trench such that the contact is horizontally offset from the first electrode present within the trench.

The invention discloses a high-entropy oxide / tungsten oxide heterojunction memristor and a method and application thereof, and belongs to the technical field of nonvolatile resistive random access memories. The reverse self-current-limiting analog memristor with the heterojunction structure structurally comprises a bottom conductive electrode, a functional layer and an upper conductive electrode from bottom to top, the functional layer is composed of a high-entropy oxide film and a tungsten oxide film. And continuously depositing a second conductive film on the functional layer by adopting a physical vapor deposition mode to serve as an upper conductive electrode to obtain the reverse self-current-limiting memristor with the high-entropy oxide / tungsten oxide heterojunction structure. The structure and the preparation process are simple, and the material cost is low; the self-current-limiting characteristic can reduce the energy consumption of the device and the overheating risk of the device by inhibiting the current overshoot, and improves the reliability and integration density of the device, thereby supporting a storage and calculation integrated neural state architecture, reducing the data migration between a calculation unit and a storage unit, and improving the reliability of the device. And a hardware basis is provided for efficient real-time sensing and multi-modal information fusion.

The invention discloses a display driving chip. The display driving chip comprises a resistive random access memory module which is used for storing default register information, mura data and burn in data, and the register information is used for configuring a register; a data input interface of the Demura module is connected to the resistive random access memory module, and the Demura module is configured to extract mura data from the resistive random access memory module and perform Demura compensation by using the mura data; a data input interface of the Gamma calibration module is connected to the resistive random access memory module, and the Gamma calibration module is configured to extract burn in data from the resistive random access memory module and perform Deburn in compensation by using the burn in data. Through the scheme of the embodiment of the invention, the requirements of the DDIC and the TDDI on the storage medium in an upgrading iteration scene can be met, and the plug-in device is simplified, so that the power consumption and the production cost of the DDIC / TDDI are further reduced.

There is provided a semiconductor structure including a single transistor single capacitor (1T1R) device including: an embedded resistive random access memory (ReRAM) having a width greater than 1 gate pitch, present at a front side or a back side of the structure; a front side contact structure electrically connected to a source region of the transistor of the 1T1R device; and a backside contact structure electrically connected to the drain region of the transistor of the 1T1R device.

The present application relates to a method, device, electronic device, and storage medium for processing a resistive random access memory (RRAM). The method includes: determining whether there is a need to process a RRAM; if there is a need to process a RRAM, performing a forward forming operation on the RRAM to be processed to obtain a RRAM after forward processing; if the conductance of the RRAM after forward processing is greater than or equal to a first preset conductance threshold, repeatedly applying a first RESET pulse to the RRAM after forward processing until the conductance of the RRAM after forward processing is less than the first preset conductance threshold, thereby obtaining a RRAM after reverse processing; and repeatedly applying a second RESET pulse to the RRAM after reverse processing until the conductance of the RRAM after reverse processing is greater than the second preset conductance threshold, thereby obtaining a target RRAM. This solves the problem of relaxation of the target memory after programming and enhances the stability of the conductance state of the RRAM after programming.

The application discloses a homopolymolybdate hybrid resistive random access memory material based on a tetraphenylstyrene molecule and a preparation method and application thereof. The preparation method comprises the following steps: dissolving a mixture of 0.05 mmol of homopolymolybdate and 0.1 mmol of the tetraphenylstyrene molecule in 10 mL of water, stirring for 2 hours, adjusting the pH to 5.0 by using HCl to obtain a mixed solution; moving the mixed solution into a 25 mL stainless steel reaction kettle lined with polytetrafluoroethylene, reacting at 160 DEG C for 3 days, and obtaining a colorless block crystal after cooling; and after filtration, washing and drying, the homopolymolybdate hybrid resistive random access memory material based on the tetraphenylstyrene molecule is obtained. The method is simple and easy to operate, raw materials are easy to obtain, and the method is easy to realize. No harmful product is generated in the preparation process, and the method is an environment-friendly green synthesis. A multi-level controllable memory storage material is prepared, and the material can be applied to a multi-level memristor.

The invention discloses an electroencephalogram signal classification method, device and equipment and a medium, and is applied to the field of signal processing.The electroencephalogram signal classification method comprises the steps that nonlinear features of target electroencephalogram signals are mapped to a two-dimensional plane, and a recurrence plot of the target electroencephalogram signals is obtained; performing recursive quantitative analysis on the recursive plot to obtain quantitative data of the target electroencephalogram signal; the target electroencephalogram signals are classified by utilizing a pre-trained electroencephalogram signal classification model in combination with the quantized data, a classification result of the target electroencephalogram signals is obtained, the electroencephalogram signal classification model is constructed based on a resistive random access memory array, and the resistive random access memory array comprises a first column used for storing positive weights and a second column used for storing negative weights. According to the method, the nonlinear features in the target electroencephalogram signals can be fully combined, the classification accuracy and classification efficiency of the target electroencephalogram signals can be improved, and the electroencephalogram signals of the epileptic in different states can be accurately classified from a large number of electroencephalogram signals.

The application relates to the field of resistive random access memory (RRAM), and specifically discloses a total dose radiation test method for RRAM, which comprises the following steps: grouping a plurality of RRAMs to obtain M groups of RRAMs, each group of RRAMs comprising N RRAMs, and the M groups of RRAMs corresponding to M initial resistance states respectively; performing a total dose radiation experiment on the M groups of RRAMs; and performing a cycle endurance experiment on the M groups of RRAMs, wherein the result of the cycle endurance experiment is used to indicate a test result of the RRAMs related to the total dose radiation. Through the test method, the change in the endurance of the RRAMs after being subjected to total dose radiation can be simulated, so as to provide an optimization scheme for the application of the RRAMs in a total dose radiation environment.

A method of fabricating a resistive random-access memory (RRAM) structure includes forming a first patterned metallization layer; disposing a dielectric layer on the first patterned metallization layer; and etching openings exposing first contact portions of the first patterned metallization layer, each opening having an annular tapered sidewall tapering inward to a corresponding one of the first contact portions. The method further includes disposing a RRAM layer stack over the dielectric layer and conformally in the openings, etching the RRAM layer stack to form mutually isolated RRAM cells, each RRAM cell comprising a portion of the RRAM layer stack remaining after the etching and disposed entirely inside a corresponding opening; disposing an interlayer dielectric (ILD) material over the dielectric layer and over the RRAM cells; forming conductive vias passing through the ILD material and contacting the RRAM cells; and forming a second patterned metallization layer on the ILD material and electrical connecting with the conductive vias.

The invention belongs to the technical field of semiconductors, discloses a silicon carbide substrate Mn-doped gallium oxide-based resistive random access memory and a preparation method thereof, and solves the problems of difficult thermal management, insufficient substrate heat dissipation capability, to-be-improved switch ratio, complex preparation process and the like of the existing gallium oxide resistive random access memory. The resistive random access memory comprises a SiC substrate, a Mn-doped beta-Ga2O3 thin film, a tungsten electrode layer and a top electrode, wherein the tungsten electrode layer is superposed on a first surface of the SiC substrate, and the Mn doped beta-Ga2O3 thin film is superposed on a second surface of the SiC substrate; and the top electrode is formed on the Mn doped beta-Ga2O3 thin film.

A memory device includes a first memory array including a plurality of first memory bits. Each of the plurality of first memory bits is configured as a one-time-programmable (OTP) memory bit. A second memory array includes a plurality of second memory bits, each of the plurality of second memory bits being configured as a multi-time-programmable (MTP) memory bit. A lock bit circuit operatively coupled to the first memory array and not the second memory array. The lock bit circuit is configured to generate a lock bit indicative of whether at least one of the plurality of first memory bits has been programmed.

Provided are a resistive random-access memory (RRAM)-based blood test system and method. The system comprises: a computing chip, an RRAM chip, a power supply module, and a sensor module; the computing chip is connected to the RRAM chip; the RRAM chip is connected to the sensor module; and the power supply module is connected to the computing chip and the RRAM chip; the sensor module is configured to test a substance in blood and convert test result data into a plurality of pieces of first voltage data; the RRAM chip is configured to preprocess the received plurality of pieces of first voltage data and obtain second current data; and the computing chip is configured to, based on the second current data, perform a function computation on the second current data according to a preset function computation model, and obtain a blood-based classification result.

The present invention discloses an embedded storage structure, a resistive random access memory and a method for preparing the same, belonging to the field of semiconductors. The present invention first prepares a first intermetallic dielectric layer on an interlayer dielectric layer of a first semiconductor structure; prepares a first metal circuit and a first electrode plate in the first intermetallic dielectric layer; continues to prepare a first barrier layer; uses an etching process to open the first intermetallic dielectric in an area on one side of the first electrode plate to form a first groove; deposits resistive random access material and conductive metal material in sequence; flattens and rests on the first barrier layer to obtain an embedded storage structure. The present invention prepares a resistive random access memory unit that changes the orientation of the electrode plate through a completely new process sequence, and prepares a resistive random access memory using this structure, making the resistive random access memory compact as a whole and compatible with the MOS process in the prior art. After simulation verification, the present invention has strong reliability and operability, and has a high production yield.

To provide a method for manufacturing a resistance change type random access memory (RRAM) element that does not require formation processes.SOLUTION: A method for manufacturing an RRAM element that can be switched to a plurality of resistance levels without forming processes includes the steps of manufacturing an RRAM cell and annealing the RRAM cell. An RRAM cell 300 includes a bottom electrode 310, an oxide switching layer 330 including at least one transition metal oxide, a top electrode 350, and an interface layer 340 between the oxide switching layer and the top electrode. The at least one transition metal oxide comprises at least one of HfOx and TaOy, where x≤2.0 and y≤2.5. The interface layer comprises at least one layer of Al2O3, MgO, Y2O3, and La2O3.SELECTED DRAWING: Figure 3

A method includes causing a first information bit to be written into a first bit cell in a first plurality of bit cells as an original logic state of the first information bit. The method also includes causing a second information bit to be written into a second bit cell in a second plurality of bit cells as an original logic state of the second information bit. The method also includes causing a third information bit to be written into a third bit cell in a third plurality of bit cells as a logically complementary state of the first information bit.