169 results about "Resistive random-access memory" patented technology

The present application discloses a computing-in-memory circuit, chip and electronic device, wherein the computing-in-memory circuit comprises: a resistive random access memory array, a clamping circuit, a current mirror and an analog-to-digital conversion circuit; the clamping circuit is connected between a signal input terminal and the resistive random access memory array, configured to input clamping voltage signal to the N resistive random access memories selected of the resistive random access memory array, wherein N is an integer and N≥2; the current mirror is connected between the resistive random access memory array and the analog-to-digital conversion circuit, configured to output convergence current to the analog-to-digital conversion circuit based on the N-way currents output from the N resistive random access memories selected; the analog-to-digital conversion circuit configured to convert the convergence current to a digital signal.

A semiconductor structure including a one-transistor one-capacitor (1T1R) device is provided that includes an embedded resistive random access memory (ReRAM) having a width larger than 1 gate pitch, that is present in a frontside or the backside of the structure, a frontside contact structure electrically connected to a source region of the transistor of the 1T1R device and a backside contact structure electrically connected to a drain region of the transistor of the 1T1R device.

The invention discloses an in-memory encryption circuit, encryption method and system based on a resistive random access memory, and relates to the technical field of semiconductors and in-memory encryption, the in-memory encryption circuit comprises an in-memory calculation chip integrating a true random number generator, a physical unclonable function, a logic calculation function and a storage function, the computing macro unit is used for storing and processing bit data containing an encrypted plaintext and a key; the master control unit is used for uniformly managing control signals of the computing macro-units and ensuring cooperative work of the computing macro-units; the switch matrix is used for realizing external input and output of logic signals and data interaction among the computing macro units; and the input and output module is used for realizing external driving and internal driving of the in-memory computing chip and completing signal and data butt joint between the in-memory computing chip and external equipment. According to the method, deep integration of encryption algorithms can be realized, and the security of in-memory encryption is improved while the area overhead is reduced.

The application discloses a homopolymolybdate hybrid resistive random access memory material based on a tetraphenylstyrene molecule and a preparation method and application thereof. The preparation method comprises the following steps: dissolving a mixture of 0.05 mmol of homopolymolybdate and 0.1 mmol of the tetraphenylstyrene molecule in 10 mL of water, stirring for 2 hours, adjusting the pH to 5.0 by using HCl to obtain a mixed solution; moving the mixed solution into a 25 mL stainless steel reaction kettle lined with polytetrafluoroethylene, reacting at 160 DEG C for 3 days, and obtaining a colorless block crystal after cooling; and after filtration, washing and drying, the homopolymolybdate hybrid resistive random access memory material based on the tetraphenylstyrene molecule is obtained. The method is simple and easy to operate, raw materials are easy to obtain, and the method is easy to realize. No harmful product is generated in the preparation process, and the method is an environment-friendly green synthesis. A multi-level controllable memory storage material is prepared, and the material can be applied to a multi-level memristor.

The invention discloses an electroencephalogram signal classification method, device and equipment and a medium, and is applied to the field of signal processing.The electroencephalogram signal classification method comprises the steps that nonlinear features of target electroencephalogram signals are mapped to a two-dimensional plane, and a recurrence plot of the target electroencephalogram signals is obtained; performing recursive quantitative analysis on the recursive plot to obtain quantitative data of the target electroencephalogram signal; the target electroencephalogram signals are classified by utilizing a pre-trained electroencephalogram signal classification model in combination with the quantized data, a classification result of the target electroencephalogram signals is obtained, the electroencephalogram signal classification model is constructed based on a resistive random access memory array, and the resistive random access memory array comprises a first column used for storing positive weights and a second column used for storing negative weights. According to the method, the nonlinear features in the target electroencephalogram signals can be fully combined, the classification accuracy and classification efficiency of the target electroencephalogram signals can be improved, and the electroencephalogram signals of the epileptic in different states can be accurately classified from a large number of electroencephalogram signals.

The invention belongs to the technical field of semiconductors, discloses a silicon carbide substrate Mn-doped gallium oxide-based resistive random access memory and a preparation method thereof, and solves the problems of difficult thermal management, insufficient substrate heat dissipation capability, to-be-improved switch ratio, complex preparation process and the like of the existing gallium oxide resistive random access memory. The resistive random access memory comprises a SiC substrate, a Mn-doped beta-Ga2O3 thin film, a tungsten electrode layer and a top electrode, wherein the tungsten electrode layer is superposed on a first surface of the SiC substrate, and the Mn doped beta-Ga2O3 thin film is superposed on a second surface of the SiC substrate; and the top electrode is formed on the Mn doped beta-Ga2O3 thin film.

A memory device includes a first memory array including a plurality of first memory bits. Each of the plurality of first memory bits is configured as a one-time-programmable (OTP) memory bit. A second memory array includes a plurality of second memory bits, each of the plurality of second memory bits being configured as a multi-time-programmable (MTP) memory bit. A lock bit circuit operatively coupled to the first memory array and not the second memory array. The lock bit circuit is configured to generate a lock bit indicative of whether at least one of the plurality of first memory bits has been programmed.

Provided are a resistive random-access memory (RRAM)-based blood test system and method. The system comprises: a computing chip, an RRAM chip, a power supply module, and a sensor module; the computing chip is connected to the RRAM chip; the RRAM chip is connected to the sensor module; and the power supply module is connected to the computing chip and the RRAM chip; the sensor module is configured to test a substance in blood and convert test result data into a plurality of pieces of first voltage data; the RRAM chip is configured to preprocess the received plurality of pieces of first voltage data and obtain second current data; and the computing chip is configured to, based on the second current data, perform a function computation on the second current data according to a preset function computation model, and obtain a blood-based classification result.

Structures including an access transistor and a resistive memory element, and methods of forming such structures. The structure comprises an access transistor including a semiconductor layer, a first source / drain region, a second source / drain region, a gate dielectric layer on the semiconductor layer, and a gate electrode overlapped with the gate dielectric layer. The gate dielectric layer has a first portion with a first thickness adjacent to the first source / drain region and a second portion with a second thickness adjacent to the second source / drain region, and the first thickness is greater than the second thickness. The structure further comprises a resistive memory element that is coupled to the first source / drain region of the access transistor.

This application provides a neural network system and a neural network calculation method, relating to the field of electronic technology, which can save chip area and power consumption. The neural network system includes a first memristor array, multiple current-to-voltage converters, and multiple resistive random access memories (RRAMs). The first memristor array includes multiple rows and columns of memristors for receiving first input data and performing multiplication and addition operations on the first input data according to configured first weights to obtain current. Each current-to-voltage converter is connected to the output terminal of at least one column of memristors in the first memristor array, for receiving the current of the corresponding column of memristors and converting the received current into voltage. Each RRAM is connected to at least one current-to-voltage converter, for receiving the voltage of the corresponding current-to-voltage converter, and obtaining one of the calculation results from the first calculation results based on the received voltage and the initial resistance state of the corresponding RRAM. The initial resistance state of each RRAM is a high resistance state.

The present disclosure provides mechanisms for reducing and suppressing random telegraph noise (RTN) in crossbar circuits. The processing device may perform a programming process to program a resistive random access memory (RRAM) device in the crossbar circuit to a target conductance value. The processing device may then determine whether a telegraph noise (RTN) value associated with the RRAM device is within a predetermined range of acceptable RTN values. If the RTN value associated with the RRAM device is not within a predetermined range of acceptable RTN values, one or more noise reduction voltages may be applied to the RRAM device until the RTN value associated with the RRAM device is within the predetermined range of acceptable RTN values.

Provided in the present application are an electroencephalogram signal classification method and apparatus, and a device. The method comprises: a first resistive random access memory in a resistive random access memory array acquiring an electroencephalogram signal to be classified, and extracting a signal feature of said electroencephalogram signal; when the similarity between the signal feature and a preset normal electroencephalogram signal feature is not greater than a preset threshold value, calling a target operation program and a target weight value that corresponds to each signal abnormality type to process said electroencephalogram signal, so as to obtain an electric-current feature value corresponding to each target weight value; and determining a signal abnormality type corresponding to the largest electric-current feature value among all electric-current feature values to be a target signal abnormality type of said electroencephalogram signal, wherein the target weight value is the difference between a first weight value and a second weight value that correspond to a signal abnormality type. By means of the present application, the data processing volume and power consumption of a neural network are effectively reduced, and the classification efficiency is improved.

The application discloses a two-dimensional resistance change memory and a preparation method thereof. 2‑x O x The materials of the first resistance change layer and the second resistance change layer are MoS2 and MoO3 respectively, the oxygen concentration difference between the first resistance change layer and the second resistance change layer facilitates oxygen ion migration, and the interface oxide layer between the top electrode and the second resistance change layer provides an oxygen ion source. The technical scheme of the application solves the problems of a small on-off ratio and high power consumption of the existing resistance change memory.

Aspects of the present disclosure provide a method of fabricating a resistive random access memory (RRAM). For example, the method can include providing a substrate, forming a first electrode on the substrate, and forming a first metal oxide layer on the first electrode. The first metal oxide layer can act as a sink or reservoir of oxygen atoms that interact with a current conducting filament. The method can further include forming a second metal oxide layer on the first metal oxide layer. The second metal oxide layer can be configured to form conduction paths. The method can further include forming a second electrode on the second metal oxide layer. In an embodiment, the first metal oxide layer can be formed on a portion of the first electrode.

A method of manufacturing a resistive random access memory includes the following steps. An interlayer dielectric layer is formed on a semiconductor substrate. A first conductive material layer is formed in a through hole of the interlayer dielectric layer. At least one interface layer is formed in the through hole. The interface layer covers a bottom surface of the first conductive material layer and exposes a portion of a side surface of the first conductive material layer. A resistive material layer is formed in the through hole and covers the interface layer and the first conductive material layer. A second conductive material layer is formed in the through hole and covers the resistive material layer. A planarization is performed on the first conductive material layer, the resistive material layer and the second conductive material layer to form an embedded resistive random access memory in the through hole.

A method for fabricating a resistive random access memory (RRAM) includes the steps of first forming an interlayer dielectric (ILD) layer on a substrate, forming a first stop layer on the ILD layer, forming a recess in the first stop layer, forming a bottom electrode in the recess, forming a metal oxide layer on the bottom electrode, forming a top electrode on the metal oxide layer, patterning the top electrode and the metal oxide layer, and then forming a spacer adjacent to the top electrode and the metal oxide layer.

A resistive random access memory and a method of forming the same are provided. The resistive random access memory includes a first electrode, a resistance switch layer located on the first electrode, a second electrode located on the resistance switch layer, and a plurality of nanoparticles located between the resistance switch layer and the second electrode.

A single bipolar coexistence resistance change memory of single-layer amorphous gallium oxide with controllable defects and a preparation method, the device comprises a lower electrode, a resistance change material layer and an upper electrode arranged in turn from bottom to top; the lower electrode, the resistance change material layer and the upper electrode are all single-layer structures, the lower electrode adopts a Pt substrate, the resistance change material layer adopts an amorphous gallium oxide film, and the upper electrode adopts an active electrode Ag; wherein the resistance change material layer is prepared by a magnetron sputtering method, the oxygen defect concentration in the amorphous gallium oxide film can be controlled by changing the proportion of argon and oxygen flow in the magnetron sputtering process, so that the device has both unipolar and bipolar modes, and only the same current limiting is used in the single bipolar reversible change, and the same current limiting condition can simplify the circuit design of the integrated resistance change memory periphery, so as to reduce the integrated circuit area and the circuit power consumption. Finally, a vacuum evaporation equipment is used to prepare a 100-200nm upper electrode Ag. The present application simplifies the process flow, and has the advantages of simple structure, low power consumption and high device performance.

The present disclosure provides a control method and device for a resistive random access memory (RRAM) array, which can be applied to the field of microelectronics technology. The control method comprises: for each RRAM in the RRAM array, performing a shaping operation on the RRAM based on a first preset voltage, a second preset voltage and a third preset voltage to obtain an activated RRAM in an activated state; and performing a setting operation on the activated RRAM based on the first preset voltage and the second preset voltage to obtain a first target RRAM with a resistance value in a first preset range, wherein the first preset voltage, the second preset voltage and the third preset voltage are generated by sub-circuits of a voltage generation circuit, and the first preset voltage, the second preset voltage and the third preset voltage are not equal to each other.

The invention discloses an initialization method and device of a resistive random access memory, and the method comprises the steps: obtaining a first control signal, and controlling a first memory bank in the resistive random access memory to carry out Forming operation according to the first control signal; the operation state of the first memory bank is determined, and the operation state comprises operation completion and operation non-completion; and when the operation state is operation completion, controlling a second memory bank in the resistive random access memory to perform Forming operation according to the first control signal, acquiring a second control signal at the same time, controlling the first memory bank to perform Pre-cycling operation according to the second control signal, and so on until all memory banks in the resistive random access memory are controlled to complete Pre-cycling operation, the initialization of the resistive random access memory is completed; therefore, the initialization time is greatly saved, and the initialization efficiency is improved.

The invention provides an embedded data engineering feature extraction and AI quantitative data de-noising technology and device, belongs to the technical field of data processing, and solves the technical problem of technical bottleneck of high-dimensional data preprocessing in a scene in which edge device resources are limited. Comprising the following steps: quantitative sensing noise modeling: executing dynamic range mapping on original input data through a differentiable non-uniform quantizer to generate a quantized data stream; synchronously constructing a hardware noise injection model to simulate quantization error distribution; low-precision adversarial denoising: inputting the quantized data stream into a lightweight adversarial denoising network; a dynamic bit width switching mechanism: selecting a 4 / 6 / 8bit calculation mode in real time based on the signal-to-noise ratio of an input signal; feature-denoising joint optimization: extracting an activation tensor of a middle layer of a denoising network as feature pyramid input, and reducing feature redundancy through a mutual information maximization loss function; and extracting features in the nonvolatile memory: calculating feature vectors in situ on the cross array of the resistive random access memory, and skipping a data moving process. The method has the technical effects of adaptively adjusting quantization precision to reduce errors, inhibiting feature degradation by dynamic bit width switching, reducing feature redundancy by joint optimization and improving data processing efficiency.

The invention provides a silver-doped lanthanum ferrite nanofiber, a preparation method thereof and a resistive random access memory, and relates to the technical field of semiconductor storage. The silver-doped lanthanum ferrite nanofiber provided by the invention comprises a lanthanum ferrite nanofiber and silver doped in a lanthanum ferrite lattice in the lanthanum ferrite nanofiber, the molar ratio of lanthanum element to iron element to silver element in the silver-doped lanthanum ferrite nanofiber is 1: 1: x, and x is more than 0 and less than 0.1. The resistive random access memory assembled by the silver-doped lanthanum ferrite nanofibers provided by the invention has good resistance change performance, shows a higher on-off ratio (the on-off ratio reaches 103), and is stable and reliable in performance. The invention provides the preparation method of the silver-doped lanthanum ferrite nanofiber, the doping concentration of silver in the lanthanum ferrite nanofiber can be accurately controlled, and uniform distribution of silver in a final product is ensured, so that the resistance change performance of lanthanum ferrite is effectively improved; the preparation method is simple to operate, low in cost and capable of realizing large-scale preparation.

The invention relates to a resistive random access memory write circuit and an operation method thereof. The resistive random access memory write-in circuit comprises a pull-up transistor M1, a detection transistor M2, a pull-down transistor M3, a bias current source I1, a logic circuit, an array gate tube and a resistive random access memory array, one end of the pull-up transistor M1 is connected with a write operation voltage source, and the other end of the pull-up transistor M1 is connected with a first end of a target memory device in the resistive random access memory array through the array gate tube; one end of the pull-down transistor M3 is grounded, and the other end of the pull-down transistor M3 is connected with the second end of the target memory device through the array gate tube; the grid electrode of the detection transistor M2 is connected with the first end of a target memory device in the resistive random access memory array through the array gate tube, the drain electrode is connected with the bias current source I1, and the source electrode is grounded; the input end of the logic circuit is connected with the connection node of the detection transistor M2 and the bias current source I1, and the output end is connected with the grid electrode of the pull-up transistor M1. According to the scheme, the writing efficiency of the resistive random access memory is improved.

The present disclosure provides a semiconductor integrated circuit device and a manufacturing method therefor. In the device, an electrode in a resistive random-access memory (RRAM) cell is directly connected to a metal layer, thereby omitting the steps of filling a connection via with other metal materials (such as tungsten) and of polishing. The manufacturing process is hence simplified, and different degrees of depressions caused by polishing are correspondingly reduced. The uniformity of resistive performance of the RRAM and the quality of the semiconductor integrated circuit device are hence greatly improved. In addition, a resistive layer having a trench structure is formed by using a trench where an original connection via is located, thereby embedding the entire RRAM cell into the trench. The structure of the RRAM cell is more compact, a gap between RRAM cells is smaller, and the requirements for miniaturization and high density can thus be better met.

The application provides a resistive random memory and a preparation method thereof, and relates to the technical field of semiconductors.The resistive random memory comprises a prefabricated substrate, a dielectric layer arranged on the prefabricated substrate, and a resistive random memory device arranged on the dielectric layer.The resistive random memory device comprises a bottom electrode penetrating through the dielectric layer and embedded in the prefabricated substrate, a resistive layer covering the sidewall of the bottom electrode and arranged apart from the prefabricated substrate, and a top electrode comprising an insulating layer and at least one sub-electrode, wherein the insulating layer separates the sub-electrodes, each sub-electrode is arranged on the side of the resistive layer away from the bottom electrode, the extension direction of the sub-electrode is perpendicular to the sidewall of the bottom electrode and extends away from the bottom electrode, one side surface of the sub-electrode is attached to the dielectric layer, and the upper surface of the top electrode is located in the same horizontal plane as the upper surface of the resistive layer and the upper surface of the bottom electrode.The resistive random memory provided by the application can improve the storage density and the uniformity of the unit performance while ensuring the efficiency of the manufacturing process.

A CMO-based metallic filament (MF) resistive random access memory (MF-ReRAM) cell is provided in which the metallic filament is specifically designed to confine electric potential of the top electrode in a circular plug area of the MF. The CMO-based MF-ReRAM cell has non- volatile-multilevel storage capability in the back-end-of-the-line (BEOL), and such a memory cell can be integrated in a highly dense crossbar architecture.

A resistive random access memory (ReRAM) includes a resistive cell that switches between a low resistance state (LRS) after setting or a high resistance state (HRS) after resetting. Resistance filaments have the risk that oxygen vacancies of a resistance layer are compounded with oxygen in a removal layer. As a result of the compounding process, the cell may switch from the LRS to the HRS over time, and the cell is further affected by temperature and applied voltage. An improved structure includes an inert electrode over which a resistive layer is formed. A zirconia (ZrO2) mitigation layer is formed over the resistive layer, and a purge layer is formed over the mitigation layer. The resistive layer and the ZrO2 layer typically have a total thickness of 5 nm, wherein the ZrO2 layer is in the range of 1-2.5 nm. The ZrO2 layer may further be doped with a trivalent element, such as aluminum (Al) or lanthanum (La), in a doping range of 1%-15%.

A method of forming a memory device with a laterally-recessed free layer includes forming a bottom electrode above an electrically conductive structure embedded within an interconnect dielectric material. A magnetic tunnel junction stack is formed above the bottom electrode. Forming the magnetic tunnel junction stack includes forming a magnetic reference layer above the bottom electrode, forming a tunnel barrier layer above the magnetic reference layer, and forming a magnetic free layer above the tunnel barrier layer. Opposed lateral portions of the magnetic free layer are recessed, and sidewall spacers are formed on the recessed opposed lateral portions of the magnetic free layer for confining an active region of the memory device formed by the magnetic free layer and the tunnel barrier layer.

A method can include forming two vertical transfer field effect transistors stacked on top of one another and separated by a resistive random access memory structure. The two vertical transfer field effect transistors can include a source (104, 112), a channel (106, 110), and a drain, where a contact layer (152) of the resistive random access memory structure functions as the drain for both vertical transfer field effect transistors. Forming the two vertical transfer field effect transistors can further include forming a first source (104) and a second source (112). The first source (104) is a bottom source and the second source (112) is a top source. The method can include forming a gate conductor layer (138, 140) around the channels (106, 110). The resistive random access memory structure can include a faceted epitaxial body (144) defined by cusps. The cusps of the faceted epitaxial body (144) can extend vertically toward one another. The faceted epitaxial body (144) can be between the two vertical transfer field effect transistors.