472 results about "Resistive random-access memory" patented technology

The invention provides a resistive random access memory ReRAM data judgment method based on sneak path correlation. The method comprises the implementation steps that parameters are initialized; calculating a reading resistance value of the ReRAM storage unit; classifying the ReRAM storage units based on the sneak path correlation; calculating a log-likelihood ratio and a judgment threshold of each type of storage unit; and obtaining a ReRAM data judgment result. The storage units are classified according to the sneak path correlation values of the row and the column where each storage unit is located, and the likelihood ratio function of each category of storage units is calculated according to the conditional probability distribution of the resistance value read by the storage data of each storage unit under different value conditions. According to the method for calculating the likelihood ratio function by using the sneak path correlation, the influence of the difference of interference suffered by different storage units on the bit error rate is fully considered, and the judgment precision is effectively improved.

The present application discloses a computing-in-memory circuit, chip and electronic device, wherein the computing-in-memory circuit comprises: a resistive random access memory array, a clamping circuit, a current mirror and an analog-to-digital conversion circuit; the clamping circuit is connected between a signal input terminal and the resistive random access memory array, configured to input clamping voltage signal to the N resistive random access memories selected of the resistive random access memory array, wherein N is an integer and N≥2; the current mirror is connected between the resistive random access memory array and the analog-to-digital conversion circuit, configured to output convergence current to the analog-to-digital conversion circuit based on the N-way currents output from the N resistive random access memories selected; the analog-to-digital conversion circuit configured to convert the convergence current to a digital signal.

A magnetic tunnel junction pillar is positioned above a bottom electrode composed of a metal-oxide region in contact with a first portion of the magnetic tunnel junction pillar and a metal region surrounding the metal-oxide region. A sidewall spacer is positioned along sidewalls of the magnetic tunnel junction pillar, and the metal region is in contact with a bottom surface of the sidewall spacer and a second portion of the magnetic tunnel junction pillar.

A semiconductor structure comprises a first transistor, a second transistor vertically stacked over the first transistor, a source / drain region shared between the first transistor and the second transistor, and a resistive random-access memory device connected to the shared source / drain region.

A resistive random access memory is provided including an asymmetrical or symmetrical bottom electrode which has an angled profile which forms an interface with a memory switching layer. The angled profile can include a slanted surface or one including a plurality of slanted surfaces that converge into a point. Bottom electrodes having such angled profiles provide more forming area, which can reduce forming voltage without area penalty. In some embodiments in which the slanted surfaces converge into a point, bottom electrodes having such an angled profile can also provide a more controlled area for the forming process to occur.

The embodiment of the invention provides a resistive random access memory device and a manufacturing method and an operation method thereof. The resistive random access memory device comprises a substrate structure and a memory stack structure, the storage stack structure is arranged on one side of the substrate structure and comprises a first electrode, a second electrode, a resistance change reaction layer and an interface layer, the resistance change reaction layer is located between the first electrode and the second electrode and is configured to be converted from a first resistance state to a second resistance state when a level higher than that of the first electrode is applied to the second electrode, and the interface layer is configured to be connected with the first resistance state. When a level higher than that of the second electrode is applied to the first electrode, the resistance change reaction layer is converted from the second resistance state to the first resistance state, and the resistance of the resistance change reaction layer in the first resistance state is higher than that in the second resistance state; the interface layer is located between the first electrode and the resistive reaction layer and serves as an oxygen diffusion barrier layer. By arranging the interface layer, the erasing resistance and the device performance of the resistive random access memory device can be improved.

The invention discloses a resistive random access memory manufacturing method, a resistive random access memory chip manufactured by the resistive random access memory manufacturing method comprises a first resistive random access memory unit and a second resistive random access memory unit, a resistive random layer of the first resistive random access memory unit comprises a high-voltage material layer, and a resistive random layer of the second resistive random access memory unit is a high-dielectric constant material layer. The first resistive random access memory unit has the characteristic of long storage time due to the fact that the resistive random layer comprises the high-voltage material layer, and the second resistive random access memory unit has the characteristics of fast response and high operation speed due to the fact that the resistive random layer is the high-dielectric-constant material layer. According to the manufacturing method of the resistive random access memory, the two resistive random access memory units can be subjected to process integration through the innovative process, and the manufactured resistive random access memory chip can meet the requirements of two performances.

The invention discloses an analog memristor based on a Ga2O3 / TiO2 heterojunction structure and a preparation method of the analog memristor, and belongs to the field of nonvolatile resistive random access memorizers, the preparation method comprises the following steps: under a vacuum condition, depositing a conductive film on a pretreated insulating substrate by adopting a physical vapor deposition method to serve as a bottom electrode; sequentially depositing a Ga2O3 thin film and a TiO2 thin film on the bottom electrode by adopting a magnetron sputtering method, and constructing a Ga2O3 / TiO2 heterojunction as a resistive layer; and depositing a conductive thin film on the surface of the resistive layer by adopting a physical vapor deposition method to serve as a top electrode to obtain the analog memristor based on the Ga2O3 / TiO2 heterojunction structure. A Ga2O3 semiconductor material with a wide forbidden band and high electron mobility and a TiO2 material with a high dielectric constant, stability and reliability are adopted, and the excellent and high-stability heterojunction memristor is prepared through a specific sputtering process. Bionic behaviors such as synaptic plasticity can be realized, and the method has important application potential in the fields of high-density storage, neural network calculation, biological synaptic simulation and the like.

Provided is a semiconductor structure including a one-transistor-one-capacitor (1T1R) device having an embedded resistive random access memory (ReRAM) with a width greater than 1 gate pitch present at the front or back of the structure, wherein a front-side contact structure is electrically connected to a source region of the transistor of the 1T1R device and a back-side contact structure is electrically connected to a drain region of the transistor of the 1T1R device.

A semiconductor structure including a one-transistor one-capacitor (1T1R) device is provided that includes an embedded resistive random access memory (ReRAM) having a width larger than 1 gate pitch, that is present in a frontside or the backside of the structure, a frontside contact structure electrically connected to a source region of the transistor of the 1T1R device and a backside contact structure electrically connected to a drain region of the transistor of the 1T1R device.

A RRAM and its manufacturing method are provided. The RRAM includes a first dielectric layer formed on a substrate, and two memory cells. The two memory cells include two bottom electrode structures separated from each other. Each bottom electrode structure fills one of two trenches in the first dielectric layer. The two memory cells also include a resistance switching layer and a top electrode structure. The resistance switching layer is conformally formed on the surface of an opening in the first dielectric layer, and the opening is between the two trenches. The top electrode structure is on the resistance switching layer and fills the opening. A top surface of the first dielectric layer, top surfaces of the bottom electrode structures, a top surface of the resistance switching layer, and a top surface of the top electrode structure are coplanar.

The invention discloses a sensing, storage and calculation integrated three-dimensional integrated chip, a preparation method of the sensing, storage and calculation integrated three-dimensional integrated chip and a calculation method of the sensing, storage and calculation integrated three-dimensional integrated chip. The sensing memory unit comprises a stacked resistive random access memory device group, a sensing device and a gating device; the stacked resistive random access memory device group comprises at least two resistive random access memory devices which are stacked in the thickness direction; the sensing device is used for receiving an external signal and converting the external signal into an input signal, and the output end of the sensing device is coupled with the top electrode of the stacked resistive random access memory device group; the gating device is configured to receive a control signal and switch on and off according to the control signal, and the gating device is coupled with the top electrode of the stacked resistive random access memory device group; wherein the stacked resistive random access memory device group is arranged between the sensing device and the gating device along the width direction, and the at least two resistive random access memory devices share one top electrode, so that the at least two resistive random access memory devices synchronously receive an input signal or are synchronously switched on and off.

The resistive random access memory comprises a substrate and a resistive random structure located on the substrate, and the resistive random structure comprises a first electrode, a resistive random layer, an oxygen reaction layer and a second electrode which are sequentially stacked; the resistive random layer is provided with a main body part and a convex part, the convex part abuts against the first electrode, the main body part abuts against the oxygen reaction layer, and the width of the convex part is smaller than that of the main body part.

The present application discloses a resistive random access memory and an erasing compilation method, a chip, and an electronic device. The erasing compilation method for the resistive random access memory comprises: performing a first erasing compilation operation on memory cells of the resistive random access memory; when the first erasing compilation operation ends and a preset waiting time has elapsed, verifying the memory cells for which the first erasing compilation operation ends, so as to determine problematic memory cells among the memory cells for which the first erasing compilation operation ends; and performing a second erasing compilation operation on the problematic memory cells. The erasing compilation method in the present application can improve the accuracy and integrity of the erasing operation, reduce the erasing failure rate, and thus enhance the durability of the resistive random access memory.

The present invention discloses an 8T2R non-volatile SRAM unit circuit, including a non-volatile data storage circuit composed of two resistive random access memories RRAM, a resistive random access memory UR on the top and a resistive random access memory BR on the bottom; a transmission gate circuit composed of an N-type MOSFET and a P-type MOSFET, the N-type MOSFET is recorded as NT, and the P-type MOSFET is recorded as PT; two P-type MOSFETs and two N-type MOSFETs constitute two inverters, and the two inverters are connected end to end, the two P-type MOSFETs are respectively recorded as a left pull-up transistor LUT and a right pull-up transistor RUT, the two N-type MOSFETs are respectively recorded as a left pull-down transistor LDT and a right pull-down transistor RDT, and the left access transistor LAT and the right access transistor RAT constitute a storage unit of a 6T-SRAM. The circuit adds a non-volatile unit RRAM on the basis of the read, write and hold capabilities of the SRAM, so that the SRAM has the ability to not lose power-off data and to recover power-on data.

A semiconductor structure is provided that includes a resistive random access memory on a surface of a bit line (28) embedded in a shallow trench isolation structure (12). The structure may also include a source line (SL) over the bit line (28) or embedded in the shallow trench isolation structure (12).

A MRAM circuit is provided in the present invention, wherein each memory cell includes a first transistor with a first gate, a first source and a first drain and the first gate is connected to a first word line, a second transistor with a second gate, a second source and a second drain and a second gate is connected to a second word line, and the second source and the second drain are connected respectively with the first source and the first drain, a first MTJ with one terminal connected to the first source and the second source and another terminal connected to a source line, and a second MTJ with one terminal connected to the first drain and the second drain and another terminal connected to a bit line.

The invention discloses an efficient hypergraph processing method and device based on a variable resistance type memory, and aims to solve the bottleneck problem of a traditional hypergraph processing architecture in the aspect of memory access. Comprising the following steps: on the basis of a hybrid in-memory computing architecture of a variable resistive random access memory, combining two in-memory computing engines of an analog resistive random access memory and a digital resistive random access memory, and dividing the workload of a hypergraph into a dense format and a sparse format by utilizing the overlapping characteristic of the hypergraph; and different workloads can be efficiently executed on the adaptive processing engine, so that higher performance and energy efficiency are realized. According to the method, a novel efficient software and hardware collaborative design scheme is provided for hypergraph processing, and wide application of hypergraph processing is promoted.

The invention discloses a resistive random access memory structure and a manufacturing method thereof. The resistive random access memory structure comprises a bottom electrode, a resistive random layer and a top electrode which are sequentially stacked from bottom to top, the upper surface of the bottom electrode is in Schottky contact with the lower surface of the resistive layer, and the lower surface of the top electrode is in ohmic contact with the upper surface of the resistive layer; the resistive layer is a single oxide film layer; the bottom electrode and the top electrode are made of the same metal nitride, and the atomic number ratio of metal elements to nitrogen elements in the top electrode is larger than the atomic number ratio of metal elements to nitrogen elements in the bottom electrode. The structure of the memory can be simplified, and the process complexity and the manufacturing cost can be reduced.

The invention relates to a resistive random access memory structure and a preparation method thereof. The memory structure comprises a semiconductor substrate, and a lower insertion layer thin film, a dielectric layer thin film and a top electrode are sequentially formed on the semiconductor substrate; the semiconductor substrate adopts a substrate Pt / Ti / SiO2 / Si or FTO as a bottom electrode; the lower intercalation layer thin film is made of ZnO, TiO, SiOx or AlOx; the dielectric layer film is made of a ZnO semiconductor material, at least one of magnetic transition metal elements Mn, Ti, Cr and Ni is introduced, and the doping amount of the transition metal is 1%-7% at. The lower intercalation layer and the dielectric layer film are prepared on the surface of the semiconductor substrate through a pulse laser deposition method. The method comprises the following steps: preparing a Mn-doped ZnO target material by adopting a sol-gel method; preparing a lower intercalation film and a dielectric layer film by adopting pulse laser deposition; a metal mask plate is used for assisting in preparing the top electrode. According to the invention, the working stability and reliability of the resistive random access memory are improved.

The invention discloses an in-memory encryption circuit, encryption method and system based on a resistive random access memory, and relates to the technical field of semiconductors and in-memory encryption, the in-memory encryption circuit comprises an in-memory calculation chip integrating a true random number generator, a physical unclonable function, a logic calculation function and a storage function, the computing macro unit is used for storing and processing bit data containing an encrypted plaintext and a key; the master control unit is used for uniformly managing control signals of the computing macro-units and ensuring cooperative work of the computing macro-units; the switch matrix is used for realizing external input and output of logic signals and data interaction among the computing macro units; and the input and output module is used for realizing external driving and internal driving of the in-memory computing chip and completing signal and data butt joint between the in-memory computing chip and external equipment. According to the method, deep integration of encryption algorithms can be realized, and the security of in-memory encryption is improved while the area overhead is reduced.

The invention discloses a stability-enhanced flexible self-supporting resistive random access memory and a preparation method thereof. The preparation method comprises the following steps: synthesizing MXene solid powder by taking MAX-phase Ti3AlC2 powder as a raw material; carrying out suction filtration by using MXene solid powder to obtain a bottom electrode composed of an MXene self-supporting film; preparing an oxide thin film on the MXene self-supporting thin film to form an oxide semiconductor layer; and preparing a top electrode on the upper surface of the oxide semiconductor layer. The flexible MXene self-supporting thin film is used as the bottom electrode to be applied to the resistive random access memory, so that the flexibility, the conductivity and the long-term stability of the resistive random access memory can be remarkably improved.

A memory device includes a trench to a first conductive structure; a first electrode comprising a conformal conductive material within the trench, the first electrode in electrical communication with the first conductive structure and present on a sidewall of the trench; the switch layer exists in the groove on the first electrode and extends to the outside of the groove; and a second electrode on the switching layer and overfilling the trench. The memory device also includes a contact on a portion of the second electrode that overfills the trench such that the contact is horizontally offset from the first electrode present within the trench.

The invention discloses a high-entropy oxide / tungsten oxide heterojunction memristor and a method and application thereof, and belongs to the technical field of nonvolatile resistive random access memories. The reverse self-current-limiting analog memristor with the heterojunction structure structurally comprises a bottom conductive electrode, a functional layer and an upper conductive electrode from bottom to top, the functional layer is composed of a high-entropy oxide film and a tungsten oxide film. And continuously depositing a second conductive film on the functional layer by adopting a physical vapor deposition mode to serve as an upper conductive electrode to obtain the reverse self-current-limiting memristor with the high-entropy oxide / tungsten oxide heterojunction structure. The structure and the preparation process are simple, and the material cost is low; the self-current-limiting characteristic can reduce the energy consumption of the device and the overheating risk of the device by inhibiting the current overshoot, and improves the reliability and integration density of the device, thereby supporting a storage and calculation integrated neural state architecture, reducing the data migration between a calculation unit and a storage unit, and improving the reliability of the device. And a hardware basis is provided for efficient real-time sensing and multi-modal information fusion.

The invention discloses a display driving chip. The display driving chip comprises a resistive random access memory module which is used for storing default register information, mura data and burn in data, and the register information is used for configuring a register; a data input interface of the Demura module is connected to the resistive random access memory module, and the Demura module is configured to extract mura data from the resistive random access memory module and perform Demura compensation by using the mura data; a data input interface of the Gamma calibration module is connected to the resistive random access memory module, and the Gamma calibration module is configured to extract burn in data from the resistive random access memory module and perform Deburn in compensation by using the burn in data. Through the scheme of the embodiment of the invention, the requirements of the DDIC and the TDDI on the storage medium in an upgrading iteration scene can be met, and the plug-in device is simplified, so that the power consumption and the production cost of the DDIC / TDDI are further reduced.

The invention belongs to the technical field of organic / polymer neuromorphic information storage, and provides an ion covalent organic framework memristor device with vinylidene connection and preparation and application thereof. Specifically, two construction units (triphenylbenzene and trinuclear copper) with different activities grow a vinyl-bridged ion covalent organic framework film on the surface of ITO through a green hydrothermal method, and the vinyl-bridged ion covalent organic framework film is used as a resistive random access memory. According to the method, a large-area and uniform-texture two-dimensional COF film is successfully grown on the ITO substrate through a green substrate assisted hydrothermal method, and the subsequent film forming processing problem caused by the intrinsic characteristics of vinyl COF is effectively solved; the adopted hydrothermal method opens up a new path for large-scale low-carbon production of the high-crystallinity two-dimensional vinyl ion covalent organic framework material, and has profound significance and value.

There is provided a semiconductor structure including a single transistor single capacitor (1T1R) device including: an embedded resistive random access memory (ReRAM) having a width greater than 1 gate pitch, present at a front side or a back side of the structure; a front side contact structure electrically connected to a source region of the transistor of the 1T1R device; and a backside contact structure electrically connected to the drain region of the transistor of the 1T1R device.

A resistive random access memory (RRAM) structure includes a RRAM cell, spacers and a dielectric layer. The RRAM cell is disposed on a substrate. The spacers are disposed beside the RRAM cell, wherein widths of top surfaces of the spacers are larger than or equal to widths of bottom surfaces of the spacers. The dielectric layer blanketly covers the substrate and sandwiches the RRAM cell, wherein the spacers are located in the dielectric layer. A method for forming the resistive random access memory (RRAM) structure is also provided.

The present application relates to a method, device, electronic device, and storage medium for processing a resistive random access memory (RRAM). The method includes: determining whether there is a need to process a RRAM; if there is a need to process a RRAM, performing a forward forming operation on the RRAM to be processed to obtain a RRAM after forward processing; if the conductance of the RRAM after forward processing is greater than or equal to a first preset conductance threshold, repeatedly applying a first RESET pulse to the RRAM after forward processing until the conductance of the RRAM after forward processing is less than the first preset conductance threshold, thereby obtaining a RRAM after reverse processing; and repeatedly applying a second RESET pulse to the RRAM after reverse processing until the conductance of the RRAM after reverse processing is greater than the second preset conductance threshold, thereby obtaining a target RRAM. This solves the problem of relaxation of the target memory after programming and enhances the stability of the conductance state of the RRAM after programming.

The application discloses a homopolymolybdate hybrid resistive random access memory material based on a tetraphenylstyrene molecule and a preparation method and application thereof. The preparation method comprises the following steps: dissolving a mixture of 0.05 mmol of homopolymolybdate and 0.1 mmol of the tetraphenylstyrene molecule in 10 mL of water, stirring for 2 hours, adjusting the pH to 5.0 by using HCl to obtain a mixed solution; moving the mixed solution into a 25 mL stainless steel reaction kettle lined with polytetrafluoroethylene, reacting at 160 DEG C for 3 days, and obtaining a colorless block crystal after cooling; and after filtration, washing and drying, the homopolymolybdate hybrid resistive random access memory material based on the tetraphenylstyrene molecule is obtained. The method is simple and easy to operate, raw materials are easy to obtain, and the method is easy to realize. No harmful product is generated in the preparation process, and the method is an environment-friendly green synthesis. A multi-level controllable memory storage material is prepared, and the material can be applied to a multi-level memristor.