3 results about "External memory interface" patented technology

The invention discloses a verification system of an FSMC multi-memory interface based on a UVM, and belongs to the technical field of chip verification. The verification system of the FSMC multi-memory interface based on the UVM comprises a test layer, a simulation instruction definition layer, an AHB bus interface component, an assertion inspection component and an external memory interface component. The problems that in the prior art, a single memory is mainly connected for verification, only a single protocol can be verified, the verification means is limited, and the efficiency and the coverage rate are not high are solved, the transmission type of the AHB is defined in the environment configuration component, therefore, the verification diversity is improved, the verification requirements for verifying different memory interfaces are well met, and the verification efficiency is improved. According to the interface protocol verification method and device, the randomized excitation and self-checking function conforming to the protocol can be generated, the verification comprehensiveness is greatly improved, the pertinence and correctness of the verified module are greatly improved, the verification efficiency is improved, the code cost is reduced, and the accuracy of interface protocol verification is improved.

The invention discloses a cache control system for asynchronous data communication between a satellite-borne processor and a communication controller. The system comprises a processor, a communication controller, a shared data memory, a first bus driver and a second bus driver, the input ends of the first bus driver and the second bus driver are respectively connected with the processor, and the output ends are respectively connected with a bus of the shared data memory; when the bus driver is in an enabled state, the access of the processor to the shared data memory is realized; the processor comprises a plurality of external memory interfaces, a universal interface and an interrupt input interface; the communication controller comprises a plurality of communication memory interfaces, a host interface, an arbitration signal interface and an interrupt output interface; each communication memory interface is respectively connected with a bus of the shared data memory; each host interface is respectively hung on the corresponding external memory interface; each arbitration signal interface is connected with the corresponding universal interface; and the interrupt output interface is connected with the interrupt input interface. According to the invention, asynchronous data sharing and exchange between the processor and the communication controller can be realized, and time sequence mismatch and access conflict are avoided.

This application provides an example system and an example method for chaining DMA transfers from a dataflow graph running across multiple CGRPs. One example first CGRP comprises a first set of coarse-grained reconfigurable units (CGRUs) including a first CGRU, a first external network, a second external network, a first external memory interface (EMI), and first external network shim (Eshim). The first Eshim to receive over the first external network a first transfer (TX) frame of a DMA transfer comprising first frame data from a second CGRP, initiate a memory write of the first frame data to a first memory. The first Eshim to receive a first completion message that indicates the memory write has completed, and to trigger a second DMA transfer of a second TX frame comprising a first subset of the first frame data to a third CGRP utilizing the second external network.