183 results about "External memory interface" patented technology

A digital data processor integrated circuit (1) includes a plurality of functionally identical first processor elements (6A) and a second processor element (5). The first processor elements are bidirectionally coupled to a first cache (12) via a crossbar switch matrix (8). The second processor element is coupled to a second cache (11). Each of the first cache and the second cache contain a two-way, set-associative cache memory that uses a least-recently-used (LRU) replacement algorithm and that operates with a use-as-fill mode to minimize a number of wait states said processor elements need experience before continuing execution after a cache-miss. An operation of each of the first processor elements and an operation of the second processor element are locked together during an execution of a single instruction read from the second cache. The instruction specifies, in a first portion that is coupled in common to each of the plurality of first processor elements, the operation of each of the plurality of first processor elements in parallel. A second portion of the instruction specifies the operation of the second processor element. Also included is a motion estimator (7) and an internal data bus coupling together a first parallel port (3A), a second parallel port (3B), a third parallel port (3C), an external memory interface (2), and a data input/output of the first cache and the second cache.

The invention provides systems and methods for using radio frequency (RF) transponders interrogators for storing and retrieving data files. In one embodiment, the RF interrogator comprises a microcontroller module that retrieves a data file from a buffer memory space and breaks up the data file into multiple data packets, each data packet comprising a data file identifier and a sequence number. The present invention also provides a data storage device that comprises an RF transponder and a microcontroller that is in communication with the transponder via the external memory interface. In one embodiment, the transponder receives data over an RF broadcast, assigns an address to the data, and sends the data to the microcontroller via the external memory interface for storage at the assigned address.

An integrated circuit (IC) for optimizing data presentation to an external memory interface bus is provided. The IC is in communication with the external memory via the external memory interface bus. The IC includes an encoder that may encode the data that are being sent to an external memory. The encoder encodes the data based on the logic value of the majority of bits in the data. The encoder is capable of setting a status bit to indicate that the data are encoded. Further connected in series with the encoder is a parity generator that sets the parity bit logic value based on whether the number of logic 1s in the data, along with the status bit, is even or odd. The IC also includes a parity checker to detect whether any error occurred in the data during transmission. The decoder within the IC decodes the data to the original data.

Wireless and other external connectivity technology is used in various ways to enhance or improve upon existing radar detector and police activity detection systems. External memory interfaces, such as SD cards or USB, provide external storage. Wireless interfaces such as Bluetooth, Zigbee, 802.11, and wireless personal area network communication protocols, allow a detector processor to interact wirelessly with external devices, such as a Bluetooth headset, a cellular network device providing a server connection, or toggle buttons used to indicate the presence of police activity at a current position. Further, radar detectors are upgraded to provide GPS capabilities, using the existing power/data connector of the radar detector.

The invention provides an integrated navigation computer based on DSP and FPGA and used for integrated navigation of GPS and an inertial navigation system, consisting of a data input module, a data collecting module, a navigation solution module and a data output module. The data input module realizes the level conversion of input signals; the data collecting module utilizes the FPGA to realize the synchronous collection of IMU pulse signals and GPS signals; the navigation solution module concurrently read the data collected by the data collecting module by the external memory interface of a high-speed floating-point type DSP and completes the real-time integrated navigation of inertia or GPS; the navigation result is output by the data output module; furthermore, the output information has the characteristic of multi-redundancy. The navigation computer has high integration, small volume, light weight, low power loss, good real-time performance, strong expansibility, convenient system updating, and can be widely applied to the navigation of moving carriers such as aircrafts, ships and ground vehicles, etc.

A CPU 5 is provided with both the functionality of issuing an external bus access request directly to an external memory interface 3 and the functionality of issuing a DMA transfer request to a DMAC 4. Accordingly, in the case where data is randomly accessed at discrete addresses, an external bus access request is issued directly to the external memory interface 3, and in the case of data block transfer or page swapping as requested by a virtual memory management unit or the like, a DMA transfer request is issued to the DMAC 4, so that it is possible to effectively access the external memory 50.

A multiprocessor system (40) includes a MPU subsystem (12), with master MPU (16) and shared memory (24), and a DSP/Coprocessor subsystem (14), with one or more slave DSP/Coprocessors (26). The system memory (20) is accessed by each DSP/Coprocessor subsystem (14) through a cache (28) and external memory interface (30). A verification interface (42) is used in verification mode to isolate the DSP/Coprocessor subsystem (14) from the MPU subsystem (12) and to translate system memory requests from the external memory interfaces (30) (through an arbiter (52), where multiple external memory interfaces are used) to a protocol which can be used to access the data from the shared memory (24).

The invention relates to a parallel microprocessor and a corresponding realization method which are based on FPGA development. The parallel microprocessor comprises a CPU which is a 32-bit fixed-point CPU formed by a fetch decoding unit, a process management unit and an integer instruction execution unit; a communication module formed by a plurality of units of LINK channels and In/Out controllers; an arbitration controller used for arbitrating internal and external address buses and a data bus of the CPU; an external memory interface used for providing reading/writing time-sequence logic for an external memory; an interruption/time-sequence controller used for providing timing and interruption for the CPU; an internal memory used for providing the instructions of the CPU and quickly accessing data. The CPU is also provided with a floating point unit (FPU) combining the 32-bit fixed-point CPU to form a 64-bit floating point CPU. The 32-bit fixed-point parallel microprocessor and the 64-bit floating point parallel microprocessor provided by the invention work stably, bring convenience for system modification and debugging, accelerate verification speed and provide a low-cost operation platform for programs written in OccamII language.

A network switch having switch ports for full-duplex communication of data packets with respective network nodes according to Ethernet (IEEE 802.3) protocol that flexibly assigns memory access slots to access an external memory according to programmable information. A scheduler within an external memory interface assigns the memory access slots to the respective network switch ports according to a programmed sequence written into an assignment table memory from an external programmable data storage device.

A method and apparatus allowing efficient access control to a common data bus by including an isolation device to separate the common data bus, a priority-based arbiter to control access to the internal portion of the common data bus including a processor or other bus master, and a time slot arbiter to control access to the external portion of the common data bus including multiple bus masters, an external memory interface, etc. The common external memory may be allocated for exclusive or non-exclusive use by the various devices utilizing either portion of the isolated common data bus. External devices accessing the external memory may communicate directly with one or more bus masters, e.g., on the internal portion of the common data bus.

The invention discloses an embedded type navigation information processor based on a DSP (digital signal processor) and an FPGA (field programmable gata array). The navigation information processor comprises a data acquisition module, a logic control management module, a navigation data processing module, a navigation data output module and a Flash program solidification module. The DSP of the navigation data processing module is connected with a Flash, an SDRAM (synchronous dynamic random access memory) and the FPGA outside the DSP through an EMIF (external memory interface). The Flash program solidification module is connected with an external development computer through a serial port. The data acquisition module acquires data and synchronizing signals output by an IMU (inertial measurement unit) and a GNSS (global navigation satellite system). Address decoding and time synchronization are carried out through the logic control management module, and the results are input to an SDRAM (synchronous dynamic random access memory) of the DSP. Strapdown calculating and filtering algorithm are carried out by the navigation data processing module. Navigation information data are sent to other application devices in the form of network messages through the navigation data processing module. The navigation information processor is a special navigation information processor hardware platform applicable to a strapdown inertial navigation system, and meets the requirements for miniaturization, low power consumption and high accuracy of an SINS (ship's inertial navigation system)/ GNSS integrated navigation system.

A network switch for network communications includes a first data port interface supporting a plurality of data ports transmitting and receiving data at a first data rate. A second data port interface supports a plurality of data ports transmitting and receiving data at a second data rate. A CPU interface is configured to communicate with a CPU, and an internal memory communicates with the first data port interface and the second data port interface. A memory management unit is provided, including an external memory interface, for communicating data from at least one of the first data port interface and the second data port interface and an external memory. A communication channel is provided, for communicating data and messaging information between the first data port interface, the second data port interface, the internal memory, and the memory management unit. One data port interface of the first data port interface and the second data port interface includes a fast filtering process, with the fast filtering processor filtering packets coming into the one data port interface. Selective filter action is taken based upon a filtering result.

The invention relates to a special ASIC (Application Specific Integrated Circuit) chip system for spaceflight. The special ASIC chip system comprises a MIPS (Million Instructions Per Second) nucleus, a PCI (Programmable Communications Interface) bus interface, an ISA (Internet Security And Acceleration) bus interface, a 1553B bus terminal interface, a 1553B protocol processor, a network interface, a CAN (Controller Area Network) interface, an EMI (External Memory Interface), AD acquisition control logic, OC door control logic, UART (Universal Asynchronous Receiver/Transmitter) serial port, PWM (Pulse Width Modulation) interface, a pulse counter PPC, PCM (Pulse Code Modulation) telemetry remote control module and a general input/output module, wherein the MIPS nucleus, the PCI bus interface, the ISA bus interface, the 1553B bus terminal interface, the 1553B protocol processor, a network interface, the CAN interface and the EMI are connected to an AMBA AXI (Advanced Microcontroller Bus Architecture Advanced eXtensible Interface) bus; and the AD acquisition control logic, the OC door control logic, the UART serial port, the PWM interface, the pulse counter PPC, the PCM telemetry remote control module and the general input/output module are connected to an AMBA APB (All Points Bulletin) bus; and the AMBA AXI bus is connected with the AMBA APB bus through an AXI/APB bridge.

The invention provides a method and a system for external download of a DSP (digital signal processor) program and an FPGA (field programmable gate array) program. The system comprises a 1553B interface circuit, a DSP processor, a DSP storage unit, a watchdog circuit, an FPGA and an FPGA storage unit. The 1553B interface circuit is connected with the DSP processor through an EMIFA (external memory interface A), the watchdog circuit is connected with the DSP processor through a GPIO (general purpose input/output) interface, and the DSP storage unit is connected with the DSP processor through an EMIFB (external memory interface B) and a GPIO interface. The FPGA storage unit is connected with the DSP processor through a McBsp interface, the DSP processor is connected with the FPGA through a GPIO interface, and the FPGA storage unit is connected with the FPGA through a serial bus. The method and the system for external download of the DSP program and the FPGA program have the advantage that practicability, reliability and real-time performance of the system for external download can be improved.

The invention discloses an external memory interface consisting of a control unit, an address output channel, a reading-writing and chip-selection unit, a data input channel and a data output channel, wherein, the three 32-bit address mapped registers are designed in the control unit, which ensures that a 32-bit digital signal processor has the ability of interacting with a multiple bit-width external memory. The interface can synchronously make access operations to an 8-bit external memory, a 16-bit external memory and a 32-bit external memory, thereby improving the extensibility and the working flexibility of the 32-bit digital signal processor; at the same time, the interface has a simple structure, is easy to control and miniaturize, and is convenient to be realized on the chips.

The invention relates to a radiation resistance and reinforcement parallel on-board computer system and a use method thereof, belongs to the field of on-board computer radiation resistance and reinforcement, and is realized through three DSP (Digital Signal Processor) chips and four FPGA (Field Programmable Gate Array) chips. The system consists of a system control unit and three same subsystems, wherein the system control unit is realized on one FPGA, and each subsystem comprises one DSP and one FPGA, and is connected with the system control unit. The system adopts a '2 parallel + 1 backup' structure, the two DSPs carry out parallel processing of on-board tasks, and the rest DSP serves as a backup DSP, and the backup DSP replaces the failed DSP when the DSP carrying out concurrent working has unrecoverable faults. The three DSPs are all interconnected through an external memory interface (EMIF) and a hardware platform interface (HPI). The system selects different backup mechanisms which comprise a fixed backup mechanism, a rotary backup mechanism and a preprocessing backup mechanism according to requirements of the on-board tasks.

The present invention provides a music playback and manipulation system for generating audio playback of digital musical comprising; a user control device having an external memory interface for providing access to random access memory and read only memory, a mass storage host controller for providing access to and control of data from, a user controller interface and an audio subsystem interface; a mass storage device for storing a plurality of audio files; and a user control device for varying playback parameters of said audio files.

The invention relates to a universal device and a universal method for protocol conversion, which belong to the field of virtual simulation tests. The existing problem of low conversion efficiency and precision in the protocol conversion by software is solved. The device comprises two JTAG interface modules, a 96-pin extension interface module, an RJ45 interface module, an FPGA, a signal processor and a memory, wherein the FPGA comprises a receiving buffer unit, a protocol matching module, a register module and a sending buffer unit. The FPGA stores the protocol data input by a 96-pin extension interface module into a receiving buffer unit and meanwhile sends to a protocol matching module for matching, the result is stored in a register module after the protocol matching module completes protocol matching, and the data in a receiving buffer unit and the information in a register region can be accessed by a signal processor through an external memory interface; the protocol conversion is performed through the signal processor and the conversion result is sent out through the signal processor. The universal device and the method are specifically applied in the field of protocol conversion.

When the cache memory unit reads the last word of a page of the cache memory, the external memory interface reads ahead data of a prescribed number of pages ahead of the relevant page. Thus, data corresponding to the access request to the external main memory is always held in the cache memory. This prevents degradation of parallel processing capability of the data driven type information processing apparatus.

The invention discloses a multi-mode startup embedded system, comprising a chip mode configuration port (101), a configuration control register (102), an internal memory (106), an external memory interface (105), an I/O communication module (104), a CPU (103) and a system bus (107). After the system is electrified, the startup mode of the system is determined according to information of the chip configuration port, wherein the startup mode of the system comprises startup from the internal memory, startup from the external memory, startup from the external communication equipment and the like. Users can select the startup mode of the embedded system through the chip mode configuration port. The invention not only can realize multi-mode startup of the embedded system, but also can realize multimode upgrading of system firmware, and meets the requirement of upgrading once again and multiple applications on the embedded system currently.

The invention relates to an off-chip Nor Flash bus interface hardware encryption device which comprises an EMI (external memory interface), a data reading decryption passage, a data reading bypass passage, a data writing passage and an AES (advanced encryption standard) encryption engine, wherein the EMI is used for CPU (central processing unit) extensible external memories, the three passages connects the EMI with external Nor Flash memories, the AES encryption engine is connected between a CPU and the data reading decryption passage and used for plaintext data encryption, and the data reading decryption passage comprises an address analyzing unit, an address comparing unit, an indication control unit, a cipher text buffer unit, an AES decryption engine, a plaintext buffer unit and a secret key storage unit. Hardware-software combination is used to provide data encryption for off-chip Nor Flash memories. The device supports a bypass function, data can be written into off-chip Nor Flash memories in plaintext and read in plaintext, so that data storage flexibility is achieved. By the device which is flexible in extensibility, easy to design, high in reliability and safety and the like, Nor Flash bus interface encryption is achieved.