11 results about "External memory interface" patented technology

The invention discloses a verification system of an FSMC multi-memory interface based on a UVM, and belongs to the technical field of chip verification. The verification system of the FSMC multi-memory interface based on the UVM comprises a test layer, a simulation instruction definition layer, an AHB bus interface component, an assertion inspection component and an external memory interface component. The problems that in the prior art, a single memory is mainly connected for verification, only a single protocol can be verified, the verification means is limited, and the efficiency and the coverage rate are not high are solved, the transmission type of the AHB is defined in the environment configuration component, therefore, the verification diversity is improved, the verification requirements for verifying different memory interfaces are well met, and the verification efficiency is improved. According to the interface protocol verification method and device, the randomized excitation and self-checking function conforming to the protocol can be generated, the verification comprehensiveness is greatly improved, the pertinence and correctness of the verified module are greatly improved, the verification efficiency is improved, the code cost is reduced, and the accuracy of interface protocol verification is improved.

A device includes a data path, a first interface connected to the data path and configured to receive a request from a processor package to write a data value to a memory address, and a controller connected to the data path and configured to receive the request to write the data value to the memory address and to calculate a Hamming code of the data value. The controller is configured to transmit the data value and the Hamming code on the data path. The device includes an external memory interleave connected to the data path. The external memory interleave is configured to receive the data value and calculate a test Hamming code of the data value and to determine whether to send the data value to an external memory interface to be written to the memory address based on a comparison of the Hamming code and the test Hamming code.

In an example embodiment, a device includes an address protocol controller configured to receive an access request that includes an address associated with an external memory, and an external memory interface controller coupled to the address protocol controller and configured to couple to the external memory. The address protocol controller is configured to determine, based on a type of the external memory device, whether to generate a modified address associated with the address in the access request. Based on the external memory device being a first type, the address protocol controller is configured to provide the address to the external memory. Based on the external memory being a second type, the address protocol controller is configured to generate the modified address and provide the modified address to the external memory interface controller to access the external memory.

The invention discloses a DSP (Digital Signal Processor) and FPGA (Field Programmable Gate Array) collaborative guiding system and method, aiming at solving the problem that a DSP and an FPGA in the prior art cannot share one storage device. The system comprises an FPGA (Field Programmable Gate Array), a DSP (Digital Signal Processor) and an SPI (Serial Peripheral Interface) memory, wherein the FPGA is connected with the SPI memory through an SPI interface and is connected with the DSP through an EMIF (External Memory Interface) interface, so that the DSP can be controlled The DSP loads data from the RAM of the FPGA through an EMIF (external memory interface); and the SPI memory stores FPGA programs and dual-backup bootstrap and application programs in a centralized manner. The method is based on the system and comprises the following steps: firstly loading a self program through the FPGA, then reading a bootstrap program in the SPI memory for verification, then storing the bootstrap program in a self RAM, then cancelling DSP reset to enable the DSP to load the bootstrap program, and finally reading an application program through the FPGA for verification and execution. The FPGA is used for transfer, the characteristic that only one program can be guided after the DSP is powered on is broken through, the DSP and the FPGA share one SPI memory, the storage and guiding reliability is improved, and the cost and the PCB area are reduced.

The invention relates to enhanced support for volatile and non-volatile external memory. In an example embodiment, an apparatus includes an address protocol controller (127) configured to receive an access request including an address associated with an external memory (130); and an external memory interface controller (129) coupled to the address protocol controller (127) and configured to be coupled to the external memory (130). The address protocol controller (127) is configured to determine whether to generate a modified address associated with the address in the access request based on a type of the external memory device (130). Based on the external memory device (130) being of a first type, the address protocol controller (127) is configured to provide the address to the external memory (130). Based on the external memory (130) being of a second type, the address protocol controller (127) is configured to generate the modified address and provide the modified address to the external memory interface controller (129) to access the external memory (130).

The invention discloses a servo drive control system of a three-self-inertial-unit testing device. The servo drive control system comprises a processor, a CPLD, a drive circuit and a rotary transformer decoding circuit. The rotary transformer decoding circuit is used for converting a rotary transformer signal output by the rotary transformer into an angle signal and a speed signal; the processor is used for analyzing the angle signal and the speed signal to obtain current position information of the rotary table, processing the current position information of the rotary table to obtain current speed information of the rotary table, and outputting an enabling control signal based on the current speed information of the rotary table; the CPLD is connected with an external memory interface of the processor for address decoding processing and logic processing; the drive circuit drives the rotating mechanism and the locking mechanism in response to the enable control signal. According to the invention, the integrated control of the two brushless motors and the two brush motors is realized, and the two dual-channel rotary transformers are integrated to carry out high-precision decoding coupling processing and servo closed-loop control, so that the stability and response speed of the system are improved.

The application discloses a Chiplet-based matrix chain multiplication accelerator and a matrix chain multiplication acceleration method. The matrix chain multiplication accelerator comprises a first matrix multiplication module, a first external memory interface, a nonlinear processing module, a second matrix multiplication module and a second external memory interface, and the modules are connected through Chiplet interconnection. The method comprises the following steps: obtaining operator data of a Tranformer network and preprocessing the operator data to obtain a matrix chain data stream; based on the matrix chain data stream, performing initialization processing on the matrix chain multiplication accelerator to obtain an initialized matrix chain multiplication accelerator; inputting the matrix chain data stream into the initialized matrix chain multiplication accelerator to perform matrix multiplication operation, and obtaining attention matrix data. The application can improve the utilization rate of processing elements, thereby reducing the memory access frequency and the delay of data transmission, and improving the calculation efficiency. The application can be widely applied to the field of computer hardware acceleration technology.

The application discloses a design method of a multi-core SoC shared external memory interface, wherein a global control register, a clock configuration register and a space control register are internally designed and configured in an external memory interface controller, clock configuration of the external memory interface controller, frequency division coefficient when a system clock is selected, and external memory timing control are performed, the global control register is used for configuring internal working clock of the external memory interface controller and reading external memory state, the clock configuration register is used for configuring output clock of the external memory interface controller and connecting working clock of the external memory, and the space control register is used for external memory read-write timing control of four memory spaces supported by the external memory interface controller; the application optimizes external memory interfaces of multiple processor cores by adopting simplified design, shares one external memory interface, and achieves the effect of reducing system size and improving work efficiency.

The invention discloses a cache control system for asynchronous data communication between a satellite-borne processor and a communication controller. The system comprises a processor, a communication controller, a shared data memory, a first bus driver and a second bus driver, the input ends of the first bus driver and the second bus driver are respectively connected with the processor, and the output ends are respectively connected with a bus of the shared data memory; when the bus driver is in an enabled state, the access of the processor to the shared data memory is realized; the processor comprises a plurality of external memory interfaces, a universal interface and an interrupt input interface; the communication controller comprises a plurality of communication memory interfaces, a host interface, an arbitration signal interface and an interrupt output interface; each communication memory interface is respectively connected with a bus of the shared data memory; each host interface is respectively hung on the corresponding external memory interface; each arbitration signal interface is connected with the corresponding universal interface; and the interrupt output interface is connected with the interrupt input interface. According to the invention, asynchronous data sharing and exchange between the processor and the communication controller can be realized, and time sequence mismatch and access conflict are avoided.

Integrated circuits may include registers that store register states. Only a subset of the registers may store critical register states. The subset of registers may be specially demarcated, such as using synthesis directions in the hardware description, and may be coupled to dedicated extraction / loading circuitry. The extraction / loading circuitry may be implemented using soft or hard logic or can leverage existing programming or debugging circuitry on a programmable integrated circuit. The extraction / loading mechanism may also be implemented using multiplexers and associated control circuitry, scan chain circuitry, a memory-mapped interface, a tool-instantiated or user-instantiated finite state machine, or external memory interface logic. Accessing critical register states in this way can help improve efficiency with live migration events, debugging, retiming, and other integrated circuit operations.

This application provides an example system and an example method for chaining DMA transfers from a dataflow graph running across multiple CGRPs. One example first CGRP comprises a first set of coarse-grained reconfigurable units (CGRUs) including a first CGRU, a first external network, a second external network, a first external memory interface (EMI), and first external network shim (Eshim). The first Eshim to receive over the first external network a first transfer (TX) frame of a DMA transfer comprising first frame data from a second CGRP, initiate a memory write of the first frame data to a first memory. The first Eshim to receive a first completion message that indicates the memory write has completed, and to trigger a second DMA transfer of a second TX frame comprising a first subset of the first frame data to a third CGRP utilizing the second external network.