208 results about "Parity bit" patented technology

Apparatuses, systems, and methods for enhanced metadata information. The memory array includes a number of column planes and an extra column plane. A memory device is set in an x4 single-pass operational mode. In this mode, the memory may store a data codeword in a selected ones of the column planes, and metadata may be stored in a non-selected ones of the column planes and in the extra column plane. An error correction code circuit (ECC) may store parity bits associated with the data and metadata in the non-selected ones of the column planes. In this manner, the data, metadata, and parity may be accessed as part of a single access of the memory array.

Apparatuses, systems, and methods for single-pass access of ECC information, metadata information, or combinations thereof. The memory array includes a number of column planes and an extra column plane. A memory device may be set in an ×4 single-pass operational mode. In this mode, the memory may store data in a selected ones of the column planes, and metadata may be stored in the extra column plane. An error correction code circuit (ECC) may store parity bits associated with the data and metadata in non-selected ones of the column planes. In this manner, the data, metadata, and parity may be accessed as part of a single access of the memory array.

Apparatuses, systems, and methods for enhanced metadata information. The memory array includes a number of column planes and an extra column plane. A memory device is set in an x4 single-pass operational mode. In this mode, the memory may store a data codeword in a selected ones of the column planes, and metadata may be stored in a non-selected ones of the column planes and in the extra column plane. An error correction code circuit (ECC) may store parity bits associated with the data and metadata in the non-selected ones of the column planes. In this manner, the data, metadata, and parity may be accessed as part of a single access of the memory array.

Apparatuses, systems, and methods for single-pass access of ECC information, metadata information, or combinations thereof. The memory array includes a number of column planes and an extra column plane. A memory device may be set in an ×4 single-pass operational mode. In this mode, the memory may store data in a selected ones of the column planes, and metadata may be stored in the extra column plane. An error correction code circuit (ECC) may store parity bits associated with the data and metadata in non-selected ones of the column planes. In this manner, the data, metadata, and parity may be accessed as part of a single access of the memory array.

Methods, systems, and devices for wireless communications are described. In some cases, a first wireless device may communicate, with a second wireless device, a control signal indicating a systematic polar code configuration, the systematic polar code configuration indicating for the first wireless device to perform systematic polar encoding on a first set of bits associated with a non-uniform bit distribution. As such, the first wireless device may apply a systematic polar code to the first set of bits to generate a systematic polar codeword based on the systematic polar code configuration. In such cases, the systematic polar codeword may include a set of parity bits and a set of systematic bits. Thus, the first wireless device may transmit at least the set of parity bits of the systematic polar code.

The invention discloses a serial port communication method based on a browser. The method comprises the following steps: requesting a user to authorize to access a serial port device through a navigator.series. Request Port (); the method comprises the following steps: creating a serial port control type instance by constructing a function constructor, and configuring indexes, a baud rate, a data bit, a stop bit and a check bit parameter; calling an openPort () method to open a serial port, and introducing configuration parameters to establish connection; the method comprises the following steps of: acquiring a flow reader through a port.readable. GetReader (), establishing a read-write lock, analyzing return data according to a read type parameter, judging the type of a sent instruction according to the write type parameter, automatically converting instruction data, acquiring the flow reader through the port.readable. GetReader (), establishing the read-write lock, analyzing the return data according to the read type parameter, and calling the port.relayLock () to release the read-write lock after the data is received and transmitted; and instantiating the serial port control component in the Web page, and dynamically managing the connection state and the data flow. According to the invention, serial port communication can be realized only by opening the browser without installing extra software; pure front-end implementation is realized, and a back-end server or a local program is not needed; and the method accords with the modern Web standard and has strong future compatibility.

Disclosed is a method comprising, by a transmitter apparatus, partitioning (901) an input data stream to obtain a bit stream X1 and a bit stream X2; subjecting (902) the bit stream X2 to encoding by LDPC encoders, to obtain X2 parity bits, and X2 information bits; applying (903) SPC encoding to the X2 parity bits, together with the bit stream X1, to obtain sign bits, wherein the bit stream X1 is used as padding bits; subjecting (904) the sign bits, the padding bits, and the X2 information bits, to an interleaver operation to obtain an interleaver output; subjecting (905) the interleaver output to Gray mapping to form multiple consecutive quadratic amplitude modulation, QAM, symbols; modulating (905) the QAM symbols by quadratic amplitude modulation to obtain a modulated data stream; and transmitting (906) the modulated data stream via a radio access network or optical fibre communication network.

The embodiment of the invention discloses a data processing method capable of being applied to a high-speed optical transmission network. The method comprises the following steps: obtaining second bit data according to first bit data of which the number of bits is din, the second bit data comprising the bits in the din first bit data, dCRC check bits and / or dPAD filling bits; scrambling the second bit data to obtain third bit data, wherein the bit number dscr of the third bit data is equal to din + dCP, and dCP is equal to dCRC + dPAD; then probability constellation shaping PCS processing is carried out on a first bit subset in a first bit set with the bit number of m to obtain a second bit subset, and the first bit set is obtained from the third bit data; performing FEC coding and interleaving processing on the second bit subset and a third bit subset except the first bit subset in the first bit set to obtain a second bit set; according to the invention, different values of the din, the m and the dCP are given, the existing 400G network can be compatible, the performance is excellent, and the cost is low.

Embodiments of the present disclosure relate to a memory system and an operating method thereof. The memory system can include a memory device and a memory controller configured to, when receiving a flush command indicating data to be cached in a data cache is flushed to the memory device from a host, flush first data to be cached in the data cache to the memory device, a size of the first data being less than a size of a reference write unit, write first parity associated with the first data to a parity storage block, update a value of a parity location pointer indicating a location where the first parity is written, and set a parity write flag indicating whether parity at a location pointed to by the parity location pointer is valid.

Methods, systems, and devices for wireless communications are described. A first device may identify parameters for staircase encoding. The first device may perform a staircase encoding procedure on information bits in accordance with the parameters to generate encoded bits. At current step of the staircase encoding procedure, the first device may concatenate a first set of shaping bits with a first set of information bits to generate a second set of bits, perform a channel decoding procedure on the second set of bits to generate a second set of shaping bits for a subsequent step of the staircase encoding procedure, perform an encoding procedure on a third set of bits to generate a set of parity bits, and map the third set of bits and the set of parity bits to a set of symbols to generate a fourth set of bits for the subsequent step.

Certain aspects of this disclosure generally relate to techniques for enhanced puncturing and low-density parity-check (LDPC) code structures. A method for wireless communication by a transmitting device is provided. This method generally includes: encoding a set of information bits based on an LDPC code to generate a codeword, the LDPC code being defined by a basic matrix having a first number of variable nodes and a second number of parity nodes; puncturing the codeword according to a puncturing pattern designed to puncture bits corresponding to at least two of the variable nodes to generate a punctured codeword; adding at least one additional parity bit to the punctured at least two variable nodes; and transmitting the punctured codeword.

Various aspects of the present disclosure generally relate to wireless communications. In some aspects, a wireless communication device (WCD) may send an indication of supporting a plurality of parity mapping schemes for communication. The WCD may receive a communication having a first parity mapping scheme and a second parity mapping scheme, the first parity mapping scheme being different from the second parity mapping scheme. Numerous other aspects are described.

The present invention discloses a UART controller and a method for detecting the validity of data transmission. The UART controller includes a receiver for receiving external data; a transmitter for sending data to the outside; and a UART data transceiver control unit for controlling the receiver and the transmitter to transmit and receive data and to perform interrupt control in a timely manner. The present invention provides a UART controller and a method for detecting the validity of data transmission to solve the problem that, during the data transmission process of a UART serial port, there is no parity check bit or there is an even number of bit data transmission errors during the transmission of a frame of data, resulting in an inability to detect data transmission errors. The present invention solves the problem that, when the transmitted data is too large or the chip communication distance is too long, data errors accumulate, resulting in an inability to detect and interrupt data transmission in a timely manner. The present invention solves the problem that, during the data transmission process of a UART serial port, data transmission errors due to poor anti-interference ability lead to an inability to interrupt data transmission in a timely manner.

According to one embodiment, a nonvolatile memory includes a plurality of memory areas and controller circuit including an error correction code encoder. The error correction code encoder encodes a first data to generate a first parity in a first operation and encodes a second data to generate a second parity in a second operation. The controller circuit writes the first data and the first parity into a first memory area among the plurality of memory areas and writes the second data and the second parity into a second memory area among the plurality of memory areas. The size of the second data is smaller than the size of the first data and the size of the second parity is equal to the size of the first parity.

Leveraging stochastic physical characteristics of resistive switching devices to generate data having very low cross correlation among bits of that data is disclosed. Data generated from stochastic physical characteristics can also be referred to as physical unclonable feature—or function—(PUF) data. Additionally, error correction functions for PUF data generated from resistive switching memory cells are provided. The error correction functions facilitate additional redundancy and longevity of PUF data, among other benefits. Different embodiments include addressing arrangements to incorporate ECC parity bits among generated PUF data bits, even for differential PUF bits respectively defined by multiple memory cells in different portions of a resistive memory array.

An example includes a method for decoding a shaped codeword that includes shaped data and the shaped parity bits. The shaped codeword has been encoded via an identity matrix comprising an array of layers and block columns of parity data. The method also includes recovering parity data from the shaped parity data of the shaped codeword via the controller. Recovering the parity data includes comparing a syndrome weight of each of a plurality of block columns of the shaped parity data with a threshold and flipping bits of each of the block columns of the shaped parity data in response to the syndrome weight of the respective one of the block columns being greater than the threshold to recover parity data from the shaped parity data of the shaped codeword. The method further includes decoding the shaped data based on the recovered parity data via the controller.

A memory controller generates Mi codewords each including a parity with a size Ni, divides each of the parities of the Mi codewords into K partial parities, determines K×A codewords from Mi codewords for Mi write information and the K or less partial parities of the K×A codewords, selects partial parities from the K×A codewords, generates Mi write information including the selected partial parities, and allocates continuous addresses of the nonvolatile memory to the K or less partial parities included in each of the Mi write information. A number of write information with sizes of the included partial parities matched becomes larger.

A receiver (115) receives pulse trains (r0, r1) encoding a plurality of bits (b) using a convolutional code {3, 2, 5} whose systematic bit g0 and parity bit g1 are mapped into two binary trains (21, 22) depending respectively on g0^g1 and g1. Noting that the convolutional coding and the mapping lead to modulation (bz-1^b^b.z+1, bz-1^b.z+1, bz-1^b.z+1), a demodulator demodulates the pairs of received pulse trains (r0, r1) into respective pairs of LLR values ​​(b0, b1) and a Viterbi decoder built on a convolutional code {3, 7, 5} decodes each pair of LLR values ​​into a decoded bit (d). Optimal decoding is thus achieved, notably offering a gain estimated at 1.8 dB (in error rate) without additional complexity. See Figure 3 for the abbreviated version.

A method (of operating compute-in-memory memory (CIM) system) includes: for first groups each of which including a multiplier and a first bit-error detector, the CIM system including (in a first region of a semiconductor die) an array memory cells configured to store first bits, an array of multipliers and first bit-error detectors, a first array memory cells arranged in first rows and first columns, the first array being configured to store first words; second ones of the memory cells being arranged in a second array configured to store parity bits corresponding to the first bits: performing generation of the first words by performing one or more multiplications of (A) input words and associated first checksum words and (B) corresponding weight words and associated second checksum words, and performing generation a row-based bit-error locus-inferable signal or a column-based bit-error locus-inferable signal based on selected ones of the first words.

The application discloses an intelligent decoding method for UART serial signals, which comprises the following steps: firstly, automatically recognizing unknown baud rate, data bit number, stop bit length and whether the UART protocol signal contains a parity check bit and other key parameters by using a large amount of data; and secondly, decoding and processing subsequent UART protocol signals according to cascaded decoding modules. Through the intelligent decoding of the UART protocol signal, the correct data information and baud rate can be accurately parsed without manually configuring or trying various decoding settings, so that the decoding process of the UART protocol signal can be greatly simplified, and the operation burden of the user can be reduced.

Methods, systems, and devices for wireless communications are described. A user equipment (UE) may generate an encoding matrix including a set of information columns including systematic bits, a first set of core parity columns including a first set of parity bits, and one or more sets of extension parity columns including a second set of parity bits. The UE may puncture one or more of the systematic bits with the first set of parity bits, the second set of parity bits, or a combination thereof, based on an offset value indicating an initial column of the encoding matrix. The UE may encode an initial message in accordance with the encoding matrix based on the offset indicating the initial column of the encoding matrix.

This application is directed to protecting a data item by storing data bits with integrity bits. The data bits are assigned into a second number of data sets. Data bits of each data set are combined to determine a third number of respective coding bits based on a respective coding pattern. The integrity bits include a set of single-bit error correcting (SEC) code bits and a set of parity bits. Each SEC code bit is a combination of a respective bit of the third number of respective coding bits of each of the second number of data sets, and each parity bit is a combination of a respective subset of SEC code bits and data bits in a respective one of the second number of data sets. These integrity bits are stored with the first number of data bits in a memory for protecting the data item.

An apparatus may include a receiver and one or more processors. The receiver may receive log likelihood ratio (LLR) values corresponding to encoded data that is encoded using a low-density parity-check (LDPC) code. The one or more processors may identify a number of punctured parity bits corresponding to the encoded data, determine that the number of punctured parity bits is less than a threshold, and remove, from a first parity check matrix corresponding to the encoded data, one or more rows corresponding to the number of punctured parity bits to generate a second parity check matrix. The one or more processors may determine, using the LLR values and the second parity check matrix, that there is an error in the LLR values, and an LDPC decoder may decode, based at least on the determination, the LLR values to resolve the error.

Methods, error correction circuits, and circuit modules using error correction circuits are provided for performing co-bit calculations for error correction by means of circuit complexity reduction. Methods and related devices for co-bit computations for error correction by means of circuit complexity reduction are provided. The method comprises: in an error correction circuit using a predetermined error correction code, configuring a first group of XOR operational circuits in a plurality of XOR operational circuits corresponding to a predetermined codeword length, rather than all XOR operational circuits in the plurality of XOR operational circuits, so as to reduce the circuit complexity of the error correction circuit and improve the error correction efficiency of the error correction circuit. Wherein the first set of XOR operational circuits may be a set of optimized XOR operational circuits implemented based on co-located bit coverage reduction; and performing the co-bit calculation using the first set of XOR operational circuits for error correction corresponding to a shorter codeword length, where a smaller XOR operand and a shorter critical path length can be achieved.

A memory device and an operating method of operating the memory device are provided. The method includes: obtaining, by a memory controller, channel selection information indicating positions of data bits and shaping parity bits; generating, by the memory controller, an alignment vector by aligning the data bits and the shaped parity bits having an arbitrary value based on the channel selection information; generating, by the memory controller, second LLR information of the target vector based on the first LLR information related to the alignment vector; determining, by the memory controller, a value of a shaped parity based on the target vector and the second LLR information; performing, by the memory controller, an update operation on the shaped parity based on the determined value; and generating, by the memory controller after performing the update operation, a codeword with respect to the input data based on a first matrix multiplication calculation of the target vector and the first generated matrix.

A sending method, a receiving method, an apparatus, a system, a device, and a storage medium. The receiving method includes: obtaining an encoded data block, where the encoded data block includes a plurality of data blocks, a plurality of first parity bits, and an FEC parity bit, the plurality of first parity bits are in one-to-one correspondence with the plurality of data blocks, and the FEC parity bit corresponds to the plurality of data blocks; and then checking the corresponding data blocks based on the plurality of first parity bits and / or the FEC parity bit, to obtain a decoding result of the encoded data block.

Methods, systems, and devices for wireless communications are described that provide for a transmitter (e.g., a user equipment (UE) or base station) and receiver (e.g., a UE or base station) to transmit and receive data packets that are encoded according to an outer coding technique. The outer coding technique may provide for data bits and parity bits to be included in a single physical layer transmission. In some cases, data packets (e.g., data bits) may be segmented into multiple subpackets, and coding may be performed across different subpackets of different data packets (e.g., in a diagonal coding pattern). In some examples, each transmission in the physical layer may contain both data subpackets and parity subpackets, which may balance an input and an output load of a buffer (e.g., a layer two (L2) decoding buffer at the receiver) during decoding.

A coding method and apparatus for a polar code, which relate to the technical field of communications, and can enable a nested PC-Polar code to reuse a sub-block interleaving rate matching mode of an NR PC-Polar code, so as to improve the NR compatibility. The method comprises: on the basis of a reliability sequence having a length of N, mapping an information bit sequence having a length of k to k bits of a first sequence having a length of N to obtain a second sequence, the second sequence comprising k information bits, x parity check (PC) bits and N-k-x frozen bits, wherein k, N and x are all positive integers, m information bits among the k information bits are the first m bits ranked in descending order of reliability in the second sequence, and the remaining (k-m) information bits among the k information bits are bits in the second sequence that correspond to the first (k-m) information bits ranked in descending order of reliability in a preset information bit set, and the x PC bits are x PC bits in a preset PC bit set; and performing polar coding on the second sequence to obtain a third sequence.

The described technology provides a multi-level error correction method, including encoding data received from a double data rate (DDR) memory by performing primary coding to generate transitional symbols, wherein the primary coding comprising at least one of cyclical redundancy check (CRC) encoding and single error correction double error detection (SECDED) encoding, performing a secondary coding on the transitional symbols to generate inner codes, the inner codes comprising code 1 parities generated from the transitional symbols and code 2 parities generated from the transitional symbols and metadata stored on the DDR memory, wherein the secondary coding comprising Reed Solomon (RS) encoding, and saving the inner codes on parity bit storage locations on a die of the DDR memory.