115 results about "Parity bit" patented technology

Apparatuses, systems, and methods for enhanced metadata information. The memory array includes a number of column planes and an extra column plane. A memory device is set in an x4 single-pass operational mode. In this mode, the memory may store a data codeword in a selected ones of the column planes, and metadata may be stored in a non-selected ones of the column planes and in the extra column plane. An error correction code circuit (ECC) may store parity bits associated with the data and metadata in the non-selected ones of the column planes. In this manner, the data, metadata, and parity may be accessed as part of a single access of the memory array.

Apparatuses, systems, and methods for enhanced metadata information. The memory array includes a number of column planes and an extra column plane. A memory device is set in an x4 single-pass operational mode. In this mode, the memory may store a data codeword in a selected ones of the column planes, and metadata may be stored in a non-selected ones of the column planes and in the extra column plane. An error correction code circuit (ECC) may store parity bits associated with the data and metadata in the non-selected ones of the column planes. In this manner, the data, metadata, and parity may be accessed as part of a single access of the memory array.

Apparatuses, systems, and methods for single-pass access of ECC information, metadata information, or combinations thereof. The memory array includes a number of column planes and an extra column plane. A memory device may be set in an ×4 single-pass operational mode. In this mode, the memory may store data in a selected ones of the column planes, and metadata may be stored in the extra column plane. An error correction code circuit (ECC) may store parity bits associated with the data and metadata in non-selected ones of the column planes. In this manner, the data, metadata, and parity may be accessed as part of a single access of the memory array.

Embodiments of the present disclosure relate to a memory system and an operating method thereof. The memory system can include a memory device and a memory controller configured to, when receiving a flush command indicating data to be cached in a data cache is flushed to the memory device from a host, flush first data to be cached in the data cache to the memory device, a size of the first data being less than a size of a reference write unit, write first parity associated with the first data to a parity storage block, update a value of a parity location pointer indicating a location where the first parity is written, and set a parity write flag indicating whether parity at a location pointed to by the parity location pointer is valid.

Various aspects of the present disclosure generally relate to wireless communications. In some aspects, a wireless communication device (WCD) may send an indication of supporting a plurality of parity mapping schemes for communication. The WCD may receive a communication having a first parity mapping scheme and a second parity mapping scheme, the first parity mapping scheme being different from the second parity mapping scheme. Numerous other aspects are described.

Leveraging stochastic physical characteristics of resistive switching devices to generate data having very low cross correlation among bits of that data is disclosed. Data generated from stochastic physical characteristics can also be referred to as physical unclonable feature—or function—(PUF) data. Additionally, error correction functions for PUF data generated from resistive switching memory cells are provided. The error correction functions facilitate additional redundancy and longevity of PUF data, among other benefits. Different embodiments include addressing arrangements to incorporate ECC parity bits among generated PUF data bits, even for differential PUF bits respectively defined by multiple memory cells in different portions of a resistive memory array.

An example includes a method for decoding a shaped codeword that includes shaped data and the shaped parity bits. The shaped codeword has been encoded via an identity matrix comprising an array of layers and block columns of parity data. The method also includes recovering parity data from the shaped parity data of the shaped codeword via the controller. Recovering the parity data includes comparing a syndrome weight of each of a plurality of block columns of the shaped parity data with a threshold and flipping bits of each of the block columns of the shaped parity data in response to the syndrome weight of the respective one of the block columns being greater than the threshold to recover parity data from the shaped parity data of the shaped codeword. The method further includes decoding the shaped data based on the recovered parity data via the controller.

A memory controller generates Mi codewords each including a parity with a size Ni, divides each of the parities of the Mi codewords into K partial parities, determines K×A codewords from Mi codewords for Mi write information and the K or less partial parities of the K×A codewords, selects partial parities from the K×A codewords, generates Mi write information including the selected partial parities, and allocates continuous addresses of the nonvolatile memory to the K or less partial parities included in each of the Mi write information. A number of write information with sizes of the included partial parities matched becomes larger.

A method (of operating compute-in-memory memory (CIM) system) includes: for first groups each of which including a multiplier and a first bit-error detector, the CIM system including (in a first region of a semiconductor die) an array memory cells configured to store first bits, an array of multipliers and first bit-error detectors, a first array memory cells arranged in first rows and first columns, the first array being configured to store first words; second ones of the memory cells being arranged in a second array configured to store parity bits corresponding to the first bits: performing generation of the first words by performing one or more multiplications of (A) input words and associated first checksum words and (B) corresponding weight words and associated second checksum words, and performing generation a row-based bit-error locus-inferable signal or a column-based bit-error locus-inferable signal based on selected ones of the first words.

Methods, systems, and devices for wireless communications are described. A user equipment (UE) may generate an encoding matrix including a set of information columns including systematic bits, a first set of core parity columns including a first set of parity bits, and one or more sets of extension parity columns including a second set of parity bits. The UE may puncture one or more of the systematic bits with the first set of parity bits, the second set of parity bits, or a combination thereof, based on an offset value indicating an initial column of the encoding matrix. The UE may encode an initial message in accordance with the encoding matrix based on the offset indicating the initial column of the encoding matrix.

This application is directed to protecting a data item by storing data bits with integrity bits. The data bits are assigned into a second number of data sets. Data bits of each data set are combined to determine a third number of respective coding bits based on a respective coding pattern. The integrity bits include a set of single-bit error correcting (SEC) code bits and a set of parity bits. Each SEC code bit is a combination of a respective bit of the third number of respective coding bits of each of the second number of data sets, and each parity bit is a combination of a respective subset of SEC code bits and data bits in a respective one of the second number of data sets. These integrity bits are stored with the first number of data bits in a memory for protecting the data item.

An apparatus may include a receiver and one or more processors. The receiver may receive log likelihood ratio (LLR) values corresponding to encoded data that is encoded using a low-density parity-check (LDPC) code. The one or more processors may identify a number of punctured parity bits corresponding to the encoded data, determine that the number of punctured parity bits is less than a threshold, and remove, from a first parity check matrix corresponding to the encoded data, one or more rows corresponding to the number of punctured parity bits to generate a second parity check matrix. The one or more processors may determine, using the LLR values and the second parity check matrix, that there is an error in the LLR values, and an LDPC decoder may decode, based at least on the determination, the LLR values to resolve the error.

Methods, error correction circuits, and circuit modules using error correction circuits are provided for performing co-bit calculations for error correction by means of circuit complexity reduction. Methods and related devices for co-bit computations for error correction by means of circuit complexity reduction are provided. The method comprises: in an error correction circuit using a predetermined error correction code, configuring a first group of XOR operational circuits in a plurality of XOR operational circuits corresponding to a predetermined codeword length, rather than all XOR operational circuits in the plurality of XOR operational circuits, so as to reduce the circuit complexity of the error correction circuit and improve the error correction efficiency of the error correction circuit. Wherein the first set of XOR operational circuits may be a set of optimized XOR operational circuits implemented based on co-located bit coverage reduction; and performing the co-bit calculation using the first set of XOR operational circuits for error correction corresponding to a shorter codeword length, where a smaller XOR operand and a shorter critical path length can be achieved.

A memory device and an operating method of operating the memory device are provided. The method includes: obtaining, by a memory controller, channel selection information indicating positions of data bits and shaping parity bits; generating, by the memory controller, an alignment vector by aligning the data bits and the shaped parity bits having an arbitrary value based on the channel selection information; generating, by the memory controller, second LLR information of the target vector based on the first LLR information related to the alignment vector; determining, by the memory controller, a value of a shaped parity based on the target vector and the second LLR information; performing, by the memory controller, an update operation on the shaped parity based on the determined value; and generating, by the memory controller after performing the update operation, a codeword with respect to the input data based on a first matrix multiplication calculation of the target vector and the first generated matrix.

A sending method, a receiving method, an apparatus, a system, a device, and a storage medium. The receiving method includes: obtaining an encoded data block, where the encoded data block includes a plurality of data blocks, a plurality of first parity bits, and an FEC parity bit, the plurality of first parity bits are in one-to-one correspondence with the plurality of data blocks, and the FEC parity bit corresponds to the plurality of data blocks; and then checking the corresponding data blocks based on the plurality of first parity bits and / or the FEC parity bit, to obtain a decoding result of the encoded data block.

Methods, systems, and devices for wireless communications are described that provide for a transmitter (e.g., a user equipment (UE) or base station) and receiver (e.g., a UE or base station) to transmit and receive data packets that are encoded according to an outer coding technique. The outer coding technique may provide for data bits and parity bits to be included in a single physical layer transmission. In some cases, data packets (e.g., data bits) may be segmented into multiple subpackets, and coding may be performed across different subpackets of different data packets (e.g., in a diagonal coding pattern). In some examples, each transmission in the physical layer may contain both data subpackets and parity subpackets, which may balance an input and an output load of a buffer (e.g., a layer two (L2) decoding buffer at the receiver) during decoding.

A coding method and apparatus for a polar code, which relate to the technical field of communications, and can enable a nested PC-Polar code to reuse a sub-block interleaving rate matching mode of an NR PC-Polar code, so as to improve the NR compatibility. The method comprises: on the basis of a reliability sequence having a length of N, mapping an information bit sequence having a length of k to k bits of a first sequence having a length of N to obtain a second sequence, the second sequence comprising k information bits, x parity check (PC) bits and N-k-x frozen bits, wherein k, N and x are all positive integers, m information bits among the k information bits are the first m bits ranked in descending order of reliability in the second sequence, and the remaining (k-m) information bits among the k information bits are bits in the second sequence that correspond to the first (k-m) information bits ranked in descending order of reliability in a preset information bit set, and the x PC bits are x PC bits in a preset PC bit set; and performing polar coding on the second sequence to obtain a third sequence.

A memory buffer services commands from a host to access data in a memory using parity bits augmented with metadata for improved error correction and detection (EDC). The memory buffer performs EDC-protocol translation so EDC can be optimized for host-side and memory-side correction and detection. The memory buffer also services each host-side memory transaction with two or more memory-side transactions to efficiently read, write, and store metadata for each requested cache-line access.

The present application provides an information processing method based on a coupled code, and a communication apparatus. The method comprises: dividing first information bits into C first blocks, the C first blocks having the same length; and performing coupled encoding on the basis of the C first blocks to obtain a codeword sequence, wherein a parity bit corresponding to an i-th first block among the C first blocks is obtained on the basis of information bits of the i-th first block and information bits of a first blocks, i being an integer greater than or equal to 2, a being an integer greater than or equal to 1, and C being an integer greater than or equal to 2. In the method, coupled encoding is performed on the C first blocks obtained by dividing the first information bits, thereby filling the gap for the first information bits in a coupled encoding scheme; moreover, by using the characteristics of coupled encoding, the i-th first block and the a first blocks are encoded on the basis of a coupling relationship, thereby improving the encoding and decoding performance of each first block.

This application discloses a data processing method and a data processing apparatus. First data processing is performed on multiple first data streams encoded with a first FEC to obtain m second data streams. Each second data stream undergoes second FEC encoding, and each codeword after second FEC encoding includes N bits, where N = K + S, K represents the number of information bits, and S represents the number of parity bits. Second data processing is performed on each of the m second data streams to obtain m third data streams. Each third data stream includes at least one bit sequence, each bit sequence including P + W bits, where P bits in each bit sequence come from the second data streams, and W bits in each bit sequence are added alignment markers, where P = N × b. Third data processing is performed on the m third data streams to obtain Y modulation symbol streams, each modulation symbol stream being modulated, and the baud rate value of each modulation symbol stream being an integer multiple of the typical Ethernet reference clock frequency value.

Apparatuses, systems, and methods for enhanced metadata information. The memory array includes a number of column planes and an extra column plane. A memory device is set in an x4 single-pass operational mode. In this mode, the memory may store a data codeword in a selected ones of the column planes, and metadata may be stored in a non-selected ones of the column planes and in the extra column plane. An error correction code circuit (ECC) may store parity bits associated with the data and metadata in the non-selected ones of the column planes. In this manner, the data, metadata, and parity may be accessed as part of a single access of the memory array.

An apparatus may be configured to generate a set of parity bits for a set of data packets associated with an application; generating an encoded data transmission associated with the UPF, the encoded data transmission comprising a set of data packets and the generated set of parity bits; and outputting the encoded data transmission for a receiving device associated with the application. An apparatus may be configured to obtain an encoded data transmission associated with a UPF, the encoded data transmission comprising a first plurality of bits associated with a set of data packets associated with an application and a second plurality of bits associated with a set of parity bits based on the set of data packets; decoding the encoded data transmission to generate a set of data packets; and outputting the set of data packets for one of an application client or an application server associated with the application.

Methods, systems, and devices for wireless communication are described. A transmitting device may perform a boosting process on a base graph including a plurality of variable nodes and a plurality of check nodes to obtain a boosted graph. The lifting process may include replacing each edge between a plurality of variable nodes and a plurality of check nodes of the base graph with a respective unit matrix having a respective cyclic shift value. The base graph may include punctured variable nodes corresponding to each check node of one or more check nodes of the plurality of check nodes via a plurality of edges. The transmitting device may encode a plurality of information nodes and a plurality of parity nodes according to the boost map. The transmitting device may transmit a signal including a plurality of information bits and a plurality of parity bits based on encoding the plurality of information nodes and the plurality of parity nodes.

This invention discloses a parity check circuit and data verification method for a global Gray code counter in CMOS image sensors, relating to the field of automotive-grade CMOS image sensor technology. It aims to solve the problems of existing CIS architectures being unable to cover the entire data sampling verification chain, the large area overhead of traditional parity check circuits, and verification failures caused by asynchronous sampling timing misalignment. The parity check circuit includes a Gray code data input terminal, a parity bit generator, and a storage write control terminal. The parity bit generator utilizes the conversion characteristics between Gray code and binary code to generate an even parity bit by bitwise XORing the high N-i bits of an N-bit Gray code. This parity bit is equivalent to the i-th bit of the corresponding binary code and maintains a fixed phase deviation from the Gray code. The storage write control terminal controls the data and the parity bit to be written to the storage unit according to the phase deviation. This invention achieves end-to-end data reliability verification, significantly reduces chip area, adapts to asynchronous sampling timing, and meets the functional safety requirements of automotive-grade CIS.

Methods, systems, and devices for error protection for managed memory devices are described. In some examples, a memory system may receive data units from a host device. The data units may include respective sets of parity bits, and the memory system may perform an error detection operation on the data units. A first controller of the memory system may generate a protocol unit using data (e.g., a subset of data) from the data units. The protocol unit may include a set of parity bits (e.g., a different set of parity bits), and a second controller of the memory system may perform an error detection operation on the protocol unit. The second controller of the memory system may generate a data storage unit using data (e.g., a subset of data) from the protocol unit, and may store the data unit and another set of parity bits to a memory device.

The described technology provides a multi-level error correction method including encoding data received from a dual data rate (DDR) memory by performing primary encoding to generate transition symbols, where the primary encoding includes at least one of cyclic redundancy check (CRC) encoding and single error correction dual error detection (SECDED) encoding; performing secondary encoding on the transition symbol to generate an inner code, the inner code including a Code 1 parity generated from the transition symbol and a Code 2 parity generated from the transition symbol and metadata stored on the DDR memory, where the secondary encoding includes Reed-Solomon (RS) encoding, and saving the inner code on a parity storage location on a die of the DDR memory.

Methods, memory devices, and systems for utilizing DDR5 DRAM dice without SEC parity bits, while still providing chipkill protection and RAS performance are described. The disclosed devices utilize a solution based upon locked RAID (LRAID) which omits the on-die SEC bits but retains RAS protections including chipkill protections. The system achieves this protection by replacing the Reed-Solomon parity bits with RAID parity bits, CRC bits, end-to-end SEC bits, and an end-to-end CRC. The SEC protection is enabled, in some examples, by a memory controller, such as by an on-ASIC memory controller making this an on-ASIC SEC rather than an on-die SEC.

An apparatus may include a receiver and one or more processors. The receiver may receive log likelihood ratio (LLR) values corresponding to encoded data that is encoded using a low-density parity-check (LDPC) code. The one or more processors may identify a number of punctured parity bits corresponding to the encoded data, determine that the number of punctured parity bits is less than a threshold, and remove, from a first parity check matrix corresponding to the encoded data, one or more rows corresponding to the number of punctured parity bits to generate a second parity check matrix. The one or more processors may determine, using the LLR values and the second parity check matrix, that there is an error in the LLR values, and an LDPC decoder may decode, based at least on the determination, the LLR values to resolve the error.

In an example method, probabilistic constellation shaping (PCS) processing is performed on a first bit set in k bits, to obtain a second bit set. Forward error correction (FEC) encoding is performed on the second bit set and a third bit set in the k bits excluding the first bit set, to obtain a fourth bit set. The fourth bit set includes m0 first bit subsets, and each of the first bit subsets includes F0 bits. First interleaving processing is performed on the fourth bit set to obtain a fifth bit set. The fifth bit set includes m0 second bit subsets, each of the second bit subsets includes F0 bits, F0 / 2 bits in each of the second bit subsets are from the second bit set, and the other F0 / 2 bits in each of the second bit subsets are from the third bit set and / or parity bits of the FEC encoding.

The invention relates to a memory including an ECC circuit and an operating method of the memory. A memory includes: a first ECC decoder circuit configured to correct errors of first data having a plurality of bits, second data having one or more bits, and first parity bits and generate a first error correction result; a second ECC decoder circuit configured to correct errors of the first data and third data having one or more bits and generate a second error correction result by using the first data, the third data, and the first parity bit; and a first selection circuit configured to select one of the first error correction result and the second error correction result.