361 results about "Parity bit" patented technology

A codeword read from memory includes data blocks including data and supplemental blocks including error correction code (ECC) symbols for detecting and correcting data errors. Metadata can be stored in the supplemental blocks to increase memory utilization but using bits of the supplemental blocks for metadata leaves too few bits remaining for the ECC symbols. To maintain error protection, the supplemental blocks include ECC symbols to protect a first data portion of the codeword and parity bits configured to protect a second data portion of the codeword. Errors in the first data portion can be located and corrected using the ECC symbols. Errors in the second data portion can be detected by the parity. For example, the first data portion is encoded based on the second data portion, so locations of parity errors correspond to locations of symbol errors, and parity errors can be corrected.

Apparatuses, systems, and methods for scalable 1-pass error correction code operations. A memory device includes an error correction code (ECC) circuit which generates a number of parity bits based on a plurality of data bits during a write operation. The number of parity bits may be selected based on a setting in a mode register. The data and parity are written to the memory array as part of a single access pass. The data may be written to a selected portion of the data column planes, while the parity is written to one or more column planes of the extra column plane or a non-selected portion of the data column planes.

Apparatuses, systems, and methods for enhanced metadata information. The memory array includes a number of column planes and an extra column plane. A memory device is set in an x4 single-pass operational mode. In this mode, the memory may store a data codeword in a selected ones of the column planes, and metadata may be stored in a non-selected ones of the column planes and in the extra column plane. An error correction code circuit (ECC) may store parity bits associated with the data and metadata in the non-selected ones of the column planes. In this manner, the data, metadata, and parity may be accessed as part of a single access of the memory array.

Apparatuses, systems, and methods for single-pass access of ECC information, metadata information, or combinations thereof. The memory array includes a number of column planes and an extra column plane. A memory device may be set in an ×4 single-pass operational mode. In this mode, the memory may store data in a selected ones of the column planes, and metadata may be stored in the extra column plane. An error correction code circuit (ECC) may store parity bits associated with the data and metadata in non-selected ones of the column planes. In this manner, the data, metadata, and parity may be accessed as part of a single access of the memory array.

Apparatuses, systems, and methods for enhanced metadata information. The memory array includes a number of column planes and an extra column plane. A memory device is set in an x4 single-pass operational mode. In this mode, the memory may store a data codeword in a selected ones of the column planes, and metadata may be stored in a non-selected ones of the column planes and in the extra column plane. An error correction code circuit (ECC) may store parity bits associated with the data and metadata in the non-selected ones of the column planes. In this manner, the data, metadata, and parity may be accessed as part of a single access of the memory array.

Implementations described herein relate to command address fault detection using a parity bit. A memory device may receive, from a host device via a command address (CA) bus and during a unit interval, a set of CA bits associated with a CA word. The memory device may receive, from the host device via a parity bus and during the unit interval, a first parity bit that is based on the set of CA bits and a parity generation process. The memory device may generate a second parity bit based on the set of CA bits and the parity generation process. The memory device may compare the first parity bit and the second parity bit. The memory device may selectively transmit an alert signal to the host device based on a result of comparing the first parity bit and the second parity bit.

Apparatuses, systems, and methods for single-pass access of ECC information, metadata information, or combinations thereof. The memory array includes a number of column planes and an extra column plane. A memory device may be set in an ×4 single-pass operational mode. In this mode, the memory may store data in a selected ones of the column planes, and metadata may be stored in the extra column plane. An error correction code circuit (ECC) may store parity bits associated with the data and metadata in non-selected ones of the column planes. In this manner, the data, metadata, and parity may be accessed as part of a single access of the memory array.

The invention discloses a serial port communication transmission method and system with high baud rate tolerance. The method comprises the following steps: S1, monitoring a serial port communication line until a level change from logic '1' to logic '0' is detected, and detecting a start bit of a data frame through a triple acknowledgement mechanism; s2, after the transmission of the data bits and the optional parity check bits is completed, continuously monitoring the serial port communication line until the level change from the logic '0' to the logic '1' is detected, and confirming a stop bit for detecting a data frame through triple sampling; and S3, after the stop bit of the data frame is ended, returning to the step S1 to detect the start bit of the next frame of data. According to the invention, by adopting a triple acknowledgement mechanism and a triple sampling acknowledgement method, the start bit and the stop bit of the data frame can be accurately detected, accurate receiving of data can be kept even under the conditions of Baud rate change and noise interference, and an efficient and reliable serial port communication solution is provided for users.

This disclosure describes systems, methods, and devices for probabilistic constellation shaping in wireless transmissions may include a device configured to generate, using a first quadrature amplitude modulation (QAM) order shaping encoder associated with a first code rate, shaped amplitude bits; generate, using a forward error correcting (FEC) encoder and a second code rate smaller than the first code rate, parity bits for the shaped amplitude bits; cause to transmit, using a channel, a first portion of the parity bits as sign bits for the shaped amplitude bits; and cause to transmit, using the channel, a second portion of the parity bits.

The invention provides a polarization code optimization method for a TLC flash memory, which belongs to the technical field of polarization code optimization of an NAND flash memory, and comprises the following steps of: firstly, constructing a polarization code based on a Monte Carlo method: randomly generating code words in each simulation, coding after setting frozen bits, transmitting and reading data through a flash memory channel, counting and accumulating sub-channel error times by using SC decoding, and calculating an error probability; the information bit determination process is optimized according to P / E cycle times for flash memory characteristics; data to be stored in a flash memory are coded based on PC-CASCL, an original binary bit sequence is averagely segmented, PC codes of all sub-segments are added with check bits, after the sub-segments are combined, CRC coding is carried out through a preset polynomial, polar code coding is carried out on a result, and the result is stored in the flash memory. After the coded data is read from the flash memory, decoding is carried out through PC-CASCL, a decoder is initialized, the maximum path number is set, a path list is created, whether the bits are odd-even check bits or not is judged and checked bit by bit, and after all the bits are decoded, an optimal path is selected as output through CRC code check.

Methods, systems, and devices for wireless communication are described to support replacing values of one or more information bit vectors with one or more corresponding sets of parity bits. A first wireless device may replace an information bit vector with a parity bit vector, using a set of information bits of the information bit vector and based on a parity check matrix, which may result in generating the set of information bits at an information bit vector corresponding to a parity bit column of the parity check matrix, during encoding. The first wireless device may perform a transmission to a second wireless device, which may receive the transmission, decode the set of information bits to the information bit vector corresponding to the parity bit column. The second wireless device may replace other bit estimates of a vector corresponding to an information bit column with the set of information bits.

The disclosure relates to a 5th Generation (5G) or pre-5G communication system for supporting a higher data rate after a 4th Generation (4G) communication system such as long term evolution (LTE). The disclosure is for transmitting and receiving data and control information in a wireless communication system. A method of operating a terminal may include receiving from a base station an instruction for Limited Buffer Rate Matching (LBRM), obtaining at least one parameter required to perform the LBRM, determining a limited range of parity bits for the LBRM, based on the parameters, and transmitting or receiving data, based on the limited range.

Memory devices, systems including memory devices, and methods of operating memory devices are described, in which a host device may access a group of memory cells (e.g., portion of an array configurable to store ECC parity bits) otherwise reserved for ECC functionality of a memory device. The memory device may include a register to indicate whether its ECC functionality is enabled or disabled. When the register indicates the ECC functionality is disabled, the memory device may increase a storage capacity available to the host device by making the group of memory cells available for user-accessible data. Additionally or alternatively, the memory device may store metadata associated with various operational aspects of the memory device in the group of memory cells. Moreover, the memory device may modify a burst length to accommodate additional information to be stored in or read from the group of memory cells.

A storage device includes a nonvolatile memory device including a memory cell array and a storage controller to control the nonvolatile memory device. The memory cell array includes word-lines, memory cells and word-line cut regions dividing the word-lines into memory blocks. The storage controller includes an error correction code (ECC) engine including an ECC encoder and a memory interface. The ECC encoder performs a first ECC encoding operation on each of sub data units in user data to generate parity bits and generate a plurality of ECC sectors, selects outer cell bits to be stored in outer cells to constitute an outer ECC sector including the outer cell bits and performs a second ECC encoding operation on the outer ECC sector to generate outer parity bits. The memory interface transmits, to the nonvolatile memory device, a codeword set including the ECC sectors and the outer parity bits.

The invention discloses a polar code coding method and device, relates to the technical field of communication, and can enable a nested PC-Polar code to multiplex a sub-block interleaving rate matching mode of an NR PC-Polar code and improve NR compatibility. The method comprises the following steps: mapping an information bit sequence with the length of k to k bits of a first sequence with the length of N according to a reliability sequence with the length of N to obtain a second sequence; wherein the second sequence comprises k information bits, x parity check PC bits and N-k-x frozen bits, and k, N and x are all positive integers; m information bits in the k information bits are the first m bits ranked according to the reliability from high to low in the second sequence, and the remaining (k-m) information bits in the k information bits are the bits corresponding to the first (k-m) information bits ranked according to the reliability from high to low in the preset information bit set in the second sequence; the x PC bits are x PC bits in a preset PC bit set; and performing polarization coding on the second sequence to obtain a third sequence.

Methods, systems, and devices for wireless communications are described. In some cases, a first wireless device may communicate, with a second wireless device, a control signal indicating a systematic polar code configuration, the systematic polar code configuration indicating for the first wireless device to perform systematic polar encoding on a first set of bits associated with a non-uniform bit distribution. As such, the first wireless device may apply a systematic polar code to the first set of bits to generate a systematic polar codeword based on the systematic polar code configuration. In such cases, the systematic polar codeword may include a set of parity bits and a set of systematic bits. Thus, the first wireless device may transmit at least the set of parity bits of the systematic polar code.

A method of transmitting power by a wireless power transmitter, the method including receiving a plurality of packets including a foreign object detection (FOD) status packet from a wireless power receiver; determining whether a foreign object is present in a charging area of the wireless power transmitter on the basis of the FOD status packet; and transmitting, to the wireless power receiver, a response signal indicating whether the foreign object is present in the charging area of the wireless power transmitter on the basis of a result of the determination, wherein the response signal is determined using a measured peak frequency of a power signal transmitted by the wireless power transmitter and a reference peak frequency included in the FOD status packet received from the wireless power receiver, wherein the plurality of packets further include at least one of a signal strength packet, an end power transfer packet, a power control hold-off packet, a control error packet, a renegotiation packet, an eight-bit received power packet, and a charging status packet, to which a byte encoding technique is applied, and wherein the byte encoding technique is a technique of inserting a start bit, a stop bit, and a parity bit into an encoded binary bit stream of a packet having a length of eight bits.

A memory control circuit stores codewords in a memory module configured to limit errors to one wire of a memory interface. A codeword includes a first block with a first data portion and a second block with a second data portion. An error correction code symbol in the second block is used to locate and correct errors in the second block. Some bits of the first block are repurposed as metadata. The remaining bits are used as parity bits for detecting errors in the first block. The second block is merged with the first block before being stored to memory and demerged from the first block in a memory read operation. Demerging causes errors in the first block to create errors in a corresponding location in the second block. The location of errors found in the second block is used to locate and correct parity errors in the first block.

An apparatus may include a transmitter and one or more processors configured to identify a code rate of a low-density parity-check (LDPC) code, receive, by an LDPC encoder, a set of information bits and encode, using the code rate, the set of information bits to generate a set of encoded bits and a set of parity bits, generate, from the set of encoded bits, a matrix of bit arrays, discard one or more parity bits from the set of parity bits to generate a parity bit array with a size equal to a number of column of the matrix, generate a bit array by concatenating (1) one or more bit arrays selected from the matrix of bit arrays and (2) one or more bits selected from the parity bit array corresponding to the one or more bit arrays, and modulate, by a modulator, the bit array to generate modulated data.

The invention discloses an LDPC encoder based on a DVB-S2 protocol, a transmitting terminal and a test platform, and the LDPC encoder comprises an information bit matrix multi-port input RAM which is used for storing input information bits; the check matrix multi-port ROM is used for storing a check matrix; the accumulative sum matrix RAM is used for storing the accumulative sum matrix generated by the accumulative sum matrix calculation module; the check bit matrix RAM is used for storing a check bit matrix; the check matrix calculation module reads a check matrix from the check matrix multi-port ROM, and the check matrix is converted into a cyclic shift matrix through preprocessing; the accumulative sum matrix calculation module is used for reading information bits from the information bit matrix multi-port input RAM, executing loop right shift and accumulative operation, and calculating to obtain an accumulative sum matrix; and the check bit matrix initialization module is used for calculating a check bit matrix initialization vector according to a calculation result of the accumulation and matrix calculation module.

Methods, systems, and devices for implicit storage of metadata at a memory device are described. A memory device may perform an error correction code (ECC) decoding operation on a first set of parity bits for a set of data and a second set of parity bits for the set of data. The memory device may compare the first set of parity bits to the second set of parity bits based on the ECC decoding operation indicating that the set of data has an uncorrectable error, the first set of parity bits to the second set of parity bits. The memory device may recover metadata information, for the set of data, previously received by the memory device, based on the comparison.

The invention discloses a serial port communication method based on a browser. The method comprises the following steps: requesting a user to authorize to access a serial port device through a navigator.series. Request Port (); the method comprises the following steps: creating a serial port control type instance by constructing a function constructor, and configuring indexes, a baud rate, a data bit, a stop bit and a check bit parameter; calling an openPort () method to open a serial port, and introducing configuration parameters to establish connection; the method comprises the following steps of: acquiring a flow reader through a port.readable. GetReader (), establishing a read-write lock, analyzing return data according to a read type parameter, judging the type of a sent instruction according to the write type parameter, automatically converting instruction data, acquiring the flow reader through the port.readable. GetReader (), establishing the read-write lock, analyzing the return data according to the read type parameter, and calling the port.relayLock () to release the read-write lock after the data is received and transmitted; and instantiating the serial port control component in the Web page, and dynamically managing the connection state and the data flow. According to the invention, serial port communication can be realized only by opening the browser without installing extra software; pure front-end implementation is realized, and a back-end server or a local program is not needed; and the method accords with the modern Web standard and has strong future compatibility.

A memory device includes a memory cell array including a first memory region storing first data, a page buffer including a first latch configured to store data dumped from the memory cell array, and a control logic circuit configured to receive parity adjustment information from an external device and control an operation of the memory cell array. The first data includes first user data and first parity data including parity bits generated based on the first user data, and the control logic circuit dumps first parity data of which a size is adjusted based on the parity adjustment information to the first latch.

Disclosed is a method comprising, by a transmitter apparatus, partitioning (901) an input data stream to obtain a bit stream X1 and a bit stream X2; subjecting (902) the bit stream X2 to encoding by LDPC encoders, to obtain X2 parity bits, and X2 information bits; applying (903) SPC encoding to the X2 parity bits, together with the bit stream X1, to obtain sign bits, wherein the bit stream X1 is used as padding bits; subjecting (904) the sign bits, the padding bits, and the X2 information bits, to an interleaver operation to obtain an interleaver output; subjecting (905) the interleaver output to Gray mapping to form multiple consecutive quadratic amplitude modulation, QAM, symbols; modulating (905) the QAM symbols by quadratic amplitude modulation to obtain a modulated data stream; and transmitting (906) the modulated data stream via a radio access network or optical fibre communication network.

The invention discloses an improved serial cancellation list flipping decoding method and device, a medium and a product, and relates to the technical field of coding, the method comprises the following steps: in a continuous iteration process, generating a candidate path list based on an index of a current decoding bit and a flipping set in a flipping set list; performing circulation to obtain candidate paths passing through cyclic redundancy check bits and candidate paths passing through all parity check bits in the candidate path list; and storing the candidate path with the minimum path metric value into the bit sequence, updating the flip set list, and storing the candidate path which has the minimum path metric value and passes cyclic redundancy check bits into the bit sequence. And taking the bit sequence in which the candidate path is stored as a decoded bit sequence, and ending decoding. According to the method and the device, the balance between DECC and complexity performance can be realized, so that the performance of the polarization code is further improved, and the competitiveness of the polarization code in a future high-reliability and low-energy-consumption communication scene is enhanced.

The invention relates to a high-speed two-bus communication protocol method and system. Data communication transmission is carried out on a two-bus circuit by adopting an SWANBUS protocol frame format; comprising an uplink area, a downlink area, a space area and a free area, the downlink region adopts a modified Miller code coding format and comprises a start bit, a data bit and a corresponding Hamming code check bit; the uplink region comprises a start bit, a data bit and a corresponding parity check bit; the blank area is in a high level; the idle area keeps high level; the SWANBUS protocol can ensure the stable power supply of the terminal because the bus level of the SWANBUS protocol is relatively high, and power supply and communication can be realized only by two wires, so that the cost is greatly reduced; in terms of performance, an uplink and downlink independent frame format is adopted, the high-speed communication requirement which cannot be achieved by a traditional fire-fighting two-way bus can be met, flexibility and changeability are achieved in development, and meanwhile the error rate of information transmission is greatly reduced.

The embodiment of the invention discloses a data processing method capable of being applied to a high-speed optical transmission network. The method comprises the following steps: obtaining second bit data according to first bit data of which the number of bits is din, the second bit data comprising the bits in the din first bit data, dCRC check bits and / or dPAD filling bits; scrambling the second bit data to obtain third bit data, wherein the bit number dscr of the third bit data is equal to din + dCP, and dCP is equal to dCRC + dPAD; then probability constellation shaping PCS processing is carried out on a first bit subset in a first bit set with the bit number of m to obtain a second bit subset, and the first bit set is obtained from the third bit data; performing FEC coding and interleaving processing on the second bit subset and a third bit subset except the first bit subset in the first bit set to obtain a second bit set; according to the invention, different values of the din, the m and the dCP are given, the existing 400G network can be compatible, the performance is excellent, and the cost is low.

Embodiments of the present disclosure relate to a memory system and an operating method thereof. The memory system can include a memory device and a memory controller configured to, when receiving a flush command indicating data to be cached in a data cache is flushed to the memory device from a host, flush first data to be cached in the data cache to the memory device, a size of the first data being less than a size of a reference write unit, write first parity associated with the first data to a parity storage block, update a value of a parity location pointer indicating a location where the first parity is written, and set a parity write flag indicating whether parity at a location pointed to by the parity location pointer is valid.

Apparatuses, systems, and methods for module level error correction. Multiple memory devices a packaged together in a memory module. The module includes a module error correction code (ECC) circuit which pools information multiple memory devices on the module. In an example read operation, multiple memory devices each provide a codeword which includes data bits and parity bits. The codewords may include data bits provided along a data bus and parity bits provided along a parity bus. The ECC circuit pools the codewords and detects errors in the pooled codewords.